2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/bitset.h"
53 #include "util/macros.h"
54 #include "util/hash_table.h"
55 #include "util/list.h"
56 #include "util/sparse_array.h"
57 #include "util/u_atomic.h"
58 #include "util/u_vector.h"
59 #include "util/u_math.h"
61 #include "util/xmlconfig.h"
63 #include "vk_debug_report.h"
65 /* Pre-declarations needed for WSI entrypoints */
68 typedef struct xcb_connection_t xcb_connection_t
;
69 typedef uint32_t xcb_visualid_t
;
70 typedef uint32_t xcb_window_t
;
74 struct anv_buffer_view
;
75 struct anv_image_view
;
78 struct gen_aux_map_context
;
80 struct gen_perf_config
;
82 #include <vulkan/vulkan.h>
83 #include <vulkan/vulkan_intel.h>
84 #include <vulkan/vk_icd.h>
86 #include "anv_android.h"
87 #include "anv_entrypoints.h"
88 #include "anv_extensions.h"
91 #include "dev/gen_debug.h"
92 #include "common/intel_log.h"
93 #include "wsi_common.h"
95 #define NSEC_PER_SEC 1000000000ull
97 /* anv Virtual Memory Layout
98 * =========================
100 * When the anv driver is determining the virtual graphics addresses of memory
101 * objects itself using the softpin mechanism, the following memory ranges
104 * Three special considerations to notice:
106 * (1) the dynamic state pool is located within the same 4 GiB as the low
107 * heap. This is to work around a VF cache issue described in a comment in
108 * anv_physical_device_init_heaps.
110 * (2) the binding table pool is located at lower addresses than the surface
111 * state pool, within a 4 GiB range. This allows surface state base addresses
112 * to cover both binding tables (16 bit offsets) and surface states (32 bit
115 * (3) the last 4 GiB of the address space is withheld from the high
116 * heap. Various hardware units will read past the end of an object for
117 * various reasons. This healthy margin prevents reads from wrapping around
120 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
121 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
122 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
123 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
124 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
125 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
126 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
127 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
128 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
129 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
130 #define HIGH_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
132 #define LOW_HEAP_SIZE \
133 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
134 #define DYNAMIC_STATE_POOL_SIZE \
135 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
136 #define BINDING_TABLE_POOL_SIZE \
137 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
138 #define SURFACE_STATE_POOL_SIZE \
139 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
140 #define INSTRUCTION_STATE_POOL_SIZE \
141 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
143 /* Allowing different clear colors requires us to perform a depth resolve at
144 * the end of certain render passes. This is because while slow clears store
145 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
146 * See the PRMs for examples describing when additional resolves would be
147 * necessary. To enable fast clears without requiring extra resolves, we set
148 * the clear value to a globally-defined one. We could allow different values
149 * if the user doesn't expect coherent data during or after a render passes
150 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
151 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
152 * 1.0f seems to be the only value used. The only application that doesn't set
153 * this value does so through the usage of an seemingly uninitialized clear
156 #define ANV_HZ_FC_VAL 1.0f
159 #define MAX_XFB_BUFFERS 4
160 #define MAX_XFB_STREAMS 4
163 #define MAX_VIEWPORTS 16
164 #define MAX_SCISSORS 16
165 #define MAX_PUSH_CONSTANTS_SIZE 128
166 #define MAX_DYNAMIC_BUFFERS 16
167 #define MAX_IMAGES 64
168 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
169 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
170 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
172 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
174 * "The surface state model is used when a Binding Table Index (specified
175 * in the message descriptor) of less than 240 is specified. In this model,
176 * the Binding Table Index is used to index into the binding table, and the
177 * binding table entry contains a pointer to the SURFACE_STATE."
179 * Binding table values above 240 are used for various things in the hardware
180 * such as stateless, stateless with incoherent cache, SLM, and bindless.
182 #define MAX_BINDING_TABLE_SIZE 240
184 /* The kernel relocation API has a limitation of a 32-bit delta value
185 * applied to the address before it is written which, in spite of it being
186 * unsigned, is treated as signed . Because of the way that this maps to
187 * the Vulkan API, we cannot handle an offset into a buffer that does not
188 * fit into a signed 32 bits. The only mechanism we have for dealing with
189 * this at the moment is to limit all VkDeviceMemory objects to a maximum
190 * of 2GB each. The Vulkan spec allows us to do this:
192 * "Some platforms may have a limit on the maximum size of a single
193 * allocation. For example, certain systems may fail to create
194 * allocations with a size greater than or equal to 4GB. Such a limit is
195 * implementation-dependent, and if such a failure occurs then the error
196 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
198 * We don't use vk_error here because it's not an error so much as an
199 * indication to the application that the allocation is too large.
201 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
203 #define ANV_SVGS_VB_INDEX MAX_VBS
204 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
206 /* We reserve this MI ALU register for the purpose of handling predication.
207 * Other code which uses the MI ALU should leave it alone.
209 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
211 /* For gen12 we set the streamout buffers using 4 separate commands
212 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
213 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
214 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
215 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
216 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
217 * 3DSTATE_SO_BUFFER_INDEX_0.
219 #define SO_BUFFER_INDEX_0_CMD 0x60
220 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
222 static inline uint32_t
223 align_down_npot_u32(uint32_t v
, uint32_t a
)
228 static inline uint32_t
229 align_u32(uint32_t v
, uint32_t a
)
231 assert(a
!= 0 && a
== (a
& -a
));
232 return (v
+ a
- 1) & ~(a
- 1);
235 static inline uint64_t
236 align_u64(uint64_t v
, uint64_t a
)
238 assert(a
!= 0 && a
== (a
& -a
));
239 return (v
+ a
- 1) & ~(a
- 1);
242 static inline int32_t
243 align_i32(int32_t v
, int32_t a
)
245 assert(a
!= 0 && a
== (a
& -a
));
246 return (v
+ a
- 1) & ~(a
- 1);
249 /** Alignment must be a power of 2. */
251 anv_is_aligned(uintmax_t n
, uintmax_t a
)
253 assert(a
== (a
& -a
));
254 return (n
& (a
- 1)) == 0;
257 static inline uint32_t
258 anv_minify(uint32_t n
, uint32_t levels
)
260 if (unlikely(n
== 0))
263 return MAX2(n
>> levels
, 1);
267 anv_clamp_f(float f
, float min
, float max
)
280 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
282 if (*inout_mask
& clear_mask
) {
283 *inout_mask
&= ~clear_mask
;
290 static inline union isl_color_value
291 vk_to_isl_color(VkClearColorValue color
)
293 return (union isl_color_value
) {
303 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
305 uintptr_t mask
= (1ull << bits
) - 1;
307 return (void *) (ptr
& ~mask
);
310 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
312 uintptr_t value
= (uintptr_t) ptr
;
313 uintptr_t mask
= (1ull << bits
) - 1;
314 return value
| (mask
& flags
);
317 #define for_each_bit(b, dword) \
318 for (uint32_t __dword = (dword); \
319 (b) = __builtin_ffs(__dword) - 1, __dword; \
320 __dword &= ~(1 << (b)))
322 #define typed_memcpy(dest, src, count) ({ \
323 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
324 memcpy((dest), (src), (count) * sizeof(*(src))); \
327 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
328 * to be added here in order to utilize mapping in debug/error/perf macros.
330 #define REPORT_OBJECT_TYPE(o) \
331 __builtin_choose_expr ( \
332 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
333 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
334 __builtin_choose_expr ( \
335 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
336 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
337 __builtin_choose_expr ( \
338 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
339 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
340 __builtin_choose_expr ( \
341 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
342 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
343 __builtin_choose_expr ( \
344 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
345 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
346 __builtin_choose_expr ( \
347 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
348 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
349 __builtin_choose_expr ( \
350 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
351 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
352 __builtin_choose_expr ( \
353 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
354 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
355 __builtin_choose_expr ( \
356 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
357 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
358 __builtin_choose_expr ( \
359 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
360 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
361 __builtin_choose_expr ( \
362 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
363 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
364 __builtin_choose_expr ( \
365 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
366 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
367 __builtin_choose_expr ( \
368 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
369 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
370 __builtin_choose_expr ( \
371 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
372 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
373 __builtin_choose_expr ( \
374 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
375 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
376 __builtin_choose_expr ( \
377 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
378 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
379 __builtin_choose_expr ( \
380 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
381 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
382 __builtin_choose_expr ( \
383 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
384 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
385 __builtin_choose_expr ( \
386 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
387 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
388 __builtin_choose_expr ( \
389 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
390 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
391 __builtin_choose_expr ( \
392 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
393 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
394 __builtin_choose_expr ( \
395 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
396 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
397 __builtin_choose_expr ( \
398 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
399 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
400 __builtin_choose_expr ( \
401 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
402 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
403 __builtin_choose_expr ( \
404 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
405 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
406 __builtin_choose_expr ( \
407 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
408 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
409 __builtin_choose_expr ( \
410 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
411 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
412 __builtin_choose_expr ( \
413 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
414 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
415 __builtin_choose_expr ( \
416 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
417 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
418 __builtin_choose_expr ( \
419 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
420 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
421 __builtin_choose_expr ( \
422 __builtin_types_compatible_p (__typeof (o), void*), \
423 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
424 /* The void expression results in a compile-time error \
425 when assigning the result to something. */ \
426 (void)0)))))))))))))))))))))))))))))))
428 /* Whenever we generate an error, pass it through this function. Useful for
429 * debugging, where we can break on it. Only call at error site, not when
430 * propagating errors. Might be useful to plug in a stack trace here.
433 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
434 VkDebugReportObjectTypeEXT type
, VkResult error
,
435 const char *file
, int line
, const char *format
,
438 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
439 VkDebugReportObjectTypeEXT type
, VkResult error
,
440 const char *file
, int line
, const char *format
, ...)
441 anv_printflike(7, 8);
444 #define vk_error(error) __vk_errorf(NULL, NULL,\
445 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
446 error, __FILE__, __LINE__, NULL)
447 #define vk_errorv(instance, obj, error, format, args)\
448 __vk_errorv(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
449 __FILE__, __LINE__, format, args)
450 #define vk_errorf(instance, obj, error, format, ...)\
451 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
452 __FILE__, __LINE__, format, ## __VA_ARGS__)
454 #define vk_error(error) error
455 #define vk_errorf(instance, obj, error, format, ...) error
459 * Warn on ignored extension structs.
461 * The Vulkan spec requires us to ignore unsupported or unknown structs in
462 * a pNext chain. In debug mode, emitting warnings for ignored structs may
463 * help us discover structs that we should not have ignored.
466 * From the Vulkan 1.0.38 spec:
468 * Any component of the implementation (the loader, any enabled layers,
469 * and drivers) must skip over, without processing (other than reading the
470 * sType and pNext members) any chained structures with sType values not
471 * defined by extensions supported by that component.
473 #define anv_debug_ignored_stype(sType) \
474 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
476 void __anv_perf_warn(struct anv_instance
*instance
, const void *object
,
477 VkDebugReportObjectTypeEXT type
, const char *file
,
478 int line
, const char *format
, ...)
479 anv_printflike(6, 7);
480 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
481 void anv_loge_v(const char *format
, va_list va
);
484 * Print a FINISHME message, including its source location.
486 #define anv_finishme(format, ...) \
488 static bool reported = false; \
490 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
497 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
499 #define anv_perf_warn(instance, obj, format, ...) \
501 static bool reported = false; \
502 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
503 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
504 format, ##__VA_ARGS__); \
509 /* A non-fatal assert. Useful for debugging. */
511 #define anv_assert(x) ({ \
512 if (unlikely(!(x))) \
513 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
516 #define anv_assert(x)
519 /* A multi-pointer allocator
521 * When copying data structures from the user (such as a render pass), it's
522 * common to need to allocate data for a bunch of different things. Instead
523 * of doing several allocations and having to handle all of the error checking
524 * that entails, it can be easier to do a single allocation. This struct
525 * helps facilitate that. The intended usage looks like this:
528 * anv_multialloc_add(&ma, &main_ptr, 1);
529 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
530 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
532 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
533 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
535 struct anv_multialloc
{
543 #define ANV_MULTIALLOC_INIT \
544 ((struct anv_multialloc) { 0, })
546 #define ANV_MULTIALLOC(_name) \
547 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
549 __attribute__((always_inline
))
551 _anv_multialloc_add(struct anv_multialloc
*ma
,
552 void **ptr
, size_t size
, size_t align
)
554 size_t offset
= align_u64(ma
->size
, align
);
555 ma
->size
= offset
+ size
;
556 ma
->align
= MAX2(ma
->align
, align
);
558 /* Store the offset in the pointer. */
559 *ptr
= (void *)(uintptr_t)offset
;
561 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
562 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
565 #define anv_multialloc_add_size(_ma, _ptr, _size) \
566 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
568 #define anv_multialloc_add(_ma, _ptr, _count) \
569 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
571 __attribute__((always_inline
))
573 anv_multialloc_alloc(struct anv_multialloc
*ma
,
574 const VkAllocationCallbacks
*alloc
,
575 VkSystemAllocationScope scope
)
577 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
581 /* Fill out each of the pointers with their final value.
583 * for (uint32_t i = 0; i < ma->ptr_count; i++)
584 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
586 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
587 * constant, GCC is incapable of figuring this out and unrolling the loop
588 * so we have to give it a little help.
590 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
591 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
592 if ((_i) < ma->ptr_count) \
593 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
594 _ANV_MULTIALLOC_UPDATE_POINTER(0);
595 _ANV_MULTIALLOC_UPDATE_POINTER(1);
596 _ANV_MULTIALLOC_UPDATE_POINTER(2);
597 _ANV_MULTIALLOC_UPDATE_POINTER(3);
598 _ANV_MULTIALLOC_UPDATE_POINTER(4);
599 _ANV_MULTIALLOC_UPDATE_POINTER(5);
600 _ANV_MULTIALLOC_UPDATE_POINTER(6);
601 _ANV_MULTIALLOC_UPDATE_POINTER(7);
602 #undef _ANV_MULTIALLOC_UPDATE_POINTER
607 __attribute__((always_inline
))
609 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
610 const VkAllocationCallbacks
*parent_alloc
,
611 const VkAllocationCallbacks
*alloc
,
612 VkSystemAllocationScope scope
)
614 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
622 /* Index into the current validation list. This is used by the
623 * validation list building alrogithm to track which buffers are already
624 * in the validation list so that we can ensure uniqueness.
628 /* Index for use with util_sparse_array_free_list */
631 /* Last known offset. This value is provided by the kernel when we
632 * execbuf and is used as the presumed offset for the next bunch of
639 /* Map for internally mapped BOs.
641 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
645 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
648 /** True if this BO may be shared with other processes */
651 /** True if this BO is a wrapper
653 * When set to true, none of the fields in this BO are meaningful except
654 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
655 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
656 * is set in the physical device.
660 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
661 bool has_fixed_address
:1;
663 /** True if this BO wraps a host pointer */
664 bool from_host_ptr
:1;
667 static inline struct anv_bo
*
668 anv_bo_unwrap(struct anv_bo
*bo
)
670 while (bo
->is_wrapper
)
675 /* Represents a lock-free linked list of "free" things. This is used by
676 * both the block pool and the state pools. Unfortunately, in order to
677 * solve the ABA problem, we can't use a single uint32_t head.
679 union anv_free_list
{
683 /* A simple count that is incremented every time the head changes. */
686 /* Make sure it's aligned to 64 bits. This will make atomic operations
687 * faster on 32 bit platforms.
689 uint64_t u64
__attribute__ ((aligned (8)));
692 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
694 struct anv_block_state
{
700 /* Make sure it's aligned to 64 bits. This will make atomic operations
701 * faster on 32 bit platforms.
703 uint64_t u64
__attribute__ ((aligned (8)));
707 #define anv_block_pool_foreach_bo(bo, pool) \
708 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
709 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
712 #define ANV_MAX_BLOCK_POOL_BOS 20
714 struct anv_block_pool
{
715 struct anv_device
*device
;
718 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
719 * around the actual BO so that we grow the pool after the wrapper BO has
720 * been put in a relocation list. This is only used in the non-softpin
723 struct anv_bo wrapper_bo
;
725 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
731 /* The address where the start of the pool is pinned. The various bos that
732 * are created as the pool grows will have addresses in the range
733 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
735 uint64_t start_address
;
737 /* The offset from the start of the bo to the "center" of the block
738 * pool. Pointers to allocated blocks are given by
739 * bo.map + center_bo_offset + offsets.
741 uint32_t center_bo_offset
;
743 /* Current memory map of the block pool. This pointer may or may not
744 * point to the actual beginning of the block pool memory. If
745 * anv_block_pool_alloc_back has ever been called, then this pointer
746 * will point to the "center" position of the buffer and all offsets
747 * (negative or positive) given out by the block pool alloc functions
748 * will be valid relative to this pointer.
750 * In particular, map == bo.map + center_offset
752 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
753 * since it will handle the softpin case as well, where this points to NULL.
759 * Array of mmaps and gem handles owned by the block pool, reclaimed when
760 * the block pool is destroyed.
762 struct u_vector mmap_cleanups
;
764 struct anv_block_state state
;
766 struct anv_block_state back_state
;
769 /* Block pools are backed by a fixed-size 1GB memfd */
770 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
772 /* The center of the block pool is also the middle of the memfd. This may
773 * change in the future if we decide differently for some reason.
775 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
777 static inline uint32_t
778 anv_block_pool_size(struct anv_block_pool
*pool
)
780 return pool
->state
.end
+ pool
->back_state
.end
;
790 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
792 struct anv_fixed_size_state_pool
{
793 union anv_free_list free_list
;
794 struct anv_block_state block
;
797 #define ANV_MIN_STATE_SIZE_LOG2 6
798 #define ANV_MAX_STATE_SIZE_LOG2 21
800 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
802 struct anv_free_entry
{
804 struct anv_state state
;
807 struct anv_state_table
{
808 struct anv_device
*device
;
810 struct anv_free_entry
*map
;
812 struct anv_block_state state
;
813 struct u_vector cleanups
;
816 struct anv_state_pool
{
817 struct anv_block_pool block_pool
;
819 struct anv_state_table table
;
821 /* The size of blocks which will be allocated from the block pool */
824 /** Free list for "back" allocations */
825 union anv_free_list back_alloc_free_list
;
827 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
830 struct anv_state_stream_block
;
832 struct anv_state_stream
{
833 struct anv_state_pool
*state_pool
;
835 /* The size of blocks to allocate from the state pool */
838 /* Current block we're allocating from */
839 struct anv_state block
;
841 /* Offset into the current block at which to allocate the next state */
844 /* List of all blocks allocated from this pool */
845 struct anv_state_stream_block
*block_list
;
848 /* The block_pool functions exported for testing only. The block pool should
849 * only be used via a state pool (see below).
851 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
852 struct anv_device
*device
,
853 uint64_t start_address
,
854 uint32_t initial_size
);
855 void anv_block_pool_finish(struct anv_block_pool
*pool
);
856 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
857 uint32_t block_size
, uint32_t *padding
);
858 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
859 uint32_t block_size
);
860 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
862 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
863 struct anv_device
*device
,
864 uint64_t start_address
,
865 uint32_t block_size
);
866 void anv_state_pool_finish(struct anv_state_pool
*pool
);
867 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
868 uint32_t state_size
, uint32_t alignment
);
869 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
870 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
871 void anv_state_stream_init(struct anv_state_stream
*stream
,
872 struct anv_state_pool
*state_pool
,
873 uint32_t block_size
);
874 void anv_state_stream_finish(struct anv_state_stream
*stream
);
875 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
876 uint32_t size
, uint32_t alignment
);
878 VkResult
anv_state_table_init(struct anv_state_table
*table
,
879 struct anv_device
*device
,
880 uint32_t initial_entries
);
881 void anv_state_table_finish(struct anv_state_table
*table
);
882 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
884 void anv_free_list_push(union anv_free_list
*list
,
885 struct anv_state_table
*table
,
886 uint32_t idx
, uint32_t count
);
887 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
888 struct anv_state_table
*table
);
891 static inline struct anv_state
*
892 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
894 return &table
->map
[idx
].state
;
897 * Implements a pool of re-usable BOs. The interface is identical to that
898 * of block_pool except that each block is its own BO.
901 struct anv_device
*device
;
903 struct util_sparse_array_free_list free_list
[16];
906 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
907 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
908 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
909 struct anv_bo
**bo_out
);
910 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
912 struct anv_scratch_pool
{
913 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
914 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
917 void anv_scratch_pool_init(struct anv_device
*device
,
918 struct anv_scratch_pool
*pool
);
919 void anv_scratch_pool_finish(struct anv_device
*device
,
920 struct anv_scratch_pool
*pool
);
921 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
922 struct anv_scratch_pool
*pool
,
923 gl_shader_stage stage
,
924 unsigned per_thread_scratch
);
926 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
927 struct anv_bo_cache
{
928 struct util_sparse_array bo_map
;
929 pthread_mutex_t mutex
;
932 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
933 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
935 struct anv_memory_type
{
936 /* Standard bits passed on to the client */
937 VkMemoryPropertyFlags propertyFlags
;
940 /* Driver-internal book-keeping */
941 VkBufferUsageFlags valid_buffer_usage
;
944 struct anv_memory_heap
{
945 /* Standard bits passed on to the client */
947 VkMemoryHeapFlags flags
;
949 /* Driver-internal book-keeping */
952 bool supports_48bit_addresses
;
956 struct anv_physical_device
{
957 VK_LOADER_DATA _loader_data
;
959 struct anv_instance
* instance
;
970 struct gen_device_info info
;
971 /** Amount of "GPU memory" we want to advertise
973 * Clearly, this value is bogus since Intel is a UMA architecture. On
974 * gen7 platforms, we are limited by GTT size unless we want to implement
975 * fine-grained tracking and GTT splitting. On Broadwell and above we are
976 * practically unlimited. However, we will never report more than 3/4 of
977 * the total system ram to try and avoid running out of RAM.
979 bool supports_48bit_addresses
;
980 struct brw_compiler
* compiler
;
981 struct isl_device isl_dev
;
982 struct gen_perf_config
* perf
;
983 int cmd_parser_version
;
986 bool has_exec_capture
;
989 bool has_syncobj_wait
;
990 bool has_context_priority
;
991 bool has_context_isolation
;
992 bool has_mem_available
;
995 bool always_use_bindless
;
997 /** True if we can access buffers using A64 messages */
998 bool has_a64_buffer_access
;
999 /** True if we can use bindless access for images */
1000 bool has_bindless_images
;
1001 /** True if we can use bindless access for samplers */
1002 bool has_bindless_samplers
;
1004 bool always_flush_cache
;
1006 struct anv_device_extension_table supported_extensions
;
1007 struct anv_physical_device_dispatch_table dispatch
;
1010 uint32_t subslice_total
;
1013 uint32_t type_count
;
1014 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1015 uint32_t heap_count
;
1016 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1019 uint8_t driver_build_sha1
[20];
1020 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1021 uint8_t driver_uuid
[VK_UUID_SIZE
];
1022 uint8_t device_uuid
[VK_UUID_SIZE
];
1024 struct disk_cache
* disk_cache
;
1026 struct wsi_device wsi_device
;
1031 struct anv_app_info
{
1032 const char* app_name
;
1033 uint32_t app_version
;
1034 const char* engine_name
;
1035 uint32_t engine_version
;
1036 uint32_t api_version
;
1039 struct anv_instance
{
1040 VK_LOADER_DATA _loader_data
;
1042 VkAllocationCallbacks alloc
;
1044 struct anv_app_info app_info
;
1046 struct anv_instance_extension_table enabled_extensions
;
1047 struct anv_instance_dispatch_table dispatch
;
1048 struct anv_device_dispatch_table device_dispatch
;
1050 int physicalDeviceCount
;
1051 struct anv_physical_device physicalDevice
;
1053 bool pipeline_cache_enabled
;
1055 struct vk_debug_report_instance debug_report_callbacks
;
1057 struct driOptionCache dri_options
;
1058 struct driOptionCache available_dri_options
;
1061 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1062 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1064 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1065 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1068 struct anv_queue_submit
{
1069 struct anv_cmd_buffer
* cmd_buffer
;
1071 uint32_t fence_count
;
1072 uint32_t fence_array_length
;
1073 struct drm_i915_gem_exec_fence
* fences
;
1075 uint32_t temporary_semaphore_count
;
1076 uint32_t temporary_semaphore_array_length
;
1077 struct anv_semaphore_impl
* temporary_semaphores
;
1079 /* Semaphores to be signaled with a SYNC_FD. */
1080 struct anv_semaphore
** sync_fd_semaphores
;
1081 uint32_t sync_fd_semaphore_count
;
1082 uint32_t sync_fd_semaphore_array_length
;
1084 /* Allocated only with non shareable timelines. */
1085 struct anv_timeline
** wait_timelines
;
1086 uint32_t wait_timeline_count
;
1087 uint32_t wait_timeline_array_length
;
1088 uint64_t * wait_timeline_values
;
1090 struct anv_timeline
** signal_timelines
;
1091 uint32_t signal_timeline_count
;
1092 uint32_t signal_timeline_array_length
;
1093 uint64_t * signal_timeline_values
;
1096 bool need_out_fence
;
1099 uint32_t fence_bo_count
;
1100 uint32_t fence_bo_array_length
;
1101 /* An array of struct anv_bo pointers with lower bit used as a flag to
1102 * signal we will wait on that BO (see anv_(un)pack_ptr).
1104 uintptr_t * fence_bos
;
1106 const VkAllocationCallbacks
* alloc
;
1107 VkSystemAllocationScope alloc_scope
;
1109 struct anv_bo
* simple_bo
;
1110 uint32_t simple_bo_size
;
1112 struct list_head link
;
1116 VK_LOADER_DATA _loader_data
;
1118 struct anv_device
* device
;
1121 * A list of struct anv_queue_submit to be submitted to i915.
1123 struct list_head queued_submits
;
1125 VkDeviceQueueCreateFlags flags
;
1128 struct anv_pipeline_cache
{
1129 struct anv_device
* device
;
1130 pthread_mutex_t mutex
;
1132 struct hash_table
* nir_cache
;
1134 struct hash_table
* cache
;
1137 struct nir_xfb_info
;
1138 struct anv_pipeline_bind_map
;
1140 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1141 struct anv_device
*device
,
1142 bool cache_enabled
);
1143 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1145 struct anv_shader_bin
*
1146 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1147 const void *key
, uint32_t key_size
);
1148 struct anv_shader_bin
*
1149 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1150 const void *key_data
, uint32_t key_size
,
1151 const void *kernel_data
, uint32_t kernel_size
,
1152 const void *constant_data
,
1153 uint32_t constant_data_size
,
1154 const struct brw_stage_prog_data
*prog_data
,
1155 uint32_t prog_data_size
,
1156 const struct brw_compile_stats
*stats
,
1158 const struct nir_xfb_info
*xfb_info
,
1159 const struct anv_pipeline_bind_map
*bind_map
);
1161 struct anv_shader_bin
*
1162 anv_device_search_for_kernel(struct anv_device
*device
,
1163 struct anv_pipeline_cache
*cache
,
1164 const void *key_data
, uint32_t key_size
,
1165 bool *user_cache_bit
);
1167 struct anv_shader_bin
*
1168 anv_device_upload_kernel(struct anv_device
*device
,
1169 struct anv_pipeline_cache
*cache
,
1170 const void *key_data
, uint32_t key_size
,
1171 const void *kernel_data
, uint32_t kernel_size
,
1172 const void *constant_data
,
1173 uint32_t constant_data_size
,
1174 const struct brw_stage_prog_data
*prog_data
,
1175 uint32_t prog_data_size
,
1176 const struct brw_compile_stats
*stats
,
1178 const struct nir_xfb_info
*xfb_info
,
1179 const struct anv_pipeline_bind_map
*bind_map
);
1182 struct nir_shader_compiler_options
;
1185 anv_device_search_for_nir(struct anv_device
*device
,
1186 struct anv_pipeline_cache
*cache
,
1187 const struct nir_shader_compiler_options
*nir_options
,
1188 unsigned char sha1_key
[20],
1192 anv_device_upload_nir(struct anv_device
*device
,
1193 struct anv_pipeline_cache
*cache
,
1194 const struct nir_shader
*nir
,
1195 unsigned char sha1_key
[20]);
1198 VK_LOADER_DATA _loader_data
;
1200 VkAllocationCallbacks alloc
;
1202 struct anv_instance
* instance
;
1203 uint32_t chipset_id
;
1205 struct gen_device_info info
;
1206 struct isl_device isl_dev
;
1209 bool can_chain_batches
;
1210 bool robust_buffer_access
;
1211 struct anv_device_extension_table enabled_extensions
;
1212 struct anv_device_dispatch_table dispatch
;
1214 pthread_mutex_t vma_mutex
;
1215 struct util_vma_heap vma_lo
;
1216 struct util_vma_heap vma_hi
;
1217 uint64_t vma_lo_available
;
1218 uint64_t vma_hi_available
;
1220 /** List of all anv_device_memory objects */
1221 struct list_head memory_objects
;
1223 struct anv_bo_pool batch_bo_pool
;
1225 struct anv_bo_cache bo_cache
;
1227 struct anv_state_pool dynamic_state_pool
;
1228 struct anv_state_pool instruction_state_pool
;
1229 struct anv_state_pool binding_table_pool
;
1230 struct anv_state_pool surface_state_pool
;
1232 struct anv_bo
* workaround_bo
;
1233 struct anv_bo
* trivial_batch_bo
;
1234 struct anv_bo
* hiz_clear_bo
;
1236 struct anv_pipeline_cache default_pipeline_cache
;
1237 struct blorp_context blorp
;
1239 struct anv_state border_colors
;
1241 struct anv_state slice_hash
;
1243 struct anv_queue queue
;
1245 struct anv_scratch_pool scratch_pool
;
1247 pthread_mutex_t mutex
;
1248 pthread_cond_t queue_submit
;
1251 struct gen_batch_decode_ctx decoder_ctx
;
1253 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1254 * the cmd_buffer's list.
1256 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1258 int perf_fd
; /* -1 if no opened */
1259 uint64_t perf_metric
; /* 0 if unset */
1261 struct gen_aux_map_context
*aux_map_ctx
;
1264 static inline struct anv_state_pool
*
1265 anv_binding_table_pool(struct anv_device
*device
)
1267 if (device
->instance
->physicalDevice
.use_softpin
)
1268 return &device
->binding_table_pool
;
1270 return &device
->surface_state_pool
;
1273 static inline struct anv_state
1274 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1275 if (device
->instance
->physicalDevice
.use_softpin
)
1276 return anv_state_pool_alloc(&device
->binding_table_pool
,
1277 device
->binding_table_pool
.block_size
, 0);
1279 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1283 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1284 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1287 static inline uint32_t
1288 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1290 if (bo
->is_external
)
1291 return device
->isl_dev
.mocs
.external
;
1293 return device
->isl_dev
.mocs
.internal
;
1296 void anv_device_init_blorp(struct anv_device
*device
);
1297 void anv_device_finish_blorp(struct anv_device
*device
);
1299 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1300 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1301 const char *file
, int line
,
1302 const char *msg
, ...)
1303 anv_printflike(4, 5);
1304 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1305 const char *file
, int line
,
1306 const char *msg
, ...)
1307 anv_printflike(4, 5);
1308 #define anv_device_set_lost(dev, ...) \
1309 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1310 #define anv_queue_set_lost(queue, ...) \
1311 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1314 anv_device_is_lost(struct anv_device
*device
)
1316 return unlikely(p_atomic_read(&device
->_lost
));
1319 VkResult
anv_device_query_status(struct anv_device
*device
);
1322 enum anv_bo_alloc_flags
{
1323 /** Specifies that the BO must have a 32-bit address
1325 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1327 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1329 /** Specifies that the BO may be shared externally */
1330 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1332 /** Specifies that the BO should be mapped */
1333 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1335 /** Specifies that the BO should be snooped so we get coherency */
1336 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1338 /** Specifies that the BO should be captured in error states */
1339 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1341 /** Specifies that the BO will have an address assigned by the caller */
1342 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1344 /** Enables implicit synchronization on the BO
1346 * This is the opposite of EXEC_OBJECT_ASYNC.
1348 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1350 /** Enables implicit synchronization on the BO
1352 * This is equivalent to EXEC_OBJECT_WRITE.
1354 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1357 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1358 enum anv_bo_alloc_flags alloc_flags
,
1359 struct anv_bo
**bo
);
1360 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1361 void *host_ptr
, uint32_t size
,
1362 enum anv_bo_alloc_flags alloc_flags
,
1363 struct anv_bo
**bo_out
);
1364 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1365 enum anv_bo_alloc_flags alloc_flags
,
1366 struct anv_bo
**bo
);
1367 VkResult
anv_device_export_bo(struct anv_device
*device
,
1368 struct anv_bo
*bo
, int *fd_out
);
1369 void anv_device_release_bo(struct anv_device
*device
,
1372 static inline struct anv_bo
*
1373 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1375 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1378 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1379 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1382 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1383 void anv_queue_finish(struct anv_queue
*queue
);
1385 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1386 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1387 struct anv_batch
*batch
);
1389 uint64_t anv_gettime_ns(void);
1390 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1392 void* anv_gem_mmap(struct anv_device
*device
,
1393 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1394 void anv_gem_munmap(void *p
, uint64_t size
);
1395 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1396 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1397 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1398 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1399 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1400 int anv_gem_execbuffer(struct anv_device
*device
,
1401 struct drm_i915_gem_execbuffer2
*execbuf
);
1402 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1403 uint32_t stride
, uint32_t tiling
);
1404 int anv_gem_create_context(struct anv_device
*device
);
1405 bool anv_gem_has_context_priority(int fd
);
1406 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1407 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1409 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1411 int anv_gem_get_param(int fd
, uint32_t param
);
1412 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1413 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1414 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1415 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1416 uint32_t *active
, uint32_t *pending
);
1417 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1418 int anv_gem_reg_read(struct anv_device
*device
,
1419 uint32_t offset
, uint64_t *result
);
1420 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1421 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1422 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1423 uint32_t read_domains
, uint32_t write_domain
);
1424 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1425 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1426 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1427 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1428 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1429 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1431 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1432 uint32_t handle
, int fd
);
1433 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1434 bool anv_gem_supports_syncobj_wait(int fd
);
1435 int anv_gem_syncobj_wait(struct anv_device
*device
,
1436 uint32_t *handles
, uint32_t num_handles
,
1437 int64_t abs_timeout_ns
, bool wait_all
);
1439 bool anv_vma_alloc(struct anv_device
*device
, struct anv_bo
*bo
);
1440 void anv_vma_free(struct anv_device
*device
, struct anv_bo
*bo
);
1442 struct anv_reloc_list
{
1443 uint32_t num_relocs
;
1444 uint32_t array_length
;
1445 struct drm_i915_gem_relocation_entry
* relocs
;
1446 struct anv_bo
** reloc_bos
;
1451 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1452 const VkAllocationCallbacks
*alloc
);
1453 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1454 const VkAllocationCallbacks
*alloc
);
1456 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1457 const VkAllocationCallbacks
*alloc
,
1458 uint32_t offset
, struct anv_bo
*target_bo
,
1459 uint32_t delta
, uint64_t *address_u64_out
);
1461 struct anv_batch_bo
{
1462 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1463 struct list_head link
;
1467 /* Bytes actually consumed in this batch BO */
1470 struct anv_reloc_list relocs
;
1474 const VkAllocationCallbacks
* alloc
;
1480 struct anv_reloc_list
* relocs
;
1482 /* This callback is called (with the associated user data) in the event
1483 * that the batch runs out of space.
1485 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1489 * Current error status of the command buffer. Used to track inconsistent
1490 * or incomplete command buffer states that are the consequence of run-time
1491 * errors such as out of memory scenarios. We want to track this in the
1492 * batch because the command buffer object is not visible to some parts
1498 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1499 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1500 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1501 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1503 static inline VkResult
1504 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1506 assert(error
!= VK_SUCCESS
);
1507 if (batch
->status
== VK_SUCCESS
)
1508 batch
->status
= error
;
1509 return batch
->status
;
1513 anv_batch_has_error(struct anv_batch
*batch
)
1515 return batch
->status
!= VK_SUCCESS
;
1518 struct anv_address
{
1523 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1526 anv_address_is_null(struct anv_address addr
)
1528 return addr
.bo
== NULL
&& addr
.offset
== 0;
1531 static inline uint64_t
1532 anv_address_physical(struct anv_address addr
)
1534 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1535 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1537 return gen_canonical_address(addr
.offset
);
1540 static inline struct anv_address
1541 anv_address_add(struct anv_address addr
, uint64_t offset
)
1543 addr
.offset
+= offset
;
1548 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1550 unsigned reloc_size
= 0;
1551 if (device
->info
.gen
>= 8) {
1552 reloc_size
= sizeof(uint64_t);
1553 *(uint64_t *)p
= gen_canonical_address(v
);
1555 reloc_size
= sizeof(uint32_t);
1559 if (flush
&& !device
->info
.has_llc
)
1560 gen_flush_range(p
, reloc_size
);
1563 static inline uint64_t
1564 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1565 const struct anv_address address
, uint32_t delta
)
1567 if (address
.bo
== NULL
) {
1568 return address
.offset
+ delta
;
1570 assert(batch
->start
<= location
&& location
< batch
->end
);
1572 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1576 #define __gen_address_type struct anv_address
1577 #define __gen_user_data struct anv_batch
1578 #define __gen_combine_address _anv_combine_address
1580 /* Wrapper macros needed to work around preprocessor argument issues. In
1581 * particular, arguments don't get pre-evaluated if they are concatenated.
1582 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1583 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1584 * We can work around this easily enough with these helpers.
1586 #define __anv_cmd_length(cmd) cmd ## _length
1587 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1588 #define __anv_cmd_header(cmd) cmd ## _header
1589 #define __anv_cmd_pack(cmd) cmd ## _pack
1590 #define __anv_reg_num(reg) reg ## _num
1592 #define anv_pack_struct(dst, struc, ...) do { \
1593 struct struc __template = { \
1596 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1597 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1600 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1601 void *__dst = anv_batch_emit_dwords(batch, n); \
1603 struct cmd __template = { \
1604 __anv_cmd_header(cmd), \
1605 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1608 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1613 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1617 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1618 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1621 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1622 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1623 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1626 #define anv_batch_emit(batch, cmd, name) \
1627 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1628 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1629 __builtin_expect(_dst != NULL, 1); \
1630 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1631 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1635 struct anv_device_memory
{
1636 struct list_head link
;
1639 struct anv_memory_type
* type
;
1640 VkDeviceSize map_size
;
1643 /* If set, we are holding reference to AHardwareBuffer
1644 * which we must release when memory is freed.
1646 struct AHardwareBuffer
* ahw
;
1648 /* If set, this memory comes from a host pointer. */
1653 * Header for Vertex URB Entry (VUE)
1655 struct anv_vue_header
{
1657 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1658 uint32_t ViewportIndex
;
1662 /** Struct representing a sampled image descriptor
1664 * This descriptor layout is used for sampled images, bare sampler, and
1665 * combined image/sampler descriptors.
1667 struct anv_sampled_image_descriptor
{
1668 /** Bindless image handle
1670 * This is expected to already be shifted such that the 20-bit
1671 * SURFACE_STATE table index is in the top 20 bits.
1675 /** Bindless sampler handle
1677 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1678 * to the dynamic state base address.
1683 struct anv_texture_swizzle_descriptor
{
1686 * See also nir_intrinsic_channel_select_intel
1690 /** Unused padding to ensure the struct is a multiple of 64 bits */
1694 /** Struct representing a storage image descriptor */
1695 struct anv_storage_image_descriptor
{
1696 /** Bindless image handles
1698 * These are expected to already be shifted such that the 20-bit
1699 * SURFACE_STATE table index is in the top 20 bits.
1701 uint32_t read_write
;
1702 uint32_t write_only
;
1705 /** Struct representing a address/range descriptor
1707 * The fields of this struct correspond directly to the data layout of
1708 * nir_address_format_64bit_bounded_global addresses. The last field is the
1709 * offset in the NIR address so it must be zero so that when you load the
1710 * descriptor you get a pointer to the start of the range.
1712 struct anv_address_range_descriptor
{
1718 enum anv_descriptor_data
{
1719 /** The descriptor contains a BTI reference to a surface state */
1720 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1721 /** The descriptor contains a BTI reference to a sampler state */
1722 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1723 /** The descriptor contains an actual buffer view */
1724 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1725 /** The descriptor contains auxiliary image layout data */
1726 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1727 /** The descriptor contains auxiliary image layout data */
1728 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1729 /** anv_address_range_descriptor with a buffer address and range */
1730 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1731 /** Bindless surface handle */
1732 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1733 /** Storage image handles */
1734 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1735 /** Storage image handles */
1736 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1739 struct anv_descriptor_set_binding_layout
{
1741 /* The type of the descriptors in this binding */
1742 VkDescriptorType type
;
1745 /* Flags provided when this binding was created */
1746 VkDescriptorBindingFlagsEXT flags
;
1748 /* Bitfield representing the type of data this descriptor contains */
1749 enum anv_descriptor_data data
;
1751 /* Maximum number of YCbCr texture/sampler planes */
1752 uint8_t max_plane_count
;
1754 /* Number of array elements in this binding (or size in bytes for inline
1757 uint16_t array_size
;
1759 /* Index into the flattend descriptor set */
1760 uint16_t descriptor_index
;
1762 /* Index into the dynamic state array for a dynamic buffer */
1763 int16_t dynamic_offset_index
;
1765 /* Index into the descriptor set buffer views */
1766 int16_t buffer_view_index
;
1768 /* Offset into the descriptor buffer where this descriptor lives */
1769 uint32_t descriptor_offset
;
1771 /* Immutable samplers (or NULL if no immutable samplers) */
1772 struct anv_sampler
**immutable_samplers
;
1775 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1777 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1778 VkDescriptorType type
);
1780 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1781 const struct anv_descriptor_set_binding_layout
*binding
,
1784 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1785 const struct anv_descriptor_set_binding_layout
*binding
,
1788 struct anv_descriptor_set_layout
{
1789 /* Descriptor set layouts can be destroyed at almost any time */
1792 /* Number of bindings in this descriptor set */
1793 uint16_t binding_count
;
1795 /* Total size of the descriptor set with room for all array entries */
1798 /* Shader stages affected by this descriptor set */
1799 uint16_t shader_stages
;
1801 /* Number of buffer views in this descriptor set */
1802 uint16_t buffer_view_count
;
1804 /* Number of dynamic offsets used by this descriptor set */
1805 uint16_t dynamic_offset_count
;
1807 /* For each shader stage, which offsets apply to that stage */
1808 uint16_t stage_dynamic_offsets
[MESA_SHADER_STAGES
];
1810 /* Size of the descriptor buffer for this descriptor set */
1811 uint32_t descriptor_buffer_size
;
1813 /* Bindings in this descriptor set */
1814 struct anv_descriptor_set_binding_layout binding
[0];
1818 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1820 assert(layout
&& layout
->ref_cnt
>= 1);
1821 p_atomic_inc(&layout
->ref_cnt
);
1825 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1826 struct anv_descriptor_set_layout
*layout
)
1828 assert(layout
&& layout
->ref_cnt
>= 1);
1829 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1830 vk_free(&device
->alloc
, layout
);
1833 struct anv_descriptor
{
1834 VkDescriptorType type
;
1838 VkImageLayout layout
;
1839 struct anv_image_view
*image_view
;
1840 struct anv_sampler
*sampler
;
1844 struct anv_buffer
*buffer
;
1849 struct anv_buffer_view
*buffer_view
;
1853 struct anv_descriptor_set
{
1854 struct anv_descriptor_pool
*pool
;
1855 struct anv_descriptor_set_layout
*layout
;
1858 /* State relative to anv_descriptor_pool::bo */
1859 struct anv_state desc_mem
;
1860 /* Surface state for the descriptor buffer */
1861 struct anv_state desc_surface_state
;
1863 uint32_t buffer_view_count
;
1864 struct anv_buffer_view
*buffer_views
;
1866 /* Link to descriptor pool's desc_sets list . */
1867 struct list_head pool_link
;
1869 struct anv_descriptor descriptors
[0];
1872 struct anv_buffer_view
{
1873 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1874 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1876 struct anv_address address
;
1878 struct anv_state surface_state
;
1879 struct anv_state storage_surface_state
;
1880 struct anv_state writeonly_storage_surface_state
;
1882 struct brw_image_param storage_image_param
;
1885 struct anv_push_descriptor_set
{
1886 struct anv_descriptor_set set
;
1888 /* Put this field right behind anv_descriptor_set so it fills up the
1889 * descriptors[0] field. */
1890 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1892 /** True if the descriptor set buffer has been referenced by a draw or
1895 bool set_used_on_gpu
;
1897 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1900 struct anv_descriptor_pool
{
1906 struct util_vma_heap bo_heap
;
1908 struct anv_state_stream surface_state_stream
;
1909 void *surface_state_free_list
;
1911 struct list_head desc_sets
;
1916 enum anv_descriptor_template_entry_type
{
1917 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1918 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1919 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1922 struct anv_descriptor_template_entry
{
1923 /* The type of descriptor in this entry */
1924 VkDescriptorType type
;
1926 /* Binding in the descriptor set */
1929 /* Offset at which to write into the descriptor set binding */
1930 uint32_t array_element
;
1932 /* Number of elements to write into the descriptor set binding */
1933 uint32_t array_count
;
1935 /* Offset into the user provided data */
1938 /* Stride between elements into the user provided data */
1942 struct anv_descriptor_update_template
{
1943 VkPipelineBindPoint bind_point
;
1945 /* The descriptor set this template corresponds to. This value is only
1946 * valid if the template was created with the templateType
1947 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1951 /* Number of entries in this template */
1952 uint32_t entry_count
;
1954 /* Entries of the template */
1955 struct anv_descriptor_template_entry entries
[0];
1959 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1962 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1963 struct anv_descriptor_set
*set
,
1964 const VkDescriptorImageInfo
* const info
,
1965 VkDescriptorType type
,
1970 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
1971 struct anv_descriptor_set
*set
,
1972 VkDescriptorType type
,
1973 struct anv_buffer_view
*buffer_view
,
1978 anv_descriptor_set_write_buffer(struct anv_device
*device
,
1979 struct anv_descriptor_set
*set
,
1980 struct anv_state_stream
*alloc_stream
,
1981 VkDescriptorType type
,
1982 struct anv_buffer
*buffer
,
1985 VkDeviceSize offset
,
1986 VkDeviceSize range
);
1988 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
1989 struct anv_descriptor_set
*set
,
1996 anv_descriptor_set_write_template(struct anv_device
*device
,
1997 struct anv_descriptor_set
*set
,
1998 struct anv_state_stream
*alloc_stream
,
1999 const struct anv_descriptor_update_template
*template,
2003 anv_descriptor_set_create(struct anv_device
*device
,
2004 struct anv_descriptor_pool
*pool
,
2005 struct anv_descriptor_set_layout
*layout
,
2006 struct anv_descriptor_set
**out_set
);
2009 anv_descriptor_set_destroy(struct anv_device
*device
,
2010 struct anv_descriptor_pool
*pool
,
2011 struct anv_descriptor_set
*set
);
2013 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2014 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2015 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2016 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2017 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2018 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2020 struct anv_pipeline_binding
{
2021 /** Index in the descriptor set
2023 * This is a flattened index; the descriptor set layout is already taken
2028 /** The descriptor set this surface corresponds to.
2030 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2031 * binding is not a normal descriptor set but something else.
2036 /** Plane in the binding index for images */
2039 /** Input attachment index (relative to the subpass) */
2040 uint8_t input_attachment_index
;
2042 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2043 uint8_t dynamic_offset_index
;
2046 /** For a storage image, whether it is write-only */
2049 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2050 * assuming POD zero-initialization.
2055 struct anv_push_range
{
2056 /** Index in the descriptor set */
2059 /** Descriptor set index */
2062 /** Dynamic offset index (for dynamic UBOs) */
2063 uint8_t dynamic_offset_index
;
2065 /** Start offset in units of 32B */
2068 /** Range in units of 32B */
2072 struct anv_pipeline_layout
{
2074 struct anv_descriptor_set_layout
*layout
;
2075 uint32_t dynamic_offset_start
;
2080 unsigned char sha1
[20];
2084 struct anv_device
* device
;
2087 VkBufferUsageFlags usage
;
2089 /* Set when bound */
2090 struct anv_address address
;
2093 static inline uint64_t
2094 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2096 assert(offset
<= buffer
->size
);
2097 if (range
== VK_WHOLE_SIZE
) {
2098 return buffer
->size
- offset
;
2100 assert(range
+ offset
>= range
);
2101 assert(range
+ offset
<= buffer
->size
);
2106 enum anv_cmd_dirty_bits
{
2107 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2108 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2109 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2110 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2111 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2112 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2113 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2114 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2115 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2116 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2117 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2118 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2119 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2120 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2122 typedef uint32_t anv_cmd_dirty_mask_t
;
2124 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2125 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2126 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2127 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2128 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2129 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2130 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2131 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2132 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2133 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2134 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2136 static inline enum anv_cmd_dirty_bits
2137 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2140 case VK_DYNAMIC_STATE_VIEWPORT
:
2141 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2142 case VK_DYNAMIC_STATE_SCISSOR
:
2143 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2144 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2145 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2146 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2147 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2148 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2149 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2150 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2151 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2152 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2153 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2154 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2155 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2156 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2157 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2158 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2159 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2161 assert(!"Unsupported dynamic state");
2167 enum anv_pipe_bits
{
2168 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2169 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2170 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2171 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2172 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2173 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2174 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2175 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2176 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2177 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2178 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2179 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2181 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2182 * a flush has happened but not a CS stall. The next time we do any sort
2183 * of invalidation we need to insert a CS stall at that time. Otherwise,
2184 * we would have to CS stall on every flush which could be bad.
2186 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2188 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2189 * target operations related to transfer commands with VkBuffer as
2190 * destination are ongoing. Some operations like copies on the command
2191 * streamer might need to be aware of this to trigger the appropriate stall
2192 * before they can proceed with the copy.
2194 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2197 #define ANV_PIPE_FLUSH_BITS ( \
2198 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2199 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2200 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2201 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2203 #define ANV_PIPE_STALL_BITS ( \
2204 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2205 ANV_PIPE_DEPTH_STALL_BIT | \
2206 ANV_PIPE_CS_STALL_BIT)
2208 #define ANV_PIPE_INVALIDATE_BITS ( \
2209 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2210 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2211 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2212 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2213 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2214 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
2216 static inline enum anv_pipe_bits
2217 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2219 enum anv_pipe_bits pipe_bits
= 0;
2222 for_each_bit(b
, flags
) {
2223 switch ((VkAccessFlagBits
)(1 << b
)) {
2224 case VK_ACCESS_SHADER_WRITE_BIT
:
2225 /* We're transitioning a buffer that was previously used as write
2226 * destination through the data port. To make its content available
2227 * to future operations, flush the data cache.
2229 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2231 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2232 /* We're transitioning a buffer that was previously used as render
2233 * target. To make its content available to future operations, flush
2234 * the render target cache.
2236 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2238 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2239 /* We're transitioning a buffer that was previously used as depth
2240 * buffer. To make its content available to future operations, flush
2243 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2245 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2246 /* We're transitioning a buffer that was previously used as a
2247 * transfer write destination. Generic write operations include color
2248 * & depth operations as well as buffer operations like :
2249 * - vkCmdClearColorImage()
2250 * - vkCmdClearDepthStencilImage()
2251 * - vkCmdBlitImage()
2252 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2254 * Most of these operations are implemented using Blorp which writes
2255 * through the render target, so flush that cache to make it visible
2256 * to future operations. And for depth related operations we also
2257 * need to flush the depth cache.
2259 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2260 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2262 case VK_ACCESS_MEMORY_WRITE_BIT
:
2263 /* We're transitioning a buffer for generic write operations. Flush
2266 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2269 break; /* Nothing to do */
2276 static inline enum anv_pipe_bits
2277 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2279 enum anv_pipe_bits pipe_bits
= 0;
2282 for_each_bit(b
, flags
) {
2283 switch ((VkAccessFlagBits
)(1 << b
)) {
2284 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2285 /* Indirect draw commands take a buffer as input that we're going to
2286 * read from the command streamer to load some of the HW registers
2287 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2288 * command streamer stall so that all the cache flushes have
2289 * completed before the command streamer loads from memory.
2291 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2292 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2293 * through a vertex buffer, so invalidate that cache.
2295 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2296 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2297 * UBO from the buffer, so we need to invalidate constant cache.
2299 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2301 case VK_ACCESS_INDEX_READ_BIT
:
2302 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2303 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2304 * commands, so we invalidate the VF cache to make sure there is no
2305 * stale data when we start rendering.
2307 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2309 case VK_ACCESS_UNIFORM_READ_BIT
:
2310 /* We transitioning a buffer to be used as uniform data. Because
2311 * uniform is accessed through the data port & sampler, we need to
2312 * invalidate the texture cache (sampler) & constant cache (data
2313 * port) to avoid stale data.
2315 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2316 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2318 case VK_ACCESS_SHADER_READ_BIT
:
2319 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2320 case VK_ACCESS_TRANSFER_READ_BIT
:
2321 /* Transitioning a buffer to be read through the sampler, so
2322 * invalidate the texture cache, we don't want any stale data.
2324 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2326 case VK_ACCESS_MEMORY_READ_BIT
:
2327 /* Transitioning a buffer for generic read, invalidate all the
2330 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2332 case VK_ACCESS_MEMORY_WRITE_BIT
:
2333 /* Generic write, make sure all previously written things land in
2336 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2338 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2339 /* Transitioning a buffer for conditional rendering. We'll load the
2340 * content of this buffer into HW registers using the command
2341 * streamer, so we need to stall the command streamer to make sure
2342 * any in-flight flush operations have completed.
2344 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2347 break; /* Nothing to do */
2354 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2355 VK_IMAGE_ASPECT_COLOR_BIT | \
2356 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2357 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2358 VK_IMAGE_ASPECT_PLANE_2_BIT)
2359 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2360 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2361 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2362 VK_IMAGE_ASPECT_PLANE_2_BIT)
2364 struct anv_vertex_binding
{
2365 struct anv_buffer
* buffer
;
2366 VkDeviceSize offset
;
2369 struct anv_xfb_binding
{
2370 struct anv_buffer
* buffer
;
2371 VkDeviceSize offset
;
2375 struct anv_push_constants
{
2376 /** Push constant data provided by the client through vkPushConstants */
2377 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2379 /** Dynamic offsets for dynamic UBOs and SSBOs */
2380 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2383 /** Base workgroup ID
2385 * Used for vkCmdDispatchBase.
2387 uint32_t base_work_group_id
[3];
2391 * This is never set by software but is implicitly filled out when
2392 * uploading the push constants for compute shaders.
2394 uint32_t subgroup_id
;
2396 /** Pad out to a multiple of 32 bytes */
2401 struct anv_dynamic_state
{
2404 VkViewport viewports
[MAX_VIEWPORTS
];
2409 VkRect2D scissors
[MAX_SCISSORS
];
2420 float blend_constants
[4];
2430 } stencil_compare_mask
;
2435 } stencil_write_mask
;
2440 } stencil_reference
;
2448 extern const struct anv_dynamic_state default_dynamic_state
;
2450 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2451 const struct anv_dynamic_state
*src
,
2452 uint32_t copy_mask
);
2454 struct anv_surface_state
{
2455 struct anv_state state
;
2456 /** Address of the surface referred to by this state
2458 * This address is relative to the start of the BO.
2460 struct anv_address address
;
2461 /* Address of the aux surface, if any
2463 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2465 * With the exception of gen8, the bottom 12 bits of this address' offset
2466 * include extra aux information.
2468 struct anv_address aux_address
;
2469 /* Address of the clear color, if any
2471 * This address is relative to the start of the BO.
2473 struct anv_address clear_address
;
2477 * Attachment state when recording a renderpass instance.
2479 * The clear value is valid only if there exists a pending clear.
2481 struct anv_attachment_state
{
2482 enum isl_aux_usage aux_usage
;
2483 enum isl_aux_usage input_aux_usage
;
2484 struct anv_surface_state color
;
2485 struct anv_surface_state input
;
2487 VkImageLayout current_layout
;
2488 VkImageLayout current_stencil_layout
;
2489 VkImageAspectFlags pending_clear_aspects
;
2490 VkImageAspectFlags pending_load_aspects
;
2492 VkClearValue clear_value
;
2493 bool clear_color_is_zero_one
;
2494 bool clear_color_is_zero
;
2496 /* When multiview is active, attachments with a renderpass clear
2497 * operation have their respective layers cleared on the first
2498 * subpass that uses them, and only in that subpass. We keep track
2499 * of this using a bitfield to indicate which layers of an attachment
2500 * have not been cleared yet when multiview is active.
2502 uint32_t pending_clear_views
;
2503 struct anv_image_view
* image_view
;
2506 /** State tracking for vertex buffer flushes
2508 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2509 * addresses. If you happen to have two vertex buffers which get placed
2510 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2511 * collisions. In order to solve this problem, we track vertex address ranges
2512 * which are live in the cache and invalidate the cache if one ever exceeds 32
2515 struct anv_vb_cache_range
{
2516 /* Virtual address at which the live vertex buffer cache range starts for
2517 * this vertex buffer index.
2521 /* Virtual address of the byte after where vertex buffer cache range ends.
2522 * This is exclusive such that end - start is the size of the range.
2527 /** State tracking for particular pipeline bind point
2529 * This struct is the base struct for anv_cmd_graphics_state and
2530 * anv_cmd_compute_state. These are used to track state which is bound to a
2531 * particular type of pipeline. Generic state that applies per-stage such as
2532 * binding table offsets and push constants is tracked generically with a
2533 * per-stage array in anv_cmd_state.
2535 struct anv_cmd_pipeline_state
{
2536 struct anv_pipeline
*pipeline
;
2538 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2539 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2542 /** State tracking for graphics pipeline
2544 * This has anv_cmd_pipeline_state as a base struct to track things which get
2545 * bound to a graphics pipeline. Along with general pipeline bind point state
2546 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2547 * state which is graphics-specific.
2549 struct anv_cmd_graphics_state
{
2550 struct anv_cmd_pipeline_state base
;
2552 anv_cmd_dirty_mask_t dirty
;
2555 struct anv_vb_cache_range ib_bound_range
;
2556 struct anv_vb_cache_range ib_dirty_range
;
2557 struct anv_vb_cache_range vb_bound_ranges
[33];
2558 struct anv_vb_cache_range vb_dirty_ranges
[33];
2560 struct anv_dynamic_state dynamic
;
2563 struct anv_buffer
*index_buffer
;
2564 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2565 uint32_t index_offset
;
2569 /** State tracking for compute pipeline
2571 * This has anv_cmd_pipeline_state as a base struct to track things which get
2572 * bound to a compute pipeline. Along with general pipeline bind point state
2573 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2574 * state which is compute-specific.
2576 struct anv_cmd_compute_state
{
2577 struct anv_cmd_pipeline_state base
;
2579 bool pipeline_dirty
;
2581 struct anv_address num_workgroups
;
2584 /** State required while building cmd buffer */
2585 struct anv_cmd_state
{
2586 /* PIPELINE_SELECT.PipelineSelection */
2587 uint32_t current_pipeline
;
2588 const struct gen_l3_config
* current_l3_config
;
2589 uint32_t last_aux_map_state
;
2591 struct anv_cmd_graphics_state gfx
;
2592 struct anv_cmd_compute_state compute
;
2594 enum anv_pipe_bits pending_pipe_bits
;
2595 VkShaderStageFlags descriptors_dirty
;
2596 VkShaderStageFlags push_constants_dirty
;
2598 struct anv_framebuffer
* framebuffer
;
2599 struct anv_render_pass
* pass
;
2600 struct anv_subpass
* subpass
;
2601 VkRect2D render_area
;
2602 uint32_t restart_index
;
2603 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2605 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2606 VkShaderStageFlags push_constant_stages
;
2607 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2608 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2609 struct anv_state samplers
[MESA_SHADER_STAGES
];
2611 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2612 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2613 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2616 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2617 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2618 * and before invoking the secondary in ExecuteCommands.
2620 bool pma_fix_enabled
;
2623 * Whether or not we know for certain that HiZ is enabled for the current
2624 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2625 * enabled or not, this will be false.
2629 bool conditional_render_enabled
;
2632 * Last rendering scale argument provided to
2633 * genX(cmd_buffer_emit_hashing_mode)().
2635 unsigned current_hash_scale
;
2638 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2639 * valid only when recording a render pass instance.
2641 struct anv_attachment_state
* attachments
;
2644 * Surface states for color render targets. These are stored in a single
2645 * flat array. For depth-stencil attachments, the surface state is simply
2648 struct anv_state render_pass_states
;
2651 * A null surface state of the right size to match the framebuffer. This
2652 * is one of the states in render_pass_states.
2654 struct anv_state null_surface_state
;
2657 struct anv_cmd_pool
{
2658 VkAllocationCallbacks alloc
;
2659 struct list_head cmd_buffers
;
2662 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2664 enum anv_cmd_buffer_exec_mode
{
2665 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2666 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2667 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2668 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2669 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2672 struct anv_cmd_buffer
{
2673 VK_LOADER_DATA _loader_data
;
2675 struct anv_device
* device
;
2677 struct anv_cmd_pool
* pool
;
2678 struct list_head pool_link
;
2680 struct anv_batch batch
;
2682 /* Fields required for the actual chain of anv_batch_bo's.
2684 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2686 struct list_head batch_bos
;
2687 enum anv_cmd_buffer_exec_mode exec_mode
;
2689 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2690 * referenced by this command buffer
2692 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2694 struct u_vector seen_bbos
;
2696 /* A vector of int32_t's for every block of binding tables.
2698 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2700 struct u_vector bt_block_states
;
2701 struct anv_state bt_next
;
2703 struct anv_reloc_list surface_relocs
;
2704 /** Last seen surface state block pool center bo offset */
2705 uint32_t last_ss_pool_center
;
2707 /* Serial for tracking buffer completion */
2710 /* Stream objects for storing temporary data */
2711 struct anv_state_stream surface_state_stream
;
2712 struct anv_state_stream dynamic_state_stream
;
2714 VkCommandBufferUsageFlags usage_flags
;
2715 VkCommandBufferLevel level
;
2717 struct anv_cmd_state state
;
2719 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2720 uint64_t intel_perf_marker
;
2723 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2724 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2725 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2726 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2727 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2728 struct anv_cmd_buffer
*secondary
);
2729 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2730 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
2731 struct anv_cmd_buffer
*cmd_buffer
,
2732 const VkSemaphore
*in_semaphores
,
2733 const uint64_t *in_wait_values
,
2734 uint32_t num_in_semaphores
,
2735 const VkSemaphore
*out_semaphores
,
2736 const uint64_t *out_signal_values
,
2737 uint32_t num_out_semaphores
,
2740 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2742 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2743 const void *data
, uint32_t size
, uint32_t alignment
);
2744 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2745 uint32_t *a
, uint32_t *b
,
2746 uint32_t dwords
, uint32_t alignment
);
2749 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2751 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2752 uint32_t entries
, uint32_t *state_offset
);
2754 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2756 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2757 uint32_t size
, uint32_t alignment
);
2760 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2762 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2763 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2764 bool depth_clamp_enable
);
2765 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2767 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2768 struct anv_render_pass
*pass
,
2769 struct anv_framebuffer
*framebuffer
,
2770 const VkClearValue
*clear_values
);
2772 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2775 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2776 gl_shader_stage stage
);
2778 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2780 const struct anv_image_view
*
2781 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2784 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2785 uint32_t num_entries
,
2786 uint32_t *state_offset
,
2787 struct anv_state
*bt_state
);
2789 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2791 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2793 enum anv_fence_type
{
2794 ANV_FENCE_TYPE_NONE
= 0,
2796 ANV_FENCE_TYPE_SYNCOBJ
,
2800 enum anv_bo_fence_state
{
2801 /** Indicates that this is a new (or newly reset fence) */
2802 ANV_BO_FENCE_STATE_RESET
,
2804 /** Indicates that this fence has been submitted to the GPU but is still
2805 * (as far as we know) in use by the GPU.
2807 ANV_BO_FENCE_STATE_SUBMITTED
,
2809 ANV_BO_FENCE_STATE_SIGNALED
,
2812 struct anv_fence_impl
{
2813 enum anv_fence_type type
;
2816 /** Fence implementation for BO fences
2818 * These fences use a BO and a set of CPU-tracked state flags. The BO
2819 * is added to the object list of the last execbuf call in a QueueSubmit
2820 * and is marked EXEC_WRITE. The state flags track when the BO has been
2821 * submitted to the kernel. We need to do this because Vulkan lets you
2822 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2823 * will say it's idle in this case.
2827 enum anv_bo_fence_state state
;
2830 /** DRM syncobj handle for syncobj-based fences */
2834 struct wsi_fence
*fence_wsi
;
2839 /* Permanent fence state. Every fence has some form of permanent state
2840 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2841 * cross-process fences) or it could just be a dummy for use internally.
2843 struct anv_fence_impl permanent
;
2845 /* Temporary fence state. A fence *may* have temporary state. That state
2846 * is added to the fence by an import operation and is reset back to
2847 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2848 * state cannot be signaled because the fence must already be signaled
2849 * before the temporary state can be exported from the fence in the other
2850 * process and imported here.
2852 struct anv_fence_impl temporary
;
2857 struct anv_state state
;
2860 enum anv_semaphore_type
{
2861 ANV_SEMAPHORE_TYPE_NONE
= 0,
2862 ANV_SEMAPHORE_TYPE_DUMMY
,
2863 ANV_SEMAPHORE_TYPE_BO
,
2864 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2865 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2866 ANV_SEMAPHORE_TYPE_TIMELINE
,
2869 struct anv_timeline_point
{
2870 struct list_head link
;
2874 /* Number of waiter on this point, when > 0 the point should not be garbage
2879 /* BO used for synchronization. */
2883 struct anv_timeline
{
2884 pthread_mutex_t mutex
;
2885 pthread_cond_t cond
;
2887 uint64_t highest_past
;
2888 uint64_t highest_pending
;
2890 struct list_head points
;
2891 struct list_head free_points
;
2894 struct anv_semaphore_impl
{
2895 enum anv_semaphore_type type
;
2898 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2899 * This BO will be added to the object list on any execbuf2 calls for
2900 * which this semaphore is used as a wait or signal fence. When used as
2901 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2905 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2906 * If the semaphore is in the unsignaled state due to either just being
2907 * created or because it has been used for a wait, fd will be -1.
2911 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2912 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2913 * import so we don't need to bother with a userspace cache.
2917 /* Non shareable timeline semaphore
2919 * Used when kernel don't have support for timeline semaphores.
2921 struct anv_timeline timeline
;
2925 struct anv_semaphore
{
2928 /* Permanent semaphore state. Every semaphore has some form of permanent
2929 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2930 * (for cross-process semaphores0 or it could just be a dummy for use
2933 struct anv_semaphore_impl permanent
;
2935 /* Temporary semaphore state. A semaphore *may* have temporary state.
2936 * That state is added to the semaphore by an import operation and is reset
2937 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2938 * semaphore with temporary state cannot be signaled because the semaphore
2939 * must already be signaled before the temporary state can be exported from
2940 * the semaphore in the other process and imported here.
2942 struct anv_semaphore_impl temporary
;
2945 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2946 struct anv_semaphore
*semaphore
);
2948 struct anv_shader_module
{
2949 unsigned char sha1
[20];
2954 static inline gl_shader_stage
2955 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
2957 assert(__builtin_popcount(vk_stage
) == 1);
2958 return ffs(vk_stage
) - 1;
2961 static inline VkShaderStageFlagBits
2962 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
2964 return (1 << mesa_stage
);
2967 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2969 #define anv_foreach_stage(stage, stage_bits) \
2970 for (gl_shader_stage stage, \
2971 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2972 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2973 __tmp &= ~(1 << (stage)))
2975 struct anv_pipeline_bind_map
{
2976 unsigned char surface_sha1
[20];
2977 unsigned char sampler_sha1
[20];
2978 unsigned char push_sha1
[20];
2980 uint32_t surface_count
;
2981 uint32_t sampler_count
;
2983 struct anv_pipeline_binding
* surface_to_descriptor
;
2984 struct anv_pipeline_binding
* sampler_to_descriptor
;
2986 struct anv_push_range push_ranges
[4];
2989 struct anv_shader_bin_key
{
2994 struct anv_shader_bin
{
2997 const struct anv_shader_bin_key
*key
;
2999 struct anv_state kernel
;
3000 uint32_t kernel_size
;
3002 struct anv_state constant_data
;
3003 uint32_t constant_data_size
;
3005 const struct brw_stage_prog_data
*prog_data
;
3006 uint32_t prog_data_size
;
3008 struct brw_compile_stats stats
[3];
3011 struct nir_xfb_info
*xfb_info
;
3013 struct anv_pipeline_bind_map bind_map
;
3016 struct anv_shader_bin
*
3017 anv_shader_bin_create(struct anv_device
*device
,
3018 const void *key
, uint32_t key_size
,
3019 const void *kernel
, uint32_t kernel_size
,
3020 const void *constant_data
, uint32_t constant_data_size
,
3021 const struct brw_stage_prog_data
*prog_data
,
3022 uint32_t prog_data_size
, const void *prog_data_param
,
3023 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
3024 const struct nir_xfb_info
*xfb_info
,
3025 const struct anv_pipeline_bind_map
*bind_map
);
3028 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3031 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3033 assert(shader
&& shader
->ref_cnt
>= 1);
3034 p_atomic_inc(&shader
->ref_cnt
);
3038 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3040 assert(shader
&& shader
->ref_cnt
>= 1);
3041 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3042 anv_shader_bin_destroy(device
, shader
);
3045 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
3046 #define MAX_PIPELINE_EXECUTABLES 7
3048 struct anv_pipeline_executable
{
3049 gl_shader_stage stage
;
3051 struct brw_compile_stats stats
;
3057 struct anv_pipeline
{
3058 struct anv_device
* device
;
3059 struct anv_batch batch
;
3060 uint32_t batch_data
[512];
3061 struct anv_reloc_list batch_relocs
;
3062 anv_cmd_dirty_mask_t dynamic_state_mask
;
3063 struct anv_dynamic_state dynamic_state
;
3067 VkPipelineCreateFlags flags
;
3068 struct anv_subpass
* subpass
;
3070 bool needs_data_cache
;
3072 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3074 uint32_t num_executables
;
3075 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
3078 const struct gen_l3_config
* l3_config
;
3079 uint32_t total_size
;
3082 VkShaderStageFlags active_stages
;
3083 struct anv_state blend_state
;
3086 struct anv_pipeline_vertex_binding
{
3089 uint32_t instance_divisor
;
3094 bool primitive_restart
;
3097 uint32_t cs_right_mask
;
3100 bool depth_test_enable
;
3101 bool writes_stencil
;
3102 bool stencil_test_enable
;
3103 bool depth_clamp_enable
;
3104 bool depth_clip_enable
;
3105 bool sample_shading_enable
;
3107 bool depth_bounds_test_enable
;
3111 uint32_t depth_stencil_state
[3];
3117 uint32_t wm_depth_stencil
[3];
3121 uint32_t wm_depth_stencil
[4];
3124 uint32_t interface_descriptor_data
[8];
3128 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
3129 gl_shader_stage stage
)
3131 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3134 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
3135 static inline const struct brw_##prefix##_prog_data * \
3136 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
3138 if (anv_pipeline_has_stage(pipeline, stage)) { \
3139 return (const struct brw_##prefix##_prog_data *) \
3140 pipeline->shaders[stage]->prog_data; \
3146 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3147 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3148 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3149 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3150 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3151 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
3153 static inline const struct brw_vue_prog_data
*
3154 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
3156 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3157 return &get_gs_prog_data(pipeline
)->base
;
3158 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3159 return &get_tes_prog_data(pipeline
)->base
;
3161 return &get_vs_prog_data(pipeline
)->base
;
3165 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
3166 struct anv_pipeline_cache
*cache
,
3167 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3168 const VkAllocationCallbacks
*alloc
);
3171 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
3172 struct anv_pipeline_cache
*cache
,
3173 const VkComputePipelineCreateInfo
*info
,
3174 const struct anv_shader_module
*module
,
3175 const char *entrypoint
,
3176 const VkSpecializationInfo
*spec_info
);
3178 struct anv_format_plane
{
3179 enum isl_format isl_format
:16;
3180 struct isl_swizzle swizzle
;
3182 /* Whether this plane contains chroma channels */
3185 /* For downscaling of YUV planes */
3186 uint8_t denominator_scales
[2];
3188 /* How to map sampled ycbcr planes to a single 4 component element. */
3189 struct isl_swizzle ycbcr_swizzle
;
3191 /* What aspect is associated to this plane */
3192 VkImageAspectFlags aspect
;
3197 struct anv_format_plane planes
[3];
3203 static inline uint32_t
3204 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3205 VkImageAspectFlags aspect_mask
)
3207 switch (aspect_mask
) {
3208 case VK_IMAGE_ASPECT_COLOR_BIT
:
3209 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3210 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3212 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3213 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3216 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3218 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3221 /* Purposefully assert with depth/stencil aspects. */
3222 unreachable("invalid image aspect");
3226 static inline VkImageAspectFlags
3227 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3230 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3231 if (util_bitcount(image_aspects
) > 1)
3232 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3233 return VK_IMAGE_ASPECT_COLOR_BIT
;
3235 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3236 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3237 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3238 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3241 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3242 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3244 const struct anv_format
*
3245 anv_get_format(VkFormat format
);
3247 static inline uint32_t
3248 anv_get_format_planes(VkFormat vk_format
)
3250 const struct anv_format
*format
= anv_get_format(vk_format
);
3252 return format
!= NULL
? format
->n_planes
: 0;
3255 struct anv_format_plane
3256 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3257 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3259 static inline enum isl_format
3260 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3261 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3263 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3266 static inline struct isl_swizzle
3267 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3269 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3270 * RGB as RGBA for texturing
3272 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3273 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3275 /* But it doesn't matter what we render to that channel */
3276 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3282 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3285 * Subsurface of an anv_image.
3287 struct anv_surface
{
3288 /** Valid only if isl_surf::size_B > 0. */
3289 struct isl_surf isl
;
3292 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3298 VkImageType type
; /**< VkImageCreateInfo::imageType */
3299 /* The original VkFormat provided by the client. This may not match any
3300 * of the actual surface formats.
3303 const struct anv_format
*format
;
3305 VkImageAspectFlags aspects
;
3308 uint32_t array_size
;
3309 uint32_t samples
; /**< VkImageCreateInfo::samples */
3311 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3312 VkImageUsageFlags stencil_usage
;
3313 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3314 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3316 /** True if this is needs to be bound to an appropriately tiled BO.
3318 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3319 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3320 * we require a dedicated allocation so that we can know to allocate a
3323 bool needs_set_tiling
;
3326 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3327 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3329 uint64_t drm_format_mod
;
3334 /* Whether the image is made of several underlying buffer objects rather a
3335 * single one with different offsets.
3339 /* All the formats that can be used when creating views of this image
3340 * are CCS_E compatible.
3342 bool ccs_e_compatible
;
3344 /* Image was created with external format. */
3345 bool external_format
;
3350 * For each foo, anv_image::planes[x].surface is valid if and only if
3351 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3352 * to figure the number associated with a given aspect.
3354 * The hardware requires that the depth buffer and stencil buffer be
3355 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3356 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3357 * allocate the depth and stencil buffers as separate surfaces in the same
3362 * -----------------------
3364 * ----------------------- |
3365 * | shadow surface0 | |
3366 * ----------------------- | Plane 0
3367 * | aux surface0 | |
3368 * ----------------------- |
3369 * | fast clear colors0 | \|/
3370 * -----------------------
3372 * ----------------------- |
3373 * | shadow surface1 | |
3374 * ----------------------- | Plane 1
3375 * | aux surface1 | |
3376 * ----------------------- |
3377 * | fast clear colors1 | \|/
3378 * -----------------------
3381 * -----------------------
3385 * Offset of the entire plane (whenever the image is disjoint this is
3393 struct anv_surface surface
;
3396 * A surface which shadows the main surface and may have different
3397 * tiling. This is used for sampling using a tiling that isn't supported
3398 * for other operations.
3400 struct anv_surface shadow_surface
;
3403 * For color images, this is the aux usage for this image when not used
3404 * as a color attachment.
3406 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
3407 * image has a HiZ buffer.
3409 enum isl_aux_usage aux_usage
;
3411 struct anv_surface aux_surface
;
3414 * Offset of the fast clear state (used to compute the
3415 * fast_clear_state_offset of the following planes).
3417 uint32_t fast_clear_state_offset
;
3420 * BO associated with this plane, set when bound.
3422 struct anv_address address
;
3425 * Address of the main surface used to fill the aux map table. This is
3426 * used at destruction of the image since the Vulkan spec does not
3427 * guarantee that the address.bo field we still be valid at destruction.
3429 uint64_t aux_map_surface_address
;
3432 * When destroying the image, also free the bo.
3438 /* The ordering of this enum is important */
3439 enum anv_fast_clear_type
{
3440 /** Image does not have/support any fast-clear blocks */
3441 ANV_FAST_CLEAR_NONE
= 0,
3442 /** Image has/supports fast-clear but only to the default value */
3443 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3444 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3445 ANV_FAST_CLEAR_ANY
= 2,
3448 /* Returns the number of auxiliary buffer levels attached to an image. */
3449 static inline uint8_t
3450 anv_image_aux_levels(const struct anv_image
* const image
,
3451 VkImageAspectFlagBits aspect
)
3453 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3455 /* The Gen12 CCS aux surface is represented with only one level. */
3456 const uint8_t aux_logical_levels
=
3457 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3458 image
->planes
[plane
].surface
.isl
.levels
:
3459 image
->planes
[plane
].aux_surface
.isl
.levels
;
3461 return image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
3462 aux_logical_levels
: 0;
3465 /* Returns the number of auxiliary buffer layers attached to an image. */
3466 static inline uint32_t
3467 anv_image_aux_layers(const struct anv_image
* const image
,
3468 VkImageAspectFlagBits aspect
,
3469 const uint8_t miplevel
)
3473 /* The miplevel must exist in the main buffer. */
3474 assert(miplevel
< image
->levels
);
3476 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3477 /* There are no layers with auxiliary data because the miplevel has no
3482 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3484 /* The Gen12 CCS aux surface is represented with only one layer. */
3485 const struct isl_extent4d
*aux_logical_level0_px
=
3486 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3487 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3488 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3490 return MAX2(aux_logical_level0_px
->array_len
,
3491 aux_logical_level0_px
->depth
>> miplevel
);
3495 static inline struct anv_address
3496 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3497 const struct anv_image
*image
,
3498 VkImageAspectFlagBits aspect
)
3500 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3502 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3503 return anv_address_add(image
->planes
[plane
].address
,
3504 image
->planes
[plane
].fast_clear_state_offset
);
3507 static inline struct anv_address
3508 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3509 const struct anv_image
*image
,
3510 VkImageAspectFlagBits aspect
)
3512 struct anv_address addr
=
3513 anv_image_get_clear_color_addr(device
, image
, aspect
);
3515 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3516 device
->isl_dev
.ss
.clear_color_state_size
:
3517 device
->isl_dev
.ss
.clear_value_size
;
3518 return anv_address_add(addr
, clear_color_state_size
);
3521 static inline struct anv_address
3522 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3523 const struct anv_image
*image
,
3524 VkImageAspectFlagBits aspect
,
3525 uint32_t level
, uint32_t array_layer
)
3527 assert(level
< anv_image_aux_levels(image
, aspect
));
3528 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3529 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3530 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3532 struct anv_address addr
=
3533 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3534 addr
.offset
+= 4; /* Go past the fast clear type */
3536 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3537 for (uint32_t l
= 0; l
< level
; l
++)
3538 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3540 addr
.offset
+= level
* image
->array_size
* 4;
3542 addr
.offset
+= array_layer
* 4;
3544 assert(addr
.offset
<
3545 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3549 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3551 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3552 const struct anv_image
*image
)
3554 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3557 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3558 * struct. There's documentation which suggests that this feature actually
3559 * reduces performance on BDW, but it has only been observed to help so
3560 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3561 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3563 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3566 return image
->samples
== 1;
3570 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3571 const struct anv_image
*image
,
3574 return device
->info
.has_aux_map
&&
3575 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3579 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3580 const struct anv_image
*image
,
3581 VkImageAspectFlagBits aspect
,
3582 enum isl_aux_usage aux_usage
,
3584 uint32_t base_layer
,
3585 uint32_t layer_count
);
3588 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3589 const struct anv_image
*image
,
3590 VkImageAspectFlagBits aspect
,
3591 enum isl_aux_usage aux_usage
,
3592 enum isl_format format
, struct isl_swizzle swizzle
,
3593 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3594 VkRect2D area
, union isl_color_value clear_color
);
3596 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3597 const struct anv_image
*image
,
3598 VkImageAspectFlags aspects
,
3599 enum isl_aux_usage depth_aux_usage
,
3601 uint32_t base_layer
, uint32_t layer_count
,
3603 float depth_value
, uint8_t stencil_value
);
3605 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3606 const struct anv_image
*src_image
,
3607 enum isl_aux_usage src_aux_usage
,
3608 uint32_t src_level
, uint32_t src_base_layer
,
3609 const struct anv_image
*dst_image
,
3610 enum isl_aux_usage dst_aux_usage
,
3611 uint32_t dst_level
, uint32_t dst_base_layer
,
3612 VkImageAspectFlagBits aspect
,
3613 uint32_t src_x
, uint32_t src_y
,
3614 uint32_t dst_x
, uint32_t dst_y
,
3615 uint32_t width
, uint32_t height
,
3616 uint32_t layer_count
,
3617 enum blorp_filter filter
);
3619 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3620 const struct anv_image
*image
,
3621 VkImageAspectFlagBits aspect
, uint32_t level
,
3622 uint32_t base_layer
, uint32_t layer_count
,
3623 enum isl_aux_op hiz_op
);
3625 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3626 const struct anv_image
*image
,
3627 VkImageAspectFlags aspects
,
3629 uint32_t base_layer
, uint32_t layer_count
,
3630 VkRect2D area
, uint8_t stencil_value
);
3632 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3633 const struct anv_image
*image
,
3634 enum isl_format format
,
3635 VkImageAspectFlagBits aspect
,
3636 uint32_t base_layer
, uint32_t layer_count
,
3637 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3640 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3641 const struct anv_image
*image
,
3642 enum isl_format format
,
3643 VkImageAspectFlagBits aspect
, uint32_t level
,
3644 uint32_t base_layer
, uint32_t layer_count
,
3645 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3649 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3650 const struct anv_image
*image
,
3651 VkImageAspectFlagBits aspect
,
3652 uint32_t base_level
, uint32_t level_count
,
3653 uint32_t base_layer
, uint32_t layer_count
);
3656 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3657 const struct anv_image
*image
,
3658 const VkImageAspectFlagBits aspect
,
3659 const VkImageLayout layout
);
3661 enum anv_fast_clear_type
3662 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3663 const struct anv_image
* const image
,
3664 const VkImageAspectFlagBits aspect
,
3665 const VkImageLayout layout
);
3667 /* This is defined as a macro so that it works for both
3668 * VkImageSubresourceRange and VkImageSubresourceLayers
3670 #define anv_get_layerCount(_image, _range) \
3671 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3672 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3674 static inline uint32_t
3675 anv_get_levelCount(const struct anv_image
*image
,
3676 const VkImageSubresourceRange
*range
)
3678 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3679 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3682 static inline VkImageAspectFlags
3683 anv_image_expand_aspects(const struct anv_image
*image
,
3684 VkImageAspectFlags aspects
)
3686 /* If the underlying image has color plane aspects and
3687 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3688 * the underlying image. */
3689 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3690 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3691 return image
->aspects
;
3697 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3698 VkImageAspectFlags aspects2
)
3700 if (aspects1
== aspects2
)
3703 /* Only 1 color aspects are compatibles. */
3704 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3705 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3706 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3712 struct anv_image_view
{
3713 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3715 VkImageAspectFlags aspect_mask
;
3717 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3721 uint32_t image_plane
;
3723 struct isl_view isl
;
3726 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3727 * image layout of SHADER_READ_ONLY_OPTIMAL or
3728 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3730 struct anv_surface_state optimal_sampler_surface_state
;
3733 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3734 * image layout of GENERAL.
3736 struct anv_surface_state general_sampler_surface_state
;
3739 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3740 * states for write-only and readable, using the real format for
3741 * write-only and the lowered format for readable.
3743 struct anv_surface_state storage_surface_state
;
3744 struct anv_surface_state writeonly_storage_surface_state
;
3746 struct brw_image_param storage_image_param
;
3750 enum anv_image_view_state_flags
{
3751 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3752 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3755 void anv_image_fill_surface_state(struct anv_device
*device
,
3756 const struct anv_image
*image
,
3757 VkImageAspectFlagBits aspect
,
3758 const struct isl_view
*view
,
3759 isl_surf_usage_flags_t view_usage
,
3760 enum isl_aux_usage aux_usage
,
3761 const union isl_color_value
*clear_color
,
3762 enum anv_image_view_state_flags flags
,
3763 struct anv_surface_state
*state_inout
,
3764 struct brw_image_param
*image_param_out
);
3766 struct anv_image_create_info
{
3767 const VkImageCreateInfo
*vk_info
;
3769 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3770 isl_tiling_flags_t isl_tiling_flags
;
3772 /** These flags will be added to any derived from VkImageCreateInfo. */
3773 isl_surf_usage_flags_t isl_extra_usage_flags
;
3776 bool external_format
;
3779 VkResult
anv_image_create(VkDevice _device
,
3780 const struct anv_image_create_info
*info
,
3781 const VkAllocationCallbacks
* alloc
,
3784 const struct anv_surface
*
3785 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3786 VkImageAspectFlags aspect_mask
);
3789 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3791 static inline struct VkExtent3D
3792 anv_sanitize_image_extent(const VkImageType imageType
,
3793 const struct VkExtent3D imageExtent
)
3795 switch (imageType
) {
3796 case VK_IMAGE_TYPE_1D
:
3797 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3798 case VK_IMAGE_TYPE_2D
:
3799 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3800 case VK_IMAGE_TYPE_3D
:
3803 unreachable("invalid image type");
3807 static inline struct VkOffset3D
3808 anv_sanitize_image_offset(const VkImageType imageType
,
3809 const struct VkOffset3D imageOffset
)
3811 switch (imageType
) {
3812 case VK_IMAGE_TYPE_1D
:
3813 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3814 case VK_IMAGE_TYPE_2D
:
3815 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3816 case VK_IMAGE_TYPE_3D
:
3819 unreachable("invalid image type");
3823 VkFormatFeatureFlags
3824 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3826 const struct anv_format
*anv_format
,
3827 VkImageTiling vk_tiling
);
3829 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3830 struct anv_state state
,
3831 enum isl_format format
,
3832 struct anv_address address
,
3833 uint32_t range
, uint32_t stride
);
3836 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3837 const struct anv_attachment_state
*att_state
,
3838 const struct anv_image_view
*iview
)
3840 const struct isl_format_layout
*view_fmtl
=
3841 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3843 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3844 if (view_fmtl->channels.c.bits) \
3845 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3847 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3848 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3849 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3850 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3852 #undef COPY_CLEAR_COLOR_CHANNEL
3856 struct anv_ycbcr_conversion
{
3857 const struct anv_format
* format
;
3858 VkSamplerYcbcrModelConversion ycbcr_model
;
3859 VkSamplerYcbcrRange ycbcr_range
;
3860 VkComponentSwizzle mapping
[4];
3861 VkChromaLocation chroma_offsets
[2];
3862 VkFilter chroma_filter
;
3863 bool chroma_reconstruction
;
3866 struct anv_sampler
{
3867 uint32_t state
[3][4];
3869 struct anv_ycbcr_conversion
*conversion
;
3871 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3872 * and with a 32-byte stride for use as bindless samplers.
3874 struct anv_state bindless_state
;
3877 struct anv_framebuffer
{
3882 uint32_t attachment_count
;
3883 struct anv_image_view
* attachments
[0];
3886 struct anv_subpass_attachment
{
3887 VkImageUsageFlagBits usage
;
3888 uint32_t attachment
;
3889 VkImageLayout layout
;
3891 /* Used only with attachment containing stencil data. */
3892 VkImageLayout stencil_layout
;
3895 struct anv_subpass
{
3896 uint32_t attachment_count
;
3899 * A pointer to all attachment references used in this subpass.
3900 * Only valid if ::attachment_count > 0.
3902 struct anv_subpass_attachment
* attachments
;
3903 uint32_t input_count
;
3904 struct anv_subpass_attachment
* input_attachments
;
3905 uint32_t color_count
;
3906 struct anv_subpass_attachment
* color_attachments
;
3907 struct anv_subpass_attachment
* resolve_attachments
;
3909 struct anv_subpass_attachment
* depth_stencil_attachment
;
3910 struct anv_subpass_attachment
* ds_resolve_attachment
;
3911 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3912 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3916 /** Subpass has a depth/stencil self-dependency */
3917 bool has_ds_self_dep
;
3919 /** Subpass has at least one color resolve attachment */
3920 bool has_color_resolve
;
3923 static inline unsigned
3924 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3926 return MAX2(1, util_bitcount(subpass
->view_mask
));
3929 struct anv_render_pass_attachment
{
3930 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3931 * its members individually.
3935 VkImageUsageFlags usage
;
3936 VkAttachmentLoadOp load_op
;
3937 VkAttachmentStoreOp store_op
;
3938 VkAttachmentLoadOp stencil_load_op
;
3939 VkImageLayout initial_layout
;
3940 VkImageLayout final_layout
;
3941 VkImageLayout first_subpass_layout
;
3943 VkImageLayout stencil_initial_layout
;
3944 VkImageLayout stencil_final_layout
;
3946 /* The subpass id in which the attachment will be used last. */
3947 uint32_t last_subpass_idx
;
3950 struct anv_render_pass
{
3951 uint32_t attachment_count
;
3952 uint32_t subpass_count
;
3953 /* An array of subpass_count+1 flushes, one per subpass boundary */
3954 enum anv_pipe_bits
* subpass_flushes
;
3955 struct anv_render_pass_attachment
* attachments
;
3956 struct anv_subpass subpasses
[0];
3959 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
3961 struct anv_query_pool
{
3963 VkQueryPipelineStatisticFlags pipeline_statistics
;
3964 /** Stride between slots, in bytes */
3966 /** Number of slots in this query pool */
3971 int anv_get_instance_entrypoint_index(const char *name
);
3972 int anv_get_device_entrypoint_index(const char *name
);
3973 int anv_get_physical_device_entrypoint_index(const char *name
);
3975 const char *anv_get_instance_entry_name(int index
);
3976 const char *anv_get_physical_device_entry_name(int index
);
3977 const char *anv_get_device_entry_name(int index
);
3980 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
3981 const struct anv_instance_extension_table
*instance
);
3983 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3984 const struct anv_instance_extension_table
*instance
);
3986 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
3987 const struct anv_instance_extension_table
*instance
,
3988 const struct anv_device_extension_table
*device
);
3990 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
3993 void anv_dump_image_to_ppm(struct anv_device
*device
,
3994 struct anv_image
*image
, unsigned miplevel
,
3995 unsigned array_layer
, VkImageAspectFlagBits aspect
,
3996 const char *filename
);
3998 enum anv_dump_action
{
3999 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
4002 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
4003 void anv_dump_finish(void);
4005 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
4007 static inline uint32_t
4008 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
4010 /* This function must be called from within a subpass. */
4011 assert(cmd_state
->pass
&& cmd_state
->subpass
);
4013 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
4015 /* The id of this subpass shouldn't exceed the number of subpasses in this
4016 * render pass minus 1.
4018 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
4022 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
4023 void anv_device_perf_init(struct anv_device
*device
);
4025 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
4027 static inline struct __anv_type * \
4028 __anv_type ## _from_handle(__VkType _handle) \
4030 return (struct __anv_type *) _handle; \
4033 static inline __VkType \
4034 __anv_type ## _to_handle(struct __anv_type *_obj) \
4036 return (__VkType) _obj; \
4039 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
4041 static inline struct __anv_type * \
4042 __anv_type ## _from_handle(__VkType _handle) \
4044 return (struct __anv_type *)(uintptr_t) _handle; \
4047 static inline __VkType \
4048 __anv_type ## _to_handle(struct __anv_type *_obj) \
4050 return (__VkType)(uintptr_t) _obj; \
4053 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4054 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
4056 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
4057 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
4058 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
4059 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
4060 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
4062 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
4063 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
4064 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
4065 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
4066 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
4067 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
4068 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
4069 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
4070 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
4071 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
4072 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
4073 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
4074 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
4075 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
4076 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
4077 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
4078 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
4079 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
4080 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
4081 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
4082 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
4083 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
4084 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
4086 /* Gen-specific function declarations */
4088 # include "anv_genX.h"
4090 # define genX(x) gen7_##x
4091 # include "anv_genX.h"
4093 # define genX(x) gen75_##x
4094 # include "anv_genX.h"
4096 # define genX(x) gen8_##x
4097 # include "anv_genX.h"
4099 # define genX(x) gen9_##x
4100 # include "anv_genX.h"
4102 # define genX(x) gen10_##x
4103 # include "anv_genX.h"
4105 # define genX(x) gen11_##x
4106 # include "anv_genX.h"
4108 # define genX(x) gen12_##x
4109 # include "anv_genX.h"
4113 #endif /* ANV_PRIVATE_H */