2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "dev/gen_device_info.h"
50 #include "blorp/blorp.h"
51 #include "compiler/brw_compiler.h"
52 #include "util/bitset.h"
53 #include "util/macros.h"
54 #include "util/hash_table.h"
55 #include "util/list.h"
56 #include "util/sparse_array.h"
57 #include "util/u_atomic.h"
58 #include "util/u_vector.h"
59 #include "util/u_math.h"
61 #include "util/xmlconfig.h"
63 #include "vk_debug_report.h"
65 /* Pre-declarations needed for WSI entrypoints */
68 typedef struct xcb_connection_t xcb_connection_t
;
69 typedef uint32_t xcb_visualid_t
;
70 typedef uint32_t xcb_window_t
;
74 struct anv_buffer_view
;
75 struct anv_image_view
;
78 struct gen_aux_map_context
;
80 struct gen_perf_config
;
82 #include <vulkan/vulkan.h>
83 #include <vulkan/vulkan_intel.h>
84 #include <vulkan/vk_icd.h>
86 #include "anv_android.h"
87 #include "anv_entrypoints.h"
88 #include "anv_extensions.h"
91 #include "dev/gen_debug.h"
92 #include "common/intel_log.h"
93 #include "wsi_common.h"
95 #define NSEC_PER_SEC 1000000000ull
97 /* anv Virtual Memory Layout
98 * =========================
100 * When the anv driver is determining the virtual graphics addresses of memory
101 * objects itself using the softpin mechanism, the following memory ranges
104 * Three special considerations to notice:
106 * (1) the dynamic state pool is located within the same 4 GiB as the low
107 * heap. This is to work around a VF cache issue described in a comment in
108 * anv_physical_device_init_heaps.
110 * (2) the binding table pool is located at lower addresses than the surface
111 * state pool, within a 4 GiB range. This allows surface state base addresses
112 * to cover both binding tables (16 bit offsets) and surface states (32 bit
115 * (3) the last 4 GiB of the address space is withheld from the high
116 * heap. Various hardware units will read past the end of an object for
117 * various reasons. This healthy margin prevents reads from wrapping around
120 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
121 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
122 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
123 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
124 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
125 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
126 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
127 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
128 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
129 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
130 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
131 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
132 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
134 #define LOW_HEAP_SIZE \
135 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
136 #define DYNAMIC_STATE_POOL_SIZE \
137 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
138 #define BINDING_TABLE_POOL_SIZE \
139 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
140 #define SURFACE_STATE_POOL_SIZE \
141 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
142 #define INSTRUCTION_STATE_POOL_SIZE \
143 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
144 #define CLIENT_VISIBLE_HEAP_SIZE \
145 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
147 /* Allowing different clear colors requires us to perform a depth resolve at
148 * the end of certain render passes. This is because while slow clears store
149 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
150 * See the PRMs for examples describing when additional resolves would be
151 * necessary. To enable fast clears without requiring extra resolves, we set
152 * the clear value to a globally-defined one. We could allow different values
153 * if the user doesn't expect coherent data during or after a render passes
154 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
155 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
156 * 1.0f seems to be the only value used. The only application that doesn't set
157 * this value does so through the usage of an seemingly uninitialized clear
160 #define ANV_HZ_FC_VAL 1.0f
163 #define MAX_XFB_BUFFERS 4
164 #define MAX_XFB_STREAMS 4
167 #define MAX_VIEWPORTS 16
168 #define MAX_SCISSORS 16
169 #define MAX_PUSH_CONSTANTS_SIZE 128
170 #define MAX_DYNAMIC_BUFFERS 16
171 #define MAX_IMAGES 64
172 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
173 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
174 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
176 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
178 * "The surface state model is used when a Binding Table Index (specified
179 * in the message descriptor) of less than 240 is specified. In this model,
180 * the Binding Table Index is used to index into the binding table, and the
181 * binding table entry contains a pointer to the SURFACE_STATE."
183 * Binding table values above 240 are used for various things in the hardware
184 * such as stateless, stateless with incoherent cache, SLM, and bindless.
186 #define MAX_BINDING_TABLE_SIZE 240
188 /* The kernel relocation API has a limitation of a 32-bit delta value
189 * applied to the address before it is written which, in spite of it being
190 * unsigned, is treated as signed . Because of the way that this maps to
191 * the Vulkan API, we cannot handle an offset into a buffer that does not
192 * fit into a signed 32 bits. The only mechanism we have for dealing with
193 * this at the moment is to limit all VkDeviceMemory objects to a maximum
194 * of 2GB each. The Vulkan spec allows us to do this:
196 * "Some platforms may have a limit on the maximum size of a single
197 * allocation. For example, certain systems may fail to create
198 * allocations with a size greater than or equal to 4GB. Such a limit is
199 * implementation-dependent, and if such a failure occurs then the error
200 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
202 * We don't use vk_error here because it's not an error so much as an
203 * indication to the application that the allocation is too large.
205 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
207 #define ANV_SVGS_VB_INDEX MAX_VBS
208 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
210 /* We reserve this MI ALU register for the purpose of handling predication.
211 * Other code which uses the MI ALU should leave it alone.
213 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
215 /* For gen12 we set the streamout buffers using 4 separate commands
216 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
217 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
218 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
219 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
220 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
221 * 3DSTATE_SO_BUFFER_INDEX_0.
223 #define SO_BUFFER_INDEX_0_CMD 0x60
224 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
226 static inline uint32_t
227 align_down_npot_u32(uint32_t v
, uint32_t a
)
232 static inline uint32_t
233 align_u32(uint32_t v
, uint32_t a
)
235 assert(a
!= 0 && a
== (a
& -a
));
236 return (v
+ a
- 1) & ~(a
- 1);
239 static inline uint64_t
240 align_down_u64(uint64_t v
, uint64_t a
)
242 assert(a
!= 0 && a
== (a
& -a
));
246 static inline uint64_t
247 align_u64(uint64_t v
, uint64_t a
)
249 return align_down_u64(v
+ a
- 1, a
);
252 static inline int32_t
253 align_i32(int32_t v
, int32_t a
)
255 assert(a
!= 0 && a
== (a
& -a
));
256 return (v
+ a
- 1) & ~(a
- 1);
259 /** Alignment must be a power of 2. */
261 anv_is_aligned(uintmax_t n
, uintmax_t a
)
263 assert(a
== (a
& -a
));
264 return (n
& (a
- 1)) == 0;
267 static inline uint32_t
268 anv_minify(uint32_t n
, uint32_t levels
)
270 if (unlikely(n
== 0))
273 return MAX2(n
>> levels
, 1);
277 anv_clamp_f(float f
, float min
, float max
)
290 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
292 if (*inout_mask
& clear_mask
) {
293 *inout_mask
&= ~clear_mask
;
300 static inline union isl_color_value
301 vk_to_isl_color(VkClearColorValue color
)
303 return (union isl_color_value
) {
313 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
315 uintptr_t mask
= (1ull << bits
) - 1;
317 return (void *) (ptr
& ~mask
);
320 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
322 uintptr_t value
= (uintptr_t) ptr
;
323 uintptr_t mask
= (1ull << bits
) - 1;
324 return value
| (mask
& flags
);
327 #define for_each_bit(b, dword) \
328 for (uint32_t __dword = (dword); \
329 (b) = __builtin_ffs(__dword) - 1, __dword; \
330 __dword &= ~(1 << (b)))
332 #define typed_memcpy(dest, src, count) ({ \
333 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
334 memcpy((dest), (src), (count) * sizeof(*(src))); \
337 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
338 * to be added here in order to utilize mapping in debug/error/perf macros.
340 #define REPORT_OBJECT_TYPE(o) \
341 __builtin_choose_expr ( \
342 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
343 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
344 __builtin_choose_expr ( \
345 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
346 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
347 __builtin_choose_expr ( \
348 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
349 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
407 __builtin_choose_expr ( \
408 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
409 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
410 __builtin_choose_expr ( \
411 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
412 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
413 __builtin_choose_expr ( \
414 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
415 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
416 __builtin_choose_expr ( \
417 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
418 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
419 __builtin_choose_expr ( \
420 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
421 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
422 __builtin_choose_expr ( \
423 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
424 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
425 __builtin_choose_expr ( \
426 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
427 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
428 __builtin_choose_expr ( \
429 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
430 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
431 __builtin_choose_expr ( \
432 __builtin_types_compatible_p (__typeof (o), void*), \
433 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
434 /* The void expression results in a compile-time error \
435 when assigning the result to something. */ \
436 (void)0)))))))))))))))))))))))))))))))
438 /* Whenever we generate an error, pass it through this function. Useful for
439 * debugging, where we can break on it. Only call at error site, not when
440 * propagating errors. Might be useful to plug in a stack trace here.
443 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
444 VkDebugReportObjectTypeEXT type
, VkResult error
,
445 const char *file
, int line
, const char *format
,
448 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
449 VkDebugReportObjectTypeEXT type
, VkResult error
,
450 const char *file
, int line
, const char *format
, ...)
451 anv_printflike(7, 8);
454 #define vk_error(error) __vk_errorf(NULL, NULL,\
455 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
456 error, __FILE__, __LINE__, NULL)
457 #define vk_errorfi(instance, obj, error, format, ...)\
458 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
459 __FILE__, __LINE__, format, ## __VA_ARGS__)
460 #define vk_errorf(device, obj, error, format, ...)\
461 vk_errorfi(anv_device_instance_or_null(device),\
462 obj, error, format, ## __VA_ARGS__)
464 #define vk_error(error) error
465 #define vk_errorfi(instance, obj, error, format, ...) error
466 #define vk_errorf(device, obj, error, format, ...) error
470 * Warn on ignored extension structs.
472 * The Vulkan spec requires us to ignore unsupported or unknown structs in
473 * a pNext chain. In debug mode, emitting warnings for ignored structs may
474 * help us discover structs that we should not have ignored.
477 * From the Vulkan 1.0.38 spec:
479 * Any component of the implementation (the loader, any enabled layers,
480 * and drivers) must skip over, without processing (other than reading the
481 * sType and pNext members) any chained structures with sType values not
482 * defined by extensions supported by that component.
484 #define anv_debug_ignored_stype(sType) \
485 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
487 void __anv_perf_warn(struct anv_device
*device
, const void *object
,
488 VkDebugReportObjectTypeEXT type
, const char *file
,
489 int line
, const char *format
, ...)
490 anv_printflike(6, 7);
491 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
492 void anv_loge_v(const char *format
, va_list va
);
495 * Print a FINISHME message, including its source location.
497 #define anv_finishme(format, ...) \
499 static bool reported = false; \
501 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
508 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
510 #define anv_perf_warn(instance, obj, format, ...) \
512 static bool reported = false; \
513 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
514 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
515 format, ##__VA_ARGS__); \
520 /* A non-fatal assert. Useful for debugging. */
522 #define anv_assert(x) ({ \
523 if (unlikely(!(x))) \
524 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
527 #define anv_assert(x)
530 /* A multi-pointer allocator
532 * When copying data structures from the user (such as a render pass), it's
533 * common to need to allocate data for a bunch of different things. Instead
534 * of doing several allocations and having to handle all of the error checking
535 * that entails, it can be easier to do a single allocation. This struct
536 * helps facilitate that. The intended usage looks like this:
539 * anv_multialloc_add(&ma, &main_ptr, 1);
540 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
541 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
543 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
544 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
546 struct anv_multialloc
{
554 #define ANV_MULTIALLOC_INIT \
555 ((struct anv_multialloc) { 0, })
557 #define ANV_MULTIALLOC(_name) \
558 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
560 __attribute__((always_inline
))
562 _anv_multialloc_add(struct anv_multialloc
*ma
,
563 void **ptr
, size_t size
, size_t align
)
565 size_t offset
= align_u64(ma
->size
, align
);
566 ma
->size
= offset
+ size
;
567 ma
->align
= MAX2(ma
->align
, align
);
569 /* Store the offset in the pointer. */
570 *ptr
= (void *)(uintptr_t)offset
;
572 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
573 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
576 #define anv_multialloc_add_size(_ma, _ptr, _size) \
577 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
579 #define anv_multialloc_add(_ma, _ptr, _count) \
580 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
582 __attribute__((always_inline
))
584 anv_multialloc_alloc(struct anv_multialloc
*ma
,
585 const VkAllocationCallbacks
*alloc
,
586 VkSystemAllocationScope scope
)
588 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
592 /* Fill out each of the pointers with their final value.
594 * for (uint32_t i = 0; i < ma->ptr_count; i++)
595 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
597 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
598 * constant, GCC is incapable of figuring this out and unrolling the loop
599 * so we have to give it a little help.
601 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
602 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
603 if ((_i) < ma->ptr_count) \
604 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
605 _ANV_MULTIALLOC_UPDATE_POINTER(0);
606 _ANV_MULTIALLOC_UPDATE_POINTER(1);
607 _ANV_MULTIALLOC_UPDATE_POINTER(2);
608 _ANV_MULTIALLOC_UPDATE_POINTER(3);
609 _ANV_MULTIALLOC_UPDATE_POINTER(4);
610 _ANV_MULTIALLOC_UPDATE_POINTER(5);
611 _ANV_MULTIALLOC_UPDATE_POINTER(6);
612 _ANV_MULTIALLOC_UPDATE_POINTER(7);
613 #undef _ANV_MULTIALLOC_UPDATE_POINTER
618 __attribute__((always_inline
))
620 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
621 const VkAllocationCallbacks
*parent_alloc
,
622 const VkAllocationCallbacks
*alloc
,
623 VkSystemAllocationScope scope
)
625 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
633 /* Index into the current validation list. This is used by the
634 * validation list building alrogithm to track which buffers are already
635 * in the validation list so that we can ensure uniqueness.
639 /* Index for use with util_sparse_array_free_list */
642 /* Last known offset. This value is provided by the kernel when we
643 * execbuf and is used as the presumed offset for the next bunch of
650 /* Map for internally mapped BOs.
652 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
656 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
659 /** True if this BO may be shared with other processes */
662 /** True if this BO is a wrapper
664 * When set to true, none of the fields in this BO are meaningful except
665 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
666 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
667 * is set in the physical device.
671 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
672 bool has_fixed_address
:1;
674 /** True if this BO wraps a host pointer */
675 bool from_host_ptr
:1;
677 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
678 bool has_client_visible_address
:1;
681 static inline struct anv_bo
*
682 anv_bo_ref(struct anv_bo
*bo
)
684 p_atomic_inc(&bo
->refcount
);
688 static inline struct anv_bo
*
689 anv_bo_unwrap(struct anv_bo
*bo
)
691 while (bo
->is_wrapper
)
696 /* Represents a lock-free linked list of "free" things. This is used by
697 * both the block pool and the state pools. Unfortunately, in order to
698 * solve the ABA problem, we can't use a single uint32_t head.
700 union anv_free_list
{
704 /* A simple count that is incremented every time the head changes. */
707 /* Make sure it's aligned to 64 bits. This will make atomic operations
708 * faster on 32 bit platforms.
710 uint64_t u64
__attribute__ ((aligned (8)));
713 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
715 struct anv_block_state
{
721 /* Make sure it's aligned to 64 bits. This will make atomic operations
722 * faster on 32 bit platforms.
724 uint64_t u64
__attribute__ ((aligned (8)));
728 #define anv_block_pool_foreach_bo(bo, pool) \
729 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
730 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
733 #define ANV_MAX_BLOCK_POOL_BOS 20
735 struct anv_block_pool
{
736 struct anv_device
*device
;
739 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
740 * around the actual BO so that we grow the pool after the wrapper BO has
741 * been put in a relocation list. This is only used in the non-softpin
744 struct anv_bo wrapper_bo
;
746 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
752 /* The address where the start of the pool is pinned. The various bos that
753 * are created as the pool grows will have addresses in the range
754 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
756 uint64_t start_address
;
758 /* The offset from the start of the bo to the "center" of the block
759 * pool. Pointers to allocated blocks are given by
760 * bo.map + center_bo_offset + offsets.
762 uint32_t center_bo_offset
;
764 /* Current memory map of the block pool. This pointer may or may not
765 * point to the actual beginning of the block pool memory. If
766 * anv_block_pool_alloc_back has ever been called, then this pointer
767 * will point to the "center" position of the buffer and all offsets
768 * (negative or positive) given out by the block pool alloc functions
769 * will be valid relative to this pointer.
771 * In particular, map == bo.map + center_offset
773 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
774 * since it will handle the softpin case as well, where this points to NULL.
780 * Array of mmaps and gem handles owned by the block pool, reclaimed when
781 * the block pool is destroyed.
783 struct u_vector mmap_cleanups
;
785 struct anv_block_state state
;
787 struct anv_block_state back_state
;
790 /* Block pools are backed by a fixed-size 1GB memfd */
791 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
793 /* The center of the block pool is also the middle of the memfd. This may
794 * change in the future if we decide differently for some reason.
796 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
798 static inline uint32_t
799 anv_block_pool_size(struct anv_block_pool
*pool
)
801 return pool
->state
.end
+ pool
->back_state
.end
;
811 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
813 struct anv_fixed_size_state_pool
{
814 union anv_free_list free_list
;
815 struct anv_block_state block
;
818 #define ANV_MIN_STATE_SIZE_LOG2 6
819 #define ANV_MAX_STATE_SIZE_LOG2 21
821 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
823 struct anv_free_entry
{
825 struct anv_state state
;
828 struct anv_state_table
{
829 struct anv_device
*device
;
831 struct anv_free_entry
*map
;
833 struct anv_block_state state
;
834 struct u_vector cleanups
;
837 struct anv_state_pool
{
838 struct anv_block_pool block_pool
;
840 struct anv_state_table table
;
842 /* The size of blocks which will be allocated from the block pool */
845 /** Free list for "back" allocations */
846 union anv_free_list back_alloc_free_list
;
848 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
851 struct anv_state_stream_block
;
853 struct anv_state_stream
{
854 struct anv_state_pool
*state_pool
;
856 /* The size of blocks to allocate from the state pool */
859 /* Current block we're allocating from */
860 struct anv_state block
;
862 /* Offset into the current block at which to allocate the next state */
865 /* List of all blocks allocated from this pool */
866 struct anv_state_stream_block
*block_list
;
869 /* The block_pool functions exported for testing only. The block pool should
870 * only be used via a state pool (see below).
872 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
873 struct anv_device
*device
,
874 uint64_t start_address
,
875 uint32_t initial_size
);
876 void anv_block_pool_finish(struct anv_block_pool
*pool
);
877 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
878 uint32_t block_size
, uint32_t *padding
);
879 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
880 uint32_t block_size
);
881 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
);
883 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
884 struct anv_device
*device
,
885 uint64_t start_address
,
886 uint32_t block_size
);
887 void anv_state_pool_finish(struct anv_state_pool
*pool
);
888 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
889 uint32_t state_size
, uint32_t alignment
);
890 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
891 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
892 void anv_state_stream_init(struct anv_state_stream
*stream
,
893 struct anv_state_pool
*state_pool
,
894 uint32_t block_size
);
895 void anv_state_stream_finish(struct anv_state_stream
*stream
);
896 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
897 uint32_t size
, uint32_t alignment
);
899 VkResult
anv_state_table_init(struct anv_state_table
*table
,
900 struct anv_device
*device
,
901 uint32_t initial_entries
);
902 void anv_state_table_finish(struct anv_state_table
*table
);
903 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
905 void anv_free_list_push(union anv_free_list
*list
,
906 struct anv_state_table
*table
,
907 uint32_t idx
, uint32_t count
);
908 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
909 struct anv_state_table
*table
);
912 static inline struct anv_state
*
913 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
915 return &table
->map
[idx
].state
;
918 * Implements a pool of re-usable BOs. The interface is identical to that
919 * of block_pool except that each block is its own BO.
922 struct anv_device
*device
;
924 struct util_sparse_array_free_list free_list
[16];
927 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
928 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
929 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
930 struct anv_bo
**bo_out
);
931 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
933 struct anv_scratch_pool
{
934 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
935 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
938 void anv_scratch_pool_init(struct anv_device
*device
,
939 struct anv_scratch_pool
*pool
);
940 void anv_scratch_pool_finish(struct anv_device
*device
,
941 struct anv_scratch_pool
*pool
);
942 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
943 struct anv_scratch_pool
*pool
,
944 gl_shader_stage stage
,
945 unsigned per_thread_scratch
);
947 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
948 struct anv_bo_cache
{
949 struct util_sparse_array bo_map
;
950 pthread_mutex_t mutex
;
953 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
954 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
956 struct anv_memory_type
{
957 /* Standard bits passed on to the client */
958 VkMemoryPropertyFlags propertyFlags
;
962 struct anv_memory_heap
{
963 /* Standard bits passed on to the client */
965 VkMemoryHeapFlags flags
;
967 /* Driver-internal book-keeping */
971 struct anv_physical_device
{
972 VK_LOADER_DATA _loader_data
;
974 /* Link in anv_instance::physical_devices */
975 struct list_head link
;
977 struct anv_instance
* instance
;
987 struct gen_device_info info
;
988 /** Amount of "GPU memory" we want to advertise
990 * Clearly, this value is bogus since Intel is a UMA architecture. On
991 * gen7 platforms, we are limited by GTT size unless we want to implement
992 * fine-grained tracking and GTT splitting. On Broadwell and above we are
993 * practically unlimited. However, we will never report more than 3/4 of
994 * the total system ram to try and avoid running out of RAM.
996 bool supports_48bit_addresses
;
997 struct brw_compiler
* compiler
;
998 struct isl_device isl_dev
;
999 struct gen_perf_config
* perf
;
1000 int cmd_parser_version
;
1002 bool has_exec_async
;
1003 bool has_exec_capture
;
1004 bool has_exec_fence
;
1006 bool has_syncobj_wait
;
1007 bool has_context_priority
;
1008 bool has_context_isolation
;
1009 bool has_mem_available
;
1013 bool always_use_bindless
;
1015 /** True if we can access buffers using A64 messages */
1016 bool has_a64_buffer_access
;
1017 /** True if we can use bindless access for images */
1018 bool has_bindless_images
;
1019 /** True if we can use bindless access for samplers */
1020 bool has_bindless_samplers
;
1022 bool always_flush_cache
;
1024 struct anv_device_extension_table supported_extensions
;
1027 uint32_t subslice_total
;
1030 uint32_t type_count
;
1031 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1032 uint32_t heap_count
;
1033 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1036 uint8_t driver_build_sha1
[20];
1037 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1038 uint8_t driver_uuid
[VK_UUID_SIZE
];
1039 uint8_t device_uuid
[VK_UUID_SIZE
];
1041 struct disk_cache
* disk_cache
;
1043 struct wsi_device wsi_device
;
1048 struct anv_app_info
{
1049 const char* app_name
;
1050 uint32_t app_version
;
1051 const char* engine_name
;
1052 uint32_t engine_version
;
1053 uint32_t api_version
;
1056 struct anv_instance
{
1057 VK_LOADER_DATA _loader_data
;
1059 VkAllocationCallbacks alloc
;
1061 struct anv_app_info app_info
;
1063 struct anv_instance_extension_table enabled_extensions
;
1064 struct anv_instance_dispatch_table dispatch
;
1065 struct anv_physical_device_dispatch_table physical_device_dispatch
;
1066 struct anv_device_dispatch_table device_dispatch
;
1068 bool physical_devices_enumerated
;
1069 struct list_head physical_devices
;
1071 bool pipeline_cache_enabled
;
1073 struct vk_debug_report_instance debug_report_callbacks
;
1075 struct driOptionCache dri_options
;
1076 struct driOptionCache available_dri_options
;
1079 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1080 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1082 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1083 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1086 struct anv_queue_submit
{
1087 struct anv_cmd_buffer
* cmd_buffer
;
1089 uint32_t fence_count
;
1090 uint32_t fence_array_length
;
1091 struct drm_i915_gem_exec_fence
* fences
;
1093 uint32_t temporary_semaphore_count
;
1094 uint32_t temporary_semaphore_array_length
;
1095 struct anv_semaphore_impl
* temporary_semaphores
;
1097 /* Semaphores to be signaled with a SYNC_FD. */
1098 struct anv_semaphore
** sync_fd_semaphores
;
1099 uint32_t sync_fd_semaphore_count
;
1100 uint32_t sync_fd_semaphore_array_length
;
1102 /* Allocated only with non shareable timelines. */
1103 struct anv_timeline
** wait_timelines
;
1104 uint32_t wait_timeline_count
;
1105 uint32_t wait_timeline_array_length
;
1106 uint64_t * wait_timeline_values
;
1108 struct anv_timeline
** signal_timelines
;
1109 uint32_t signal_timeline_count
;
1110 uint32_t signal_timeline_array_length
;
1111 uint64_t * signal_timeline_values
;
1114 bool need_out_fence
;
1117 uint32_t fence_bo_count
;
1118 uint32_t fence_bo_array_length
;
1119 /* An array of struct anv_bo pointers with lower bit used as a flag to
1120 * signal we will wait on that BO (see anv_(un)pack_ptr).
1122 uintptr_t * fence_bos
;
1124 const VkAllocationCallbacks
* alloc
;
1125 VkSystemAllocationScope alloc_scope
;
1127 struct anv_bo
* simple_bo
;
1128 uint32_t simple_bo_size
;
1130 struct list_head link
;
1134 VK_LOADER_DATA _loader_data
;
1136 struct anv_device
* device
;
1139 * A list of struct anv_queue_submit to be submitted to i915.
1141 struct list_head queued_submits
;
1143 VkDeviceQueueCreateFlags flags
;
1146 struct anv_pipeline_cache
{
1147 struct anv_device
* device
;
1148 pthread_mutex_t mutex
;
1150 struct hash_table
* nir_cache
;
1152 struct hash_table
* cache
;
1155 struct nir_xfb_info
;
1156 struct anv_pipeline_bind_map
;
1158 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1159 struct anv_device
*device
,
1160 bool cache_enabled
);
1161 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1163 struct anv_shader_bin
*
1164 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1165 const void *key
, uint32_t key_size
);
1166 struct anv_shader_bin
*
1167 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1168 const void *key_data
, uint32_t key_size
,
1169 const void *kernel_data
, uint32_t kernel_size
,
1170 const void *constant_data
,
1171 uint32_t constant_data_size
,
1172 const struct brw_stage_prog_data
*prog_data
,
1173 uint32_t prog_data_size
,
1174 const struct brw_compile_stats
*stats
,
1176 const struct nir_xfb_info
*xfb_info
,
1177 const struct anv_pipeline_bind_map
*bind_map
);
1179 struct anv_shader_bin
*
1180 anv_device_search_for_kernel(struct anv_device
*device
,
1181 struct anv_pipeline_cache
*cache
,
1182 const void *key_data
, uint32_t key_size
,
1183 bool *user_cache_bit
);
1185 struct anv_shader_bin
*
1186 anv_device_upload_kernel(struct anv_device
*device
,
1187 struct anv_pipeline_cache
*cache
,
1188 const void *key_data
, uint32_t key_size
,
1189 const void *kernel_data
, uint32_t kernel_size
,
1190 const void *constant_data
,
1191 uint32_t constant_data_size
,
1192 const struct brw_stage_prog_data
*prog_data
,
1193 uint32_t prog_data_size
,
1194 const struct brw_compile_stats
*stats
,
1196 const struct nir_xfb_info
*xfb_info
,
1197 const struct anv_pipeline_bind_map
*bind_map
);
1200 struct nir_shader_compiler_options
;
1203 anv_device_search_for_nir(struct anv_device
*device
,
1204 struct anv_pipeline_cache
*cache
,
1205 const struct nir_shader_compiler_options
*nir_options
,
1206 unsigned char sha1_key
[20],
1210 anv_device_upload_nir(struct anv_device
*device
,
1211 struct anv_pipeline_cache
*cache
,
1212 const struct nir_shader
*nir
,
1213 unsigned char sha1_key
[20]);
1216 VK_LOADER_DATA _loader_data
;
1218 VkAllocationCallbacks alloc
;
1220 struct anv_physical_device
* physical
;
1222 struct gen_device_info info
;
1223 struct isl_device isl_dev
;
1226 bool can_chain_batches
;
1227 bool robust_buffer_access
;
1228 struct anv_device_extension_table enabled_extensions
;
1229 struct anv_device_dispatch_table dispatch
;
1231 pthread_mutex_t vma_mutex
;
1232 struct util_vma_heap vma_lo
;
1233 struct util_vma_heap vma_cva
;
1234 struct util_vma_heap vma_hi
;
1236 /** List of all anv_device_memory objects */
1237 struct list_head memory_objects
;
1239 struct anv_bo_pool batch_bo_pool
;
1241 struct anv_bo_cache bo_cache
;
1243 struct anv_state_pool dynamic_state_pool
;
1244 struct anv_state_pool instruction_state_pool
;
1245 struct anv_state_pool binding_table_pool
;
1246 struct anv_state_pool surface_state_pool
;
1248 struct anv_bo
* workaround_bo
;
1249 struct anv_bo
* trivial_batch_bo
;
1250 struct anv_bo
* hiz_clear_bo
;
1252 struct anv_pipeline_cache default_pipeline_cache
;
1253 struct blorp_context blorp
;
1255 struct anv_state border_colors
;
1257 struct anv_state slice_hash
;
1259 struct anv_queue queue
;
1261 struct anv_scratch_pool scratch_pool
;
1263 pthread_mutex_t mutex
;
1264 pthread_cond_t queue_submit
;
1267 struct gen_batch_decode_ctx decoder_ctx
;
1269 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1270 * the cmd_buffer's list.
1272 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1274 int perf_fd
; /* -1 if no opened */
1275 uint64_t perf_metric
; /* 0 if unset */
1277 struct gen_aux_map_context
*aux_map_ctx
;
1280 static inline struct anv_instance
*
1281 anv_device_instance_or_null(const struct anv_device
*device
)
1283 return device
? device
->physical
->instance
: NULL
;
1286 static inline struct anv_state_pool
*
1287 anv_binding_table_pool(struct anv_device
*device
)
1289 if (device
->physical
->use_softpin
)
1290 return &device
->binding_table_pool
;
1292 return &device
->surface_state_pool
;
1295 static inline struct anv_state
1296 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1297 if (device
->physical
->use_softpin
)
1298 return anv_state_pool_alloc(&device
->binding_table_pool
,
1299 device
->binding_table_pool
.block_size
, 0);
1301 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1305 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1306 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1309 static inline uint32_t
1310 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1312 if (bo
->is_external
)
1313 return device
->isl_dev
.mocs
.external
;
1315 return device
->isl_dev
.mocs
.internal
;
1318 void anv_device_init_blorp(struct anv_device
*device
);
1319 void anv_device_finish_blorp(struct anv_device
*device
);
1321 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1322 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1323 const char *file
, int line
,
1324 const char *msg
, ...)
1325 anv_printflike(4, 5);
1326 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1327 const char *file
, int line
,
1328 const char *msg
, ...)
1329 anv_printflike(4, 5);
1330 #define anv_device_set_lost(dev, ...) \
1331 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1332 #define anv_queue_set_lost(queue, ...) \
1333 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1336 anv_device_is_lost(struct anv_device
*device
)
1338 return unlikely(p_atomic_read(&device
->_lost
));
1341 VkResult
anv_device_query_status(struct anv_device
*device
);
1344 enum anv_bo_alloc_flags
{
1345 /** Specifies that the BO must have a 32-bit address
1347 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1349 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1351 /** Specifies that the BO may be shared externally */
1352 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1354 /** Specifies that the BO should be mapped */
1355 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1357 /** Specifies that the BO should be snooped so we get coherency */
1358 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1360 /** Specifies that the BO should be captured in error states */
1361 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1363 /** Specifies that the BO will have an address assigned by the caller
1365 * Such BOs do not exist in any VMA heap.
1367 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1369 /** Enables implicit synchronization on the BO
1371 * This is the opposite of EXEC_OBJECT_ASYNC.
1373 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1375 /** Enables implicit synchronization on the BO
1377 * This is equivalent to EXEC_OBJECT_WRITE.
1379 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1381 /** Has an address which is visible to the client */
1382 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS
= (1 << 8),
1385 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1386 enum anv_bo_alloc_flags alloc_flags
,
1387 uint64_t explicit_address
,
1388 struct anv_bo
**bo
);
1389 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1390 void *host_ptr
, uint32_t size
,
1391 enum anv_bo_alloc_flags alloc_flags
,
1392 uint64_t client_address
,
1393 struct anv_bo
**bo_out
);
1394 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1395 enum anv_bo_alloc_flags alloc_flags
,
1396 uint64_t client_address
,
1397 struct anv_bo
**bo
);
1398 VkResult
anv_device_export_bo(struct anv_device
*device
,
1399 struct anv_bo
*bo
, int *fd_out
);
1400 void anv_device_release_bo(struct anv_device
*device
,
1403 static inline struct anv_bo
*
1404 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1406 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1409 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1410 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1413 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1414 void anv_queue_finish(struct anv_queue
*queue
);
1416 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1417 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1418 struct anv_batch
*batch
);
1420 uint64_t anv_gettime_ns(void);
1421 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1423 void* anv_gem_mmap(struct anv_device
*device
,
1424 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1425 void anv_gem_munmap(void *p
, uint64_t size
);
1426 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1427 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1428 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1429 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1430 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1431 int anv_gem_execbuffer(struct anv_device
*device
,
1432 struct drm_i915_gem_execbuffer2
*execbuf
);
1433 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1434 uint32_t stride
, uint32_t tiling
);
1435 int anv_gem_create_context(struct anv_device
*device
);
1436 bool anv_gem_has_context_priority(int fd
);
1437 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1438 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1440 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1442 int anv_gem_get_param(int fd
, uint32_t param
);
1443 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1444 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1445 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1446 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1447 uint32_t *active
, uint32_t *pending
);
1448 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1449 int anv_gem_reg_read(struct anv_device
*device
,
1450 uint32_t offset
, uint64_t *result
);
1451 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1452 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1453 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1454 uint32_t read_domains
, uint32_t write_domain
);
1455 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1456 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1457 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1458 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1459 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1460 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1462 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1463 uint32_t handle
, int fd
);
1464 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1465 bool anv_gem_supports_syncobj_wait(int fd
);
1466 int anv_gem_syncobj_wait(struct anv_device
*device
,
1467 uint32_t *handles
, uint32_t num_handles
,
1468 int64_t abs_timeout_ns
, bool wait_all
);
1470 uint64_t anv_vma_alloc(struct anv_device
*device
,
1471 uint64_t size
, uint64_t align
,
1472 enum anv_bo_alloc_flags alloc_flags
,
1473 uint64_t client_address
);
1474 void anv_vma_free(struct anv_device
*device
,
1475 uint64_t address
, uint64_t size
);
1477 struct anv_reloc_list
{
1478 uint32_t num_relocs
;
1479 uint32_t array_length
;
1480 struct drm_i915_gem_relocation_entry
* relocs
;
1481 struct anv_bo
** reloc_bos
;
1486 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1487 const VkAllocationCallbacks
*alloc
);
1488 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1489 const VkAllocationCallbacks
*alloc
);
1491 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1492 const VkAllocationCallbacks
*alloc
,
1493 uint32_t offset
, struct anv_bo
*target_bo
,
1494 uint32_t delta
, uint64_t *address_u64_out
);
1496 struct anv_batch_bo
{
1497 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1498 struct list_head link
;
1502 /* Bytes actually consumed in this batch BO */
1505 struct anv_reloc_list relocs
;
1509 const VkAllocationCallbacks
* alloc
;
1515 struct anv_reloc_list
* relocs
;
1517 /* This callback is called (with the associated user data) in the event
1518 * that the batch runs out of space.
1520 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1524 * Current error status of the command buffer. Used to track inconsistent
1525 * or incomplete command buffer states that are the consequence of run-time
1526 * errors such as out of memory scenarios. We want to track this in the
1527 * batch because the command buffer object is not visible to some parts
1533 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1534 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1535 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1536 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1538 static inline VkResult
1539 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1541 assert(error
!= VK_SUCCESS
);
1542 if (batch
->status
== VK_SUCCESS
)
1543 batch
->status
= error
;
1544 return batch
->status
;
1548 anv_batch_has_error(struct anv_batch
*batch
)
1550 return batch
->status
!= VK_SUCCESS
;
1553 struct anv_address
{
1558 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1561 anv_address_is_null(struct anv_address addr
)
1563 return addr
.bo
== NULL
&& addr
.offset
== 0;
1566 static inline uint64_t
1567 anv_address_physical(struct anv_address addr
)
1569 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1570 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1572 return gen_canonical_address(addr
.offset
);
1575 static inline struct anv_address
1576 anv_address_add(struct anv_address addr
, uint64_t offset
)
1578 addr
.offset
+= offset
;
1583 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1585 unsigned reloc_size
= 0;
1586 if (device
->info
.gen
>= 8) {
1587 reloc_size
= sizeof(uint64_t);
1588 *(uint64_t *)p
= gen_canonical_address(v
);
1590 reloc_size
= sizeof(uint32_t);
1594 if (flush
&& !device
->info
.has_llc
)
1595 gen_flush_range(p
, reloc_size
);
1598 static inline uint64_t
1599 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1600 const struct anv_address address
, uint32_t delta
)
1602 if (address
.bo
== NULL
) {
1603 return address
.offset
+ delta
;
1605 assert(batch
->start
<= location
&& location
< batch
->end
);
1607 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1611 #define __gen_address_type struct anv_address
1612 #define __gen_user_data struct anv_batch
1613 #define __gen_combine_address _anv_combine_address
1615 /* Wrapper macros needed to work around preprocessor argument issues. In
1616 * particular, arguments don't get pre-evaluated if they are concatenated.
1617 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1618 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1619 * We can work around this easily enough with these helpers.
1621 #define __anv_cmd_length(cmd) cmd ## _length
1622 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1623 #define __anv_cmd_header(cmd) cmd ## _header
1624 #define __anv_cmd_pack(cmd) cmd ## _pack
1625 #define __anv_reg_num(reg) reg ## _num
1627 #define anv_pack_struct(dst, struc, ...) do { \
1628 struct struc __template = { \
1631 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1632 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1635 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1636 void *__dst = anv_batch_emit_dwords(batch, n); \
1638 struct cmd __template = { \
1639 __anv_cmd_header(cmd), \
1640 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1643 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1648 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1652 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1653 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1656 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1657 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1658 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1661 #define anv_batch_emit(batch, cmd, name) \
1662 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1663 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1664 __builtin_expect(_dst != NULL, 1); \
1665 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1666 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1670 struct anv_device_memory
{
1671 struct list_head link
;
1674 struct anv_memory_type
* type
;
1675 VkDeviceSize map_size
;
1678 /* If set, we are holding reference to AHardwareBuffer
1679 * which we must release when memory is freed.
1681 struct AHardwareBuffer
* ahw
;
1683 /* If set, this memory comes from a host pointer. */
1688 * Header for Vertex URB Entry (VUE)
1690 struct anv_vue_header
{
1692 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1693 uint32_t ViewportIndex
;
1697 /** Struct representing a sampled image descriptor
1699 * This descriptor layout is used for sampled images, bare sampler, and
1700 * combined image/sampler descriptors.
1702 struct anv_sampled_image_descriptor
{
1703 /** Bindless image handle
1705 * This is expected to already be shifted such that the 20-bit
1706 * SURFACE_STATE table index is in the top 20 bits.
1710 /** Bindless sampler handle
1712 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1713 * to the dynamic state base address.
1718 struct anv_texture_swizzle_descriptor
{
1721 * See also nir_intrinsic_channel_select_intel
1725 /** Unused padding to ensure the struct is a multiple of 64 bits */
1729 /** Struct representing a storage image descriptor */
1730 struct anv_storage_image_descriptor
{
1731 /** Bindless image handles
1733 * These are expected to already be shifted such that the 20-bit
1734 * SURFACE_STATE table index is in the top 20 bits.
1736 uint32_t read_write
;
1737 uint32_t write_only
;
1740 /** Struct representing a address/range descriptor
1742 * The fields of this struct correspond directly to the data layout of
1743 * nir_address_format_64bit_bounded_global addresses. The last field is the
1744 * offset in the NIR address so it must be zero so that when you load the
1745 * descriptor you get a pointer to the start of the range.
1747 struct anv_address_range_descriptor
{
1753 enum anv_descriptor_data
{
1754 /** The descriptor contains a BTI reference to a surface state */
1755 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1756 /** The descriptor contains a BTI reference to a sampler state */
1757 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1758 /** The descriptor contains an actual buffer view */
1759 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1760 /** The descriptor contains auxiliary image layout data */
1761 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1762 /** The descriptor contains auxiliary image layout data */
1763 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1764 /** anv_address_range_descriptor with a buffer address and range */
1765 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1766 /** Bindless surface handle */
1767 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1768 /** Storage image handles */
1769 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1770 /** Storage image handles */
1771 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1774 struct anv_descriptor_set_binding_layout
{
1776 /* The type of the descriptors in this binding */
1777 VkDescriptorType type
;
1780 /* Flags provided when this binding was created */
1781 VkDescriptorBindingFlagsEXT flags
;
1783 /* Bitfield representing the type of data this descriptor contains */
1784 enum anv_descriptor_data data
;
1786 /* Maximum number of YCbCr texture/sampler planes */
1787 uint8_t max_plane_count
;
1789 /* Number of array elements in this binding (or size in bytes for inline
1792 uint16_t array_size
;
1794 /* Index into the flattend descriptor set */
1795 uint16_t descriptor_index
;
1797 /* Index into the dynamic state array for a dynamic buffer */
1798 int16_t dynamic_offset_index
;
1800 /* Index into the descriptor set buffer views */
1801 int16_t buffer_view_index
;
1803 /* Offset into the descriptor buffer where this descriptor lives */
1804 uint32_t descriptor_offset
;
1806 /* Immutable samplers (or NULL if no immutable samplers) */
1807 struct anv_sampler
**immutable_samplers
;
1810 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1812 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1813 VkDescriptorType type
);
1815 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1816 const struct anv_descriptor_set_binding_layout
*binding
,
1819 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1820 const struct anv_descriptor_set_binding_layout
*binding
,
1823 struct anv_descriptor_set_layout
{
1824 /* Descriptor set layouts can be destroyed at almost any time */
1827 /* Number of bindings in this descriptor set */
1828 uint16_t binding_count
;
1830 /* Total size of the descriptor set with room for all array entries */
1833 /* Shader stages affected by this descriptor set */
1834 uint16_t shader_stages
;
1836 /* Number of buffer views in this descriptor set */
1837 uint16_t buffer_view_count
;
1839 /* Number of dynamic offsets used by this descriptor set */
1840 uint16_t dynamic_offset_count
;
1842 /* For each shader stage, which offsets apply to that stage */
1843 uint16_t stage_dynamic_offsets
[MESA_SHADER_STAGES
];
1845 /* Size of the descriptor buffer for this descriptor set */
1846 uint32_t descriptor_buffer_size
;
1848 /* Bindings in this descriptor set */
1849 struct anv_descriptor_set_binding_layout binding
[0];
1853 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1855 assert(layout
&& layout
->ref_cnt
>= 1);
1856 p_atomic_inc(&layout
->ref_cnt
);
1860 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1861 struct anv_descriptor_set_layout
*layout
)
1863 assert(layout
&& layout
->ref_cnt
>= 1);
1864 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1865 vk_free(&device
->alloc
, layout
);
1868 struct anv_descriptor
{
1869 VkDescriptorType type
;
1873 VkImageLayout layout
;
1874 struct anv_image_view
*image_view
;
1875 struct anv_sampler
*sampler
;
1879 struct anv_buffer
*buffer
;
1884 struct anv_buffer_view
*buffer_view
;
1888 struct anv_descriptor_set
{
1889 struct anv_descriptor_pool
*pool
;
1890 struct anv_descriptor_set_layout
*layout
;
1893 /* State relative to anv_descriptor_pool::bo */
1894 struct anv_state desc_mem
;
1895 /* Surface state for the descriptor buffer */
1896 struct anv_state desc_surface_state
;
1898 uint32_t buffer_view_count
;
1899 struct anv_buffer_view
*buffer_views
;
1901 /* Link to descriptor pool's desc_sets list . */
1902 struct list_head pool_link
;
1904 struct anv_descriptor descriptors
[0];
1907 struct anv_buffer_view
{
1908 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1909 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1911 struct anv_address address
;
1913 struct anv_state surface_state
;
1914 struct anv_state storage_surface_state
;
1915 struct anv_state writeonly_storage_surface_state
;
1917 struct brw_image_param storage_image_param
;
1920 struct anv_push_descriptor_set
{
1921 struct anv_descriptor_set set
;
1923 /* Put this field right behind anv_descriptor_set so it fills up the
1924 * descriptors[0] field. */
1925 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1927 /** True if the descriptor set buffer has been referenced by a draw or
1930 bool set_used_on_gpu
;
1932 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1935 struct anv_descriptor_pool
{
1941 struct util_vma_heap bo_heap
;
1943 struct anv_state_stream surface_state_stream
;
1944 void *surface_state_free_list
;
1946 struct list_head desc_sets
;
1951 enum anv_descriptor_template_entry_type
{
1952 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
1953 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
1954 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1957 struct anv_descriptor_template_entry
{
1958 /* The type of descriptor in this entry */
1959 VkDescriptorType type
;
1961 /* Binding in the descriptor set */
1964 /* Offset at which to write into the descriptor set binding */
1965 uint32_t array_element
;
1967 /* Number of elements to write into the descriptor set binding */
1968 uint32_t array_count
;
1970 /* Offset into the user provided data */
1973 /* Stride between elements into the user provided data */
1977 struct anv_descriptor_update_template
{
1978 VkPipelineBindPoint bind_point
;
1980 /* The descriptor set this template corresponds to. This value is only
1981 * valid if the template was created with the templateType
1982 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
1986 /* Number of entries in this template */
1987 uint32_t entry_count
;
1989 /* Entries of the template */
1990 struct anv_descriptor_template_entry entries
[0];
1994 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
1997 anv_descriptor_set_write_image_view(struct anv_device
*device
,
1998 struct anv_descriptor_set
*set
,
1999 const VkDescriptorImageInfo
* const info
,
2000 VkDescriptorType type
,
2005 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
2006 struct anv_descriptor_set
*set
,
2007 VkDescriptorType type
,
2008 struct anv_buffer_view
*buffer_view
,
2013 anv_descriptor_set_write_buffer(struct anv_device
*device
,
2014 struct anv_descriptor_set
*set
,
2015 struct anv_state_stream
*alloc_stream
,
2016 VkDescriptorType type
,
2017 struct anv_buffer
*buffer
,
2020 VkDeviceSize offset
,
2021 VkDeviceSize range
);
2023 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
2024 struct anv_descriptor_set
*set
,
2031 anv_descriptor_set_write_template(struct anv_device
*device
,
2032 struct anv_descriptor_set
*set
,
2033 struct anv_state_stream
*alloc_stream
,
2034 const struct anv_descriptor_update_template
*template,
2038 anv_descriptor_set_create(struct anv_device
*device
,
2039 struct anv_descriptor_pool
*pool
,
2040 struct anv_descriptor_set_layout
*layout
,
2041 struct anv_descriptor_set
**out_set
);
2044 anv_descriptor_set_destroy(struct anv_device
*device
,
2045 struct anv_descriptor_pool
*pool
,
2046 struct anv_descriptor_set
*set
);
2048 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2049 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2050 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2051 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2052 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2053 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2055 struct anv_pipeline_binding
{
2056 /** Index in the descriptor set
2058 * This is a flattened index; the descriptor set layout is already taken
2063 /** The descriptor set this surface corresponds to.
2065 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2066 * binding is not a normal descriptor set but something else.
2071 /** Plane in the binding index for images */
2074 /** Input attachment index (relative to the subpass) */
2075 uint8_t input_attachment_index
;
2077 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2078 uint8_t dynamic_offset_index
;
2081 /** For a storage image, whether it is write-only */
2084 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2085 * assuming POD zero-initialization.
2090 struct anv_push_range
{
2091 /** Index in the descriptor set */
2094 /** Descriptor set index */
2097 /** Dynamic offset index (for dynamic UBOs) */
2098 uint8_t dynamic_offset_index
;
2100 /** Start offset in units of 32B */
2103 /** Range in units of 32B */
2107 struct anv_pipeline_layout
{
2109 struct anv_descriptor_set_layout
*layout
;
2110 uint32_t dynamic_offset_start
;
2115 unsigned char sha1
[20];
2119 struct anv_device
* device
;
2122 VkBufferUsageFlags usage
;
2124 /* Set when bound */
2125 struct anv_address address
;
2128 static inline uint64_t
2129 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2131 assert(offset
<= buffer
->size
);
2132 if (range
== VK_WHOLE_SIZE
) {
2133 return buffer
->size
- offset
;
2135 assert(range
+ offset
>= range
);
2136 assert(range
+ offset
<= buffer
->size
);
2141 enum anv_cmd_dirty_bits
{
2142 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2143 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2144 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2145 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2146 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2147 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2148 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2149 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2150 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2151 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2152 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2153 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2154 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2155 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2157 typedef uint32_t anv_cmd_dirty_mask_t
;
2159 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2160 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2161 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2162 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2163 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2164 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2165 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2166 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2167 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2168 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2169 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2171 static inline enum anv_cmd_dirty_bits
2172 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2175 case VK_DYNAMIC_STATE_VIEWPORT
:
2176 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2177 case VK_DYNAMIC_STATE_SCISSOR
:
2178 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2179 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2180 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2181 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2182 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2183 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2184 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2185 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2186 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2187 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2188 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2189 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2190 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2191 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2192 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2193 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2194 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2196 assert(!"Unsupported dynamic state");
2202 enum anv_pipe_bits
{
2203 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2204 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2205 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2206 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2207 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2208 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2209 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2210 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2211 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2212 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2213 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2214 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2216 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2217 * a flush has happened but not a CS stall. The next time we do any sort
2218 * of invalidation we need to insert a CS stall at that time. Otherwise,
2219 * we would have to CS stall on every flush which could be bad.
2221 ANV_PIPE_NEEDS_CS_STALL_BIT
= (1 << 21),
2223 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2224 * target operations related to transfer commands with VkBuffer as
2225 * destination are ongoing. Some operations like copies on the command
2226 * streamer might need to be aware of this to trigger the appropriate stall
2227 * before they can proceed with the copy.
2229 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 22),
2231 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2232 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2233 * done by writing the AUX-TT register.
2235 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
= (1 << 23),
2238 #define ANV_PIPE_FLUSH_BITS ( \
2239 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2240 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2241 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2242 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2244 #define ANV_PIPE_STALL_BITS ( \
2245 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2246 ANV_PIPE_DEPTH_STALL_BIT | \
2247 ANV_PIPE_CS_STALL_BIT)
2249 #define ANV_PIPE_INVALIDATE_BITS ( \
2250 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2251 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2252 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2253 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2254 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2255 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2256 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2258 static inline enum anv_pipe_bits
2259 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2261 enum anv_pipe_bits pipe_bits
= 0;
2264 for_each_bit(b
, flags
) {
2265 switch ((VkAccessFlagBits
)(1 << b
)) {
2266 case VK_ACCESS_SHADER_WRITE_BIT
:
2267 /* We're transitioning a buffer that was previously used as write
2268 * destination through the data port. To make its content available
2269 * to future operations, flush the data cache.
2271 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2273 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2274 /* We're transitioning a buffer that was previously used as render
2275 * target. To make its content available to future operations, flush
2276 * the render target cache.
2278 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2280 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2281 /* We're transitioning a buffer that was previously used as depth
2282 * buffer. To make its content available to future operations, flush
2285 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2287 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2288 /* We're transitioning a buffer that was previously used as a
2289 * transfer write destination. Generic write operations include color
2290 * & depth operations as well as buffer operations like :
2291 * - vkCmdClearColorImage()
2292 * - vkCmdClearDepthStencilImage()
2293 * - vkCmdBlitImage()
2294 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2296 * Most of these operations are implemented using Blorp which writes
2297 * through the render target, so flush that cache to make it visible
2298 * to future operations. And for depth related operations we also
2299 * need to flush the depth cache.
2301 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2302 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2304 case VK_ACCESS_MEMORY_WRITE_BIT
:
2305 /* We're transitioning a buffer for generic write operations. Flush
2308 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2311 break; /* Nothing to do */
2318 static inline enum anv_pipe_bits
2319 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2321 enum anv_pipe_bits pipe_bits
= 0;
2324 for_each_bit(b
, flags
) {
2325 switch ((VkAccessFlagBits
)(1 << b
)) {
2326 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2327 /* Indirect draw commands take a buffer as input that we're going to
2328 * read from the command streamer to load some of the HW registers
2329 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2330 * command streamer stall so that all the cache flushes have
2331 * completed before the command streamer loads from memory.
2333 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2334 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2335 * through a vertex buffer, so invalidate that cache.
2337 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2338 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2339 * UBO from the buffer, so we need to invalidate constant cache.
2341 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2343 case VK_ACCESS_INDEX_READ_BIT
:
2344 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2345 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2346 * commands, so we invalidate the VF cache to make sure there is no
2347 * stale data when we start rendering.
2349 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2351 case VK_ACCESS_UNIFORM_READ_BIT
:
2352 /* We transitioning a buffer to be used as uniform data. Because
2353 * uniform is accessed through the data port & sampler, we need to
2354 * invalidate the texture cache (sampler) & constant cache (data
2355 * port) to avoid stale data.
2357 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2358 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2360 case VK_ACCESS_SHADER_READ_BIT
:
2361 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2362 case VK_ACCESS_TRANSFER_READ_BIT
:
2363 /* Transitioning a buffer to be read through the sampler, so
2364 * invalidate the texture cache, we don't want any stale data.
2366 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2368 case VK_ACCESS_MEMORY_READ_BIT
:
2369 /* Transitioning a buffer for generic read, invalidate all the
2372 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2374 case VK_ACCESS_MEMORY_WRITE_BIT
:
2375 /* Generic write, make sure all previously written things land in
2378 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2380 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2381 /* Transitioning a buffer for conditional rendering. We'll load the
2382 * content of this buffer into HW registers using the command
2383 * streamer, so we need to stall the command streamer to make sure
2384 * any in-flight flush operations have completed.
2386 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2389 break; /* Nothing to do */
2396 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2397 VK_IMAGE_ASPECT_COLOR_BIT | \
2398 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2399 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2400 VK_IMAGE_ASPECT_PLANE_2_BIT)
2401 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2402 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2403 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2404 VK_IMAGE_ASPECT_PLANE_2_BIT)
2406 struct anv_vertex_binding
{
2407 struct anv_buffer
* buffer
;
2408 VkDeviceSize offset
;
2411 struct anv_xfb_binding
{
2412 struct anv_buffer
* buffer
;
2413 VkDeviceSize offset
;
2417 struct anv_push_constants
{
2418 /** Push constant data provided by the client through vkPushConstants */
2419 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2421 /** Dynamic offsets for dynamic UBOs and SSBOs */
2422 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2425 /** Base workgroup ID
2427 * Used for vkCmdDispatchBase.
2429 uint32_t base_work_group_id
[3];
2433 * This is never set by software but is implicitly filled out when
2434 * uploading the push constants for compute shaders.
2436 uint32_t subgroup_id
;
2438 /** Pad out to a multiple of 32 bytes */
2443 struct anv_dynamic_state
{
2446 VkViewport viewports
[MAX_VIEWPORTS
];
2451 VkRect2D scissors
[MAX_SCISSORS
];
2462 float blend_constants
[4];
2472 } stencil_compare_mask
;
2477 } stencil_write_mask
;
2482 } stencil_reference
;
2490 extern const struct anv_dynamic_state default_dynamic_state
;
2492 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2493 const struct anv_dynamic_state
*src
,
2494 uint32_t copy_mask
);
2496 struct anv_surface_state
{
2497 struct anv_state state
;
2498 /** Address of the surface referred to by this state
2500 * This address is relative to the start of the BO.
2502 struct anv_address address
;
2503 /* Address of the aux surface, if any
2505 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2507 * With the exception of gen8, the bottom 12 bits of this address' offset
2508 * include extra aux information.
2510 struct anv_address aux_address
;
2511 /* Address of the clear color, if any
2513 * This address is relative to the start of the BO.
2515 struct anv_address clear_address
;
2519 * Attachment state when recording a renderpass instance.
2521 * The clear value is valid only if there exists a pending clear.
2523 struct anv_attachment_state
{
2524 enum isl_aux_usage aux_usage
;
2525 enum isl_aux_usage input_aux_usage
;
2526 struct anv_surface_state color
;
2527 struct anv_surface_state input
;
2529 VkImageLayout current_layout
;
2530 VkImageLayout current_stencil_layout
;
2531 VkImageAspectFlags pending_clear_aspects
;
2532 VkImageAspectFlags pending_load_aspects
;
2534 VkClearValue clear_value
;
2535 bool clear_color_is_zero_one
;
2536 bool clear_color_is_zero
;
2538 /* When multiview is active, attachments with a renderpass clear
2539 * operation have their respective layers cleared on the first
2540 * subpass that uses them, and only in that subpass. We keep track
2541 * of this using a bitfield to indicate which layers of an attachment
2542 * have not been cleared yet when multiview is active.
2544 uint32_t pending_clear_views
;
2545 struct anv_image_view
* image_view
;
2548 /** State tracking for vertex buffer flushes
2550 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2551 * addresses. If you happen to have two vertex buffers which get placed
2552 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2553 * collisions. In order to solve this problem, we track vertex address ranges
2554 * which are live in the cache and invalidate the cache if one ever exceeds 32
2557 struct anv_vb_cache_range
{
2558 /* Virtual address at which the live vertex buffer cache range starts for
2559 * this vertex buffer index.
2563 /* Virtual address of the byte after where vertex buffer cache range ends.
2564 * This is exclusive such that end - start is the size of the range.
2569 /** State tracking for particular pipeline bind point
2571 * This struct is the base struct for anv_cmd_graphics_state and
2572 * anv_cmd_compute_state. These are used to track state which is bound to a
2573 * particular type of pipeline. Generic state that applies per-stage such as
2574 * binding table offsets and push constants is tracked generically with a
2575 * per-stage array in anv_cmd_state.
2577 struct anv_cmd_pipeline_state
{
2578 struct anv_pipeline
*pipeline
;
2580 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2581 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2584 /** State tracking for graphics pipeline
2586 * This has anv_cmd_pipeline_state as a base struct to track things which get
2587 * bound to a graphics pipeline. Along with general pipeline bind point state
2588 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2589 * state which is graphics-specific.
2591 struct anv_cmd_graphics_state
{
2592 struct anv_cmd_pipeline_state base
;
2594 anv_cmd_dirty_mask_t dirty
;
2597 struct anv_vb_cache_range ib_bound_range
;
2598 struct anv_vb_cache_range ib_dirty_range
;
2599 struct anv_vb_cache_range vb_bound_ranges
[33];
2600 struct anv_vb_cache_range vb_dirty_ranges
[33];
2602 struct anv_dynamic_state dynamic
;
2605 struct anv_buffer
*index_buffer
;
2606 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2607 uint32_t index_offset
;
2611 /** State tracking for compute pipeline
2613 * This has anv_cmd_pipeline_state as a base struct to track things which get
2614 * bound to a compute pipeline. Along with general pipeline bind point state
2615 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2616 * state which is compute-specific.
2618 struct anv_cmd_compute_state
{
2619 struct anv_cmd_pipeline_state base
;
2621 bool pipeline_dirty
;
2623 struct anv_address num_workgroups
;
2626 /** State required while building cmd buffer */
2627 struct anv_cmd_state
{
2628 /* PIPELINE_SELECT.PipelineSelection */
2629 uint32_t current_pipeline
;
2630 const struct gen_l3_config
* current_l3_config
;
2631 uint32_t last_aux_map_state
;
2633 struct anv_cmd_graphics_state gfx
;
2634 struct anv_cmd_compute_state compute
;
2636 enum anv_pipe_bits pending_pipe_bits
;
2637 VkShaderStageFlags descriptors_dirty
;
2638 VkShaderStageFlags push_constants_dirty
;
2640 struct anv_framebuffer
* framebuffer
;
2641 struct anv_render_pass
* pass
;
2642 struct anv_subpass
* subpass
;
2643 VkRect2D render_area
;
2644 uint32_t restart_index
;
2645 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2647 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2648 VkShaderStageFlags push_constant_stages
;
2649 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2650 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2651 struct anv_state samplers
[MESA_SHADER_STAGES
];
2653 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2654 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2655 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2658 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2659 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2660 * and before invoking the secondary in ExecuteCommands.
2662 bool pma_fix_enabled
;
2665 * Whether or not we know for certain that HiZ is enabled for the current
2666 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2667 * enabled or not, this will be false.
2671 bool conditional_render_enabled
;
2674 * Last rendering scale argument provided to
2675 * genX(cmd_buffer_emit_hashing_mode)().
2677 unsigned current_hash_scale
;
2680 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2681 * valid only when recording a render pass instance.
2683 struct anv_attachment_state
* attachments
;
2686 * Surface states for color render targets. These are stored in a single
2687 * flat array. For depth-stencil attachments, the surface state is simply
2690 struct anv_state render_pass_states
;
2693 * A null surface state of the right size to match the framebuffer. This
2694 * is one of the states in render_pass_states.
2696 struct anv_state null_surface_state
;
2699 struct anv_cmd_pool
{
2700 VkAllocationCallbacks alloc
;
2701 struct list_head cmd_buffers
;
2704 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2706 enum anv_cmd_buffer_exec_mode
{
2707 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2708 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2709 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2710 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2711 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2714 struct anv_cmd_buffer
{
2715 VK_LOADER_DATA _loader_data
;
2717 struct anv_device
* device
;
2719 struct anv_cmd_pool
* pool
;
2720 struct list_head pool_link
;
2722 struct anv_batch batch
;
2724 /* Fields required for the actual chain of anv_batch_bo's.
2726 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2728 struct list_head batch_bos
;
2729 enum anv_cmd_buffer_exec_mode exec_mode
;
2731 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2732 * referenced by this command buffer
2734 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2736 struct u_vector seen_bbos
;
2738 /* A vector of int32_t's for every block of binding tables.
2740 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2742 struct u_vector bt_block_states
;
2743 struct anv_state bt_next
;
2745 struct anv_reloc_list surface_relocs
;
2746 /** Last seen surface state block pool center bo offset */
2747 uint32_t last_ss_pool_center
;
2749 /* Serial for tracking buffer completion */
2752 /* Stream objects for storing temporary data */
2753 struct anv_state_stream surface_state_stream
;
2754 struct anv_state_stream dynamic_state_stream
;
2756 VkCommandBufferUsageFlags usage_flags
;
2757 VkCommandBufferLevel level
;
2759 struct anv_cmd_state state
;
2761 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2762 uint64_t intel_perf_marker
;
2765 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2766 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2767 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2768 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2769 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2770 struct anv_cmd_buffer
*secondary
);
2771 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2772 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
2773 struct anv_cmd_buffer
*cmd_buffer
,
2774 const VkSemaphore
*in_semaphores
,
2775 const uint64_t *in_wait_values
,
2776 uint32_t num_in_semaphores
,
2777 const VkSemaphore
*out_semaphores
,
2778 const uint64_t *out_signal_values
,
2779 uint32_t num_out_semaphores
,
2782 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2784 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2785 const void *data
, uint32_t size
, uint32_t alignment
);
2786 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2787 uint32_t *a
, uint32_t *b
,
2788 uint32_t dwords
, uint32_t alignment
);
2791 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2793 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2794 uint32_t entries
, uint32_t *state_offset
);
2796 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2798 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2799 uint32_t size
, uint32_t alignment
);
2802 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2804 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2805 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2806 bool depth_clamp_enable
);
2807 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2809 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2810 struct anv_render_pass
*pass
,
2811 struct anv_framebuffer
*framebuffer
,
2812 const VkClearValue
*clear_values
);
2814 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2817 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2818 gl_shader_stage stage
);
2820 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2822 const struct anv_image_view
*
2823 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2826 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2827 uint32_t num_entries
,
2828 uint32_t *state_offset
,
2829 struct anv_state
*bt_state
);
2831 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2833 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2835 enum anv_fence_type
{
2836 ANV_FENCE_TYPE_NONE
= 0,
2838 ANV_FENCE_TYPE_WSI_BO
,
2839 ANV_FENCE_TYPE_SYNCOBJ
,
2843 enum anv_bo_fence_state
{
2844 /** Indicates that this is a new (or newly reset fence) */
2845 ANV_BO_FENCE_STATE_RESET
,
2847 /** Indicates that this fence has been submitted to the GPU but is still
2848 * (as far as we know) in use by the GPU.
2850 ANV_BO_FENCE_STATE_SUBMITTED
,
2852 ANV_BO_FENCE_STATE_SIGNALED
,
2855 struct anv_fence_impl
{
2856 enum anv_fence_type type
;
2859 /** Fence implementation for BO fences
2861 * These fences use a BO and a set of CPU-tracked state flags. The BO
2862 * is added to the object list of the last execbuf call in a QueueSubmit
2863 * and is marked EXEC_WRITE. The state flags track when the BO has been
2864 * submitted to the kernel. We need to do this because Vulkan lets you
2865 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2866 * will say it's idle in this case.
2870 enum anv_bo_fence_state state
;
2873 /** DRM syncobj handle for syncobj-based fences */
2877 struct wsi_fence
*fence_wsi
;
2882 /* Permanent fence state. Every fence has some form of permanent state
2883 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2884 * cross-process fences) or it could just be a dummy for use internally.
2886 struct anv_fence_impl permanent
;
2888 /* Temporary fence state. A fence *may* have temporary state. That state
2889 * is added to the fence by an import operation and is reset back to
2890 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2891 * state cannot be signaled because the fence must already be signaled
2892 * before the temporary state can be exported from the fence in the other
2893 * process and imported here.
2895 struct anv_fence_impl temporary
;
2898 void anv_fence_reset_temporary(struct anv_device
*device
,
2899 struct anv_fence
*fence
);
2903 struct anv_state state
;
2906 enum anv_semaphore_type
{
2907 ANV_SEMAPHORE_TYPE_NONE
= 0,
2908 ANV_SEMAPHORE_TYPE_DUMMY
,
2909 ANV_SEMAPHORE_TYPE_BO
,
2910 ANV_SEMAPHORE_TYPE_WSI_BO
,
2911 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2912 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2913 ANV_SEMAPHORE_TYPE_TIMELINE
,
2916 struct anv_timeline_point
{
2917 struct list_head link
;
2921 /* Number of waiter on this point, when > 0 the point should not be garbage
2926 /* BO used for synchronization. */
2930 struct anv_timeline
{
2931 pthread_mutex_t mutex
;
2932 pthread_cond_t cond
;
2934 uint64_t highest_past
;
2935 uint64_t highest_pending
;
2937 struct list_head points
;
2938 struct list_head free_points
;
2941 struct anv_semaphore_impl
{
2942 enum anv_semaphore_type type
;
2945 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
2946 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
2947 * object list on any execbuf2 calls for which this semaphore is used as
2948 * a wait or signal fence. When used as a signal fence or when type ==
2949 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
2953 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2954 * If the semaphore is in the unsignaled state due to either just being
2955 * created or because it has been used for a wait, fd will be -1.
2959 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2960 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2961 * import so we don't need to bother with a userspace cache.
2965 /* Non shareable timeline semaphore
2967 * Used when kernel don't have support for timeline semaphores.
2969 struct anv_timeline timeline
;
2973 struct anv_semaphore
{
2976 /* Permanent semaphore state. Every semaphore has some form of permanent
2977 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2978 * (for cross-process semaphores0 or it could just be a dummy for use
2981 struct anv_semaphore_impl permanent
;
2983 /* Temporary semaphore state. A semaphore *may* have temporary state.
2984 * That state is added to the semaphore by an import operation and is reset
2985 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2986 * semaphore with temporary state cannot be signaled because the semaphore
2987 * must already be signaled before the temporary state can be exported from
2988 * the semaphore in the other process and imported here.
2990 struct anv_semaphore_impl temporary
;
2993 void anv_semaphore_reset_temporary(struct anv_device
*device
,
2994 struct anv_semaphore
*semaphore
);
2996 struct anv_shader_module
{
2997 unsigned char sha1
[20];
3002 static inline gl_shader_stage
3003 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
3005 assert(__builtin_popcount(vk_stage
) == 1);
3006 return ffs(vk_stage
) - 1;
3009 static inline VkShaderStageFlagBits
3010 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
3012 return (1 << mesa_stage
);
3015 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3017 #define anv_foreach_stage(stage, stage_bits) \
3018 for (gl_shader_stage stage, \
3019 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3020 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3021 __tmp &= ~(1 << (stage)))
3023 struct anv_pipeline_bind_map
{
3024 unsigned char surface_sha1
[20];
3025 unsigned char sampler_sha1
[20];
3026 unsigned char push_sha1
[20];
3028 uint32_t surface_count
;
3029 uint32_t sampler_count
;
3031 struct anv_pipeline_binding
* surface_to_descriptor
;
3032 struct anv_pipeline_binding
* sampler_to_descriptor
;
3034 struct anv_push_range push_ranges
[4];
3037 struct anv_shader_bin_key
{
3042 struct anv_shader_bin
{
3045 const struct anv_shader_bin_key
*key
;
3047 struct anv_state kernel
;
3048 uint32_t kernel_size
;
3050 struct anv_state constant_data
;
3051 uint32_t constant_data_size
;
3053 const struct brw_stage_prog_data
*prog_data
;
3054 uint32_t prog_data_size
;
3056 struct brw_compile_stats stats
[3];
3059 struct nir_xfb_info
*xfb_info
;
3061 struct anv_pipeline_bind_map bind_map
;
3064 struct anv_shader_bin
*
3065 anv_shader_bin_create(struct anv_device
*device
,
3066 const void *key
, uint32_t key_size
,
3067 const void *kernel
, uint32_t kernel_size
,
3068 const void *constant_data
, uint32_t constant_data_size
,
3069 const struct brw_stage_prog_data
*prog_data
,
3070 uint32_t prog_data_size
, const void *prog_data_param
,
3071 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
3072 const struct nir_xfb_info
*xfb_info
,
3073 const struct anv_pipeline_bind_map
*bind_map
);
3076 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3079 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3081 assert(shader
&& shader
->ref_cnt
>= 1);
3082 p_atomic_inc(&shader
->ref_cnt
);
3086 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3088 assert(shader
&& shader
->ref_cnt
>= 1);
3089 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3090 anv_shader_bin_destroy(device
, shader
);
3093 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
3094 #define MAX_PIPELINE_EXECUTABLES 7
3096 struct anv_pipeline_executable
{
3097 gl_shader_stage stage
;
3099 struct brw_compile_stats stats
;
3105 struct anv_pipeline
{
3106 struct anv_device
* device
;
3107 struct anv_batch batch
;
3108 uint32_t batch_data
[512];
3109 struct anv_reloc_list batch_relocs
;
3110 anv_cmd_dirty_mask_t dynamic_state_mask
;
3111 struct anv_dynamic_state dynamic_state
;
3115 VkPipelineCreateFlags flags
;
3116 struct anv_subpass
* subpass
;
3118 bool needs_data_cache
;
3120 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3122 uint32_t num_executables
;
3123 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
3126 const struct gen_l3_config
* l3_config
;
3127 uint32_t total_size
;
3130 VkShaderStageFlags active_stages
;
3131 struct anv_state blend_state
;
3134 struct anv_pipeline_vertex_binding
{
3137 uint32_t instance_divisor
;
3142 bool primitive_restart
;
3145 uint32_t cs_right_mask
;
3148 bool depth_test_enable
;
3149 bool writes_stencil
;
3150 bool stencil_test_enable
;
3151 bool depth_clamp_enable
;
3152 bool depth_clip_enable
;
3153 bool sample_shading_enable
;
3155 bool depth_bounds_test_enable
;
3159 uint32_t depth_stencil_state
[3];
3165 uint32_t wm_depth_stencil
[3];
3169 uint32_t wm_depth_stencil
[4];
3172 uint32_t interface_descriptor_data
[8];
3176 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
3177 gl_shader_stage stage
)
3179 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3182 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
3183 static inline const struct brw_##prefix##_prog_data * \
3184 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
3186 if (anv_pipeline_has_stage(pipeline, stage)) { \
3187 return (const struct brw_##prefix##_prog_data *) \
3188 pipeline->shaders[stage]->prog_data; \
3194 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3195 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3196 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3197 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3198 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3199 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
3201 static inline const struct brw_vue_prog_data
*
3202 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
3204 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3205 return &get_gs_prog_data(pipeline
)->base
;
3206 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3207 return &get_tes_prog_data(pipeline
)->base
;
3209 return &get_vs_prog_data(pipeline
)->base
;
3213 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
3214 struct anv_pipeline_cache
*cache
,
3215 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3216 const VkAllocationCallbacks
*alloc
);
3219 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
3220 struct anv_pipeline_cache
*cache
,
3221 const VkComputePipelineCreateInfo
*info
,
3222 const struct anv_shader_module
*module
,
3223 const char *entrypoint
,
3224 const VkSpecializationInfo
*spec_info
);
3226 struct anv_format_plane
{
3227 enum isl_format isl_format
:16;
3228 struct isl_swizzle swizzle
;
3230 /* Whether this plane contains chroma channels */
3233 /* For downscaling of YUV planes */
3234 uint8_t denominator_scales
[2];
3236 /* How to map sampled ycbcr planes to a single 4 component element. */
3237 struct isl_swizzle ycbcr_swizzle
;
3239 /* What aspect is associated to this plane */
3240 VkImageAspectFlags aspect
;
3245 struct anv_format_plane planes
[3];
3251 static inline uint32_t
3252 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3253 VkImageAspectFlags aspect_mask
)
3255 switch (aspect_mask
) {
3256 case VK_IMAGE_ASPECT_COLOR_BIT
:
3257 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3258 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3260 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3261 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3264 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3266 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3269 /* Purposefully assert with depth/stencil aspects. */
3270 unreachable("invalid image aspect");
3274 static inline VkImageAspectFlags
3275 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3278 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3279 if (util_bitcount(image_aspects
) > 1)
3280 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3281 return VK_IMAGE_ASPECT_COLOR_BIT
;
3283 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3284 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3285 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3286 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3289 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3290 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3292 const struct anv_format
*
3293 anv_get_format(VkFormat format
);
3295 static inline uint32_t
3296 anv_get_format_planes(VkFormat vk_format
)
3298 const struct anv_format
*format
= anv_get_format(vk_format
);
3300 return format
!= NULL
? format
->n_planes
: 0;
3303 struct anv_format_plane
3304 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3305 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3307 static inline enum isl_format
3308 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3309 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3311 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3314 bool anv_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
3315 VkImageCreateFlags create_flags
,
3317 VkImageTiling vk_tiling
,
3318 const VkImageFormatListCreateInfoKHR
*fmt_list
);
3320 static inline struct isl_swizzle
3321 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3323 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3324 * RGB as RGBA for texturing
3326 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3327 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3329 /* But it doesn't matter what we render to that channel */
3330 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3336 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3339 * Subsurface of an anv_image.
3341 struct anv_surface
{
3342 /** Valid only if isl_surf::size_B > 0. */
3343 struct isl_surf isl
;
3346 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3352 VkImageType type
; /**< VkImageCreateInfo::imageType */
3353 /* The original VkFormat provided by the client. This may not match any
3354 * of the actual surface formats.
3357 const struct anv_format
*format
;
3359 VkImageAspectFlags aspects
;
3362 uint32_t array_size
;
3363 uint32_t samples
; /**< VkImageCreateInfo::samples */
3365 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3366 VkImageUsageFlags stencil_usage
;
3367 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3368 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3370 /** True if this is needs to be bound to an appropriately tiled BO.
3372 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3373 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3374 * we require a dedicated allocation so that we can know to allocate a
3377 bool needs_set_tiling
;
3380 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3381 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3383 uint64_t drm_format_mod
;
3388 /* Whether the image is made of several underlying buffer objects rather a
3389 * single one with different offsets.
3393 /* All the formats that can be used when creating views of this image
3394 * are CCS_E compatible.
3396 bool ccs_e_compatible
;
3398 /* Image was created with external format. */
3399 bool external_format
;
3404 * For each foo, anv_image::planes[x].surface is valid if and only if
3405 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3406 * to figure the number associated with a given aspect.
3408 * The hardware requires that the depth buffer and stencil buffer be
3409 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3410 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3411 * allocate the depth and stencil buffers as separate surfaces in the same
3416 * -----------------------
3418 * ----------------------- |
3419 * | shadow surface0 | |
3420 * ----------------------- | Plane 0
3421 * | aux surface0 | |
3422 * ----------------------- |
3423 * | fast clear colors0 | \|/
3424 * -----------------------
3426 * ----------------------- |
3427 * | shadow surface1 | |
3428 * ----------------------- | Plane 1
3429 * | aux surface1 | |
3430 * ----------------------- |
3431 * | fast clear colors1 | \|/
3432 * -----------------------
3435 * -----------------------
3439 * Offset of the entire plane (whenever the image is disjoint this is
3447 struct anv_surface surface
;
3450 * A surface which shadows the main surface and may have different
3451 * tiling. This is used for sampling using a tiling that isn't supported
3452 * for other operations.
3454 struct anv_surface shadow_surface
;
3457 * The base aux usage for this image. For color images, this can be
3458 * either CCS_E or CCS_D depending on whether or not we can reliably
3459 * leave CCS on all the time.
3461 enum isl_aux_usage aux_usage
;
3463 struct anv_surface aux_surface
;
3466 * Offset of the fast clear state (used to compute the
3467 * fast_clear_state_offset of the following planes).
3469 uint32_t fast_clear_state_offset
;
3472 * BO associated with this plane, set when bound.
3474 struct anv_address address
;
3477 * Address of the main surface used to fill the aux map table. This is
3478 * used at destruction of the image since the Vulkan spec does not
3479 * guarantee that the address.bo field we still be valid at destruction.
3481 uint64_t aux_map_surface_address
;
3484 * When destroying the image, also free the bo.
3490 /* The ordering of this enum is important */
3491 enum anv_fast_clear_type
{
3492 /** Image does not have/support any fast-clear blocks */
3493 ANV_FAST_CLEAR_NONE
= 0,
3494 /** Image has/supports fast-clear but only to the default value */
3495 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3496 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3497 ANV_FAST_CLEAR_ANY
= 2,
3500 /* Returns the number of auxiliary buffer levels attached to an image. */
3501 static inline uint8_t
3502 anv_image_aux_levels(const struct anv_image
* const image
,
3503 VkImageAspectFlagBits aspect
)
3505 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3506 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
3509 /* The Gen12 CCS aux surface is represented with only one level. */
3510 return image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3511 image
->planes
[plane
].surface
.isl
.levels
:
3512 image
->planes
[plane
].aux_surface
.isl
.levels
;
3515 /* Returns the number of auxiliary buffer layers attached to an image. */
3516 static inline uint32_t
3517 anv_image_aux_layers(const struct anv_image
* const image
,
3518 VkImageAspectFlagBits aspect
,
3519 const uint8_t miplevel
)
3523 /* The miplevel must exist in the main buffer. */
3524 assert(miplevel
< image
->levels
);
3526 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3527 /* There are no layers with auxiliary data because the miplevel has no
3532 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3534 /* The Gen12 CCS aux surface is represented with only one layer. */
3535 const struct isl_extent4d
*aux_logical_level0_px
=
3536 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3537 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3538 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3540 return MAX2(aux_logical_level0_px
->array_len
,
3541 aux_logical_level0_px
->depth
>> miplevel
);
3545 static inline struct anv_address
3546 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3547 const struct anv_image
*image
,
3548 VkImageAspectFlagBits aspect
)
3550 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3552 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3553 return anv_address_add(image
->planes
[plane
].address
,
3554 image
->planes
[plane
].fast_clear_state_offset
);
3557 static inline struct anv_address
3558 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3559 const struct anv_image
*image
,
3560 VkImageAspectFlagBits aspect
)
3562 struct anv_address addr
=
3563 anv_image_get_clear_color_addr(device
, image
, aspect
);
3565 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3566 device
->isl_dev
.ss
.clear_color_state_size
:
3567 device
->isl_dev
.ss
.clear_value_size
;
3568 return anv_address_add(addr
, clear_color_state_size
);
3571 static inline struct anv_address
3572 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3573 const struct anv_image
*image
,
3574 VkImageAspectFlagBits aspect
,
3575 uint32_t level
, uint32_t array_layer
)
3577 assert(level
< anv_image_aux_levels(image
, aspect
));
3578 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3579 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3580 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3582 struct anv_address addr
=
3583 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3584 addr
.offset
+= 4; /* Go past the fast clear type */
3586 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3587 for (uint32_t l
= 0; l
< level
; l
++)
3588 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3590 addr
.offset
+= level
* image
->array_size
* 4;
3592 addr
.offset
+= array_layer
* 4;
3594 assert(addr
.offset
<
3595 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3599 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3601 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3602 const struct anv_image
*image
)
3604 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3607 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3608 * struct. There's documentation which suggests that this feature actually
3609 * reduces performance on BDW, but it has only been observed to help so
3610 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3611 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3613 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3616 return image
->samples
== 1;
3620 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3621 const struct anv_image
*image
,
3624 return device
->info
.has_aux_map
&&
3625 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3629 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3630 const struct anv_image
*image
,
3631 VkImageAspectFlagBits aspect
,
3632 enum isl_aux_usage aux_usage
,
3634 uint32_t base_layer
,
3635 uint32_t layer_count
);
3638 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3639 const struct anv_image
*image
,
3640 VkImageAspectFlagBits aspect
,
3641 enum isl_aux_usage aux_usage
,
3642 enum isl_format format
, struct isl_swizzle swizzle
,
3643 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3644 VkRect2D area
, union isl_color_value clear_color
);
3646 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3647 const struct anv_image
*image
,
3648 VkImageAspectFlags aspects
,
3649 enum isl_aux_usage depth_aux_usage
,
3651 uint32_t base_layer
, uint32_t layer_count
,
3653 float depth_value
, uint8_t stencil_value
);
3655 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3656 const struct anv_image
*src_image
,
3657 enum isl_aux_usage src_aux_usage
,
3658 uint32_t src_level
, uint32_t src_base_layer
,
3659 const struct anv_image
*dst_image
,
3660 enum isl_aux_usage dst_aux_usage
,
3661 uint32_t dst_level
, uint32_t dst_base_layer
,
3662 VkImageAspectFlagBits aspect
,
3663 uint32_t src_x
, uint32_t src_y
,
3664 uint32_t dst_x
, uint32_t dst_y
,
3665 uint32_t width
, uint32_t height
,
3666 uint32_t layer_count
,
3667 enum blorp_filter filter
);
3669 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3670 const struct anv_image
*image
,
3671 VkImageAspectFlagBits aspect
, uint32_t level
,
3672 uint32_t base_layer
, uint32_t layer_count
,
3673 enum isl_aux_op hiz_op
);
3675 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3676 const struct anv_image
*image
,
3677 VkImageAspectFlags aspects
,
3679 uint32_t base_layer
, uint32_t layer_count
,
3680 VkRect2D area
, uint8_t stencil_value
);
3682 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3683 const struct anv_image
*image
,
3684 enum isl_format format
,
3685 VkImageAspectFlagBits aspect
,
3686 uint32_t base_layer
, uint32_t layer_count
,
3687 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3690 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3691 const struct anv_image
*image
,
3692 enum isl_format format
,
3693 VkImageAspectFlagBits aspect
, uint32_t level
,
3694 uint32_t base_layer
, uint32_t layer_count
,
3695 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3699 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3700 const struct anv_image
*image
,
3701 VkImageAspectFlagBits aspect
,
3702 uint32_t base_level
, uint32_t level_count
,
3703 uint32_t base_layer
, uint32_t layer_count
);
3706 anv_layout_to_aux_state(const struct gen_device_info
* const devinfo
,
3707 const struct anv_image
*image
,
3708 const VkImageAspectFlagBits aspect
,
3709 const VkImageLayout layout
);
3712 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3713 const struct anv_image
*image
,
3714 const VkImageAspectFlagBits aspect
,
3715 const VkImageUsageFlagBits usage
,
3716 const VkImageLayout layout
);
3718 enum anv_fast_clear_type
3719 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3720 const struct anv_image
* const image
,
3721 const VkImageAspectFlagBits aspect
,
3722 const VkImageLayout layout
);
3724 /* This is defined as a macro so that it works for both
3725 * VkImageSubresourceRange and VkImageSubresourceLayers
3727 #define anv_get_layerCount(_image, _range) \
3728 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3729 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3731 static inline uint32_t
3732 anv_get_levelCount(const struct anv_image
*image
,
3733 const VkImageSubresourceRange
*range
)
3735 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3736 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3739 static inline VkImageAspectFlags
3740 anv_image_expand_aspects(const struct anv_image
*image
,
3741 VkImageAspectFlags aspects
)
3743 /* If the underlying image has color plane aspects and
3744 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3745 * the underlying image. */
3746 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3747 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3748 return image
->aspects
;
3754 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3755 VkImageAspectFlags aspects2
)
3757 if (aspects1
== aspects2
)
3760 /* Only 1 color aspects are compatibles. */
3761 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3762 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3763 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3769 struct anv_image_view
{
3770 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3772 VkImageAspectFlags aspect_mask
;
3774 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3778 uint32_t image_plane
;
3780 struct isl_view isl
;
3783 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3784 * image layout of SHADER_READ_ONLY_OPTIMAL or
3785 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3787 struct anv_surface_state optimal_sampler_surface_state
;
3790 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3791 * image layout of GENERAL.
3793 struct anv_surface_state general_sampler_surface_state
;
3796 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3797 * states for write-only and readable, using the real format for
3798 * write-only and the lowered format for readable.
3800 struct anv_surface_state storage_surface_state
;
3801 struct anv_surface_state writeonly_storage_surface_state
;
3803 struct brw_image_param storage_image_param
;
3807 enum anv_image_view_state_flags
{
3808 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3809 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3812 void anv_image_fill_surface_state(struct anv_device
*device
,
3813 const struct anv_image
*image
,
3814 VkImageAspectFlagBits aspect
,
3815 const struct isl_view
*view
,
3816 isl_surf_usage_flags_t view_usage
,
3817 enum isl_aux_usage aux_usage
,
3818 const union isl_color_value
*clear_color
,
3819 enum anv_image_view_state_flags flags
,
3820 struct anv_surface_state
*state_inout
,
3821 struct brw_image_param
*image_param_out
);
3823 struct anv_image_create_info
{
3824 const VkImageCreateInfo
*vk_info
;
3826 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3827 isl_tiling_flags_t isl_tiling_flags
;
3829 /** These flags will be added to any derived from VkImageCreateInfo. */
3830 isl_surf_usage_flags_t isl_extra_usage_flags
;
3833 bool external_format
;
3836 VkResult
anv_image_create(VkDevice _device
,
3837 const struct anv_image_create_info
*info
,
3838 const VkAllocationCallbacks
* alloc
,
3841 const struct anv_surface
*
3842 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
3843 VkImageAspectFlags aspect_mask
);
3846 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3848 static inline VkExtent3D
3849 anv_sanitize_image_extent(const VkImageType imageType
,
3850 const VkExtent3D imageExtent
)
3852 switch (imageType
) {
3853 case VK_IMAGE_TYPE_1D
:
3854 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3855 case VK_IMAGE_TYPE_2D
:
3856 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3857 case VK_IMAGE_TYPE_3D
:
3860 unreachable("invalid image type");
3864 static inline VkOffset3D
3865 anv_sanitize_image_offset(const VkImageType imageType
,
3866 const VkOffset3D imageOffset
)
3868 switch (imageType
) {
3869 case VK_IMAGE_TYPE_1D
:
3870 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3871 case VK_IMAGE_TYPE_2D
:
3872 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3873 case VK_IMAGE_TYPE_3D
:
3876 unreachable("invalid image type");
3880 VkFormatFeatureFlags
3881 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3883 const struct anv_format
*anv_format
,
3884 VkImageTiling vk_tiling
);
3886 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3887 struct anv_state state
,
3888 enum isl_format format
,
3889 struct anv_address address
,
3890 uint32_t range
, uint32_t stride
);
3893 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3894 const struct anv_attachment_state
*att_state
,
3895 const struct anv_image_view
*iview
)
3897 const struct isl_format_layout
*view_fmtl
=
3898 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3900 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3901 if (view_fmtl->channels.c.bits) \
3902 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3904 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3905 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3906 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3907 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3909 #undef COPY_CLEAR_COLOR_CHANNEL
3913 struct anv_ycbcr_conversion
{
3914 const struct anv_format
* format
;
3915 VkSamplerYcbcrModelConversion ycbcr_model
;
3916 VkSamplerYcbcrRange ycbcr_range
;
3917 VkComponentSwizzle mapping
[4];
3918 VkChromaLocation chroma_offsets
[2];
3919 VkFilter chroma_filter
;
3920 bool chroma_reconstruction
;
3923 struct anv_sampler
{
3924 uint32_t state
[3][4];
3926 struct anv_ycbcr_conversion
*conversion
;
3928 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3929 * and with a 32-byte stride for use as bindless samplers.
3931 struct anv_state bindless_state
;
3934 struct anv_framebuffer
{
3939 uint32_t attachment_count
;
3940 struct anv_image_view
* attachments
[0];
3943 struct anv_subpass_attachment
{
3944 VkImageUsageFlagBits usage
;
3945 uint32_t attachment
;
3946 VkImageLayout layout
;
3948 /* Used only with attachment containing stencil data. */
3949 VkImageLayout stencil_layout
;
3952 struct anv_subpass
{
3953 uint32_t attachment_count
;
3956 * A pointer to all attachment references used in this subpass.
3957 * Only valid if ::attachment_count > 0.
3959 struct anv_subpass_attachment
* attachments
;
3960 uint32_t input_count
;
3961 struct anv_subpass_attachment
* input_attachments
;
3962 uint32_t color_count
;
3963 struct anv_subpass_attachment
* color_attachments
;
3964 struct anv_subpass_attachment
* resolve_attachments
;
3966 struct anv_subpass_attachment
* depth_stencil_attachment
;
3967 struct anv_subpass_attachment
* ds_resolve_attachment
;
3968 VkResolveModeFlagBitsKHR depth_resolve_mode
;
3969 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
3973 /** Subpass has a depth/stencil self-dependency */
3974 bool has_ds_self_dep
;
3976 /** Subpass has at least one color resolve attachment */
3977 bool has_color_resolve
;
3980 static inline unsigned
3981 anv_subpass_view_count(const struct anv_subpass
*subpass
)
3983 return MAX2(1, util_bitcount(subpass
->view_mask
));
3986 struct anv_render_pass_attachment
{
3987 /* TODO: Consider using VkAttachmentDescription instead of storing each of
3988 * its members individually.
3992 VkImageUsageFlags usage
;
3993 VkAttachmentLoadOp load_op
;
3994 VkAttachmentStoreOp store_op
;
3995 VkAttachmentLoadOp stencil_load_op
;
3996 VkImageLayout initial_layout
;
3997 VkImageLayout final_layout
;
3998 VkImageLayout first_subpass_layout
;
4000 VkImageLayout stencil_initial_layout
;
4001 VkImageLayout stencil_final_layout
;
4003 /* The subpass id in which the attachment will be used last. */
4004 uint32_t last_subpass_idx
;
4007 struct anv_render_pass
{
4008 uint32_t attachment_count
;
4009 uint32_t subpass_count
;
4010 /* An array of subpass_count+1 flushes, one per subpass boundary */
4011 enum anv_pipe_bits
* subpass_flushes
;
4012 struct anv_render_pass_attachment
* attachments
;
4013 struct anv_subpass subpasses
[0];
4016 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
4018 struct anv_query_pool
{
4020 VkQueryPipelineStatisticFlags pipeline_statistics
;
4021 /** Stride between slots, in bytes */
4023 /** Number of slots in this query pool */
4028 int anv_get_instance_entrypoint_index(const char *name
);
4029 int anv_get_device_entrypoint_index(const char *name
);
4030 int anv_get_physical_device_entrypoint_index(const char *name
);
4032 const char *anv_get_instance_entry_name(int index
);
4033 const char *anv_get_physical_device_entry_name(int index
);
4034 const char *anv_get_device_entry_name(int index
);
4037 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
4038 const struct anv_instance_extension_table
*instance
);
4040 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4041 const struct anv_instance_extension_table
*instance
);
4043 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4044 const struct anv_instance_extension_table
*instance
,
4045 const struct anv_device_extension_table
*device
);
4047 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
4050 void anv_dump_image_to_ppm(struct anv_device
*device
,
4051 struct anv_image
*image
, unsigned miplevel
,
4052 unsigned array_layer
, VkImageAspectFlagBits aspect
,
4053 const char *filename
);
4055 enum anv_dump_action
{
4056 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
4059 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
4060 void anv_dump_finish(void);
4062 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
4064 static inline uint32_t
4065 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
4067 /* This function must be called from within a subpass. */
4068 assert(cmd_state
->pass
&& cmd_state
->subpass
);
4070 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
4072 /* The id of this subpass shouldn't exceed the number of subpasses in this
4073 * render pass minus 1.
4075 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
4079 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
4080 void anv_device_perf_init(struct anv_device
*device
);
4082 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
4084 static inline struct __anv_type * \
4085 __anv_type ## _from_handle(__VkType _handle) \
4087 return (struct __anv_type *) _handle; \
4090 static inline __VkType \
4091 __anv_type ## _to_handle(struct __anv_type *_obj) \
4093 return (__VkType) _obj; \
4096 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
4098 static inline struct __anv_type * \
4099 __anv_type ## _from_handle(__VkType _handle) \
4101 return (struct __anv_type *)(uintptr_t) _handle; \
4104 static inline __VkType \
4105 __anv_type ## _to_handle(struct __anv_type *_obj) \
4107 return (__VkType)(uintptr_t) _obj; \
4110 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4111 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
4113 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
4114 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
4115 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
4116 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
4117 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
4119 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
4120 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
4121 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
4122 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
4123 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
4124 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
4125 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
4126 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
4127 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
4128 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
4129 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
4130 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
4131 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
4132 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
4133 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
4134 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
4135 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
4136 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
4137 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
4138 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
4139 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
4140 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
4141 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
4143 /* Gen-specific function declarations */
4145 # include "anv_genX.h"
4147 # define genX(x) gen7_##x
4148 # include "anv_genX.h"
4150 # define genX(x) gen75_##x
4151 # include "anv_genX.h"
4153 # define genX(x) gen8_##x
4154 # include "anv_genX.h"
4156 # define genX(x) gen9_##x
4157 # include "anv_genX.h"
4159 # define genX(x) gen10_##x
4160 # include "anv_genX.h"
4162 # define genX(x) gen11_##x
4163 # include "anv_genX.h"
4165 # define genX(x) gen12_##x
4166 # include "anv_genX.h"
4170 #endif /* ANV_PRIVATE_H */