src/intel/vulkan/gen7_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #if GEN_GEN == 7 && !GEN_IS_HASWELL
  36 void
  37 gen7_cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
  38                                          uint32_t stages)
  39 {
  40    static const uint32_t sampler_state_opcodes[] = {
  41       [MESA_SHADER_VERTEX]                      = 43,
  42       [MESA_SHADER_TESS_CTRL]                   = 44, /* HS */
  43       [MESA_SHADER_TESS_EVAL]                   = 45, /* DS */
  44       [MESA_SHADER_GEOMETRY]                    = 46,
  45       [MESA_SHADER_FRAGMENT]                    = 47,
  46       [MESA_SHADER_COMPUTE]                     = 0,
  47    };
  48
  49    static const uint32_t binding_table_opcodes[] = {
  50       [MESA_SHADER_VERTEX]                      = 38,
  51       [MESA_SHADER_TESS_CTRL]                   = 39,
  52       [MESA_SHADER_TESS_EVAL]                   = 40,
  53       [MESA_SHADER_GEOMETRY]                    = 41,
  54       [MESA_SHADER_FRAGMENT]                    = 42,
  55       [MESA_SHADER_COMPUTE]                     = 0,
  56    };
  57
  58    anv_foreach_stage(s, stages) {
  59       if (cmd_buffer->state.samplers[s].alloc_size > 0) {
  60          anv_batch_emit(&cmd_buffer->batch,
  61                         GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS),
  62                         ._3DCommandSubOpcode  = sampler_state_opcodes[s],
  63                         .PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset);
  64       }
  65
  66       /* Always emit binding table pointers if we're asked to, since on SKL
  67        * this is what flushes push constants. */
  68       anv_batch_emit(&cmd_buffer->batch,
  69                      GENX(3DSTATE_BINDING_TABLE_POINTERS_VS),
  70                      ._3DCommandSubOpcode  = binding_table_opcodes[s],
  71                      .PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset);
  72    }
  73 }
  74
  75 uint32_t
  76 gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer)
  77 {
  78    VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
  79                               cmd_buffer->state.pipeline->active_stages;
  80
  81    VkResult result = VK_SUCCESS;
  82    anv_foreach_stage(s, dirty) {
  83       result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
  84                                             &cmd_buffer->state.samplers[s]);
  85       if (result != VK_SUCCESS)
  86          break;
  87       result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
  88                                                  &cmd_buffer->state.binding_tables[s]);
  89       if (result != VK_SUCCESS)
  90          break;
  91    }
  92
  93    if (result != VK_SUCCESS) {
  94       assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
  95
  96       result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
  97       assert(result == VK_SUCCESS);
  98
  99       /* Re-emit state base addresses so we get the new surface state base
 100        * address before we start emitting binding tables etc.
 101        */
 102       anv_cmd_buffer_emit_state_base_address(cmd_buffer);
 103
 104       /* Re-emit all active binding tables */
 105       dirty |= cmd_buffer->state.pipeline->active_stages;
 106       anv_foreach_stage(s, dirty) {
 107          result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
 108                                                &cmd_buffer->state.samplers[s]);
 109          if (result != VK_SUCCESS)
 110             return result;
 111          result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
 112                                                     &cmd_buffer->state.binding_tables[s]);
 113          if (result != VK_SUCCESS)
 114             return result;
 115       }
 116    }
 117
 118    cmd_buffer->state.descriptors_dirty &= ~dirty;
 119
 120    return dirty;
 121 }
 122 #endif /* GEN_GEN == 7 && !GEN_IS_HASWELL */
 123
 124 static inline int64_t
 125 clamp_int64(int64_t x, int64_t min, int64_t max)
 126 {
 127    if (x < min)
 128       return min;
 129    else if (x < max)
 130       return x;
 131    else
 132       return max;
 133 }
 134
 135 #if GEN_GEN == 7 && !GEN_IS_HASWELL
 136 void
 137 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
 138 {
 139    uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 140    const VkRect2D *scissors =  cmd_buffer->state.dynamic.scissor.scissors;
 141    struct anv_state scissor_state =
 142       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
 143
 144    for (uint32_t i = 0; i < count; i++) {
 145       const VkRect2D *s = &scissors[i];
 146
 147       /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
 148        * ymax < ymin for empty clips.  In case clip x, y, width height are all
 149        * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
 150        * what we want. Just special case empty clips and produce a canonical
 151        * empty clip. */
 152       static const struct GEN7_SCISSOR_RECT empty_scissor = {
 153          .ScissorRectangleYMin = 1,
 154          .ScissorRectangleXMin = 1,
 155          .ScissorRectangleYMax = 0,
 156          .ScissorRectangleXMax = 0
 157       };
 158
 159       const int max = 0xffff;
 160       struct GEN7_SCISSOR_RECT scissor = {
 161          /* Do this math using int64_t so overflow gets clamped correctly. */
 162          .ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
 163          .ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
 164          .ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
 165          .ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
 166       };
 167
 168       if (s->extent.width <= 0 || s->extent.height <= 0) {
 169          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
 170                                 &empty_scissor);
 171       } else {
 172          GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
 173       }
 174    }
 175
 176    anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_SCISSOR_STATE_POINTERS,
 177                   .ScissorRectPointer = scissor_state.offset);
 178
 179    if (!cmd_buffer->device->info.has_llc)
 180       anv_state_clflush(scissor_state);
 181 }
 182 #endif
 183
 184 static const uint32_t vk_to_gen_index_type[] = {
 185    [VK_INDEX_TYPE_UINT16]                       = INDEX_WORD,
 186    [VK_INDEX_TYPE_UINT32]                       = INDEX_DWORD,
 187 };
 188
 189 static const uint32_t restart_index_for_type[] = {
 190    [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 191    [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 192 };
 193
 194 void genX(CmdBindIndexBuffer)(
 195     VkCommandBuffer                             commandBuffer,
 196     VkBuffer                                    _buffer,
 197     VkDeviceSize                                offset,
 198     VkIndexType                                 indexType)
 199 {
 200    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 201    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 202
 203    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 204    if (GEN_IS_HASWELL)
 205       cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 206    cmd_buffer->state.gen7.index_buffer = buffer;
 207    cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
 208    cmd_buffer->state.gen7.index_offset = offset;
 209 }
 210
 211 static VkResult
 212 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 213 {
 214    struct anv_device *device = cmd_buffer->device;
 215    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 216    struct anv_state surfaces = { 0, }, samplers = { 0, };
 217    VkResult result;
 218
 219    result = anv_cmd_buffer_emit_samplers(cmd_buffer,
 220                                          MESA_SHADER_COMPUTE, &samplers);
 221    if (result != VK_SUCCESS)
 222       return result;
 223    result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
 224                                               MESA_SHADER_COMPUTE, &surfaces);
 225    if (result != VK_SUCCESS)
 226       return result;
 227
 228    struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
 229
 230    const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
 231    const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
 232
 233    unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
 234    unsigned push_constant_data_size =
 235       (prog_data->nr_params + local_id_dwords) * 4;
 236    unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
 237    unsigned push_constant_regs = reg_aligned_constant_size / 32;
 238
 239    if (push_state.alloc_size) {
 240       anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD),
 241                      .CURBETotalDataLength = push_state.alloc_size,
 242                      .CURBEDataStartAddress = push_state.offset);
 243    }
 244
 245    assert(prog_data->total_shared <= 64 * 1024);
 246    uint32_t slm_size = 0;
 247    if (prog_data->total_shared > 0) {
 248       /* slm_size is in 4k increments, but must be a power of 2. */
 249       slm_size = 4 * 1024;
 250       while (slm_size < prog_data->total_shared)
 251          slm_size <<= 1;
 252       slm_size /= 4 * 1024;
 253    }
 254
 255    struct anv_state state =
 256       anv_state_pool_emit(&device->dynamic_state_pool,
 257                           GENX(INTERFACE_DESCRIPTOR_DATA), 64,
 258                           .KernelStartPointer = pipeline->cs_simd,
 259                           .BindingTablePointer = surfaces.offset,
 260                           .SamplerStatePointer = samplers.offset,
 261                           .ConstantURBEntryReadLength =
 262                              push_constant_regs,
 263 #if !GEN_IS_HASWELL
 264                           .ConstantURBEntryReadOffset = 0,
 265 #endif
 266                           .BarrierEnable = cs_prog_data->uses_barrier,
 267                           .SharedLocalMemorySize = slm_size,
 268                           .NumberofThreadsinGPGPUThreadGroup =
 269                              pipeline->cs_thread_width_max);
 270
 271    const uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
 272    anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD),
 273                   .InterfaceDescriptorTotalLength = size,
 274                   .InterfaceDescriptorDataStartAddress = state.offset);
 275
 276    return VK_SUCCESS;
 277 }
 278
 279 #define emit_lri(batch, reg, imm)                       \
 280    anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),    \
 281                   .RegisterOffset = __anv_reg_num(reg), \
 282                   .DataDWord = imm)
 283
 284 void
 285 genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm)
 286 {
 287    /* References for GL state:
 288     *
 289     * - commits e307cfa..228d5a3
 290     * - src/mesa/drivers/dri/i965/gen7_l3_state.c
 291     */
 292
 293    uint32_t l3cr2_slm, l3cr2_noslm;
 294    anv_pack_struct(&l3cr2_noslm, GENX(L3CNTLREG2),
 295                    .URBAllocation = 24,
 296                    .ROAllocation = 0,
 297                    .DCAllocation = 16);
 298    anv_pack_struct(&l3cr2_slm, GENX(L3CNTLREG2),
 299                    .SLMEnable = 1,
 300                    .URBAllocation = 16,
 301                    .URBLowBandwidth = 1,
 302                    .ROAllocation = 0,
 303                    .DCAllocation = 8);
 304    const uint32_t l3cr2_val = enable_slm ? l3cr2_slm : l3cr2_noslm;
 305    bool changed = cmd_buffer->state.current_l3_config != l3cr2_val;
 306
 307    if (changed) {
 308       /* According to the hardware docs, the L3 partitioning can only be
 309        * changed while the pipeline is completely drained and the caches are
 310        * flushed, which involves a first PIPE_CONTROL flush which stalls the
 311        * pipeline...
 312        */
 313       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 314                      .DCFlushEnable = true,
 315                      .PostSyncOperation = NoWrite,
 316                      .CommandStreamerStallEnable = true);
 317
 318       /* ...followed by a second pipelined PIPE_CONTROL that initiates
 319        * invalidation of the relevant caches. Note that because RO
 320        * invalidation happens at the top of the pipeline (i.e. right away as
 321        * the PIPE_CONTROL command is processed by the CS) we cannot combine it
 322        * with the previous stalling flush as the hardware documentation
 323        * suggests, because that would cause the CS to stall on previous
 324        * rendering *after* RO invalidation and wouldn't prevent the RO caches
 325        * from being polluted by concurrent rendering before the stall
 326        * completes. This intentionally doesn't implement the SKL+ hardware
 327        * workaround suggesting to enable CS stall on PIPE_CONTROLs with the
 328        * texture cache invalidation bit set for GPGPU workloads because the
 329        * previous and subsequent PIPE_CONTROLs already guarantee that there is
 330        * no concurrent GPGPU kernel execution (see SKL HSD 2132585).
 331        */
 332       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 333                      .TextureCacheInvalidationEnable = true,
 334                      .ConstantCacheInvalidationEnable = true,
 335                      .InstructionCacheInvalidateEnable = true,
 336                      .StateCacheInvalidationEnable = true,
 337                      .PostSyncOperation = NoWrite);
 338
 339       /* Now send a third stalling flush to make sure that invalidation is
 340        * complete when the L3 configuration registers are modified.
 341        */
 342       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 343                      .DCFlushEnable = true,
 344                      .PostSyncOperation = NoWrite,
 345                      .CommandStreamerStallEnable = true);
 346
 347       anv_finishme("write GEN7_L3SQCREG1");
 348       emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG2), l3cr2_val);
 349
 350       uint32_t l3cr3_slm, l3cr3_noslm;
 351       anv_pack_struct(&l3cr3_noslm, GENX(L3CNTLREG3),
 352                       .ISAllocation = 8,
 353                       .CAllocation = 4,
 354                       .TAllocation = 8);
 355       anv_pack_struct(&l3cr3_slm, GENX(L3CNTLREG3),
 356                       .ISAllocation = 8,
 357                       .CAllocation = 8,
 358                       .TAllocation = 8);
 359       const uint32_t l3cr3_val = enable_slm ? l3cr3_slm : l3cr3_noslm;
 360       emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG3), l3cr3_val);
 361
 362       cmd_buffer->state.current_l3_config = l3cr2_val;
 363    }
 364 }
 365
 366 void
 367 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
 368 {
 369    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 370    const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
 371    VkResult result;
 372
 373    assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
 374
 375    bool needs_slm = cs_prog_data->base.total_shared > 0;
 376    genX(cmd_buffer_config_l3)(cmd_buffer, needs_slm);
 377
 378    genX(flush_pipeline_select_gpgpu)(cmd_buffer);
 379
 380    if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
 381       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 382
 383    if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
 384        (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
 385       /* FIXME: figure out descriptors for gen7 */
 386       result = flush_compute_descriptor_set(cmd_buffer);
 387       assert(result == VK_SUCCESS);
 388       cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
 389    }
 390
 391    cmd_buffer->state.compute_dirty = 0;
 392 }
 393
 394 void
 395 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 396 {
 397    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 398
 399    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 400                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 401                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
 402                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
 403
 404       const struct anv_image_view *iview =
 405          anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 406       const struct anv_image *image = iview ? iview->image : NULL;
 407       const struct anv_format *anv_format =
 408          iview ? anv_format_for_vk_format(iview->vk_format) : NULL;
 409       const bool has_depth = iview && anv_format->has_depth;
 410       const uint32_t depth_format = has_depth ?
 411          isl_surf_get_depth_format(&cmd_buffer->device->isl_dev,
 412                                    &image->depth_surface.isl) : D16_UNORM;
 413
 414       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 415       struct GENX(3DSTATE_SF) sf = {
 416          GENX(3DSTATE_SF_header),
 417          .DepthBufferSurfaceFormat = depth_format,
 418          .LineWidth = cmd_buffer->state.dynamic.line_width,
 419          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 420          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 421          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 422       };
 423       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 424
 425       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
 426    }
 427
 428    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 429                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 430       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 431       struct anv_state cc_state =
 432          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 433                                             GENX(COLOR_CALC_STATE_length) * 4,
 434                                             64);
 435       struct GENX(COLOR_CALC_STATE) cc = {
 436          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 437          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 438          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 439          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 440          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 441          .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 442       };
 443       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 444       if (!cmd_buffer->device->info.has_llc)
 445          anv_state_clflush(cc_state);
 446
 447       anv_batch_emit(&cmd_buffer->batch,
 448                      GENX(3DSTATE_CC_STATE_POINTERS),
 449                      .ColorCalcStatePointer = cc_state.offset);
 450    }
 451
 452    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 453                                   ANV_CMD_DIRTY_RENDER_TARGETS |
 454                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 455                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 456       uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
 457       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 458
 459       struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
 460          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 461          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 462
 463          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 464          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 465       };
 466       GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
 467
 468       struct anv_state ds_state =
 469          anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
 470                                       pipeline->gen7.depth_stencil_state,
 471                                       GENX(DEPTH_STENCIL_STATE_length), 64);
 472
 473       anv_batch_emit(&cmd_buffer->batch,
 474                      GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS),
 475                      .PointertoDEPTH_STENCIL_STATE = ds_state.offset);
 476    }
 477
 478    if (cmd_buffer->state.gen7.index_buffer &&
 479        cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 480                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 481       struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
 482       uint32_t offset = cmd_buffer->state.gen7.index_offset;
 483
 484 #if GEN_IS_HASWELL
 485       anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF,
 486                      .IndexedDrawCutIndexEnable = pipeline->primitive_restart,
 487                      .CutIndex = cmd_buffer->state.restart_index);
 488 #endif
 489
 490       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER),
 491 #if !GEN_IS_HASWELL
 492                      .CutIndexEnable = pipeline->primitive_restart,
 493 #endif
 494                      .IndexFormat = cmd_buffer->state.gen7.index_type,
 495                      .MemoryObjectControlState = GENX(MOCS),
 496                      .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
 497                      .BufferEndingAddress = { buffer->bo, buffer->offset + buffer->size });
 498    }
 499
 500    cmd_buffer->state.dirty = 0;
 501 }
 502
 503 void genX(CmdSetEvent)(
 504     VkCommandBuffer                             commandBuffer,
 505     VkEvent                                     event,
 506     VkPipelineStageFlags                        stageMask)
 507 {
 508    stub();
 509 }
 510
 511 void genX(CmdResetEvent)(
 512     VkCommandBuffer                             commandBuffer,
 513     VkEvent                                     event,
 514     VkPipelineStageFlags                        stageMask)
 515 {
 516    stub();
 517 }
 518
 519 void genX(CmdWaitEvents)(
 520     VkCommandBuffer                             commandBuffer,
 521     uint32_t                                    eventCount,
 522     const VkEvent*                              pEvents,
 523     VkPipelineStageFlags                        srcStageMask,
 524     VkPipelineStageFlags                        destStageMask,
 525     uint32_t                                    memoryBarrierCount,
 526     const VkMemoryBarrier*                      pMemoryBarriers,
 527     uint32_t                                    bufferMemoryBarrierCount,
 528     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 529     uint32_t                                    imageMemoryBarrierCount,
 530     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 531 {
 532    stub();
 533 }