src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #if GEN_GEN == 8
  36 void
  37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
  38 {
  39    uint32_t count = cmd_buffer->state.dynamic.viewport.count;
  40    const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
  41    struct anv_state sf_clip_state =
  42       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  43
  44    for (uint32_t i = 0; i < count; i++) {
  45       const VkViewport *vp = &viewports[i];
  46
  47       /* The gen7 state struct has just the matrix and guardband fields, the
  48        * gen8 struct adds the min/max viewport fields. */
  49       struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
  50          .ViewportMatrixElementm00 = vp->width / 2,
  51          .ViewportMatrixElementm11 = vp->height / 2,
  52          .ViewportMatrixElementm22 = 1.0,
  53          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  54          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  55          .ViewportMatrixElementm32 = 0.0,
  56          .XMinClipGuardband = -1.0f,
  57          .XMaxClipGuardband = 1.0f,
  58          .YMinClipGuardband = -1.0f,
  59          .YMaxClipGuardband = 1.0f,
  60          .XMinViewPort = vp->x,
  61          .XMaxViewPort = vp->x + vp->width - 1,
  62          .YMinViewPort = vp->y,
  63          .YMaxViewPort = vp->y + vp->height - 1,
  64       };
  65
  66       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
  67                                  &sf_clip_viewport);
  68    }
  69
  70    if (!cmd_buffer->device->info.has_llc)
  71       anv_state_clflush(sf_clip_state);
  72
  73    anv_batch_emit(&cmd_buffer->batch,
  74                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
  75       clip.SFClipViewportPointer = sf_clip_state.offset;
  76    }
  77 }
  78
  79 void
  80 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
  81                                     bool depth_clamp_enable)
  82 {
  83    uint32_t count = cmd_buffer->state.dynamic.viewport.count;
  84    const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
  85    struct anv_state cc_state =
  86       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  87
  88    for (uint32_t i = 0; i < count; i++) {
  89       const VkViewport *vp = &viewports[i];
  90
  91       struct GENX(CC_VIEWPORT) cc_viewport = {
  92          .MinimumDepth = depth_clamp_enable ? vp->minDepth : 0.0f,
  93          .MaximumDepth = depth_clamp_enable ? vp->maxDepth : 1.0f,
  94       };
  95
  96       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
  97    }
  98
  99    if (!cmd_buffer->device->info.has_llc)
 100       anv_state_clflush(cc_state);
 101
 102    anv_batch_emit(&cmd_buffer->batch,
 103                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
 104       cc.CCViewportPointer = cc_state.offset;
 105    }
 106 }
 107 #endif
 108
 109 static void
 110 __emit_genx_sf_state(struct anv_cmd_buffer *cmd_buffer)
 111 {
 112       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 113       struct GENX(3DSTATE_SF) sf = {
 114          GENX(3DSTATE_SF_header),
 115          .LineWidth = cmd_buffer->state.dynamic.line_width,
 116       };
 117       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 118       /* FIXME: gen9.fs */
 119       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 120                            cmd_buffer->state.pipeline->gen8.sf);
 121 }
 122
 123 #include "genxml/gen9_pack.h"
 124 static void
 125 __emit_gen9_sf_state(struct anv_cmd_buffer *cmd_buffer)
 126 {
 127       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 128       struct GEN9_3DSTATE_SF sf = {
 129          GEN9_3DSTATE_SF_header,
 130          .LineWidth = cmd_buffer->state.dynamic.line_width,
 131       };
 132       GEN9_3DSTATE_SF_pack(NULL, sf_dw, &sf);
 133       /* FIXME: gen9.fs */
 134       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 135                            cmd_buffer->state.pipeline->gen8.sf);
 136 }
 137
 138 static void
 139 __emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
 140 {
 141    if (cmd_buffer->device->info.is_cherryview)
 142       __emit_gen9_sf_state(cmd_buffer);
 143    else
 144       __emit_genx_sf_state(cmd_buffer);
 145 }
 146
 147 void
 148 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 149 {
 150    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 151
 152    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 153                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 154       __emit_sf_state(cmd_buffer);
 155    }
 156
 157    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 158                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 159       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 160       struct GENX(3DSTATE_RASTER) raster = {
 161          GENX(3DSTATE_RASTER_header),
 162          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 163          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 164          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 165       };
 166       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 167       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 168                            pipeline->gen8.raster);
 169    }
 170
 171    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 172     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 173     * across different state packets for gen8 and gen9. We handle that by
 174     * using a big old #if switch here.
 175     */
 176 #if GEN_GEN == 8
 177    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 178                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 179       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 180       struct anv_state cc_state =
 181          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 182                                             GENX(COLOR_CALC_STATE_length) * 4,
 183                                             64);
 184       struct GENX(COLOR_CALC_STATE) cc = {
 185          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 186          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 187          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 188          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 189          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 190          .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 191       };
 192       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 193
 194       if (!cmd_buffer->device->info.has_llc)
 195          anv_state_clflush(cc_state);
 196
 197       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 198          ccp.ColorCalcStatePointer        = cc_state.offset;
 199          ccp.ColorCalcStatePointerValid   = true;
 200       }
 201    }
 202
 203    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 204                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 205                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 206       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 207       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 208
 209       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 210          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 211
 212          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 213          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 214
 215          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 216          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 217       };
 218       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 219                                           &wm_depth_stencil);
 220
 221       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 222                            pipeline->gen8.wm_depth_stencil);
 223    }
 224 #else
 225    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 226       struct anv_state cc_state =
 227          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 228                                             GEN9_COLOR_CALC_STATE_length * 4,
 229                                             64);
 230       struct GEN9_COLOR_CALC_STATE cc = {
 231          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 232          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 233          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 234          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 235       };
 236       GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
 237
 238       if (!cmd_buffer->device->info.has_llc)
 239          anv_state_clflush(cc_state);
 240
 241       anv_batch_emit(&cmd_buffer->batch, GEN9_3DSTATE_CC_STATE_POINTERS, ccp) {
 242          ccp.ColorCalcStatePointer = cc_state.offset;
 243          ccp.ColorCalcStatePointerValid = true;
 244       }
 245    }
 246
 247    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 248                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 249                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 250                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 251       uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
 252       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 253       struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
 254          GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
 255
 256          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 257          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 258
 259          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 260          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 261
 262          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 263          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 264       };
 265       GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
 266
 267       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 268                            pipeline->gen9.wm_depth_stencil);
 269    }
 270 #endif
 271
 272    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 273                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 274       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
 275          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 276          vf.CutIndex                   = cmd_buffer->state.restart_index;
 277       }
 278    }
 279
 280    cmd_buffer->state.dirty = 0;
 281 }
 282
 283 void genX(CmdBindIndexBuffer)(
 284     VkCommandBuffer                             commandBuffer,
 285     VkBuffer                                    _buffer,
 286     VkDeviceSize                                offset,
 287     VkIndexType                                 indexType)
 288 {
 289    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 290    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 291
 292    static const uint32_t vk_to_gen_index_type[] = {
 293       [VK_INDEX_TYPE_UINT16]                    = INDEX_WORD,
 294       [VK_INDEX_TYPE_UINT32]                    = INDEX_DWORD,
 295    };
 296
 297    static const uint32_t restart_index_for_type[] = {
 298       [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 299       [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 300    };
 301
 302    cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 303
 304    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 305       ib.IndexFormat                = vk_to_gen_index_type[indexType];
 306       ib.MemoryObjectControlState   = GENX(MOCS);
 307       ib.BufferStartingAddress      =
 308          (struct anv_address) { buffer->bo, buffer->offset + offset };
 309       ib.BufferSize                 = buffer->size - offset;
 310    }
 311
 312    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 313 }
 314
 315 static VkResult
 316 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 317 {
 318    struct anv_device *device = cmd_buffer->device;
 319    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 320    struct anv_state surfaces = { 0, }, samplers = { 0, };
 321    VkResult result;
 322
 323    result = anv_cmd_buffer_emit_samplers(cmd_buffer,
 324                                          MESA_SHADER_COMPUTE, &samplers);
 325    if (result != VK_SUCCESS)
 326       return result;
 327    result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
 328                                               MESA_SHADER_COMPUTE, &surfaces);
 329    if (result != VK_SUCCESS)
 330       return result;
 331
 332    struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
 333
 334    const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
 335    const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
 336
 337    if (push_state.alloc_size) {
 338       anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
 339          curbe.CURBETotalDataLength    = push_state.alloc_size;
 340          curbe.CURBEDataStartAddress   = push_state.offset;
 341       }
 342    }
 343
 344    const uint32_t slm_size = encode_slm_size(GEN_GEN, prog_data->total_shared);
 345
 346    struct anv_state state =
 347       anv_state_pool_emit(&device->dynamic_state_pool,
 348                           GENX(INTERFACE_DESCRIPTOR_DATA), 64,
 349                           .KernelStartPointer = pipeline->cs_simd,
 350                           .KernelStartPointerHigh = 0,
 351                           .BindingTablePointer = surfaces.offset,
 352                           .BindingTableEntryCount = 0,
 353                           .SamplerStatePointer = samplers.offset,
 354                           .SamplerCount = 0,
 355                           .ConstantIndirectURBEntryReadLength =
 356                              cs_prog_data->push.per_thread.regs,
 357                           .ConstantURBEntryReadOffset = 0,
 358                           .BarrierEnable = cs_prog_data->uses_barrier,
 359                           .SharedLocalMemorySize = slm_size,
 360                           .NumberofThreadsinGPGPUThreadGroup =
 361                              cs_prog_data->threads,
 362                           .CrossThreadConstantDataReadLength =
 363                              cs_prog_data->push.cross_thread.regs);
 364
 365    uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
 366    anv_batch_emit(&cmd_buffer->batch,
 367                   GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
 368       mid.InterfaceDescriptorTotalLength        = size;
 369       mid.InterfaceDescriptorDataStartAddress   = state.offset;
 370    }
 371
 372    return VK_SUCCESS;
 373 }
 374
 375 void
 376 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
 377 {
 378    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 379    MAYBE_UNUSED VkResult result;
 380
 381    assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
 382
 383    genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->urb.l3_config);
 384
 385    genX(flush_pipeline_select_gpgpu)(cmd_buffer);
 386
 387    if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
 388       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 389
 390    if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
 391        (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
 392       result = flush_compute_descriptor_set(cmd_buffer);
 393       assert(result == VK_SUCCESS);
 394       cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
 395    }
 396
 397    cmd_buffer->state.compute_dirty = 0;
 398
 399    genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
 400 }
 401
 402
 403 /**
 404  * Emit the HZ_OP packet in the sequence specified by the BDW PRM section
 405  * entitled: "Optimized Depth Buffer Clear and/or Stencil Buffer Clear."
 406  *
 407  * \todo Enable Stencil Buffer-only clears
 408  */
 409 void
 410 genX(cmd_buffer_emit_hz_op)(struct anv_cmd_buffer *cmd_buffer,
 411                           enum blorp_hiz_op op)
 412 {
 413    struct anv_cmd_state *cmd_state = &cmd_buffer->state;
 414    const struct anv_image_view *iview =
 415       anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 416
 417    if (iview == NULL || !anv_image_has_hiz(iview->image))
 418       return;
 419
 420    const uint32_t ds = cmd_state->subpass->depth_stencil_attachment;
 421
 422    /* Section 7.4. of the Vulkan 1.0.27 spec states:
 423     *
 424     *   "The render area must be contained within the framebuffer dimensions."
 425     *
 426     * Therefore, the only way the extent of the render area can match that of
 427     * the image view is if the render area offset equals (0, 0).
 428     */
 429    const bool full_surface_op =
 430              cmd_state->render_area.extent.width == iview->extent.width &&
 431              cmd_state->render_area.extent.height == iview->extent.height;
 432    if (full_surface_op)
 433       assert(cmd_state->render_area.offset.x == 0 &&
 434              cmd_state->render_area.offset.y == 0);
 435
 436    /* This variable corresponds to the Pixel Dim column in the table below */
 437    struct isl_extent2d px_dim;
 438
 439    /* Validate that we can perform the HZ operation and that it's necessary. */
 440    switch (op) {
 441    case BLORP_HIZ_OP_DEPTH_CLEAR:
 442       if (cmd_buffer->state.pass->attachments[ds].load_op !=
 443           VK_ATTACHMENT_LOAD_OP_CLEAR)
 444          return;
 445
 446       /* Apply alignment restrictions. Despite the BDW PRM mentioning this is
 447        * only needed for a depth buffer surface type of D16_UNORM, testing
 448        * showed it to be necessary for other depth formats as well
 449        * (e.g., D32_FLOAT).
 450        */
 451 #if GEN_GEN == 8
 452       /* Pre-SKL, HiZ has an 8x4 sample block. As the number of samples
 453        * increases, the number of pixels representable by this block
 454        * decreases by a factor of the sample dimensions. Sample dimensions
 455        * scale following the MSAA interleaved pattern.
 456        *
 457        * Sample|Sample|Pixel
 458        * Count |Dim   |Dim
 459        * ===================
 460        *    1  | 1x1  | 8x4
 461        *    2  | 2x1  | 4x4
 462        *    4  | 2x2  | 4x2
 463        *    8  | 4x2  | 2x2
 464        *   16  | 4x4  | 2x1
 465        *
 466        * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
 467        */
 468       /* This variable corresponds to the Sample Dim column in the table
 469        * above.
 470        */
 471       const struct isl_extent2d sa_dim =
 472          isl_get_interleaved_msaa_px_size_sa(iview->image->samples);
 473       px_dim.w = 8 / sa_dim.w;
 474       px_dim.h = 4 / sa_dim.h;
 475 #elif GEN_GEN >= 9
 476       /* SKL+, the sample block becomes a "pixel block" so the expected
 477        * pixel dimension is a constant 8x4 px for all sample counts.
 478        */
 479       px_dim = (struct isl_extent2d) { .w = 8, .h = 4};
 480 #endif
 481
 482       if (!full_surface_op) {
 483          /* Fast depth clears clear an entire sample block at a time. As a
 484           * result, the rectangle must be aligned to the pixel dimensions of
 485           * a sample block for a successful operation.
 486           *
 487           * Fast clears can still work if the offset is aligned and the render
 488           * area offset + extent touches the edge of a depth buffer whose extent
 489           * is unaligned. This is because each physical HiZ miplevel is padded
 490           * by the px_dim. In this case, the size of the clear rectangle will be
 491           * padded later on in this function.
 492           */
 493          if (cmd_state->render_area.offset.x % px_dim.w ||
 494              cmd_state->render_area.offset.y % px_dim.h)
 495             return;
 496          if (cmd_state->render_area.offset.x +
 497              cmd_state->render_area.extent.width != iview->extent.width &&
 498              cmd_state->render_area.extent.width % px_dim.w)
 499             return;
 500          if (cmd_state->render_area.offset.y +
 501              cmd_state->render_area.extent.height != iview->extent.height &&
 502              cmd_state->render_area.extent.height % px_dim.h)
 503             return;
 504       }
 505       break;
 506    case BLORP_HIZ_OP_DEPTH_RESOLVE:
 507       if (cmd_buffer->state.pass->attachments[ds].store_op !=
 508           VK_ATTACHMENT_STORE_OP_STORE)
 509          return;
 510       break;
 511    case BLORP_HIZ_OP_HIZ_RESOLVE:
 512       if (cmd_buffer->state.pass->attachments[ds].load_op !=
 513           VK_ATTACHMENT_LOAD_OP_LOAD)
 514          return;
 515       break;
 516    case BLORP_HIZ_OP_NONE:
 517       unreachable("Invalid HiZ OP");
 518       break;
 519    }
 520
 521    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_WM_HZ_OP), hzp) {
 522       switch (op) {
 523       case BLORP_HIZ_OP_DEPTH_CLEAR:
 524          hzp.StencilBufferClearEnable = VK_IMAGE_ASPECT_STENCIL_BIT &
 525                             cmd_state->attachments[ds].pending_clear_aspects;
 526          hzp.DepthBufferClearEnable = VK_IMAGE_ASPECT_DEPTH_BIT &
 527                             cmd_state->attachments[ds].pending_clear_aspects;
 528          hzp.FullSurfaceDepthandStencilClear = full_surface_op;
 529          hzp.StencilClearValue =
 530             cmd_state->attachments[ds].clear_value.depthStencil.stencil & 0xff;
 531
 532          /* Mark aspects as cleared */
 533          cmd_state->attachments[ds].pending_clear_aspects = 0;
 534          break;
 535       case BLORP_HIZ_OP_DEPTH_RESOLVE:
 536          hzp.DepthBufferResolveEnable = true;
 537          break;
 538       case BLORP_HIZ_OP_HIZ_RESOLVE:
 539          hzp.HierarchicalDepthBufferResolveEnable = true;
 540          break;
 541       case BLORP_HIZ_OP_NONE:
 542          unreachable("Invalid HiZ OP");
 543          break;
 544       }
 545
 546       if (op != BLORP_HIZ_OP_DEPTH_CLEAR) {
 547          /* The Optimized HiZ resolve rectangle must be the size of the full RT
 548           * and aligned to 8x4. The non-optimized Depth resolve rectangle must
 549           * be the size of the full RT. The same alignment is assumed to be
 550           * required.
 551           */
 552          hzp.ClearRectangleXMin = 0;
 553          hzp.ClearRectangleYMin = 0;
 554          hzp.ClearRectangleXMax = align_u32(iview->extent.width, 8);
 555          hzp.ClearRectangleYMax = align_u32(iview->extent.height, 4);
 556       } else {
 557          /* This clear rectangle is aligned */
 558          hzp.ClearRectangleXMin = cmd_state->render_area.offset.x;
 559          hzp.ClearRectangleYMin = cmd_state->render_area.offset.y;
 560          hzp.ClearRectangleXMax = cmd_state->render_area.offset.x +
 561             align_u32(cmd_state->render_area.extent.width, px_dim.width);
 562          hzp.ClearRectangleYMax = cmd_state->render_area.offset.y +
 563             align_u32(cmd_state->render_area.extent.height, px_dim.height);
 564       }
 565
 566
 567       /* Due to a hardware issue, this bit MBZ */
 568       hzp.ScissorRectangleEnable = false;
 569       hzp.NumberofMultisamples = ffs(iview->image->samples) - 1;
 570       hzp.SampleMask = 0xFFFF;
 571    }
 572
 573    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 574       pc.PostSyncOperation = WriteImmediateData;
 575       pc.Address =
 576          (struct anv_address){ &cmd_buffer->device->workaround_bo, 0 };
 577    }
 578
 579    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_WM_HZ_OP), hzp);
 580
 581    if (!full_surface_op && op == BLORP_HIZ_OP_DEPTH_CLEAR) {
 582       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 583          pc.DepthStallEnable = true;
 584          pc.DepthCacheFlushEnable = true;
 585       }
 586    }
 587 }
 588
 589 void genX(CmdSetEvent)(
 590     VkCommandBuffer                             commandBuffer,
 591     VkEvent                                     _event,
 592     VkPipelineStageFlags                        stageMask)
 593 {
 594    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 595    ANV_FROM_HANDLE(anv_event, event, _event);
 596
 597    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 598       pc.DestinationAddressType  = DAT_PPGTT,
 599       pc.PostSyncOperation       = WriteImmediateData,
 600       pc.Address = (struct anv_address) {
 601          &cmd_buffer->device->dynamic_state_block_pool.bo,
 602          event->state.offset
 603       };
 604       pc.ImmediateData           = VK_EVENT_SET;
 605    }
 606 }
 607
 608 void genX(CmdResetEvent)(
 609     VkCommandBuffer                             commandBuffer,
 610     VkEvent                                     _event,
 611     VkPipelineStageFlags                        stageMask)
 612 {
 613    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 614    ANV_FROM_HANDLE(anv_event, event, _event);
 615
 616    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 617       pc.DestinationAddressType  = DAT_PPGTT;
 618       pc.PostSyncOperation       = WriteImmediateData;
 619       pc.Address = (struct anv_address) {
 620          &cmd_buffer->device->dynamic_state_block_pool.bo,
 621          event->state.offset
 622       };
 623       pc.ImmediateData           = VK_EVENT_RESET;
 624    }
 625 }
 626
 627 void genX(CmdWaitEvents)(
 628     VkCommandBuffer                             commandBuffer,
 629     uint32_t                                    eventCount,
 630     const VkEvent*                              pEvents,
 631     VkPipelineStageFlags                        srcStageMask,
 632     VkPipelineStageFlags                        destStageMask,
 633     uint32_t                                    memoryBarrierCount,
 634     const VkMemoryBarrier*                      pMemoryBarriers,
 635     uint32_t                                    bufferMemoryBarrierCount,
 636     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 637     uint32_t                                    imageMemoryBarrierCount,
 638     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 639 {
 640    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 641    for (uint32_t i = 0; i < eventCount; i++) {
 642       ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
 643
 644       anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT), sem) {
 645          sem.WaitMode            = PollingMode,
 646          sem.CompareOperation    = COMPARE_SAD_EQUAL_SDD,
 647          sem.SemaphoreDataDword  = VK_EVENT_SET,
 648          sem.SemaphoreAddress = (struct anv_address) {
 649             &cmd_buffer->device->dynamic_state_block_pool.bo,
 650             event->state.offset
 651          };
 652       }
 653    }
 654
 655    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 656                             false, /* byRegion */
 657                             memoryBarrierCount, pMemoryBarriers,
 658                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 659                             imageMemoryBarrierCount, pImageMemoryBarriers);
 660 }