src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34 #include "common/gen_guardband.h"
  35
  36 #if GEN_GEN == 8
  37 void
  38 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
  39 {
  40    struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
  41    uint32_t count = cmd_buffer->state.gfx.dynamic.viewport.count;
  42    const VkViewport *viewports =
  43       cmd_buffer->state.gfx.dynamic.viewport.viewports;
  44    struct anv_state sf_clip_state =
  45       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  46
  47    for (uint32_t i = 0; i < count; i++) {
  48       const VkViewport *vp = &viewports[i];
  49
  50       /* The gen7 state struct has just the matrix and guardband fields, the
  51        * gen8 struct adds the min/max viewport fields. */
  52       struct GENX(SF_CLIP_VIEWPORT) sfv = {
  53          .ViewportMatrixElementm00 = vp->width / 2,
  54          .ViewportMatrixElementm11 = vp->height / 2,
  55          .ViewportMatrixElementm22 = vp->maxDepth - vp->minDepth,
  56          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  57          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  58          .ViewportMatrixElementm32 = vp->minDepth,
  59          .XMinClipGuardband = -1.0f,
  60          .XMaxClipGuardband = 1.0f,
  61          .YMinClipGuardband = -1.0f,
  62          .YMaxClipGuardband = 1.0f,
  63          .XMinViewPort = vp->x,
  64          .XMaxViewPort = vp->x + vp->width - 1,
  65          .YMinViewPort = MIN2(vp->y, vp->y + vp->height),
  66          .YMaxViewPort = MAX2(vp->y, vp->y + vp->height) - 1,
  67       };
  68
  69       if (fb) {
  70          /* We can only calculate a "real" guardband clip if we know the
  71           * framebuffer at the time we emit the packet.  Otherwise, we have
  72           * fall back to a worst-case guardband of [-1, 1].
  73           */
  74          gen_calculate_guardband_size(fb->width, fb->height,
  75                                       sfv.ViewportMatrixElementm00,
  76                                       sfv.ViewportMatrixElementm11,
  77                                       sfv.ViewportMatrixElementm30,
  78                                       sfv.ViewportMatrixElementm31,
  79                                       &sfv.XMinClipGuardband,
  80                                       &sfv.XMaxClipGuardband,
  81                                       &sfv.YMinClipGuardband,
  82                                       &sfv.YMaxClipGuardband);
  83       }
  84
  85       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64, &sfv);
  86    }
  87
  88    anv_batch_emit(&cmd_buffer->batch,
  89                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
  90       clip.SFClipViewportPointer = sf_clip_state.offset;
  91    }
  92 }
  93
  94 void
  95 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
  96                                     bool depth_clamp_enable)
  97 {
  98    uint32_t count = cmd_buffer->state.gfx.dynamic.viewport.count;
  99    const VkViewport *viewports =
 100       cmd_buffer->state.gfx.dynamic.viewport.viewports;
 101    struct anv_state cc_state =
 102       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
 103
 104    for (uint32_t i = 0; i < count; i++) {
 105       const VkViewport *vp = &viewports[i];
 106
 107       /* From the Vulkan spec:
 108        *
 109        *    "It is valid for minDepth to be greater than or equal to
 110        *    maxDepth."
 111        */
 112       float min_depth = MIN2(vp->minDepth, vp->maxDepth);
 113       float max_depth = MAX2(vp->minDepth, vp->maxDepth);
 114
 115       struct GENX(CC_VIEWPORT) cc_viewport = {
 116          .MinimumDepth = depth_clamp_enable ? min_depth : 0.0f,
 117          .MaximumDepth = depth_clamp_enable ? max_depth : 1.0f,
 118       };
 119
 120       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
 121    }
 122
 123    anv_batch_emit(&cmd_buffer->batch,
 124                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
 125       cc.CCViewportPointer = cc_state.offset;
 126    }
 127 }
 128 #endif
 129
 130 void
 131 genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
 132 {
 133    if (cmd_buffer->state.pma_fix_enabled == enable)
 134       return;
 135
 136    cmd_buffer->state.pma_fix_enabled = enable;
 137
 138    /* According to the Broadwell PIPE_CONTROL documentation, software should
 139     * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
 140     * prior to the LRI.  If stencil buffer writes are enabled, then a Render
 141     * Cache Flush is also necessary.
 142     *
 143     * The Skylake docs say to use a depth stall rather than a command
 144     * streamer stall.  However, the hardware seems to violently disagree.
 145     * A full command streamer stall seems to be needed in both cases.
 146     */
 147    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 148       pc.DepthCacheFlushEnable = true;
 149       pc.CommandStreamerStallEnable = true;
 150       pc.RenderTargetCacheFlushEnable = true;
 151 #if GEN_GEN >= 12
 152       pc.TileCacheFlushEnable = true;
 153
 154       /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
 155        * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
 156        */
 157       pc.DepthStallEnable = true;
 158 #endif
 159    }
 160
 161 #if GEN_GEN == 9
 162
 163    uint32_t cache_mode;
 164    anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0),
 165                    .STCPMAOptimizationEnable = enable,
 166                    .STCPMAOptimizationEnableMask = true);
 167    anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 168       lri.RegisterOffset   = GENX(CACHE_MODE_0_num);
 169       lri.DataDWord        = cache_mode;
 170    }
 171
 172 #elif GEN_GEN == 8
 173
 174    uint32_t cache_mode;
 175    anv_pack_struct(&cache_mode, GENX(CACHE_MODE_1),
 176                    .NPPMAFixEnable = enable,
 177                    .NPEarlyZFailsDisable = enable,
 178                    .NPPMAFixEnableMask = true,
 179                    .NPEarlyZFailsDisableMask = true);
 180    anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 181       lri.RegisterOffset   = GENX(CACHE_MODE_1_num);
 182       lri.DataDWord        = cache_mode;
 183    }
 184
 185 #endif /* GEN_GEN == 8 */
 186
 187    /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
 188     * Flush bits is often necessary.  We do it regardless because it's easier.
 189     * The render cache flush is also necessary if stencil writes are enabled.
 190     *
 191     * Again, the Skylake docs give a different set of flushes but the BDW
 192     * flushes seem to work just as well.
 193     */
 194    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 195       pc.DepthStallEnable = true;
 196       pc.DepthCacheFlushEnable = true;
 197       pc.RenderTargetCacheFlushEnable = true;
 198 #if GEN_GEN >= 12
 199       pc.TileCacheFlushEnable = true;
 200 #endif
 201    }
 202 }
 203
 204 UNUSED static bool
 205 want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer)
 206 {
 207    assert(GEN_GEN == 8);
 208
 209    /* From the Broadwell PRM Vol. 2c CACHE_MODE_1::NP_PMA_FIX_ENABLE:
 210     *
 211     *    SW must set this bit in order to enable this fix when following
 212     *    expression is TRUE.
 213     *
 214     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 215     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
 216     *    (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 217     *    (3DSTATE_DEPTH_BUFFER::HIZ Enable) &&
 218     *    !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) &&
 219     *    (3DSTATE_PS_EXTRA::PixelShaderValid) &&
 220     *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 221     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 222     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 223     *      3DSTATE_WM_HZ_OP::StencilBufferClear) &&
 224     *    (3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable) &&
 225     *    (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 226     *       3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 227     *       3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 228     *       3DSTATE_PS_BLEND::AlphaTestEnable ||
 229     *       3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
 230     *      3DSTATE_WM::ForceKillPix != ForceOff &&
 231     *      ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 232     *        3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
 233     *       (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 234     *        3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
 235     *        3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
 236     *     (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 237     */
 238
 239    /* These are always true:
 240     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 241     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
 242     */
 243
 244    /* We only enable the PMA fix if we know for certain that HiZ is enabled.
 245     * If we don't know whether HiZ is enabled or not, we disable the PMA fix
 246     * and there is no harm.
 247     *
 248     * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 249     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 250     */
 251    if (!cmd_buffer->state.hiz_enabled)
 252       return false;
 253
 254    /* 3DSTATE_PS_EXTRA::PixelShaderValid */
 255    struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
 256    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT))
 257       return false;
 258
 259    /* !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) */
 260    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 261    if (wm_prog_data->early_fragment_tests)
 262       return false;
 263
 264    /* We never use anv_pipeline for HiZ ops so this is trivially true:
 265     *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 266     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 267     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 268     *      3DSTATE_WM_HZ_OP::StencilBufferClear)
 269     */
 270
 271    /* 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable */
 272    if (!pipeline->depth_test_enable)
 273       return false;
 274
 275    /* (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 276     *    3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 277     *    3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 278     *    3DSTATE_PS_BLEND::AlphaTestEnable ||
 279     *    3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
 280     *   3DSTATE_WM::ForceKillPix != ForceOff &&
 281     *   ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 282     *     3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
 283     *    (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 284     *     3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
 285     *     3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
 286     *  (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 287     */
 288    return (pipeline->kill_pixel && (pipeline->writes_depth ||
 289                                     pipeline->writes_stencil)) ||
 290           wm_prog_data->computed_depth_mode != PSCDEPTH_OFF;
 291 }
 292
 293 UNUSED static bool
 294 want_stencil_pma_fix(struct anv_cmd_buffer *cmd_buffer)
 295 {
 296    if (GEN_GEN > 9)
 297       return false;
 298    assert(GEN_GEN == 9);
 299
 300    /* From the Skylake PRM Vol. 2c CACHE_MODE_1::STC PMA Optimization Enable:
 301     *
 302     *    Clearing this bit will force the STC cache to wait for pending
 303     *    retirement of pixels at the HZ-read stage and do the STC-test for
 304     *    Non-promoted, R-computed and Computed depth modes instead of
 305     *    postponing the STC-test to RCPFE.
 306     *
 307     *    STC_TEST_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 308     *                  3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
 309     *
 310     *    STC_WRITE_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 311     *                   (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 312     *                    3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
 313     *
 314     *    COMP_STC_EN = STC_TEST_EN &&
 315     *                  3DSTATE_PS_EXTRA::PixelShaderComputesStencil
 316     *
 317     *    SW parses the pipeline states to generate the following logical
 318     *    signal indicating if PMA FIX can be enabled.
 319     *
 320     *    STC_PMA_OPT =
 321     *       3DSTATE_WM::ForceThreadDispatch != 1 &&
 322     *       !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
 323     *       3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
 324     *       3DSTATE_DEPTH_BUFFER::HIZ Enable &&
 325     *       !(3DSTATE_WM::EDSC_Mode == 2) &&
 326     *       3DSTATE_PS_EXTRA::PixelShaderValid &&
 327     *       !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 328     *         3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 329     *         3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 330     *         3DSTATE_WM_HZ_OP::StencilBufferClear) &&
 331     *       (COMP_STC_EN || STC_WRITE_EN) &&
 332     *       ((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 333     *         3DSTATE_WM::ForceKillPix == ON ||
 334     *         3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 335     *         3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 336     *         3DSTATE_PS_BLEND::AlphaTestEnable ||
 337     *         3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
 338     *        (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 339     */
 340
 341    /* These are always true:
 342     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 343     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
 344     */
 345
 346    /* We only enable the PMA fix if we know for certain that HiZ is enabled.
 347     * If we don't know whether HiZ is enabled or not, we disable the PMA fix
 348     * and there is no harm.
 349     *
 350     * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 351     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 352     */
 353    if (!cmd_buffer->state.hiz_enabled)
 354       return false;
 355
 356    /* We can't possibly know if HiZ is enabled without the framebuffer */
 357    assert(cmd_buffer->state.framebuffer);
 358
 359    /* HiZ is enabled so we had better have a depth buffer with HiZ */
 360    const struct anv_image_view *ds_iview =
 361       anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 362    assert(ds_iview && ds_iview->image->planes[0].aux_usage == ISL_AUX_USAGE_HIZ);
 363
 364    /* 3DSTATE_PS_EXTRA::PixelShaderValid */
 365    struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
 366    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT))
 367       return false;
 368
 369    /* !(3DSTATE_WM::EDSC_Mode == 2) */
 370    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 371    if (wm_prog_data->early_fragment_tests)
 372       return false;
 373
 374    /* We never use anv_pipeline for HiZ ops so this is trivially true:
 375    *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 376     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 377     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 378     *      3DSTATE_WM_HZ_OP::StencilBufferClear)
 379     */
 380
 381    /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 382     * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
 383     */
 384    const bool stc_test_en =
 385       (ds_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 386       pipeline->stencil_test_enable;
 387
 388    /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 389     * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 390     *  3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
 391     */
 392    const bool stc_write_en =
 393       (ds_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 394       (cmd_buffer->state.gfx.dynamic.stencil_write_mask.front ||
 395        cmd_buffer->state.gfx.dynamic.stencil_write_mask.back) &&
 396       pipeline->writes_stencil;
 397
 398    /* STC_TEST_EN && 3DSTATE_PS_EXTRA::PixelShaderComputesStencil */
 399    const bool comp_stc_en = stc_test_en && wm_prog_data->computed_stencil;
 400
 401    /* COMP_STC_EN || STC_WRITE_EN */
 402    if (!(comp_stc_en || stc_write_en))
 403       return false;
 404
 405    /* (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 406     *  3DSTATE_WM::ForceKillPix == ON ||
 407     *  3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 408     *  3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 409     *  3DSTATE_PS_BLEND::AlphaTestEnable ||
 410     *  3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
 411     * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF)
 412     */
 413    return pipeline->kill_pixel ||
 414           wm_prog_data->computed_depth_mode != PSCDEPTH_OFF;
 415 }
 416
 417 void
 418 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 419 {
 420    struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
 421    struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
 422
 423    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 424                                       ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 425       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 426       struct GENX(3DSTATE_SF) sf = {
 427          GENX(3DSTATE_SF_header),
 428       };
 429 #if GEN_GEN == 8
 430       if (cmd_buffer->device->info.is_cherryview) {
 431          sf.CHVLineWidth = d->line_width;
 432       } else {
 433          sf.LineWidth = d->line_width;
 434       }
 435 #else
 436       sf.LineWidth = d->line_width,
 437 #endif
 438       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 439       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen8.sf);
 440    }
 441
 442    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 443                                       ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 444       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 445       struct GENX(3DSTATE_RASTER) raster = {
 446          GENX(3DSTATE_RASTER_header),
 447          .GlobalDepthOffsetConstant = d->depth_bias.bias,
 448          .GlobalDepthOffsetScale = d->depth_bias.slope,
 449          .GlobalDepthOffsetClamp = d->depth_bias.clamp
 450       };
 451       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 452       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 453                            pipeline->gen8.raster);
 454    }
 455
 456    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 457     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 458     * across different state packets for gen8 and gen9. We handle that by
 459     * using a big old #if switch here.
 460     */
 461 #if GEN_GEN == 8
 462    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 463                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 464       struct anv_state cc_state =
 465          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 466                                             GENX(COLOR_CALC_STATE_length) * 4,
 467                                             64);
 468       struct GENX(COLOR_CALC_STATE) cc = {
 469          .BlendConstantColorRed = d->blend_constants[0],
 470          .BlendConstantColorGreen = d->blend_constants[1],
 471          .BlendConstantColorBlue = d->blend_constants[2],
 472          .BlendConstantColorAlpha = d->blend_constants[3],
 473          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 474          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 475       };
 476       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 477
 478       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 479          ccp.ColorCalcStatePointer        = cc_state.offset;
 480          ccp.ColorCalcStatePointerValid   = true;
 481       }
 482    }
 483
 484    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 485                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 486                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 487                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 488       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 489
 490       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 491          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 492
 493          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 494          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 495
 496          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 497          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 498
 499          .StencilBufferWriteEnable =
 500             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 501             pipeline->writes_stencil,
 502       };
 503       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 504                                           &wm_depth_stencil);
 505
 506       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 507                            pipeline->gen8.wm_depth_stencil);
 508
 509       genX(cmd_buffer_enable_pma_fix)(cmd_buffer,
 510                                       want_depth_pma_fix(cmd_buffer));
 511    }
 512 #else
 513    if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 514       struct anv_state cc_state =
 515          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 516                                             GENX(COLOR_CALC_STATE_length) * 4,
 517                                             64);
 518       struct GENX(COLOR_CALC_STATE) cc = {
 519          .BlendConstantColorRed = d->blend_constants[0],
 520          .BlendConstantColorGreen = d->blend_constants[1],
 521          .BlendConstantColorBlue = d->blend_constants[2],
 522          .BlendConstantColorAlpha = d->blend_constants[3],
 523       };
 524       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 525
 526       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 527          ccp.ColorCalcStatePointer = cc_state.offset;
 528          ccp.ColorCalcStatePointerValid = true;
 529       }
 530    }
 531
 532    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 533                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 534                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 535                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 536                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 537       uint32_t dwords[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 538       struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
 539          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 540
 541          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 542          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 543
 544          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 545          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 546
 547          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 548          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 549
 550          .StencilBufferWriteEnable =
 551             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 552             pipeline->writes_stencil,
 553       };
 554       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dwords, &wm_depth_stencil);
 555
 556       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 557                            pipeline->gen9.wm_depth_stencil);
 558
 559       genX(cmd_buffer_enable_pma_fix)(cmd_buffer,
 560                                       want_stencil_pma_fix(cmd_buffer));
 561    }
 562 #endif
 563
 564 #if GEN_GEN >= 12
 565    if(cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 566                                      ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)) {
 567       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BOUNDS), db) {
 568          db.DepthBoundsTestValueModifyDisable = false;
 569          db.DepthBoundsTestEnableModifyDisable = false;
 570          db.DepthBoundsTestEnable = pipeline->depth_bounds_test_enable;
 571          db.DepthBoundsTestMinValue = d->depth_bounds.min;
 572          db.DepthBoundsTestMaxValue = d->depth_bounds.max;
 573       }
 574    }
 575 #endif
 576
 577    if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE) {
 578       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) {
 579          ls.LineStipplePattern = d->line_stipple.pattern;
 580          ls.LineStippleInverseRepeatCount =
 581             1.0f / MAX2(1, d->line_stipple.factor);
 582          ls.LineStippleRepeatCount = d->line_stipple.factor;
 583       }
 584    }
 585
 586    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 587                                       ANV_CMD_DIRTY_INDEX_BUFFER)) {
 588       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
 589          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 590          vf.CutIndex                   = cmd_buffer->state.restart_index;
 591       }
 592    }
 593
 594    cmd_buffer->state.gfx.dirty = 0;
 595 }
 596
 597 static uint32_t vk_to_gen_index_type(VkIndexType type)
 598 {
 599    switch (type) {
 600    case VK_INDEX_TYPE_UINT8_EXT:
 601       return INDEX_BYTE;
 602    case VK_INDEX_TYPE_UINT16:
 603       return INDEX_WORD;
 604    case VK_INDEX_TYPE_UINT32:
 605       return INDEX_DWORD;
 606    default:
 607       unreachable("invalid index type");
 608    }
 609 }
 610
 611 static uint32_t restart_index_for_type(VkIndexType type)
 612 {
 613    switch (type) {
 614    case VK_INDEX_TYPE_UINT8_EXT:
 615       return UINT8_MAX;
 616    case VK_INDEX_TYPE_UINT16:
 617       return UINT16_MAX;
 618    case VK_INDEX_TYPE_UINT32:
 619       return UINT32_MAX;
 620    default:
 621       unreachable("invalid index type");
 622    }
 623 }
 624
 625 void genX(CmdBindIndexBuffer)(
 626     VkCommandBuffer                             commandBuffer,
 627     VkBuffer                                    _buffer,
 628     VkDeviceSize                                offset,
 629     VkIndexType                                 indexType)
 630 {
 631    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 632    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 633
 634    cmd_buffer->state.restart_index = restart_index_for_type(indexType);
 635
 636    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 637       ib.IndexFormat                = vk_to_gen_index_type(indexType);
 638       ib.MOCS                       = anv_mocs_for_bo(cmd_buffer->device,
 639                                                       buffer->address.bo);
 640       ib.BufferStartingAddress      = anv_address_add(buffer->address, offset);
 641       ib.BufferSize                 = buffer->size - offset;
 642    }
 643
 644    cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 645 }