src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #if GEN_GEN == 8
  36 void
  37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
  38 {
  39    uint32_t count = cmd_buffer->state.dynamic.viewport.count;
  40    const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
  41    struct anv_state sf_clip_state =
  42       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  43
  44    for (uint32_t i = 0; i < count; i++) {
  45       const VkViewport *vp = &viewports[i];
  46
  47       /* The gen7 state struct has just the matrix and guardband fields, the
  48        * gen8 struct adds the min/max viewport fields. */
  49       struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
  50          .ViewportMatrixElementm00 = vp->width / 2,
  51          .ViewportMatrixElementm11 = vp->height / 2,
  52          .ViewportMatrixElementm22 = vp->maxDepth - vp->minDepth,
  53          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  54          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  55          .ViewportMatrixElementm32 = vp->minDepth,
  56          .XMinClipGuardband = -1.0f,
  57          .XMaxClipGuardband = 1.0f,
  58          .YMinClipGuardband = -1.0f,
  59          .YMaxClipGuardband = 1.0f,
  60          .XMinViewPort = vp->x,
  61          .XMaxViewPort = vp->x + vp->width - 1,
  62          .YMinViewPort = MIN2(vp->y, vp->y + vp->height),
  63          .YMaxViewPort = MAX2(vp->y, vp->y + vp->height) - 1,
  64       };
  65
  66       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
  67                                  &sf_clip_viewport);
  68    }
  69
  70    anv_state_flush(cmd_buffer->device, sf_clip_state);
  71
  72    anv_batch_emit(&cmd_buffer->batch,
  73                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
  74       clip.SFClipViewportPointer = sf_clip_state.offset;
  75    }
  76 }
  77
  78 void
  79 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
  80                                     bool depth_clamp_enable)
  81 {
  82    uint32_t count = cmd_buffer->state.dynamic.viewport.count;
  83    const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
  84    struct anv_state cc_state =
  85       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  86
  87    for (uint32_t i = 0; i < count; i++) {
  88       const VkViewport *vp = &viewports[i];
  89
  90       struct GENX(CC_VIEWPORT) cc_viewport = {
  91          .MinimumDepth = depth_clamp_enable ? vp->minDepth : 0.0f,
  92          .MaximumDepth = depth_clamp_enable ? vp->maxDepth : 1.0f,
  93       };
  94
  95       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
  96    }
  97
  98    anv_state_flush(cmd_buffer->device, cc_state);
  99
 100    anv_batch_emit(&cmd_buffer->batch,
 101                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
 102       cc.CCViewportPointer = cc_state.offset;
 103    }
 104 }
 105 #endif
 106
 107 void
 108 genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
 109 {
 110    if (cmd_buffer->state.pma_fix_enabled == enable)
 111       return;
 112
 113    cmd_buffer->state.pma_fix_enabled = enable;
 114
 115    /* According to the Broadwell PIPE_CONTROL documentation, software should
 116     * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
 117     * prior to the LRI.  If stencil buffer writes are enabled, then a Render
 118     * Cache Flush is also necessary.
 119     *
 120     * The Skylake docs say to use a depth stall rather than a command
 121     * streamer stall.  However, the hardware seems to violently disagree.
 122     * A full command streamer stall seems to be needed in both cases.
 123     */
 124    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 125       pc.DepthCacheFlushEnable = true;
 126       pc.CommandStreamerStallEnable = true;
 127       pc.RenderTargetCacheFlushEnable = true;
 128    }
 129
 130 #if GEN_GEN == 9
 131
 132    uint32_t cache_mode;
 133    anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0),
 134                    .STCPMAOptimizationEnable = enable,
 135                    .STCPMAOptimizationEnableMask = true);
 136    anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 137       lri.RegisterOffset   = GENX(CACHE_MODE_0_num);
 138       lri.DataDWord        = cache_mode;
 139    }
 140
 141 #elif GEN_GEN == 8
 142
 143    uint32_t cache_mode;
 144    anv_pack_struct(&cache_mode, GENX(CACHE_MODE_1),
 145                    .NPPMAFixEnable = enable,
 146                    .NPEarlyZFailsDisable = enable,
 147                    .NPPMAFixEnableMask = true,
 148                    .NPEarlyZFailsDisableMask = true);
 149    anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 150       lri.RegisterOffset   = GENX(CACHE_MODE_1_num);
 151       lri.DataDWord        = cache_mode;
 152    }
 153
 154 #endif /* GEN_GEN == 8 */
 155
 156    /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
 157     * Flush bits is often necessary.  We do it regardless because it's easier.
 158     * The render cache flush is also necessary if stencil writes are enabled.
 159     *
 160     * Again, the Skylake docs give a different set of flushes but the BDW
 161     * flushes seem to work just as well.
 162     */
 163    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 164       pc.DepthStallEnable = true;
 165       pc.DepthCacheFlushEnable = true;
 166       pc.RenderTargetCacheFlushEnable = true;
 167    }
 168 }
 169
 170 UNUSED static bool
 171 want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer)
 172 {
 173    assert(GEN_GEN == 8);
 174
 175    /* From the Broadwell PRM Vol. 2c CACHE_MODE_1::NP_PMA_FIX_ENABLE:
 176     *
 177     *    SW must set this bit in order to enable this fix when following
 178     *    expression is TRUE.
 179     *
 180     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 181     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
 182     *    (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 183     *    (3DSTATE_DEPTH_BUFFER::HIZ Enable) &&
 184     *    !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) &&
 185     *    (3DSTATE_PS_EXTRA::PixelShaderValid) &&
 186     *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 187     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 188     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 189     *      3DSTATE_WM_HZ_OP::StencilBufferClear) &&
 190     *    (3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable) &&
 191     *    (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 192     *       3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 193     *       3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 194     *       3DSTATE_PS_BLEND::AlphaTestEnable ||
 195     *       3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
 196     *      3DSTATE_WM::ForceKillPix != ForceOff &&
 197     *      ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 198     *        3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
 199     *       (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 200     *        3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
 201     *        3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
 202     *     (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 203     */
 204
 205    /* These are always true:
 206     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 207     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
 208     */
 209
 210    /* We only enable the PMA fix if we know for certain that HiZ is enabled.
 211     * If we don't know whether HiZ is enabled or not, we disable the PMA fix
 212     * and there is no harm.
 213     *
 214     * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 215     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 216     */
 217    if (!cmd_buffer->state.hiz_enabled)
 218       return false;
 219
 220    /* 3DSTATE_PS_EXTRA::PixelShaderValid */
 221    struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
 222    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT))
 223       return false;
 224
 225    /* !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) */
 226    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 227    if (wm_prog_data->early_fragment_tests)
 228       return false;
 229
 230    /* We never use anv_pipeline for HiZ ops so this is trivially true:
 231     *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 232     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 233     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 234     *      3DSTATE_WM_HZ_OP::StencilBufferClear)
 235     */
 236
 237    /* 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable */
 238    if (!pipeline->depth_test_enable)
 239       return false;
 240
 241    /* (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 242     *    3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 243     *    3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 244     *    3DSTATE_PS_BLEND::AlphaTestEnable ||
 245     *    3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
 246     *   3DSTATE_WM::ForceKillPix != ForceOff &&
 247     *   ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 248     *     3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
 249     *    (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 250     *     3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
 251     *     3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
 252     *  (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 253     */
 254    return (pipeline->kill_pixel && (pipeline->writes_depth ||
 255                                     pipeline->writes_stencil)) ||
 256           wm_prog_data->computed_depth_mode != PSCDEPTH_OFF;
 257 }
 258
 259 UNUSED static bool
 260 want_stencil_pma_fix(struct anv_cmd_buffer *cmd_buffer)
 261 {
 262    if (GEN_GEN > 9)
 263       return false;
 264    assert(GEN_GEN == 9);
 265
 266    /* From the Skylake PRM Vol. 2c CACHE_MODE_1::STC PMA Optimization Enable:
 267     *
 268     *    Clearing this bit will force the STC cache to wait for pending
 269     *    retirement of pixels at the HZ-read stage and do the STC-test for
 270     *    Non-promoted, R-computed and Computed depth modes instead of
 271     *    postponing the STC-test to RCPFE.
 272     *
 273     *    STC_TEST_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 274     *                  3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
 275     *
 276     *    STC_WRITE_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 277     *                   (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 278     *                    3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
 279     *
 280     *    COMP_STC_EN = STC_TEST_EN &&
 281     *                  3DSTATE_PS_EXTRA::PixelShaderComputesStencil
 282     *
 283     *    SW parses the pipeline states to generate the following logical
 284     *    signal indicating if PMA FIX can be enabled.
 285     *
 286     *    STC_PMA_OPT =
 287     *       3DSTATE_WM::ForceThreadDispatch != 1 &&
 288     *       !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
 289     *       3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
 290     *       3DSTATE_DEPTH_BUFFER::HIZ Enable &&
 291     *       !(3DSTATE_WM::EDSC_Mode == 2) &&
 292     *       3DSTATE_PS_EXTRA::PixelShaderValid &&
 293     *       !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 294     *         3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 295     *         3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 296     *         3DSTATE_WM_HZ_OP::StencilBufferClear) &&
 297     *       (COMP_STC_EN || STC_WRITE_EN) &&
 298     *       ((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 299     *         3DSTATE_WM::ForceKillPix == ON ||
 300     *         3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 301     *         3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 302     *         3DSTATE_PS_BLEND::AlphaTestEnable ||
 303     *         3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
 304     *        (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 305     */
 306
 307    /* These are always true:
 308     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 309     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
 310     */
 311
 312    /* We only enable the PMA fix if we know for certain that HiZ is enabled.
 313     * If we don't know whether HiZ is enabled or not, we disable the PMA fix
 314     * and there is no harm.
 315     *
 316     * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 317     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 318     */
 319    if (!cmd_buffer->state.hiz_enabled)
 320       return false;
 321
 322    /* We can't possibly know if HiZ is enabled without the framebuffer */
 323    assert(cmd_buffer->state.framebuffer);
 324
 325    /* HiZ is enabled so we had better have a depth buffer with HiZ */
 326    const struct anv_image_view *ds_iview =
 327       anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 328    assert(ds_iview && ds_iview->image->planes[0].aux_usage == ISL_AUX_USAGE_HIZ);
 329
 330    /* 3DSTATE_PS_EXTRA::PixelShaderValid */
 331    struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
 332    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT))
 333       return false;
 334
 335    /* !(3DSTATE_WM::EDSC_Mode == 2) */
 336    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 337    if (wm_prog_data->early_fragment_tests)
 338       return false;
 339
 340    /* We never use anv_pipeline for HiZ ops so this is trivially true:
 341    *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 342     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 343     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 344     *      3DSTATE_WM_HZ_OP::StencilBufferClear)
 345     */
 346
 347    /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 348     * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
 349     */
 350    const bool stc_test_en =
 351       (ds_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 352       pipeline->stencil_test_enable;
 353
 354    /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 355     * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 356     *  3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
 357     */
 358    const bool stc_write_en =
 359       (ds_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 360       pipeline->writes_stencil;
 361
 362    /* STC_TEST_EN && 3DSTATE_PS_EXTRA::PixelShaderComputesStencil */
 363    const bool comp_stc_en = stc_test_en && wm_prog_data->computed_stencil;
 364
 365    /* COMP_STC_EN || STC_WRITE_EN */
 366    if (!(comp_stc_en || stc_write_en))
 367       return false;
 368
 369    /* (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 370     *  3DSTATE_WM::ForceKillPix == ON ||
 371     *  3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 372     *  3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 373     *  3DSTATE_PS_BLEND::AlphaTestEnable ||
 374     *  3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
 375     * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF)
 376     */
 377    return pipeline->kill_pixel ||
 378           wm_prog_data->computed_depth_mode != PSCDEPTH_OFF;
 379 }
 380
 381 void
 382 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 383 {
 384    struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
 385    struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 386
 387    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 388                                       ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 389       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 390       struct GENX(3DSTATE_SF) sf = {
 391          GENX(3DSTATE_SF_header),
 392       };
 393 #if GEN_GEN == 8
 394       if (cmd_buffer->device->info.is_cherryview) {
 395          sf.CHVLineWidth = d->line_width;
 396       } else {
 397          sf.LineWidth = d->line_width;
 398       }
 399 #else
 400       sf.LineWidth = d->line_width,
 401 #endif
 402       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 403       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen8.sf);
 404    }
 405
 406    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 407                                       ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 408       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 409       struct GENX(3DSTATE_RASTER) raster = {
 410          GENX(3DSTATE_RASTER_header),
 411          .GlobalDepthOffsetConstant = d->depth_bias.bias,
 412          .GlobalDepthOffsetScale = d->depth_bias.slope,
 413          .GlobalDepthOffsetClamp = d->depth_bias.clamp
 414       };
 415       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 416       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 417                            pipeline->gen8.raster);
 418    }
 419
 420    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 421     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 422     * across different state packets for gen8 and gen9. We handle that by
 423     * using a big old #if switch here.
 424     */
 425 #if GEN_GEN == 8
 426    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 427                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 428       struct anv_state cc_state =
 429          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 430                                             GENX(COLOR_CALC_STATE_length) * 4,
 431                                             64);
 432       struct GENX(COLOR_CALC_STATE) cc = {
 433          .BlendConstantColorRed = d->blend_constants[0],
 434          .BlendConstantColorGreen = d->blend_constants[1],
 435          .BlendConstantColorBlue = d->blend_constants[2],
 436          .BlendConstantColorAlpha = d->blend_constants[3],
 437          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 438          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 439       };
 440       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 441
 442       anv_state_flush(cmd_buffer->device, cc_state);
 443
 444       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 445          ccp.ColorCalcStatePointer        = cc_state.offset;
 446          ccp.ColorCalcStatePointerValid   = true;
 447       }
 448    }
 449
 450    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 451                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 452                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 453                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 454       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 455
 456       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 457          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 458
 459          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 460          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 461
 462          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 463          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 464
 465          .StencilBufferWriteEnable =
 466             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 467             pipeline->writes_stencil,
 468       };
 469       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 470                                           &wm_depth_stencil);
 471
 472       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 473                            pipeline->gen8.wm_depth_stencil);
 474
 475       genX(cmd_buffer_enable_pma_fix)(cmd_buffer,
 476                                       want_depth_pma_fix(cmd_buffer));
 477    }
 478 #else
 479    if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 480       struct anv_state cc_state =
 481          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 482                                             GENX(COLOR_CALC_STATE_length) * 4,
 483                                             64);
 484       struct GENX(COLOR_CALC_STATE) cc = {
 485          .BlendConstantColorRed = d->blend_constants[0],
 486          .BlendConstantColorGreen = d->blend_constants[1],
 487          .BlendConstantColorBlue = d->blend_constants[2],
 488          .BlendConstantColorAlpha = d->blend_constants[3],
 489       };
 490       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 491
 492       anv_state_flush(cmd_buffer->device, cc_state);
 493
 494       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 495          ccp.ColorCalcStatePointer = cc_state.offset;
 496          ccp.ColorCalcStatePointerValid = true;
 497       }
 498    }
 499
 500    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 501                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 502                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 503                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 504                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 505       uint32_t dwords[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 506       struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
 507          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 508
 509          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 510          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 511
 512          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 513          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 514
 515          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 516          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 517
 518          .StencilBufferWriteEnable =
 519             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 520             pipeline->writes_stencil,
 521       };
 522       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dwords, &wm_depth_stencil);
 523
 524       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 525                            pipeline->gen9.wm_depth_stencil);
 526
 527       genX(cmd_buffer_enable_pma_fix)(cmd_buffer,
 528                                       want_stencil_pma_fix(cmd_buffer));
 529    }
 530 #endif
 531
 532    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 533                                       ANV_CMD_DIRTY_INDEX_BUFFER)) {
 534       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
 535          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 536          vf.CutIndex                   = cmd_buffer->state.restart_index;
 537       }
 538    }
 539
 540    cmd_buffer->state.gfx.dirty = 0;
 541 }
 542
 543 void genX(CmdBindIndexBuffer)(
 544     VkCommandBuffer                             commandBuffer,
 545     VkBuffer                                    _buffer,
 546     VkDeviceSize                                offset,
 547     VkIndexType                                 indexType)
 548 {
 549    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 550    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 551
 552    static const uint32_t vk_to_gen_index_type[] = {
 553       [VK_INDEX_TYPE_UINT16]                    = INDEX_WORD,
 554       [VK_INDEX_TYPE_UINT32]                    = INDEX_DWORD,
 555    };
 556
 557    static const uint32_t restart_index_for_type[] = {
 558       [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 559       [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 560    };
 561
 562    cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 563
 564    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 565       ib.IndexFormat                = vk_to_gen_index_type[indexType];
 566       ib.MemoryObjectControlState   = GENX(MOCS);
 567       ib.BufferStartingAddress      =
 568          (struct anv_address) { buffer->bo, buffer->offset + offset };
 569       ib.BufferSize                 = buffer->size - offset;
 570    }
 571
 572    cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 573 }
 574
 575 /* Set of stage bits for which are pipelined, i.e. they get queued by the
 576  * command streamer for later execution.
 577  */
 578 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
 579    (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
 580     VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
 581     VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
 582     VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
 583     VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
 584     VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
 585     VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
 586     VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
 587     VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
 588     VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
 589     VK_PIPELINE_STAGE_TRANSFER_BIT | \
 590     VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
 591     VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
 592     VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
 593
 594 void genX(CmdSetEvent)(
 595     VkCommandBuffer                             commandBuffer,
 596     VkEvent                                     _event,
 597     VkPipelineStageFlags                        stageMask)
 598 {
 599    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 600    ANV_FROM_HANDLE(anv_event, event, _event);
 601
 602    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 603       if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
 604          pc.StallAtPixelScoreboard = true;
 605          pc.CommandStreamerStallEnable = true;
 606       }
 607
 608       pc.DestinationAddressType  = DAT_PPGTT,
 609       pc.PostSyncOperation       = WriteImmediateData,
 610       pc.Address = (struct anv_address) {
 611          &cmd_buffer->device->dynamic_state_pool.block_pool.bo,
 612          event->state.offset
 613       };
 614       pc.ImmediateData           = VK_EVENT_SET;
 615    }
 616 }
 617
 618 void genX(CmdResetEvent)(
 619     VkCommandBuffer                             commandBuffer,
 620     VkEvent                                     _event,
 621     VkPipelineStageFlags                        stageMask)
 622 {
 623    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 624    ANV_FROM_HANDLE(anv_event, event, _event);
 625
 626    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 627       if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
 628          pc.StallAtPixelScoreboard = true;
 629          pc.CommandStreamerStallEnable = true;
 630       }
 631
 632       pc.DestinationAddressType  = DAT_PPGTT;
 633       pc.PostSyncOperation       = WriteImmediateData;
 634       pc.Address = (struct anv_address) {
 635          &cmd_buffer->device->dynamic_state_pool.block_pool.bo,
 636          event->state.offset
 637       };
 638       pc.ImmediateData           = VK_EVENT_RESET;
 639    }
 640 }
 641
 642 void genX(CmdWaitEvents)(
 643     VkCommandBuffer                             commandBuffer,
 644     uint32_t                                    eventCount,
 645     const VkEvent*                              pEvents,
 646     VkPipelineStageFlags                        srcStageMask,
 647     VkPipelineStageFlags                        destStageMask,
 648     uint32_t                                    memoryBarrierCount,
 649     const VkMemoryBarrier*                      pMemoryBarriers,
 650     uint32_t                                    bufferMemoryBarrierCount,
 651     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 652     uint32_t                                    imageMemoryBarrierCount,
 653     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 654 {
 655    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 656    for (uint32_t i = 0; i < eventCount; i++) {
 657       ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
 658
 659       anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT), sem) {
 660          sem.WaitMode            = PollingMode,
 661          sem.CompareOperation    = COMPARE_SAD_EQUAL_SDD,
 662          sem.SemaphoreDataDword  = VK_EVENT_SET,
 663          sem.SemaphoreAddress = (struct anv_address) {
 664             &cmd_buffer->device->dynamic_state_pool.block_pool.bo,
 665             event->state.offset
 666          };
 667       }
 668    }
 669
 670    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 671                             false, /* byRegion */
 672                             memoryBarrierCount, pMemoryBarriers,
 673                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 674                             imageMemoryBarrierCount, pImageMemoryBarriers);
 675 }