src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #if GEN_GEN == 8
  36 void
  37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
  38 {
  39    uint32_t count = cmd_buffer->state.dynamic.viewport.count;
  40    const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
  41    struct anv_state sf_clip_state =
  42       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  43    struct anv_state cc_state =
  44       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  45
  46    for (uint32_t i = 0; i < count; i++) {
  47       const VkViewport *vp = &viewports[i];
  48
  49       /* The gen7 state struct has just the matrix and guardband fields, the
  50        * gen8 struct adds the min/max viewport fields. */
  51       struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
  52          .ViewportMatrixElementm00 = vp->width / 2,
  53          .ViewportMatrixElementm11 = vp->height / 2,
  54          .ViewportMatrixElementm22 = 1.0,
  55          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  56          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  57          .ViewportMatrixElementm32 = 0.0,
  58          .XMinClipGuardband = -1.0f,
  59          .XMaxClipGuardband = 1.0f,
  60          .YMinClipGuardband = -1.0f,
  61          .YMaxClipGuardband = 1.0f,
  62          .XMinViewPort = vp->x,
  63          .XMaxViewPort = vp->x + vp->width - 1,
  64          .YMinViewPort = vp->y,
  65          .YMaxViewPort = vp->y + vp->height - 1,
  66       };
  67
  68       struct GENX(CC_VIEWPORT) cc_viewport = {
  69          .MinimumDepth = vp->minDepth,
  70          .MaximumDepth = vp->maxDepth
  71       };
  72
  73       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
  74                                  &sf_clip_viewport);
  75       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
  76    }
  77
  78    if (!cmd_buffer->device->info.has_llc) {
  79       anv_state_clflush(sf_clip_state);
  80       anv_state_clflush(cc_state);
  81    }
  82
  83    anv_batch_emit(&cmd_buffer->batch,
  84                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
  85       cc.CCViewportPointer = cc_state.offset;
  86    }
  87    anv_batch_emit(&cmd_buffer->batch,
  88                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
  89       clip.SFClipViewportPointer = sf_clip_state.offset;
  90    }
  91 }
  92 #endif
  93
  94 void
  95 genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm)
  96 {
  97    /* References for GL state:
  98     *
  99     * - commits e307cfa..228d5a3
 100     * - src/mesa/drivers/dri/i965/gen7_l3_state.c
 101     */
 102
 103    uint32_t l3cr_slm, l3cr_noslm;
 104    anv_pack_struct(&l3cr_noslm, GENX(L3CNTLREG),
 105                    .URBAllocation = 48,
 106                    .AllAllocation = 48);
 107    anv_pack_struct(&l3cr_slm, GENX(L3CNTLREG),
 108                    .SLMEnable = 1,
 109                    .URBAllocation = 16,
 110                    .AllAllocation = 48);
 111    const uint32_t l3cr_val = enable_slm ? l3cr_slm : l3cr_noslm;
 112    bool changed = cmd_buffer->state.current_l3_config != l3cr_val;
 113
 114    if (changed) {
 115       /* According to the hardware docs, the L3 partitioning can only be
 116        * changed while the pipeline is completely drained and the caches are
 117        * flushed, which involves a first PIPE_CONTROL flush which stalls the
 118        * pipeline...
 119        */
 120       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 121          pc.DCFlushEnable              = true;
 122          pc.PostSyncOperation          = NoWrite;
 123          pc.CommandStreamerStallEnable = true;
 124       }
 125
 126       /* ...followed by a second pipelined PIPE_CONTROL that initiates
 127        * invalidation of the relevant caches. Note that because RO
 128        * invalidation happens at the top of the pipeline (i.e. right away as
 129        * the PIPE_CONTROL command is processed by the CS) we cannot combine it
 130        * with the previous stalling flush as the hardware documentation
 131        * suggests, because that would cause the CS to stall on previous
 132        * rendering *after* RO invalidation and wouldn't prevent the RO caches
 133        * from being polluted by concurrent rendering before the stall
 134        * completes. This intentionally doesn't implement the SKL+ hardware
 135        * workaround suggesting to enable CS stall on PIPE_CONTROLs with the
 136        * texture cache invalidation bit set for GPGPU workloads because the
 137        * previous and subsequent PIPE_CONTROLs already guarantee that there is
 138        * no concurrent GPGPU kernel execution (see SKL HSD 2132585).
 139        */
 140       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 141          pc.TextureCacheInvalidationEnable   = true,
 142          pc.ConstantCacheInvalidationEnable  = true,
 143          pc.InstructionCacheInvalidateEnable = true,
 144          pc.StateCacheInvalidationEnable     = true,
 145          pc.PostSyncOperation                = NoWrite;
 146       }
 147
 148       /* Now send a third stalling flush to make sure that invalidation is
 149        * complete when the L3 configuration registers are modified.
 150        */
 151       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 152          pc.DCFlushEnable              = true;
 153          pc.PostSyncOperation          = NoWrite;
 154          pc.CommandStreamerStallEnable = true;
 155       }
 156
 157       anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 158          lri.RegisterOffset   = GENX(L3CNTLREG_num);
 159          lri.DataDWord        = l3cr_val;
 160       }
 161       cmd_buffer->state.current_l3_config = l3cr_val;
 162    }
 163 }
 164
 165 static void
 166 __emit_genx_sf_state(struct anv_cmd_buffer *cmd_buffer)
 167 {
 168       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 169       struct GENX(3DSTATE_SF) sf = {
 170          GENX(3DSTATE_SF_header),
 171          .LineWidth = cmd_buffer->state.dynamic.line_width,
 172       };
 173       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 174       /* FIXME: gen9.fs */
 175       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 176                            cmd_buffer->state.pipeline->gen8.sf);
 177 }
 178
 179 #include "genxml/gen9_pack.h"
 180 static void
 181 __emit_gen9_sf_state(struct anv_cmd_buffer *cmd_buffer)
 182 {
 183       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 184       struct GEN9_3DSTATE_SF sf = {
 185          GEN9_3DSTATE_SF_header,
 186          .LineWidth = cmd_buffer->state.dynamic.line_width,
 187       };
 188       GEN9_3DSTATE_SF_pack(NULL, sf_dw, &sf);
 189       /* FIXME: gen9.fs */
 190       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 191                            cmd_buffer->state.pipeline->gen8.sf);
 192 }
 193
 194 static void
 195 __emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
 196 {
 197    if (cmd_buffer->device->info.is_cherryview)
 198       __emit_gen9_sf_state(cmd_buffer);
 199    else
 200       __emit_genx_sf_state(cmd_buffer);
 201 }
 202
 203 void
 204 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 205 {
 206    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 207
 208    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 209                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 210       __emit_sf_state(cmd_buffer);
 211    }
 212
 213    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 214                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 215       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 216       struct GENX(3DSTATE_RASTER) raster = {
 217          GENX(3DSTATE_RASTER_header),
 218          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 219          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 220          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 221       };
 222       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 223       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 224                            pipeline->gen8.raster);
 225    }
 226
 227    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 228     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 229     * across different state packets for gen8 and gen9. We handle that by
 230     * using a big old #if switch here.
 231     */
 232 #if GEN_GEN == 8
 233    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 234                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 235       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 236       struct anv_state cc_state =
 237          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 238                                             GENX(COLOR_CALC_STATE_length) * 4,
 239                                             64);
 240       struct GENX(COLOR_CALC_STATE) cc = {
 241          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 242          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 243          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 244          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 245          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 246          .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 247       };
 248       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 249
 250       if (!cmd_buffer->device->info.has_llc)
 251          anv_state_clflush(cc_state);
 252
 253       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 254          ccp.ColorCalcStatePointer        = cc_state.offset;
 255          ccp.ColorCalcStatePointerValid   = true;
 256       }
 257    }
 258
 259    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 260                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 261                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 262       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 263       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 264
 265       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 266          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 267
 268          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 269          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 270
 271          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 272          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 273       };
 274       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 275                                           &wm_depth_stencil);
 276
 277       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 278                            pipeline->gen8.wm_depth_stencil);
 279    }
 280 #else
 281    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 282       struct anv_state cc_state =
 283          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 284                                             GEN9_COLOR_CALC_STATE_length * 4,
 285                                             64);
 286       struct GEN9_COLOR_CALC_STATE cc = {
 287          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 288          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 289          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 290          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 291       };
 292       GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
 293
 294       if (!cmd_buffer->device->info.has_llc)
 295          anv_state_clflush(cc_state);
 296
 297       anv_batch_emit(&cmd_buffer->batch, GEN9_3DSTATE_CC_STATE_POINTERS, ccp) {
 298          ccp.ColorCalcStatePointer = cc_state.offset;
 299          ccp.ColorCalcStatePointerValid = true;
 300       }
 301    }
 302
 303    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 304                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 305                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 306                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 307       uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
 308       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 309       struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
 310          GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
 311
 312          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 313          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 314
 315          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 316          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 317
 318          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 319          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 320       };
 321       GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
 322
 323       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 324                            pipeline->gen9.wm_depth_stencil);
 325    }
 326 #endif
 327
 328    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 329                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 330       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
 331          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 332          vf.CutIndex                   = cmd_buffer->state.restart_index;
 333       }
 334    }
 335
 336    cmd_buffer->state.dirty = 0;
 337 }
 338
 339 void genX(CmdBindIndexBuffer)(
 340     VkCommandBuffer                             commandBuffer,
 341     VkBuffer                                    _buffer,
 342     VkDeviceSize                                offset,
 343     VkIndexType                                 indexType)
 344 {
 345    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 346    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 347
 348    static const uint32_t vk_to_gen_index_type[] = {
 349       [VK_INDEX_TYPE_UINT16]                    = INDEX_WORD,
 350       [VK_INDEX_TYPE_UINT32]                    = INDEX_DWORD,
 351    };
 352
 353    static const uint32_t restart_index_for_type[] = {
 354       [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 355       [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 356    };
 357
 358    cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 359
 360    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 361       ib.IndexFormat                = vk_to_gen_index_type[indexType];
 362       ib.MemoryObjectControlState   = GENX(MOCS);
 363       ib.BufferStartingAddress      =
 364          (struct anv_address) { buffer->bo, buffer->offset + offset };
 365       ib.BufferSize                 = buffer->size - offset;
 366    }
 367
 368    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 369 }
 370
 371 static VkResult
 372 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 373 {
 374    struct anv_device *device = cmd_buffer->device;
 375    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 376    struct anv_state surfaces = { 0, }, samplers = { 0, };
 377    VkResult result;
 378
 379    result = anv_cmd_buffer_emit_samplers(cmd_buffer,
 380                                          MESA_SHADER_COMPUTE, &samplers);
 381    if (result != VK_SUCCESS)
 382       return result;
 383    result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
 384                                               MESA_SHADER_COMPUTE, &surfaces);
 385    if (result != VK_SUCCESS)
 386       return result;
 387
 388    struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
 389
 390    const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
 391    const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
 392
 393    unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
 394    unsigned push_constant_data_size =
 395       (prog_data->nr_params + local_id_dwords) * 4;
 396    unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
 397    unsigned push_constant_regs = reg_aligned_constant_size / 32;
 398
 399    if (push_state.alloc_size) {
 400       anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
 401          curbe.CURBETotalDataLength    = push_state.alloc_size;
 402          curbe.CURBEDataStartAddress   = push_state.offset;
 403       }
 404    }
 405
 406    assert(prog_data->total_shared <= 64 * 1024);
 407    uint32_t slm_size = 0;
 408    if (prog_data->total_shared > 0) {
 409       /* slm_size is in 4k increments, but must be a power of 2. */
 410       slm_size = 4 * 1024;
 411       while (slm_size < prog_data->total_shared)
 412          slm_size <<= 1;
 413       slm_size /= 4 * 1024;
 414    }
 415
 416    struct anv_state state =
 417       anv_state_pool_emit(&device->dynamic_state_pool,
 418                           GENX(INTERFACE_DESCRIPTOR_DATA), 64,
 419                           .KernelStartPointer = pipeline->cs_simd,
 420                           .KernelStartPointerHigh = 0,
 421                           .BindingTablePointer = surfaces.offset,
 422                           .BindingTableEntryCount = 0,
 423                           .SamplerStatePointer = samplers.offset,
 424                           .SamplerCount = 0,
 425                           .ConstantIndirectURBEntryReadLength = push_constant_regs,
 426                           .ConstantURBEntryReadOffset = 0,
 427                           .BarrierEnable = cs_prog_data->uses_barrier,
 428                           .SharedLocalMemorySize = slm_size,
 429                           .NumberofThreadsinGPGPUThreadGroup =
 430                              pipeline->cs_thread_width_max);
 431
 432    uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
 433    anv_batch_emit(&cmd_buffer->batch,
 434                   GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
 435       mid.InterfaceDescriptorTotalLength        = size;
 436       mid.InterfaceDescriptorDataStartAddress   = state.offset;
 437    }
 438
 439    return VK_SUCCESS;
 440 }
 441
 442 void
 443 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
 444 {
 445    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 446    const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
 447    VkResult result;
 448
 449    assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
 450
 451    bool needs_slm = cs_prog_data->base.total_shared > 0;
 452    genX(cmd_buffer_config_l3)(cmd_buffer, needs_slm);
 453
 454    genX(flush_pipeline_select_gpgpu)(cmd_buffer);
 455
 456    if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
 457       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 458
 459    if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
 460        (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
 461       result = flush_compute_descriptor_set(cmd_buffer);
 462       assert(result == VK_SUCCESS);
 463       cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
 464    }
 465
 466    cmd_buffer->state.compute_dirty = 0;
 467 }
 468
 469 void genX(CmdSetEvent)(
 470     VkCommandBuffer                             commandBuffer,
 471     VkEvent                                     _event,
 472     VkPipelineStageFlags                        stageMask)
 473 {
 474    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 475    ANV_FROM_HANDLE(anv_event, event, _event);
 476
 477    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 478       pc.DestinationAddressType  = DAT_PPGTT,
 479       pc.PostSyncOperation       = WriteImmediateData,
 480       pc.Address = (struct anv_address) {
 481          &cmd_buffer->device->dynamic_state_block_pool.bo,
 482          event->state.offset
 483       };
 484       pc.ImmediateData           = VK_EVENT_SET;
 485    }
 486 }
 487
 488 void genX(CmdResetEvent)(
 489     VkCommandBuffer                             commandBuffer,
 490     VkEvent                                     _event,
 491     VkPipelineStageFlags                        stageMask)
 492 {
 493    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 494    ANV_FROM_HANDLE(anv_event, event, _event);
 495
 496    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 497       pc.DestinationAddressType  = DAT_PPGTT;
 498       pc.PostSyncOperation       = WriteImmediateData;
 499       pc.Address = (struct anv_address) {
 500          &cmd_buffer->device->dynamic_state_block_pool.bo,
 501          event->state.offset
 502       };
 503       pc.ImmediateData           = VK_EVENT_RESET;
 504    }
 505 }
 506
 507 void genX(CmdWaitEvents)(
 508     VkCommandBuffer                             commandBuffer,
 509     uint32_t                                    eventCount,
 510     const VkEvent*                              pEvents,
 511     VkPipelineStageFlags                        srcStageMask,
 512     VkPipelineStageFlags                        destStageMask,
 513     uint32_t                                    memoryBarrierCount,
 514     const VkMemoryBarrier*                      pMemoryBarriers,
 515     uint32_t                                    bufferMemoryBarrierCount,
 516     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 517     uint32_t                                    imageMemoryBarrierCount,
 518     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 519 {
 520    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 521    for (uint32_t i = 0; i < eventCount; i++) {
 522       ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
 523
 524       anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT), sem) {
 525          sem.WaitMode            = PollingMode,
 526          sem.CompareOperation    = COMPARE_SAD_EQUAL_SDD,
 527          sem.SemaphoreDataDword  = VK_EVENT_SET,
 528          sem.SemaphoreAddress = (struct anv_address) {
 529             &cmd_buffer->device->dynamic_state_block_pool.bo,
 530             event->state.offset
 531          };
 532       }
 533    }
 534
 535    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 536                             false, /* byRegion */
 537                             memoryBarrierCount, pMemoryBarriers,
 538                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 539                             imageMemoryBarrierCount, pImageMemoryBarriers);
 540 }