2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
37 emit_viewport_state(struct anv_cmd_buffer
*cmd_buffer
,
38 uint32_t count
, const VkViewport
*viewports
)
40 struct anv_state sf_clip_state
=
41 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 64, 64);
42 struct anv_state cc_state
=
43 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 8, 32);
45 for (uint32_t i
= 0; i
< count
; i
++) {
46 const VkViewport
*vp
= &viewports
[i
];
48 /* The gen7 state struct has just the matrix and guardband fields, the
49 * gen8 struct adds the min/max viewport fields. */
50 struct GENX(SF_CLIP_VIEWPORT
) sf_clip_viewport
= {
51 .ViewportMatrixElementm00
= vp
->width
/ 2,
52 .ViewportMatrixElementm11
= vp
->height
/ 2,
53 .ViewportMatrixElementm22
= 1.0,
54 .ViewportMatrixElementm30
= vp
->x
+ vp
->width
/ 2,
55 .ViewportMatrixElementm31
= vp
->y
+ vp
->height
/ 2,
56 .ViewportMatrixElementm32
= 0.0,
57 .XMinClipGuardband
= -1.0f
,
58 .XMaxClipGuardband
= 1.0f
,
59 .YMinClipGuardband
= -1.0f
,
60 .YMaxClipGuardband
= 1.0f
,
61 .XMinViewPort
= vp
->x
,
62 .XMaxViewPort
= vp
->x
+ vp
->width
- 1,
63 .YMinViewPort
= vp
->y
,
64 .YMaxViewPort
= vp
->y
+ vp
->height
- 1,
67 struct GENX(CC_VIEWPORT
) cc_viewport
= {
68 .MinimumDepth
= vp
->minDepth
,
69 .MaximumDepth
= vp
->maxDepth
72 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_state
.map
+ i
* 64,
74 GENX(CC_VIEWPORT_pack
)(NULL
, cc_state
.map
+ i
* 8, &cc_viewport
);
77 if (!cmd_buffer
->device
->info
.has_llc
) {
78 anv_state_clflush(sf_clip_state
);
79 anv_state_clflush(cc_state
);
82 anv_batch_emit(&cmd_buffer
->batch
,
83 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
),
84 .CCViewportPointer
= cc_state
.offset
);
85 anv_batch_emit(&cmd_buffer
->batch
,
86 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
),
87 .SFClipViewportPointer
= sf_clip_state
.offset
);
91 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
)
93 if (cmd_buffer
->state
.dynamic
.viewport
.count
> 0) {
94 emit_viewport_state(cmd_buffer
, cmd_buffer
->state
.dynamic
.viewport
.count
,
95 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
97 /* If viewport count is 0, this is taken to mean "use the default" */
98 emit_viewport_state(cmd_buffer
, 1,
102 .width
= cmd_buffer
->state
.framebuffer
->width
,
103 .height
= cmd_buffer
->state
.framebuffer
->height
,
111 #define emit_lri(batch, reg, imm) \
112 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), \
113 .RegisterOffset = __anv_reg_num(reg), \
117 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
, bool enable_slm
)
119 /* References for GL state:
121 * - commits e307cfa..228d5a3
122 * - src/mesa/drivers/dri/i965/gen7_l3_state.c
125 uint32_t l3cr_slm
, l3cr_noslm
;
126 anv_pack_struct(&l3cr_noslm
, GENX(L3CNTLREG
),
128 .AllAllocation
= 48);
129 anv_pack_struct(&l3cr_slm
, GENX(L3CNTLREG
),
132 .AllAllocation
= 48);
133 const uint32_t l3cr_val
= enable_slm
? l3cr_slm
: l3cr_noslm
;
134 bool changed
= cmd_buffer
->state
.current_l3_config
!= l3cr_val
;
137 /* According to the hardware docs, the L3 partitioning can only be
138 * changed while the pipeline is completely drained and the caches are
139 * flushed, which involves a first PIPE_CONTROL flush which stalls the
142 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
143 .DCFlushEnable
= true,
144 .PostSyncOperation
= NoWrite
,
145 .CommandStreamerStallEnable
= true);
147 /* ...followed by a second pipelined PIPE_CONTROL that initiates
148 * invalidation of the relevant caches. Note that because RO
149 * invalidation happens at the top of the pipeline (i.e. right away as
150 * the PIPE_CONTROL command is processed by the CS) we cannot combine it
151 * with the previous stalling flush as the hardware documentation
152 * suggests, because that would cause the CS to stall on previous
153 * rendering *after* RO invalidation and wouldn't prevent the RO caches
154 * from being polluted by concurrent rendering before the stall
155 * completes. This intentionally doesn't implement the SKL+ hardware
156 * workaround suggesting to enable CS stall on PIPE_CONTROLs with the
157 * texture cache invalidation bit set for GPGPU workloads because the
158 * previous and subsequent PIPE_CONTROLs already guarantee that there is
159 * no concurrent GPGPU kernel execution (see SKL HSD 2132585).
161 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
162 .TextureCacheInvalidationEnable
= true,
163 .ConstantCacheInvalidationEnable
= true,
164 .InstructionCacheInvalidateEnable
= true,
165 .PostSyncOperation
= NoWrite
);
167 /* Now send a third stalling flush to make sure that invalidation is
168 * complete when the L3 configuration registers are modified.
170 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
171 .DCFlushEnable
= true,
172 .PostSyncOperation
= NoWrite
,
173 .CommandStreamerStallEnable
= true);
175 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG
), l3cr_val
);
176 cmd_buffer
->state
.current_l3_config
= l3cr_val
;
181 __emit_genx_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
183 uint32_t sf_dw
[GENX(3DSTATE_SF_length
)];
184 struct GENX(3DSTATE_SF
) sf
= {
185 GENX(3DSTATE_SF_header
),
186 .LineWidth
= cmd_buffer
->state
.dynamic
.line_width
,
188 GENX(3DSTATE_SF_pack
)(NULL
, sf_dw
, &sf
);
190 anv_batch_emit_merge(&cmd_buffer
->batch
, sf_dw
,
191 cmd_buffer
->state
.pipeline
->gen8
.sf
);
194 #include "genxml/gen9_pack.h"
196 __emit_gen9_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
198 uint32_t sf_dw
[GENX(3DSTATE_SF_length
)];
199 struct GEN9_3DSTATE_SF sf
= {
200 GEN9_3DSTATE_SF_header
,
201 .LineWidth
= cmd_buffer
->state
.dynamic
.line_width
,
203 GEN9_3DSTATE_SF_pack(NULL
, sf_dw
, &sf
);
205 anv_batch_emit_merge(&cmd_buffer
->batch
, sf_dw
,
206 cmd_buffer
->state
.pipeline
->gen8
.sf
);
210 __emit_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
212 if (cmd_buffer
->device
->info
.is_cherryview
)
213 __emit_gen9_sf_state(cmd_buffer
);
215 __emit_genx_sf_state(cmd_buffer
);
219 genX(cmd_buffer_flush_dynamic_state
)(struct anv_cmd_buffer
*cmd_buffer
)
221 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
223 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
224 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)) {
225 __emit_sf_state(cmd_buffer
);
228 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
229 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)){
230 uint32_t raster_dw
[GENX(3DSTATE_RASTER_length
)];
231 struct GENX(3DSTATE_RASTER
) raster
= {
232 GENX(3DSTATE_RASTER_header
),
233 .GlobalDepthOffsetConstant
= cmd_buffer
->state
.dynamic
.depth_bias
.bias
,
234 .GlobalDepthOffsetScale
= cmd_buffer
->state
.dynamic
.depth_bias
.slope
,
235 .GlobalDepthOffsetClamp
= cmd_buffer
->state
.dynamic
.depth_bias
.clamp
237 GENX(3DSTATE_RASTER_pack
)(NULL
, raster_dw
, &raster
);
238 anv_batch_emit_merge(&cmd_buffer
->batch
, raster_dw
,
239 pipeline
->gen8
.raster
);
242 /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
243 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
244 * across different state packets for gen8 and gen9. We handle that by
245 * using a big old #if switch here.
248 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
|
249 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
250 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
251 struct anv_state cc_state
=
252 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
253 GENX(COLOR_CALC_STATE_length
) * 4,
255 struct GENX(COLOR_CALC_STATE
) cc
= {
256 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
257 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
258 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
259 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
260 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
261 .BackFaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
263 GENX(COLOR_CALC_STATE_pack
)(NULL
, cc_state
.map
, &cc
);
265 if (!cmd_buffer
->device
->info
.has_llc
)
266 anv_state_clflush(cc_state
);
268 anv_batch_emit(&cmd_buffer
->batch
,
269 GENX(3DSTATE_CC_STATE_POINTERS
),
270 .ColorCalcStatePointer
= cc_state
.offset
,
271 .ColorCalcStatePointerValid
= true);
274 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
275 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
276 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
)) {
277 uint32_t wm_depth_stencil_dw
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
278 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
280 struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
) = {
281 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
283 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
284 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
286 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
287 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
289 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, wm_depth_stencil_dw
,
292 anv_batch_emit_merge(&cmd_buffer
->batch
, wm_depth_stencil_dw
,
293 pipeline
->gen8
.wm_depth_stencil
);
296 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
) {
297 struct anv_state cc_state
=
298 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
299 GEN9_COLOR_CALC_STATE_length
* 4,
301 struct GEN9_COLOR_CALC_STATE cc
= {
302 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
303 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
304 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
305 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
307 GEN9_COLOR_CALC_STATE_pack(NULL
, cc_state
.map
, &cc
);
309 if (!cmd_buffer
->device
->info
.has_llc
)
310 anv_state_clflush(cc_state
);
312 anv_batch_emit(&cmd_buffer
->batch
,
313 GEN9_3DSTATE_CC_STATE_POINTERS
,
314 .ColorCalcStatePointer
= cc_state
.offset
,
315 .ColorCalcStatePointerValid
= true);
318 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
319 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
320 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
321 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
322 uint32_t dwords
[GEN9_3DSTATE_WM_DEPTH_STENCIL_length
];
323 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
324 struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
= {
325 GEN9_3DSTATE_WM_DEPTH_STENCIL_header
,
327 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
328 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
330 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
331 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
333 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
334 .BackfaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
336 GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL
, dwords
, &wm_depth_stencil
);
338 anv_batch_emit_merge(&cmd_buffer
->batch
, dwords
,
339 pipeline
->gen9
.wm_depth_stencil
);
343 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
344 ANV_CMD_DIRTY_INDEX_BUFFER
)) {
345 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_VF
),
346 .IndexedDrawCutIndexEnable
= pipeline
->primitive_restart
,
347 .CutIndex
= cmd_buffer
->state
.restart_index
,
351 cmd_buffer
->state
.dirty
= 0;
354 void genX(CmdBindIndexBuffer
)(
355 VkCommandBuffer commandBuffer
,
358 VkIndexType indexType
)
360 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
361 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
363 static const uint32_t vk_to_gen_index_type
[] = {
364 [VK_INDEX_TYPE_UINT16
] = INDEX_WORD
,
365 [VK_INDEX_TYPE_UINT32
] = INDEX_DWORD
,
368 static const uint32_t restart_index_for_type
[] = {
369 [VK_INDEX_TYPE_UINT16
] = UINT16_MAX
,
370 [VK_INDEX_TYPE_UINT32
] = UINT32_MAX
,
373 cmd_buffer
->state
.restart_index
= restart_index_for_type
[indexType
];
375 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_INDEX_BUFFER
),
376 .IndexFormat
= vk_to_gen_index_type
[indexType
],
377 .MemoryObjectControlState
= GENX(MOCS
),
378 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
379 .BufferSize
= buffer
->size
- offset
);
381 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_INDEX_BUFFER
;
385 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
387 struct anv_device
*device
= cmd_buffer
->device
;
388 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
389 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
392 result
= anv_cmd_buffer_emit_samplers(cmd_buffer
,
393 MESA_SHADER_COMPUTE
, &samplers
);
394 if (result
!= VK_SUCCESS
)
396 result
= anv_cmd_buffer_emit_binding_table(cmd_buffer
,
397 MESA_SHADER_COMPUTE
, &surfaces
);
398 if (result
!= VK_SUCCESS
)
401 struct anv_state push_state
= anv_cmd_buffer_cs_push_constants(cmd_buffer
);
403 const struct brw_cs_prog_data
*cs_prog_data
= get_cs_prog_data(pipeline
);
404 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
406 unsigned local_id_dwords
= cs_prog_data
->local_invocation_id_regs
* 8;
407 unsigned push_constant_data_size
=
408 (prog_data
->nr_params
+ local_id_dwords
) * 4;
409 unsigned reg_aligned_constant_size
= ALIGN(push_constant_data_size
, 32);
410 unsigned push_constant_regs
= reg_aligned_constant_size
/ 32;
412 if (push_state
.alloc_size
) {
413 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
),
414 .CURBETotalDataLength
= push_state
.alloc_size
,
415 .CURBEDataStartAddress
= push_state
.offset
);
418 assert(prog_data
->total_shared
<= 64 * 1024);
419 uint32_t slm_size
= 0;
420 if (prog_data
->total_shared
> 0) {
421 /* slm_size is in 4k increments, but must be a power of 2. */
423 while (slm_size
< prog_data
->total_shared
)
425 slm_size
/= 4 * 1024;
428 struct anv_state state
=
429 anv_state_pool_emit(&device
->dynamic_state_pool
,
430 GENX(INTERFACE_DESCRIPTOR_DATA
), 64,
431 .KernelStartPointer
= pipeline
->cs_simd
,
432 .KernelStartPointerHigh
= 0,
433 .BindingTablePointer
= surfaces
.offset
,
434 .BindingTableEntryCount
= 0,
435 .SamplerStatePointer
= samplers
.offset
,
437 .ConstantIndirectURBEntryReadLength
= push_constant_regs
,
438 .ConstantURBEntryReadOffset
= 0,
439 .BarrierEnable
= cs_prog_data
->uses_barrier
,
440 .SharedLocalMemorySize
= slm_size
,
441 .NumberofThreadsinGPGPUThreadGroup
=
442 pipeline
->cs_thread_width_max
);
444 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
445 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
),
446 .InterfaceDescriptorTotalLength
= size
,
447 .InterfaceDescriptorDataStartAddress
= state
.offset
);
453 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
455 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
456 const struct brw_cs_prog_data
*cs_prog_data
= get_cs_prog_data(pipeline
);
459 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
461 bool needs_slm
= cs_prog_data
->base
.total_shared
> 0;
462 genX(cmd_buffer_config_l3
)(cmd_buffer
, needs_slm
);
464 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
466 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)
467 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
469 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
470 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
471 result
= flush_compute_descriptor_set(cmd_buffer
);
472 assert(result
== VK_SUCCESS
);
473 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
476 cmd_buffer
->state
.compute_dirty
= 0;
479 void genX(CmdSetEvent
)(
480 VkCommandBuffer commandBuffer
,
482 VkPipelineStageFlags stageMask
)
484 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
485 ANV_FROM_HANDLE(anv_event
, event
, _event
);
487 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
488 .DestinationAddressType
= DAT_PPGTT
,
489 .PostSyncOperation
= WriteImmediateData
,
491 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
494 .ImmediateData
= VK_EVENT_SET
);
497 void genX(CmdResetEvent
)(
498 VkCommandBuffer commandBuffer
,
500 VkPipelineStageFlags stageMask
)
502 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
503 ANV_FROM_HANDLE(anv_event
, event
, _event
);
505 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
),
506 .DestinationAddressType
= DAT_PPGTT
,
507 .PostSyncOperation
= WriteImmediateData
,
509 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
512 .ImmediateData
= VK_EVENT_RESET
);
515 void genX(CmdWaitEvents
)(
516 VkCommandBuffer commandBuffer
,
518 const VkEvent
* pEvents
,
519 VkPipelineStageFlags srcStageMask
,
520 VkPipelineStageFlags destStageMask
,
521 uint32_t memoryBarrierCount
,
522 const VkMemoryBarrier
* pMemoryBarriers
,
523 uint32_t bufferMemoryBarrierCount
,
524 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
525 uint32_t imageMemoryBarrierCount
,
526 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
528 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
529 for (uint32_t i
= 0; i
< eventCount
; i
++) {
530 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
532 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
),
533 .WaitMode
= PollingMode
,
534 .CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
535 .SemaphoreDataDword
= VK_EVENT_SET
,
536 .SemaphoreAddress
= {
537 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
542 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
543 false, /* byRegion */
544 memoryBarrierCount
, pMemoryBarriers
,
545 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
546 imageMemoryBarrierCount
, pImageMemoryBarriers
);