src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #if GEN_GEN == 8
  36 void
  37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
  38 {
  39    uint32_t count = cmd_buffer->state.gfx.dynamic.viewport.count;
  40    const VkViewport *viewports =
  41       cmd_buffer->state.gfx.dynamic.viewport.viewports;
  42    struct anv_state sf_clip_state =
  43       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  44
  45    for (uint32_t i = 0; i < count; i++) {
  46       const VkViewport *vp = &viewports[i];
  47
  48       /* The gen7 state struct has just the matrix and guardband fields, the
  49        * gen8 struct adds the min/max viewport fields. */
  50       struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
  51          .ViewportMatrixElementm00 = vp->width / 2,
  52          .ViewportMatrixElementm11 = vp->height / 2,
  53          .ViewportMatrixElementm22 = vp->maxDepth - vp->minDepth,
  54          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  55          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  56          .ViewportMatrixElementm32 = vp->minDepth,
  57          .XMinClipGuardband = -1.0f,
  58          .XMaxClipGuardband = 1.0f,
  59          .YMinClipGuardband = -1.0f,
  60          .YMaxClipGuardband = 1.0f,
  61          .XMinViewPort = vp->x,
  62          .XMaxViewPort = vp->x + vp->width - 1,
  63          .YMinViewPort = MIN2(vp->y, vp->y + vp->height),
  64          .YMaxViewPort = MAX2(vp->y, vp->y + vp->height) - 1,
  65       };
  66
  67       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
  68                                  &sf_clip_viewport);
  69    }
  70
  71    anv_batch_emit(&cmd_buffer->batch,
  72                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
  73       clip.SFClipViewportPointer = sf_clip_state.offset;
  74    }
  75 }
  76
  77 void
  78 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
  79                                     bool depth_clamp_enable)
  80 {
  81    uint32_t count = cmd_buffer->state.gfx.dynamic.viewport.count;
  82    const VkViewport *viewports =
  83       cmd_buffer->state.gfx.dynamic.viewport.viewports;
  84    struct anv_state cc_state =
  85       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  86
  87    for (uint32_t i = 0; i < count; i++) {
  88       const VkViewport *vp = &viewports[i];
  89
  90       struct GENX(CC_VIEWPORT) cc_viewport = {
  91          .MinimumDepth = depth_clamp_enable ? vp->minDepth : 0.0f,
  92          .MaximumDepth = depth_clamp_enable ? vp->maxDepth : 1.0f,
  93       };
  94
  95       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
  96    }
  97
  98    anv_batch_emit(&cmd_buffer->batch,
  99                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
 100       cc.CCViewportPointer = cc_state.offset;
 101    }
 102 }
 103 #endif
 104
 105 void
 106 genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
 107 {
 108    if (cmd_buffer->state.pma_fix_enabled == enable)
 109       return;
 110
 111    cmd_buffer->state.pma_fix_enabled = enable;
 112
 113    /* According to the Broadwell PIPE_CONTROL documentation, software should
 114     * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
 115     * prior to the LRI.  If stencil buffer writes are enabled, then a Render
 116     * Cache Flush is also necessary.
 117     *
 118     * The Skylake docs say to use a depth stall rather than a command
 119     * streamer stall.  However, the hardware seems to violently disagree.
 120     * A full command streamer stall seems to be needed in both cases.
 121     */
 122    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 123       pc.DepthCacheFlushEnable = true;
 124       pc.CommandStreamerStallEnable = true;
 125       pc.RenderTargetCacheFlushEnable = true;
 126    }
 127
 128 #if GEN_GEN == 9
 129
 130    uint32_t cache_mode;
 131    anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0),
 132                    .STCPMAOptimizationEnable = enable,
 133                    .STCPMAOptimizationEnableMask = true);
 134    anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 135       lri.RegisterOffset   = GENX(CACHE_MODE_0_num);
 136       lri.DataDWord        = cache_mode;
 137    }
 138
 139 #elif GEN_GEN == 8
 140
 141    uint32_t cache_mode;
 142    anv_pack_struct(&cache_mode, GENX(CACHE_MODE_1),
 143                    .NPPMAFixEnable = enable,
 144                    .NPEarlyZFailsDisable = enable,
 145                    .NPPMAFixEnableMask = true,
 146                    .NPEarlyZFailsDisableMask = true);
 147    anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
 148       lri.RegisterOffset   = GENX(CACHE_MODE_1_num);
 149       lri.DataDWord        = cache_mode;
 150    }
 151
 152 #endif /* GEN_GEN == 8 */
 153
 154    /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
 155     * Flush bits is often necessary.  We do it regardless because it's easier.
 156     * The render cache flush is also necessary if stencil writes are enabled.
 157     *
 158     * Again, the Skylake docs give a different set of flushes but the BDW
 159     * flushes seem to work just as well.
 160     */
 161    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 162       pc.DepthStallEnable = true;
 163       pc.DepthCacheFlushEnable = true;
 164       pc.RenderTargetCacheFlushEnable = true;
 165    }
 166 }
 167
 168 UNUSED static bool
 169 want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer)
 170 {
 171    assert(GEN_GEN == 8);
 172
 173    /* From the Broadwell PRM Vol. 2c CACHE_MODE_1::NP_PMA_FIX_ENABLE:
 174     *
 175     *    SW must set this bit in order to enable this fix when following
 176     *    expression is TRUE.
 177     *
 178     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 179     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
 180     *    (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 181     *    (3DSTATE_DEPTH_BUFFER::HIZ Enable) &&
 182     *    !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) &&
 183     *    (3DSTATE_PS_EXTRA::PixelShaderValid) &&
 184     *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 185     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 186     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 187     *      3DSTATE_WM_HZ_OP::StencilBufferClear) &&
 188     *    (3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable) &&
 189     *    (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 190     *       3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 191     *       3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 192     *       3DSTATE_PS_BLEND::AlphaTestEnable ||
 193     *       3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
 194     *      3DSTATE_WM::ForceKillPix != ForceOff &&
 195     *      ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 196     *        3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
 197     *       (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 198     *        3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
 199     *        3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
 200     *     (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 201     */
 202
 203    /* These are always true:
 204     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 205     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
 206     */
 207
 208    /* We only enable the PMA fix if we know for certain that HiZ is enabled.
 209     * If we don't know whether HiZ is enabled or not, we disable the PMA fix
 210     * and there is no harm.
 211     *
 212     * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 213     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 214     */
 215    if (!cmd_buffer->state.hiz_enabled)
 216       return false;
 217
 218    /* 3DSTATE_PS_EXTRA::PixelShaderValid */
 219    struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
 220    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT))
 221       return false;
 222
 223    /* !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) */
 224    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 225    if (wm_prog_data->early_fragment_tests)
 226       return false;
 227
 228    /* We never use anv_pipeline for HiZ ops so this is trivially true:
 229     *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 230     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 231     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 232     *      3DSTATE_WM_HZ_OP::StencilBufferClear)
 233     */
 234
 235    /* 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable */
 236    if (!pipeline->depth_test_enable)
 237       return false;
 238
 239    /* (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 240     *    3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 241     *    3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 242     *    3DSTATE_PS_BLEND::AlphaTestEnable ||
 243     *    3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
 244     *   3DSTATE_WM::ForceKillPix != ForceOff &&
 245     *   ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
 246     *     3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
 247     *    (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 248     *     3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
 249     *     3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
 250     *  (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 251     */
 252    return (pipeline->kill_pixel && (pipeline->writes_depth ||
 253                                     pipeline->writes_stencil)) ||
 254           wm_prog_data->computed_depth_mode != PSCDEPTH_OFF;
 255 }
 256
 257 UNUSED static bool
 258 want_stencil_pma_fix(struct anv_cmd_buffer *cmd_buffer)
 259 {
 260    if (GEN_GEN > 9)
 261       return false;
 262    assert(GEN_GEN == 9);
 263
 264    /* From the Skylake PRM Vol. 2c CACHE_MODE_1::STC PMA Optimization Enable:
 265     *
 266     *    Clearing this bit will force the STC cache to wait for pending
 267     *    retirement of pixels at the HZ-read stage and do the STC-test for
 268     *    Non-promoted, R-computed and Computed depth modes instead of
 269     *    postponing the STC-test to RCPFE.
 270     *
 271     *    STC_TEST_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 272     *                  3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
 273     *
 274     *    STC_WRITE_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 275     *                   (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 276     *                    3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
 277     *
 278     *    COMP_STC_EN = STC_TEST_EN &&
 279     *                  3DSTATE_PS_EXTRA::PixelShaderComputesStencil
 280     *
 281     *    SW parses the pipeline states to generate the following logical
 282     *    signal indicating if PMA FIX can be enabled.
 283     *
 284     *    STC_PMA_OPT =
 285     *       3DSTATE_WM::ForceThreadDispatch != 1 &&
 286     *       !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
 287     *       3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
 288     *       3DSTATE_DEPTH_BUFFER::HIZ Enable &&
 289     *       !(3DSTATE_WM::EDSC_Mode == 2) &&
 290     *       3DSTATE_PS_EXTRA::PixelShaderValid &&
 291     *       !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 292     *         3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 293     *         3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 294     *         3DSTATE_WM_HZ_OP::StencilBufferClear) &&
 295     *       (COMP_STC_EN || STC_WRITE_EN) &&
 296     *       ((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 297     *         3DSTATE_WM::ForceKillPix == ON ||
 298     *         3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 299     *         3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 300     *         3DSTATE_PS_BLEND::AlphaTestEnable ||
 301     *         3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
 302     *        (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
 303     */
 304
 305    /* These are always true:
 306     *    3DSTATE_WM::ForceThreadDispatch != 1 &&
 307     *    !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
 308     */
 309
 310    /* We only enable the PMA fix if we know for certain that HiZ is enabled.
 311     * If we don't know whether HiZ is enabled or not, we disable the PMA fix
 312     * and there is no harm.
 313     *
 314     * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
 315     * 3DSTATE_DEPTH_BUFFER::HIZ Enable
 316     */
 317    if (!cmd_buffer->state.hiz_enabled)
 318       return false;
 319
 320    /* We can't possibly know if HiZ is enabled without the framebuffer */
 321    assert(cmd_buffer->state.framebuffer);
 322
 323    /* HiZ is enabled so we had better have a depth buffer with HiZ */
 324    const struct anv_image_view *ds_iview =
 325       anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
 326    assert(ds_iview && ds_iview->image->planes[0].aux_usage == ISL_AUX_USAGE_HIZ);
 327
 328    /* 3DSTATE_PS_EXTRA::PixelShaderValid */
 329    struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
 330    if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT))
 331       return false;
 332
 333    /* !(3DSTATE_WM::EDSC_Mode == 2) */
 334    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
 335    if (wm_prog_data->early_fragment_tests)
 336       return false;
 337
 338    /* We never use anv_pipeline for HiZ ops so this is trivially true:
 339    *    !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
 340     *      3DSTATE_WM_HZ_OP::DepthBufferResolve ||
 341     *      3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
 342     *      3DSTATE_WM_HZ_OP::StencilBufferClear)
 343     */
 344
 345    /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 346     * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
 347     */
 348    const bool stc_test_en =
 349       (ds_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 350       pipeline->stencil_test_enable;
 351
 352    /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
 353     * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
 354     *  3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
 355     */
 356    const bool stc_write_en =
 357       (ds_iview->image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
 358       pipeline->writes_stencil;
 359
 360    /* STC_TEST_EN && 3DSTATE_PS_EXTRA::PixelShaderComputesStencil */
 361    const bool comp_stc_en = stc_test_en && wm_prog_data->computed_stencil;
 362
 363    /* COMP_STC_EN || STC_WRITE_EN */
 364    if (!(comp_stc_en || stc_write_en))
 365       return false;
 366
 367    /* (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
 368     *  3DSTATE_WM::ForceKillPix == ON ||
 369     *  3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
 370     *  3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
 371     *  3DSTATE_PS_BLEND::AlphaTestEnable ||
 372     *  3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
 373     * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF)
 374     */
 375    return pipeline->kill_pixel ||
 376           wm_prog_data->computed_depth_mode != PSCDEPTH_OFF;
 377 }
 378
 379 void
 380 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 381 {
 382    struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
 383    struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
 384
 385    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 386                                       ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 387       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 388       struct GENX(3DSTATE_SF) sf = {
 389          GENX(3DSTATE_SF_header),
 390       };
 391 #if GEN_GEN == 8
 392       if (cmd_buffer->device->info.is_cherryview) {
 393          sf.CHVLineWidth = d->line_width;
 394       } else {
 395          sf.LineWidth = d->line_width;
 396       }
 397 #else
 398       sf.LineWidth = d->line_width,
 399 #endif
 400       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 401       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen8.sf);
 402    }
 403
 404    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 405                                       ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 406       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 407       struct GENX(3DSTATE_RASTER) raster = {
 408          GENX(3DSTATE_RASTER_header),
 409          .GlobalDepthOffsetConstant = d->depth_bias.bias,
 410          .GlobalDepthOffsetScale = d->depth_bias.slope,
 411          .GlobalDepthOffsetClamp = d->depth_bias.clamp
 412       };
 413       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 414       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 415                            pipeline->gen8.raster);
 416    }
 417
 418    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 419     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 420     * across different state packets for gen8 and gen9. We handle that by
 421     * using a big old #if switch here.
 422     */
 423 #if GEN_GEN == 8
 424    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 425                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 426       struct anv_state cc_state =
 427          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 428                                             GENX(COLOR_CALC_STATE_length) * 4,
 429                                             64);
 430       struct GENX(COLOR_CALC_STATE) cc = {
 431          .BlendConstantColorRed = d->blend_constants[0],
 432          .BlendConstantColorGreen = d->blend_constants[1],
 433          .BlendConstantColorBlue = d->blend_constants[2],
 434          .BlendConstantColorAlpha = d->blend_constants[3],
 435          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 436          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 437       };
 438       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 439
 440       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 441          ccp.ColorCalcStatePointer        = cc_state.offset;
 442          ccp.ColorCalcStatePointerValid   = true;
 443       }
 444    }
 445
 446    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 447                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 448                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 449                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 450       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 451
 452       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 453          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 454
 455          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 456          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 457
 458          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 459          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 460
 461          .StencilBufferWriteEnable =
 462             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 463             pipeline->writes_stencil,
 464       };
 465       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 466                                           &wm_depth_stencil);
 467
 468       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 469                            pipeline->gen8.wm_depth_stencil);
 470
 471       genX(cmd_buffer_enable_pma_fix)(cmd_buffer,
 472                                       want_depth_pma_fix(cmd_buffer));
 473    }
 474 #else
 475    if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 476       struct anv_state cc_state =
 477          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 478                                             GENX(COLOR_CALC_STATE_length) * 4,
 479                                             64);
 480       struct GENX(COLOR_CALC_STATE) cc = {
 481          .BlendConstantColorRed = d->blend_constants[0],
 482          .BlendConstantColorGreen = d->blend_constants[1],
 483          .BlendConstantColorBlue = d->blend_constants[2],
 484          .BlendConstantColorAlpha = d->blend_constants[3],
 485       };
 486       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 487
 488       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 489          ccp.ColorCalcStatePointer = cc_state.offset;
 490          ccp.ColorCalcStatePointerValid = true;
 491       }
 492    }
 493
 494    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 495                                       ANV_CMD_DIRTY_RENDER_TARGETS |
 496                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 497                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 498                                       ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 499       uint32_t dwords[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 500       struct GENX(3DSTATE_WM_DEPTH_STENCIL) wm_depth_stencil = {
 501          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 502
 503          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 504          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 505
 506          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 507          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 508
 509          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 510          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 511
 512          .StencilBufferWriteEnable =
 513             (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
 514             pipeline->writes_stencil,
 515       };
 516       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dwords, &wm_depth_stencil);
 517
 518       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 519                            pipeline->gen9.wm_depth_stencil);
 520
 521       genX(cmd_buffer_enable_pma_fix)(cmd_buffer,
 522                                       want_stencil_pma_fix(cmd_buffer));
 523    }
 524 #endif
 525
 526    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
 527                                       ANV_CMD_DIRTY_INDEX_BUFFER)) {
 528       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
 529          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 530          vf.CutIndex                   = cmd_buffer->state.restart_index;
 531       }
 532    }
 533
 534    cmd_buffer->state.gfx.dirty = 0;
 535 }
 536
 537 void genX(CmdBindIndexBuffer)(
 538     VkCommandBuffer                             commandBuffer,
 539     VkBuffer                                    _buffer,
 540     VkDeviceSize                                offset,
 541     VkIndexType                                 indexType)
 542 {
 543    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 544    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 545
 546    static const uint32_t vk_to_gen_index_type[] = {
 547       [VK_INDEX_TYPE_UINT16]                    = INDEX_WORD,
 548       [VK_INDEX_TYPE_UINT32]                    = INDEX_DWORD,
 549    };
 550
 551    static const uint32_t restart_index_for_type[] = {
 552       [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 553       [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 554    };
 555
 556    cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 557
 558    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 559       ib.IndexFormat                = vk_to_gen_index_type[indexType];
 560       ib.MOCS                       = anv_mocs_for_bo(cmd_buffer->device,
 561                                                       buffer->address.bo);
 562       ib.BufferStartingAddress      = anv_address_add(buffer->address, offset);
 563       ib.BufferSize                 = buffer->size - offset;
 564    }
 565
 566    cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 567 }
 568
 569 /* Set of stage bits for which are pipelined, i.e. they get queued by the
 570  * command streamer for later execution.
 571  */
 572 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
 573    (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
 574     VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
 575     VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
 576     VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
 577     VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
 578     VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
 579     VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
 580     VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
 581     VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
 582     VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
 583     VK_PIPELINE_STAGE_TRANSFER_BIT | \
 584     VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
 585     VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
 586     VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
 587
 588 void genX(CmdSetEvent)(
 589     VkCommandBuffer                             commandBuffer,
 590     VkEvent                                     _event,
 591     VkPipelineStageFlags                        stageMask)
 592 {
 593    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 594    ANV_FROM_HANDLE(anv_event, event, _event);
 595
 596    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 597       if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
 598          pc.StallAtPixelScoreboard = true;
 599          pc.CommandStreamerStallEnable = true;
 600       }
 601
 602       pc.DestinationAddressType  = DAT_PPGTT,
 603       pc.PostSyncOperation       = WriteImmediateData,
 604       pc.Address = (struct anv_address) {
 605          cmd_buffer->device->dynamic_state_pool.block_pool.bo,
 606          event->state.offset
 607       };
 608       pc.ImmediateData           = VK_EVENT_SET;
 609    }
 610 }
 611
 612 void genX(CmdResetEvent)(
 613     VkCommandBuffer                             commandBuffer,
 614     VkEvent                                     _event,
 615     VkPipelineStageFlags                        stageMask)
 616 {
 617    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 618    ANV_FROM_HANDLE(anv_event, event, _event);
 619
 620    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 621       if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
 622          pc.StallAtPixelScoreboard = true;
 623          pc.CommandStreamerStallEnable = true;
 624       }
 625
 626       pc.DestinationAddressType  = DAT_PPGTT;
 627       pc.PostSyncOperation       = WriteImmediateData;
 628       pc.Address = (struct anv_address) {
 629          cmd_buffer->device->dynamic_state_pool.block_pool.bo,
 630          event->state.offset
 631       };
 632       pc.ImmediateData           = VK_EVENT_RESET;
 633    }
 634 }
 635
 636 void genX(CmdWaitEvents)(
 637     VkCommandBuffer                             commandBuffer,
 638     uint32_t                                    eventCount,
 639     const VkEvent*                              pEvents,
 640     VkPipelineStageFlags                        srcStageMask,
 641     VkPipelineStageFlags                        destStageMask,
 642     uint32_t                                    memoryBarrierCount,
 643     const VkMemoryBarrier*                      pMemoryBarriers,
 644     uint32_t                                    bufferMemoryBarrierCount,
 645     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 646     uint32_t                                    imageMemoryBarrierCount,
 647     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 648 {
 649    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 650    for (uint32_t i = 0; i < eventCount; i++) {
 651       ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
 652
 653       anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT), sem) {
 654          sem.WaitMode            = PollingMode,
 655          sem.CompareOperation    = COMPARE_SAD_EQUAL_SDD,
 656          sem.SemaphoreDataDword  = VK_EVENT_SET,
 657          sem.SemaphoreAddress = (struct anv_address) {
 658             cmd_buffer->device->dynamic_state_pool.block_pool.bo,
 659             event->state.offset
 660          };
 661       }
 662    }
 663
 664    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 665                             false, /* byRegion */
 666                             memoryBarrierCount, pMemoryBarriers,
 667                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 668                             imageMemoryBarrierCount, pImageMemoryBarriers);
 669 }