src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 static uint32_t
  36 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
  37 {
  38    static const uint32_t push_constant_opcodes[] = {
  39       [MESA_SHADER_VERTEX]                      = 21,
  40       [MESA_SHADER_TESS_CTRL]                   = 25, /* HS */
  41       [MESA_SHADER_TESS_EVAL]                   = 26, /* DS */
  42       [MESA_SHADER_GEOMETRY]                    = 22,
  43       [MESA_SHADER_FRAGMENT]                    = 23,
  44       [MESA_SHADER_COMPUTE]                     = 0,
  45    };
  46
  47    VkShaderStageFlags flushed = 0;
  48
  49    anv_foreach_stage(stage, cmd_buffer->state.push_constants_dirty) {
  50       if (stage == MESA_SHADER_COMPUTE)
  51          continue;
  52
  53       struct anv_state state = anv_cmd_buffer_push_constants(cmd_buffer, stage);
  54
  55       if (state.offset == 0) {
  56          anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS),
  57                         ._3DCommandSubOpcode = push_constant_opcodes[stage]);
  58       } else {
  59          anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS),
  60                         ._3DCommandSubOpcode = push_constant_opcodes[stage],
  61                         .ConstantBody = {
  62                            .PointerToConstantBuffer2 = { &cmd_buffer->device->dynamic_state_block_pool.bo, state.offset },
  63                            .ConstantBuffer2ReadLength = DIV_ROUND_UP(state.alloc_size, 32),
  64                         });
  65       }
  66
  67       flushed |= mesa_to_vk_shader_stage(stage);
  68    }
  69
  70    cmd_buffer->state.push_constants_dirty &= ~flushed;
  71
  72    return flushed;
  73 }
  74
  75 #if GEN_GEN == 8
  76 static void
  77 emit_viewport_state(struct anv_cmd_buffer *cmd_buffer,
  78                     uint32_t count, const VkViewport *viewports)
  79 {
  80    struct anv_state sf_clip_state =
  81       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  82    struct anv_state cc_state =
  83       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  84
  85    for (uint32_t i = 0; i < count; i++) {
  86       const VkViewport *vp = &viewports[i];
  87
  88       /* The gen7 state struct has just the matrix and guardband fields, the
  89        * gen8 struct adds the min/max viewport fields. */
  90       struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
  91          .ViewportMatrixElementm00 = vp->width / 2,
  92          .ViewportMatrixElementm11 = vp->height / 2,
  93          .ViewportMatrixElementm22 = 1.0,
  94          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  95          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  96          .ViewportMatrixElementm32 = 0.0,
  97          .XMinClipGuardband = -1.0f,
  98          .XMaxClipGuardband = 1.0f,
  99          .YMinClipGuardband = -1.0f,
 100          .YMaxClipGuardband = 1.0f,
 101          .XMinViewPort = vp->x,
 102          .XMaxViewPort = vp->x + vp->width - 1,
 103          .YMinViewPort = vp->y,
 104          .YMaxViewPort = vp->y + vp->height - 1,
 105       };
 106
 107       struct GENX(CC_VIEWPORT) cc_viewport = {
 108          .MinimumDepth = vp->minDepth,
 109          .MaximumDepth = vp->maxDepth
 110       };
 111
 112       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
 113                                  &sf_clip_viewport);
 114       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
 115    }
 116
 117    if (!cmd_buffer->device->info.has_llc) {
 118       anv_state_clflush(sf_clip_state);
 119       anv_state_clflush(cc_state);
 120    }
 121
 122    anv_batch_emit(&cmd_buffer->batch,
 123                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC),
 124                   .CCViewportPointer = cc_state.offset);
 125    anv_batch_emit(&cmd_buffer->batch,
 126                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP),
 127                   .SFClipViewportPointer = sf_clip_state.offset);
 128 }
 129
 130 void
 131 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
 132 {
 133    if (cmd_buffer->state.dynamic.viewport.count > 0) {
 134       emit_viewport_state(cmd_buffer, cmd_buffer->state.dynamic.viewport.count,
 135                           cmd_buffer->state.dynamic.viewport.viewports);
 136    } else {
 137       /* If viewport count is 0, this is taken to mean "use the default" */
 138       emit_viewport_state(cmd_buffer, 1,
 139                           &(VkViewport) {
 140                              .x = 0.0f,
 141                              .y = 0.0f,
 142                              .width = cmd_buffer->state.framebuffer->width,
 143                              .height = cmd_buffer->state.framebuffer->height,
 144                              .minDepth = 0.0f,
 145                              .maxDepth = 1.0f,
 146                           });
 147    }
 148 }
 149 #endif
 150
 151 static void
 152 emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
 153 {
 154    anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),
 155                   .RegisterOffset = reg,
 156                   .DataDWord = imm);
 157 }
 158
 159 #define GEN8_L3CNTLREG                  0x7034
 160
 161 static void
 162 config_l3(struct anv_cmd_buffer *cmd_buffer, bool enable_slm)
 163 {
 164    /* References for GL state:
 165     *
 166     * - commits e307cfa..228d5a3
 167     * - src/mesa/drivers/dri/i965/gen7_l3_state.c
 168     */
 169
 170    uint32_t val = enable_slm ?
 171       /* All = 48 ways; URB = 16 ways; DC and RO = 0, SLM = 1 */
 172       0x60000021 :
 173       /* All = 48 ways; URB = 48 ways; DC, RO and SLM = 0 */
 174       0x60000060;
 175    bool changed = cmd_buffer->state.current_l3_config != val;
 176
 177    if (changed) {
 178       /* According to the hardware docs, the L3 partitioning can only be changed
 179        * while the pipeline is completely drained and the caches are flushed,
 180        * which involves a first PIPE_CONTROL flush which stalls the pipeline and
 181        * initiates invalidation of the relevant caches...
 182        */
 183       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 184                      .TextureCacheInvalidationEnable = true,
 185                      .ConstantCacheInvalidationEnable = true,
 186                      .InstructionCacheInvalidateEnable = true,
 187                      .DCFlushEnable = true,
 188                      .PostSyncOperation = NoWrite,
 189                      .CommandStreamerStallEnable = true);
 190
 191       /* ...followed by a second stalling flush which guarantees that
 192        * invalidation is complete when the L3 configuration registers are
 193        * modified.
 194        */
 195       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 196                      .DCFlushEnable = true,
 197                      .PostSyncOperation = NoWrite,
 198                      .CommandStreamerStallEnable = true);
 199
 200       emit_lri(&cmd_buffer->batch, GEN8_L3CNTLREG, val);
 201       cmd_buffer->state.current_l3_config = val;
 202    }
 203 }
 204
 205 static void
 206 __emit_genx_sf_state(struct anv_cmd_buffer *cmd_buffer)
 207 {
 208       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 209       struct GENX(3DSTATE_SF) sf = {
 210          GENX(3DSTATE_SF_header),
 211          .LineWidth = cmd_buffer->state.dynamic.line_width,
 212       };
 213       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 214       /* FIXME: gen9.fs */
 215       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 216                            cmd_buffer->state.pipeline->gen8.sf);
 217 }
 218
 219 #include "genxml/gen9_pack.h"
 220 static void
 221 __emit_gen9_sf_state(struct anv_cmd_buffer *cmd_buffer)
 222 {
 223       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 224       struct GEN9_3DSTATE_SF sf = {
 225          GEN9_3DSTATE_SF_header,
 226          .LineWidth = cmd_buffer->state.dynamic.line_width,
 227       };
 228       GEN9_3DSTATE_SF_pack(NULL, sf_dw, &sf);
 229       /* FIXME: gen9.fs */
 230       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 231                            cmd_buffer->state.pipeline->gen8.sf);
 232 }
 233
 234 static void
 235 __emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
 236 {
 237    if (cmd_buffer->device->info.is_cherryview)
 238       __emit_gen9_sf_state(cmd_buffer);
 239    else
 240       __emit_genx_sf_state(cmd_buffer);
 241 }
 242
 243 void
 244 genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
 245 {
 246    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 247    uint32_t *p;
 248
 249    uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
 250
 251    assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
 252
 253    config_l3(cmd_buffer, false);
 254
 255    genX(flush_pipeline_select_3d)(cmd_buffer);
 256
 257    if (vb_emit) {
 258       const uint32_t num_buffers = __builtin_popcount(vb_emit);
 259       const uint32_t num_dwords = 1 + num_buffers * 4;
 260
 261       p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
 262                           GENX(3DSTATE_VERTEX_BUFFERS));
 263       uint32_t vb, i = 0;
 264       for_each_bit(vb, vb_emit) {
 265          struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
 266          uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
 267
 268          struct GENX(VERTEX_BUFFER_STATE) state = {
 269             .VertexBufferIndex = vb,
 270             .MemoryObjectControlState = GENX(MOCS),
 271             .AddressModifyEnable = true,
 272             .BufferPitch = pipeline->binding_stride[vb],
 273             .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
 274             .BufferSize = buffer->size - offset
 275          };
 276
 277          GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, &p[1 + i * 4], &state);
 278          i++;
 279       }
 280    }
 281
 282    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_PIPELINE) {
 283       /* If somebody compiled a pipeline after starting a command buffer the
 284        * scratch bo may have grown since we started this cmd buffer (and
 285        * emitted STATE_BASE_ADDRESS).  If we're binding that pipeline now,
 286        * reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
 287       if (cmd_buffer->state.scratch_size < pipeline->total_scratch)
 288          anv_cmd_buffer_emit_state_base_address(cmd_buffer);
 289
 290       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 291
 292       /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
 293        *
 294        *    "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
 295        *    the next 3DPRIMITIVE command after programming the
 296        *    3DSTATE_PUSH_CONSTANT_ALLOC_VS"
 297        *
 298        * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
 299        * pipeline setup, we need to dirty push constants.
 300        */
 301       cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
 302    }
 303
 304    /* We emit the binding tables and sampler tables first, then emit push
 305     * constants and then finally emit binding table and sampler table
 306     * pointers.  It has to happen in this order, since emitting the binding
 307     * tables may change the push constants (in case of storage images). After
 308     * emitting push constants, on SKL+ we have to emit the corresponding
 309     * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
 310     */
 311    uint32_t dirty = 0;
 312    if (cmd_buffer->state.descriptors_dirty)
 313       dirty = gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer);
 314
 315    if (cmd_buffer->state.push_constants_dirty)
 316       dirty |= cmd_buffer_flush_push_constants(cmd_buffer);
 317
 318    if (dirty)
 319       gen7_cmd_buffer_emit_descriptor_pointers(cmd_buffer, dirty);
 320
 321    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT)
 322       gen8_cmd_buffer_emit_viewport(cmd_buffer);
 323
 324    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_SCISSOR)
 325       gen7_cmd_buffer_emit_scissor(cmd_buffer);
 326
 327    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 328                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 329       __emit_sf_state(cmd_buffer);
 330    }
 331
 332    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 333                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 334       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 335       struct GENX(3DSTATE_RASTER) raster = {
 336          GENX(3DSTATE_RASTER_header),
 337          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 338          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 339          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 340       };
 341       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 342       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 343                            pipeline->gen8.raster);
 344    }
 345
 346    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 347     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 348     * across different state packets for gen8 and gen9. We handle that by
 349     * using a big old #if switch here.
 350     */
 351 #if GEN_GEN == 8
 352    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 353                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 354       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 355       struct anv_state cc_state =
 356          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 357                                             GENX(COLOR_CALC_STATE_length) * 4,
 358                                             64);
 359       struct GENX(COLOR_CALC_STATE) cc = {
 360          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 361          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 362          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 363          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 364          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 365          .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 366       };
 367       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 368
 369       if (!cmd_buffer->device->info.has_llc)
 370          anv_state_clflush(cc_state);
 371
 372       anv_batch_emit(&cmd_buffer->batch,
 373                      GENX(3DSTATE_CC_STATE_POINTERS),
 374                      .ColorCalcStatePointer = cc_state.offset,
 375                      .ColorCalcStatePointerValid = true);
 376    }
 377
 378    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 379                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 380                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 381       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 382       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 383
 384       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 385          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 386
 387          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 388          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 389
 390          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 391          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 392       };
 393       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 394                                           &wm_depth_stencil);
 395
 396       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 397                            pipeline->gen8.wm_depth_stencil);
 398    }
 399 #else
 400    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 401       struct anv_state cc_state =
 402          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 403                                             GEN9_COLOR_CALC_STATE_length * 4,
 404                                             64);
 405       struct GEN9_COLOR_CALC_STATE cc = {
 406          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 407          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 408          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 409          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 410       };
 411       GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
 412
 413       if (!cmd_buffer->device->info.has_llc)
 414          anv_state_clflush(cc_state);
 415
 416       anv_batch_emit(&cmd_buffer->batch,
 417                      GEN9_3DSTATE_CC_STATE_POINTERS,
 418                      .ColorCalcStatePointer = cc_state.offset,
 419                      .ColorCalcStatePointerValid = true);
 420    }
 421
 422    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 423                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 424                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 425                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 426       uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
 427       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 428       struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
 429          GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
 430
 431          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 432          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 433
 434          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 435          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 436
 437          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 438          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 439       };
 440       GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
 441
 442       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 443                            pipeline->gen9.wm_depth_stencil);
 444    }
 445 #endif
 446
 447    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 448                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 449       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF),
 450          .IndexedDrawCutIndexEnable = pipeline->primitive_restart,
 451          .CutIndex = cmd_buffer->state.restart_index,
 452       );
 453    }
 454
 455    cmd_buffer->state.vb_dirty &= ~vb_emit;
 456    cmd_buffer->state.dirty = 0;
 457 }
 458
 459 void genX(CmdBindIndexBuffer)(
 460     VkCommandBuffer                             commandBuffer,
 461     VkBuffer                                    _buffer,
 462     VkDeviceSize                                offset,
 463     VkIndexType                                 indexType)
 464 {
 465    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 466    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 467
 468    static const uint32_t vk_to_gen_index_type[] = {
 469       [VK_INDEX_TYPE_UINT16]                    = INDEX_WORD,
 470       [VK_INDEX_TYPE_UINT32]                    = INDEX_DWORD,
 471    };
 472
 473    static const uint32_t restart_index_for_type[] = {
 474       [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 475       [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 476    };
 477
 478    cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 479
 480    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER),
 481                   .IndexFormat = vk_to_gen_index_type[indexType],
 482                   .MemoryObjectControlState = GENX(MOCS),
 483                   .BufferStartingAddress = { buffer->bo, buffer->offset + offset },
 484                   .BufferSize = buffer->size - offset);
 485
 486    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 487 }
 488
 489 static VkResult
 490 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 491 {
 492    struct anv_device *device = cmd_buffer->device;
 493    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 494    struct anv_state surfaces = { 0, }, samplers = { 0, };
 495    VkResult result;
 496
 497    result = anv_cmd_buffer_emit_samplers(cmd_buffer,
 498                                          MESA_SHADER_COMPUTE, &samplers);
 499    if (result != VK_SUCCESS)
 500       return result;
 501    result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
 502                                               MESA_SHADER_COMPUTE, &surfaces);
 503    if (result != VK_SUCCESS)
 504       return result;
 505
 506    struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
 507
 508    const struct brw_cs_prog_data *cs_prog_data = &pipeline->cs_prog_data;
 509    const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
 510
 511    unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
 512    unsigned push_constant_data_size =
 513       (prog_data->nr_params + local_id_dwords) * 4;
 514    unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
 515    unsigned push_constant_regs = reg_aligned_constant_size / 32;
 516
 517    if (push_state.alloc_size) {
 518       anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD),
 519                      .CURBETotalDataLength = push_state.alloc_size,
 520                      .CURBEDataStartAddress = push_state.offset);
 521    }
 522
 523    assert(prog_data->total_shared <= 64 * 1024);
 524    uint32_t slm_size = 0;
 525    if (prog_data->total_shared > 0) {
 526       /* slm_size is in 4k increments, but must be a power of 2. */
 527       slm_size = 4 * 1024;
 528       while (slm_size < prog_data->total_shared)
 529          slm_size <<= 1;
 530       slm_size /= 4 * 1024;
 531    }
 532
 533    struct anv_state state =
 534       anv_state_pool_emit(&device->dynamic_state_pool,
 535                           GENX(INTERFACE_DESCRIPTOR_DATA), 64,
 536                           .KernelStartPointer = pipeline->cs_simd,
 537                           .KernelStartPointerHigh = 0,
 538                           .BindingTablePointer = surfaces.offset,
 539                           .BindingTableEntryCount = 0,
 540                           .SamplerStatePointer = samplers.offset,
 541                           .SamplerCount = 0,
 542                           .ConstantIndirectURBEntryReadLength = push_constant_regs,
 543                           .ConstantURBEntryReadOffset = 0,
 544                           .BarrierEnable = cs_prog_data->uses_barrier,
 545                           .SharedLocalMemorySize = slm_size,
 546                           .NumberofThreadsinGPGPUThreadGroup =
 547                              pipeline->cs_thread_width_max);
 548
 549    uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
 550    anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD),
 551                   .InterfaceDescriptorTotalLength = size,
 552                   .InterfaceDescriptorDataStartAddress = state.offset);
 553
 554    return VK_SUCCESS;
 555 }
 556
 557 void
 558 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
 559 {
 560    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 561    VkResult result;
 562
 563    assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
 564
 565    bool needs_slm = pipeline->cs_prog_data.base.total_shared > 0;
 566    config_l3(cmd_buffer, needs_slm);
 567
 568    if (cmd_buffer->state.current_pipeline != GPGPU) {
 569 #if GEN_GEN < 10
 570       /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
 571        *
 572        *   Software must clear the COLOR_CALC_STATE Valid field in
 573        *   3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
 574        *   with Pipeline Select set to GPGPU.
 575        *
 576        * The internal hardware docs recommend the same workaround for Gen9
 577        * hardware too.
 578        */
 579       anv_batch_emit(&cmd_buffer->batch,
 580                      GENX(3DSTATE_CC_STATE_POINTERS));
 581 #endif
 582
 583       anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
 584 #if GEN_GEN >= 9
 585                      .MaskBits = 3,
 586 #endif
 587                      .PipelineSelection = GPGPU);
 588       cmd_buffer->state.current_pipeline = GPGPU;
 589    }
 590
 591    if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
 592       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 593
 594    if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
 595        (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
 596       result = flush_compute_descriptor_set(cmd_buffer);
 597       assert(result == VK_SUCCESS);
 598       cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
 599    }
 600
 601    cmd_buffer->state.compute_dirty = 0;
 602 }
 603
 604 void genX(CmdSetEvent)(
 605     VkCommandBuffer                             commandBuffer,
 606     VkEvent                                     _event,
 607     VkPipelineStageFlags                        stageMask)
 608 {
 609    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 610    ANV_FROM_HANDLE(anv_event, event, _event);
 611
 612    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 613                   .DestinationAddressType = DAT_PPGTT,
 614                   .PostSyncOperation = WriteImmediateData,
 615                   .Address = {
 616                      &cmd_buffer->device->dynamic_state_block_pool.bo,
 617                      event->state.offset
 618                    },
 619                   .ImmediateData = VK_EVENT_SET);
 620 }
 621
 622 void genX(CmdResetEvent)(
 623     VkCommandBuffer                             commandBuffer,
 624     VkEvent                                     _event,
 625     VkPipelineStageFlags                        stageMask)
 626 {
 627    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 628    ANV_FROM_HANDLE(anv_event, event, _event);
 629
 630    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
 631                   .DestinationAddressType = DAT_PPGTT,
 632                   .PostSyncOperation = WriteImmediateData,
 633                   .Address = {
 634                      &cmd_buffer->device->dynamic_state_block_pool.bo,
 635                      event->state.offset
 636                    },
 637                   .ImmediateData = VK_EVENT_RESET);
 638 }
 639
 640 void genX(CmdWaitEvents)(
 641     VkCommandBuffer                             commandBuffer,
 642     uint32_t                                    eventCount,
 643     const VkEvent*                              pEvents,
 644     VkPipelineStageFlags                        srcStageMask,
 645     VkPipelineStageFlags                        destStageMask,
 646     uint32_t                                    memoryBarrierCount,
 647     const VkMemoryBarrier*                      pMemoryBarriers,
 648     uint32_t                                    bufferMemoryBarrierCount,
 649     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 650     uint32_t                                    imageMemoryBarrierCount,
 651     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 652 {
 653    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 654    for (uint32_t i = 0; i < eventCount; i++) {
 655       ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
 656
 657       anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT),
 658                      .WaitMode = PollingMode,
 659                      .CompareOperation = COMPARE_SAD_EQUAL_SDD,
 660                      .SemaphoreDataDword = VK_EVENT_SET,
 661                      .SemaphoreAddress = {
 662                         &cmd_buffer->device->dynamic_state_block_pool.bo,
 663                         event->state.offset
 664                      });
 665    }
 666
 667    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 668                             false, /* byRegion */
 669                             memoryBarrierCount, pMemoryBarriers,
 670                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 671                             imageMemoryBarrierCount, pImageMemoryBarriers);
 672 }