src/intel/vulkan/gen8_cmd_buffer.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <string.h>
  27 #include <unistd.h>
  28 #include <fcntl.h>
  29
  30 #include "anv_private.h"
  31
  32 #include "genxml/gen_macros.h"
  33 #include "genxml/genX_pack.h"
  34
  35 #if GEN_GEN == 8
  36 void
  37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer)
  38 {
  39    uint32_t count = cmd_buffer->state.dynamic.viewport.count;
  40    const VkViewport *viewports = cmd_buffer->state.dynamic.viewport.viewports;
  41    struct anv_state sf_clip_state =
  42       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 64, 64);
  43    struct anv_state cc_state =
  44       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
  45
  46    for (uint32_t i = 0; i < count; i++) {
  47       const VkViewport *vp = &viewports[i];
  48
  49       /* The gen7 state struct has just the matrix and guardband fields, the
  50        * gen8 struct adds the min/max viewport fields. */
  51       struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
  52          .ViewportMatrixElementm00 = vp->width / 2,
  53          .ViewportMatrixElementm11 = vp->height / 2,
  54          .ViewportMatrixElementm22 = 1.0,
  55          .ViewportMatrixElementm30 = vp->x + vp->width / 2,
  56          .ViewportMatrixElementm31 = vp->y + vp->height / 2,
  57          .ViewportMatrixElementm32 = 0.0,
  58          .XMinClipGuardband = -1.0f,
  59          .XMaxClipGuardband = 1.0f,
  60          .YMinClipGuardband = -1.0f,
  61          .YMaxClipGuardband = 1.0f,
  62          .XMinViewPort = vp->x,
  63          .XMaxViewPort = vp->x + vp->width - 1,
  64          .YMinViewPort = vp->y,
  65          .YMaxViewPort = vp->y + vp->height - 1,
  66       };
  67
  68       struct GENX(CC_VIEWPORT) cc_viewport = {
  69          .MinimumDepth = vp->minDepth,
  70          .MaximumDepth = vp->maxDepth
  71       };
  72
  73       GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
  74                                  &sf_clip_viewport);
  75       GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
  76    }
  77
  78    if (!cmd_buffer->device->info.has_llc) {
  79       anv_state_clflush(sf_clip_state);
  80       anv_state_clflush(cc_state);
  81    }
  82
  83    anv_batch_emit(&cmd_buffer->batch,
  84                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
  85       cc.CCViewportPointer = cc_state.offset;
  86    }
  87    anv_batch_emit(&cmd_buffer->batch,
  88                   GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
  89       clip.SFClipViewportPointer = sf_clip_state.offset;
  90    }
  91 }
  92 #endif
  93
  94 static void
  95 __emit_genx_sf_state(struct anv_cmd_buffer *cmd_buffer)
  96 {
  97       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
  98       struct GENX(3DSTATE_SF) sf = {
  99          GENX(3DSTATE_SF_header),
 100          .LineWidth = cmd_buffer->state.dynamic.line_width,
 101       };
 102       GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
 103       /* FIXME: gen9.fs */
 104       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 105                            cmd_buffer->state.pipeline->gen8.sf);
 106 }
 107
 108 #include "genxml/gen9_pack.h"
 109 static void
 110 __emit_gen9_sf_state(struct anv_cmd_buffer *cmd_buffer)
 111 {
 112       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
 113       struct GEN9_3DSTATE_SF sf = {
 114          GEN9_3DSTATE_SF_header,
 115          .LineWidth = cmd_buffer->state.dynamic.line_width,
 116       };
 117       GEN9_3DSTATE_SF_pack(NULL, sf_dw, &sf);
 118       /* FIXME: gen9.fs */
 119       anv_batch_emit_merge(&cmd_buffer->batch, sf_dw,
 120                            cmd_buffer->state.pipeline->gen8.sf);
 121 }
 122
 123 static void
 124 __emit_sf_state(struct anv_cmd_buffer *cmd_buffer)
 125 {
 126    if (cmd_buffer->device->info.is_cherryview)
 127       __emit_gen9_sf_state(cmd_buffer);
 128    else
 129       __emit_genx_sf_state(cmd_buffer);
 130 }
 131
 132 void
 133 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 134 {
 135    struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 136
 137    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 138                                   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
 139       __emit_sf_state(cmd_buffer);
 140    }
 141
 142    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 143                                   ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)){
 144       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
 145       struct GENX(3DSTATE_RASTER) raster = {
 146          GENX(3DSTATE_RASTER_header),
 147          .GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
 148          .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
 149          .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
 150       };
 151       GENX(3DSTATE_RASTER_pack)(NULL, raster_dw, &raster);
 152       anv_batch_emit_merge(&cmd_buffer->batch, raster_dw,
 153                            pipeline->gen8.raster);
 154    }
 155
 156    /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
 157     * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
 158     * across different state packets for gen8 and gen9. We handle that by
 159     * using a big old #if switch here.
 160     */
 161 #if GEN_GEN == 8
 162    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
 163                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 164       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 165       struct anv_state cc_state =
 166          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 167                                             GENX(COLOR_CALC_STATE_length) * 4,
 168                                             64);
 169       struct GENX(COLOR_CALC_STATE) cc = {
 170          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 171          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 172          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 173          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 174          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 175          .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 176       };
 177       GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
 178
 179       if (!cmd_buffer->device->info.has_llc)
 180          anv_state_clflush(cc_state);
 181
 182       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
 183          ccp.ColorCalcStatePointer        = cc_state.offset;
 184          ccp.ColorCalcStatePointerValid   = true;
 185       }
 186    }
 187
 188    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 189                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 190                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
 191       uint32_t wm_depth_stencil_dw[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
 192       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 193
 194       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
 195          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 196
 197          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 198          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 199
 200          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 201          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 202       };
 203       GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, wm_depth_stencil_dw,
 204                                           &wm_depth_stencil);
 205
 206       anv_batch_emit_merge(&cmd_buffer->batch, wm_depth_stencil_dw,
 207                            pipeline->gen8.wm_depth_stencil);
 208    }
 209 #else
 210    if (cmd_buffer->state.dirty & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
 211       struct anv_state cc_state =
 212          anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 213                                             GEN9_COLOR_CALC_STATE_length * 4,
 214                                             64);
 215       struct GEN9_COLOR_CALC_STATE cc = {
 216          .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
 217          .BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
 218          .BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
 219          .BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
 220       };
 221       GEN9_COLOR_CALC_STATE_pack(NULL, cc_state.map, &cc);
 222
 223       if (!cmd_buffer->device->info.has_llc)
 224          anv_state_clflush(cc_state);
 225
 226       anv_batch_emit(&cmd_buffer->batch, GEN9_3DSTATE_CC_STATE_POINTERS, ccp) {
 227          ccp.ColorCalcStatePointer = cc_state.offset;
 228          ccp.ColorCalcStatePointerValid = true;
 229       }
 230    }
 231
 232    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 233                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
 234                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
 235                                   ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
 236       uint32_t dwords[GEN9_3DSTATE_WM_DEPTH_STENCIL_length];
 237       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 238       struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil = {
 239          GEN9_3DSTATE_WM_DEPTH_STENCIL_header,
 240
 241          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
 242          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 243
 244          .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
 245          .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
 246
 247          .StencilReferenceValue = d->stencil_reference.front & 0xff,
 248          .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
 249       };
 250       GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL, dwords, &wm_depth_stencil);
 251
 252       anv_batch_emit_merge(&cmd_buffer->batch, dwords,
 253                            pipeline->gen9.wm_depth_stencil);
 254    }
 255 #endif
 256
 257    if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
 258                                   ANV_CMD_DIRTY_INDEX_BUFFER)) {
 259       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) {
 260          vf.IndexedDrawCutIndexEnable  = pipeline->primitive_restart;
 261          vf.CutIndex                   = cmd_buffer->state.restart_index;
 262       }
 263    }
 264
 265    cmd_buffer->state.dirty = 0;
 266 }
 267
 268 void genX(CmdBindIndexBuffer)(
 269     VkCommandBuffer                             commandBuffer,
 270     VkBuffer                                    _buffer,
 271     VkDeviceSize                                offset,
 272     VkIndexType                                 indexType)
 273 {
 274    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 275    ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
 276
 277    static const uint32_t vk_to_gen_index_type[] = {
 278       [VK_INDEX_TYPE_UINT16]                    = INDEX_WORD,
 279       [VK_INDEX_TYPE_UINT32]                    = INDEX_DWORD,
 280    };
 281
 282    static const uint32_t restart_index_for_type[] = {
 283       [VK_INDEX_TYPE_UINT16]                    = UINT16_MAX,
 284       [VK_INDEX_TYPE_UINT32]                    = UINT32_MAX,
 285    };
 286
 287    cmd_buffer->state.restart_index = restart_index_for_type[indexType];
 288
 289    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
 290       ib.IndexFormat                = vk_to_gen_index_type[indexType];
 291       ib.MemoryObjectControlState   = GENX(MOCS);
 292       ib.BufferStartingAddress      =
 293          (struct anv_address) { buffer->bo, buffer->offset + offset };
 294       ib.BufferSize                 = buffer->size - offset;
 295    }
 296
 297    cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 298 }
 299
 300 static VkResult
 301 flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 302 {
 303    struct anv_device *device = cmd_buffer->device;
 304    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 305    struct anv_state surfaces = { 0, }, samplers = { 0, };
 306    VkResult result;
 307
 308    result = anv_cmd_buffer_emit_samplers(cmd_buffer,
 309                                          MESA_SHADER_COMPUTE, &samplers);
 310    if (result != VK_SUCCESS)
 311       return result;
 312    result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
 313                                               MESA_SHADER_COMPUTE, &surfaces);
 314    if (result != VK_SUCCESS)
 315       return result;
 316
 317    struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
 318
 319    const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
 320    const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
 321
 322    if (push_state.alloc_size) {
 323       anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
 324          curbe.CURBETotalDataLength    = push_state.alloc_size;
 325          curbe.CURBEDataStartAddress   = push_state.offset;
 326       }
 327    }
 328
 329    const uint32_t slm_size = encode_slm_size(GEN_GEN, prog_data->total_shared);
 330
 331    struct anv_state state =
 332       anv_state_pool_emit(&device->dynamic_state_pool,
 333                           GENX(INTERFACE_DESCRIPTOR_DATA), 64,
 334                           .KernelStartPointer = pipeline->cs_simd,
 335                           .KernelStartPointerHigh = 0,
 336                           .BindingTablePointer = surfaces.offset,
 337                           .BindingTableEntryCount = 0,
 338                           .SamplerStatePointer = samplers.offset,
 339                           .SamplerCount = 0,
 340                           .ConstantIndirectURBEntryReadLength =
 341                              cs_prog_data->push.per_thread.regs,
 342                           .ConstantURBEntryReadOffset = 0,
 343                           .BarrierEnable = cs_prog_data->uses_barrier,
 344                           .SharedLocalMemorySize = slm_size,
 345                           .NumberofThreadsinGPGPUThreadGroup =
 346                              cs_prog_data->threads,
 347                           .CrossThreadConstantDataReadLength =
 348                              cs_prog_data->push.cross_thread.regs);
 349
 350    uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
 351    anv_batch_emit(&cmd_buffer->batch,
 352                   GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
 353       mid.InterfaceDescriptorTotalLength        = size;
 354       mid.InterfaceDescriptorDataStartAddress   = state.offset;
 355    }
 356
 357    return VK_SUCCESS;
 358 }
 359
 360 void
 361 genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
 362 {
 363    struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
 364    MAYBE_UNUSED VkResult result;
 365
 366    assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
 367
 368    genX(cmd_buffer_config_l3)(cmd_buffer, pipeline);
 369
 370    genX(flush_pipeline_select_gpgpu)(cmd_buffer);
 371
 372    if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
 373       anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
 374
 375    if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
 376        (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
 377       result = flush_compute_descriptor_set(cmd_buffer);
 378       assert(result == VK_SUCCESS);
 379       cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
 380    }
 381
 382    cmd_buffer->state.compute_dirty = 0;
 383
 384    genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
 385 }
 386
 387 void genX(CmdSetEvent)(
 388     VkCommandBuffer                             commandBuffer,
 389     VkEvent                                     _event,
 390     VkPipelineStageFlags                        stageMask)
 391 {
 392    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 393    ANV_FROM_HANDLE(anv_event, event, _event);
 394
 395    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 396       pc.DestinationAddressType  = DAT_PPGTT,
 397       pc.PostSyncOperation       = WriteImmediateData,
 398       pc.Address = (struct anv_address) {
 399          &cmd_buffer->device->dynamic_state_block_pool.bo,
 400          event->state.offset
 401       };
 402       pc.ImmediateData           = VK_EVENT_SET;
 403    }
 404 }
 405
 406 void genX(CmdResetEvent)(
 407     VkCommandBuffer                             commandBuffer,
 408     VkEvent                                     _event,
 409     VkPipelineStageFlags                        stageMask)
 410 {
 411    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 412    ANV_FROM_HANDLE(anv_event, event, _event);
 413
 414    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
 415       pc.DestinationAddressType  = DAT_PPGTT;
 416       pc.PostSyncOperation       = WriteImmediateData;
 417       pc.Address = (struct anv_address) {
 418          &cmd_buffer->device->dynamic_state_block_pool.bo,
 419          event->state.offset
 420       };
 421       pc.ImmediateData           = VK_EVENT_RESET;
 422    }
 423 }
 424
 425 void genX(CmdWaitEvents)(
 426     VkCommandBuffer                             commandBuffer,
 427     uint32_t                                    eventCount,
 428     const VkEvent*                              pEvents,
 429     VkPipelineStageFlags                        srcStageMask,
 430     VkPipelineStageFlags                        destStageMask,
 431     uint32_t                                    memoryBarrierCount,
 432     const VkMemoryBarrier*                      pMemoryBarriers,
 433     uint32_t                                    bufferMemoryBarrierCount,
 434     const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
 435     uint32_t                                    imageMemoryBarrierCount,
 436     const VkImageMemoryBarrier*                 pImageMemoryBarriers)
 437 {
 438    ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 439    for (uint32_t i = 0; i < eventCount; i++) {
 440       ANV_FROM_HANDLE(anv_event, event, pEvents[i]);
 441
 442       anv_batch_emit(&cmd_buffer->batch, GENX(MI_SEMAPHORE_WAIT), sem) {
 443          sem.WaitMode            = PollingMode,
 444          sem.CompareOperation    = COMPARE_SAD_EQUAL_SDD,
 445          sem.SemaphoreDataDword  = VK_EVENT_SET,
 446          sem.SemaphoreAddress = (struct anv_address) {
 447             &cmd_buffer->device->dynamic_state_block_pool.bo,
 448             event->state.offset
 449          };
 450       }
 451    }
 452
 453    genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
 454                             false, /* byRegion */
 455                             memoryBarrierCount, pMemoryBarriers,
 456                             bufferMemoryBarrierCount, pBufferMemoryBarriers,
 457                             imageMemoryBarrierCount, pImageMemoryBarriers);
 458 }