2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
37 gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
)
39 uint32_t count
= cmd_buffer
->state
.dynamic
.viewport
.count
;
40 const VkViewport
*viewports
= cmd_buffer
->state
.dynamic
.viewport
.viewports
;
41 struct anv_state sf_clip_state
=
42 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 64, 64);
44 for (uint32_t i
= 0; i
< count
; i
++) {
45 const VkViewport
*vp
= &viewports
[i
];
47 /* The gen7 state struct has just the matrix and guardband fields, the
48 * gen8 struct adds the min/max viewport fields. */
49 struct GENX(SF_CLIP_VIEWPORT
) sf_clip_viewport
= {
50 .ViewportMatrixElementm00
= vp
->width
/ 2,
51 .ViewportMatrixElementm11
= vp
->height
/ 2,
52 .ViewportMatrixElementm22
= 1.0,
53 .ViewportMatrixElementm30
= vp
->x
+ vp
->width
/ 2,
54 .ViewportMatrixElementm31
= vp
->y
+ vp
->height
/ 2,
55 .ViewportMatrixElementm32
= 0.0,
56 .XMinClipGuardband
= -1.0f
,
57 .XMaxClipGuardband
= 1.0f
,
58 .YMinClipGuardband
= -1.0f
,
59 .YMaxClipGuardband
= 1.0f
,
60 .XMinViewPort
= vp
->x
,
61 .XMaxViewPort
= vp
->x
+ vp
->width
- 1,
62 .YMinViewPort
= MIN2(vp
->y
, vp
->y
+ vp
->height
),
63 .YMaxViewPort
= MAX2(vp
->y
, vp
->y
+ vp
->height
) - 1,
66 GENX(SF_CLIP_VIEWPORT_pack
)(NULL
, sf_clip_state
.map
+ i
* 64,
70 anv_state_flush(cmd_buffer
->device
, sf_clip_state
);
72 anv_batch_emit(&cmd_buffer
->batch
,
73 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
), clip
) {
74 clip
.SFClipViewportPointer
= sf_clip_state
.offset
;
79 gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
80 bool depth_clamp_enable
)
82 uint32_t count
= cmd_buffer
->state
.dynamic
.viewport
.count
;
83 const VkViewport
*viewports
= cmd_buffer
->state
.dynamic
.viewport
.viewports
;
84 struct anv_state cc_state
=
85 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, count
* 8, 32);
87 for (uint32_t i
= 0; i
< count
; i
++) {
88 const VkViewport
*vp
= &viewports
[i
];
90 struct GENX(CC_VIEWPORT
) cc_viewport
= {
91 .MinimumDepth
= depth_clamp_enable
? vp
->minDepth
: 0.0f
,
92 .MaximumDepth
= depth_clamp_enable
? vp
->maxDepth
: 1.0f
,
95 GENX(CC_VIEWPORT_pack
)(NULL
, cc_state
.map
+ i
* 8, &cc_viewport
);
98 anv_state_flush(cmd_buffer
->device
, cc_state
);
100 anv_batch_emit(&cmd_buffer
->batch
,
101 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), cc
) {
102 cc
.CCViewportPointer
= cc_state
.offset
;
108 __emit_genx_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
110 uint32_t sf_dw
[GENX(3DSTATE_SF_length
)];
111 struct GENX(3DSTATE_SF
) sf
= {
112 GENX(3DSTATE_SF_header
),
113 .LineWidth
= cmd_buffer
->state
.dynamic
.line_width
,
115 GENX(3DSTATE_SF_pack
)(NULL
, sf_dw
, &sf
);
117 anv_batch_emit_merge(&cmd_buffer
->batch
, sf_dw
,
118 cmd_buffer
->state
.pipeline
->gen8
.sf
);
122 gen9_emit_sf_state(struct anv_cmd_buffer
*cmd_buffer
);
127 gen9_emit_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
129 __emit_genx_sf_state(cmd_buffer
);
137 __emit_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
139 if (cmd_buffer
->device
->info
.is_cherryview
)
140 gen9_emit_sf_state(cmd_buffer
);
142 __emit_genx_sf_state(cmd_buffer
);
148 __emit_sf_state(struct anv_cmd_buffer
*cmd_buffer
)
150 __emit_genx_sf_state(cmd_buffer
);
156 genX(cmd_buffer_enable_pma_fix
)(struct anv_cmd_buffer
*cmd_buffer
, bool enable
)
158 if (cmd_buffer
->state
.pma_fix_enabled
== enable
)
161 cmd_buffer
->state
.pma_fix_enabled
= enable
;
163 /* According to the Broadwell PIPE_CONTROL documentation, software should
164 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
165 * prior to the LRI. If stencil buffer writes are enabled, then a Render
166 * Cache Flush is also necessary.
168 * The Skylake docs say to use a depth stall rather than a command
169 * streamer stall. However, the hardware seems to violently disagree.
170 * A full command streamer stall seems to be needed in both cases.
172 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
173 pc
.DepthCacheFlushEnable
= true;
174 pc
.CommandStreamerStallEnable
= true;
175 pc
.RenderTargetCacheFlushEnable
= true;
181 anv_pack_struct(&cache_mode
, GENX(CACHE_MODE_0
),
182 .STCPMAOptimizationEnable
= enable
,
183 .STCPMAOptimizationEnableMask
= true);
184 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
185 lri
.RegisterOffset
= GENX(CACHE_MODE_0_num
);
186 lri
.DataDWord
= cache_mode
;
192 anv_pack_struct(&cache_mode
, GENX(CACHE_MODE_1
),
193 .NPPMAFixEnable
= enable
,
194 .NPEarlyZFailsDisable
= enable
,
195 .NPPMAFixEnableMask
= true,
196 .NPEarlyZFailsDisableMask
= true);
197 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
198 lri
.RegisterOffset
= GENX(CACHE_MODE_1_num
);
199 lri
.DataDWord
= cache_mode
;
202 #endif /* GEN_GEN == 8 */
204 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
205 * Flush bits is often necessary. We do it regardless because it's easier.
206 * The render cache flush is also necessary if stencil writes are enabled.
208 * Again, the Skylake docs give a different set of flushes but the BDW
209 * flushes seem to work just as well.
211 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
212 pc
.DepthStallEnable
= true;
213 pc
.DepthCacheFlushEnable
= true;
214 pc
.RenderTargetCacheFlushEnable
= true;
219 want_depth_pma_fix(struct anv_cmd_buffer
*cmd_buffer
)
221 assert(GEN_GEN
== 8);
223 /* From the Broadwell PRM Vol. 2c CACHE_MODE_1::NP_PMA_FIX_ENABLE:
225 * SW must set this bit in order to enable this fix when following
226 * expression is TRUE.
228 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
229 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
230 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
231 * (3DSTATE_DEPTH_BUFFER::HIZ Enable) &&
232 * !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) &&
233 * (3DSTATE_PS_EXTRA::PixelShaderValid) &&
234 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
235 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
236 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
237 * 3DSTATE_WM_HZ_OP::StencilBufferClear) &&
238 * (3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable) &&
239 * (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
240 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
241 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
242 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
243 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
244 * 3DSTATE_WM::ForceKillPix != ForceOff &&
245 * ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
246 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
247 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
248 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
249 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
250 * (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
253 /* These are always true:
254 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
255 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
258 /* We only enable the PMA fix if we know for certain that HiZ is enabled.
259 * If we don't know whether HiZ is enabled or not, we disable the PMA fix
260 * and there is no harm.
262 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
263 * 3DSTATE_DEPTH_BUFFER::HIZ Enable
265 if (!cmd_buffer
->state
.hiz_enabled
)
268 /* 3DSTATE_PS_EXTRA::PixelShaderValid */
269 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
270 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
))
273 /* !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) */
274 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
275 if (wm_prog_data
->early_fragment_tests
)
278 /* We never use anv_pipeline for HiZ ops so this is trivially true:
279 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
280 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
281 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
282 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
285 /* 3DSTATE_WM_DEPTH_STENCIL::DepthTestEnable */
286 if (!pipeline
->depth_test_enable
)
289 /* (((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
290 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
291 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
292 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
293 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) &&
294 * 3DSTATE_WM::ForceKillPix != ForceOff &&
295 * ((3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
296 * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE) ||
297 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
298 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE &&
299 * 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE))) ||
300 * (3DSTATE_PS_EXTRA:: Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
302 return (pipeline
->kill_pixel
&& (pipeline
->writes_depth
||
303 pipeline
->writes_stencil
)) ||
304 wm_prog_data
->computed_depth_mode
!= PSCDEPTH_OFF
;
308 want_stencil_pma_fix(struct anv_cmd_buffer
*cmd_buffer
)
310 assert(GEN_GEN
== 9);
312 /* From the Skylake PRM Vol. 2c CACHE_MODE_1::STC PMA Optimization Enable:
314 * Clearing this bit will force the STC cache to wait for pending
315 * retirement of pixels at the HZ-read stage and do the STC-test for
316 * Non-promoted, R-computed and Computed depth modes instead of
317 * postponing the STC-test to RCPFE.
319 * STC_TEST_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
320 * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
322 * STC_WRITE_EN = 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
323 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
324 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
326 * COMP_STC_EN = STC_TEST_EN &&
327 * 3DSTATE_PS_EXTRA::PixelShaderComputesStencil
329 * SW parses the pipeline states to generate the following logical
330 * signal indicating if PMA FIX can be enabled.
333 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
334 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0) &&
335 * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
336 * 3DSTATE_DEPTH_BUFFER::HIZ Enable &&
337 * !(3DSTATE_WM::EDSC_Mode == 2) &&
338 * 3DSTATE_PS_EXTRA::PixelShaderValid &&
339 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
340 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
341 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
342 * 3DSTATE_WM_HZ_OP::StencilBufferClear) &&
343 * (COMP_STC_EN || STC_WRITE_EN) &&
344 * ((3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
345 * 3DSTATE_WM::ForceKillPix == ON ||
346 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
347 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
348 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
349 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
350 * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF))
353 /* These are always true:
354 * 3DSTATE_WM::ForceThreadDispatch != 1 &&
355 * !(3DSTATE_RASTER::ForceSampleCount != NUMRASTSAMPLES_0)
358 /* We only enable the PMA fix if we know for certain that HiZ is enabled.
359 * If we don't know whether HiZ is enabled or not, we disable the PMA fix
360 * and there is no harm.
362 * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) &&
363 * 3DSTATE_DEPTH_BUFFER::HIZ Enable
365 if (!cmd_buffer
->state
.hiz_enabled
)
368 /* We can't possibly know if HiZ is enabled without the framebuffer */
369 assert(cmd_buffer
->state
.framebuffer
);
371 /* HiZ is enabled so we had better have a depth buffer with HiZ */
372 const struct anv_image_view
*ds_iview
=
373 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
374 assert(ds_iview
&& ds_iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
);
376 /* 3DSTATE_PS_EXTRA::PixelShaderValid */
377 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
378 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
))
381 /* !(3DSTATE_WM::EDSC_Mode == 2) */
382 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
383 if (wm_prog_data
->early_fragment_tests
)
386 /* We never use anv_pipeline for HiZ ops so this is trivially true:
387 * !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
388 * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
389 * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
390 * 3DSTATE_WM_HZ_OP::StencilBufferClear)
393 /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
394 * 3DSTATE_WM_DEPTH_STENCIL::StencilTestEnable
396 const bool stc_test_en
=
397 (ds_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
398 pipeline
->stencil_test_enable
;
400 /* 3DSTATE_STENCIL_BUFFER::STENCIL_BUFFER_ENABLE &&
401 * (3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable &&
402 * 3DSTATE_DEPTH_BUFFER::STENCIL_WRITE_ENABLE)
404 const bool stc_write_en
=
405 (ds_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
406 pipeline
->writes_stencil
;
408 /* STC_TEST_EN && 3DSTATE_PS_EXTRA::PixelShaderComputesStencil */
409 const bool comp_stc_en
= stc_test_en
&& wm_prog_data
->computed_stencil
;
411 /* COMP_STC_EN || STC_WRITE_EN */
412 if (!(comp_stc_en
|| stc_write_en
))
415 /* (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
416 * 3DSTATE_WM::ForceKillPix == ON ||
417 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
418 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
419 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
420 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) ||
421 * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF)
423 return pipeline
->kill_pixel
||
424 wm_prog_data
->computed_depth_mode
!= PSCDEPTH_OFF
;
428 genX(cmd_buffer_flush_dynamic_state
)(struct anv_cmd_buffer
*cmd_buffer
)
430 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
432 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
433 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)) {
434 __emit_sf_state(cmd_buffer
);
437 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
438 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)){
439 uint32_t raster_dw
[GENX(3DSTATE_RASTER_length
)];
440 struct GENX(3DSTATE_RASTER
) raster
= {
441 GENX(3DSTATE_RASTER_header
),
442 .GlobalDepthOffsetConstant
= cmd_buffer
->state
.dynamic
.depth_bias
.bias
,
443 .GlobalDepthOffsetScale
= cmd_buffer
->state
.dynamic
.depth_bias
.slope
,
444 .GlobalDepthOffsetClamp
= cmd_buffer
->state
.dynamic
.depth_bias
.clamp
446 GENX(3DSTATE_RASTER_pack
)(NULL
, raster_dw
, &raster
);
447 anv_batch_emit_merge(&cmd_buffer
->batch
, raster_dw
,
448 pipeline
->gen8
.raster
);
451 /* Stencil reference values moved from COLOR_CALC_STATE in gen8 to
452 * 3DSTATE_WM_DEPTH_STENCIL in gen9. That means the dirty bits gets split
453 * across different state packets for gen8 and gen9. We handle that by
454 * using a big old #if switch here.
457 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
|
458 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
459 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
460 struct anv_state cc_state
=
461 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
462 GENX(COLOR_CALC_STATE_length
) * 4,
464 struct GENX(COLOR_CALC_STATE
) cc
= {
465 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
466 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
467 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
468 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
469 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
470 .BackFaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
472 GENX(COLOR_CALC_STATE_pack
)(NULL
, cc_state
.map
, &cc
);
474 anv_state_flush(cmd_buffer
->device
, cc_state
);
476 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), ccp
) {
477 ccp
.ColorCalcStatePointer
= cc_state
.offset
;
478 ccp
.ColorCalcStatePointerValid
= true;
482 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
483 ANV_CMD_DIRTY_RENDER_TARGETS
|
484 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
485 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
)) {
486 uint32_t wm_depth_stencil_dw
[GENX(3DSTATE_WM_DEPTH_STENCIL_length
)];
487 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
489 struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
) = {
490 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
492 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
493 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
495 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
496 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
498 .StencilBufferWriteEnable
=
499 (d
->stencil_write_mask
.front
|| d
->stencil_write_mask
.back
) &&
500 pipeline
->writes_stencil
,
502 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, wm_depth_stencil_dw
,
505 anv_batch_emit_merge(&cmd_buffer
->batch
, wm_depth_stencil_dw
,
506 pipeline
->gen8
.wm_depth_stencil
);
508 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
,
509 want_depth_pma_fix(cmd_buffer
));
512 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
) {
513 struct anv_state cc_state
=
514 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
515 GEN9_COLOR_CALC_STATE_length
* 4,
517 struct GEN9_COLOR_CALC_STATE cc
= {
518 .BlendConstantColorRed
= cmd_buffer
->state
.dynamic
.blend_constants
[0],
519 .BlendConstantColorGreen
= cmd_buffer
->state
.dynamic
.blend_constants
[1],
520 .BlendConstantColorBlue
= cmd_buffer
->state
.dynamic
.blend_constants
[2],
521 .BlendConstantColorAlpha
= cmd_buffer
->state
.dynamic
.blend_constants
[3],
523 GEN9_COLOR_CALC_STATE_pack(NULL
, cc_state
.map
, &cc
);
525 anv_state_flush(cmd_buffer
->device
, cc_state
);
527 anv_batch_emit(&cmd_buffer
->batch
, GEN9_3DSTATE_CC_STATE_POINTERS
, ccp
) {
528 ccp
.ColorCalcStatePointer
= cc_state
.offset
;
529 ccp
.ColorCalcStatePointerValid
= true;
533 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
534 ANV_CMD_DIRTY_RENDER_TARGETS
|
535 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
|
536 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
537 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
)) {
538 uint32_t dwords
[GEN9_3DSTATE_WM_DEPTH_STENCIL_length
];
539 struct anv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
540 struct GEN9_3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil
= {
541 GEN9_3DSTATE_WM_DEPTH_STENCIL_header
,
543 .StencilTestMask
= d
->stencil_compare_mask
.front
& 0xff,
544 .StencilWriteMask
= d
->stencil_write_mask
.front
& 0xff,
546 .BackfaceStencilTestMask
= d
->stencil_compare_mask
.back
& 0xff,
547 .BackfaceStencilWriteMask
= d
->stencil_write_mask
.back
& 0xff,
549 .StencilReferenceValue
= d
->stencil_reference
.front
& 0xff,
550 .BackfaceStencilReferenceValue
= d
->stencil_reference
.back
& 0xff,
552 .StencilBufferWriteEnable
=
553 (d
->stencil_write_mask
.front
|| d
->stencil_write_mask
.back
) &&
554 pipeline
->writes_stencil
,
556 GEN9_3DSTATE_WM_DEPTH_STENCIL_pack(NULL
, dwords
, &wm_depth_stencil
);
558 anv_batch_emit_merge(&cmd_buffer
->batch
, dwords
,
559 pipeline
->gen9
.wm_depth_stencil
);
561 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
,
562 want_stencil_pma_fix(cmd_buffer
));
566 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
567 ANV_CMD_DIRTY_INDEX_BUFFER
)) {
568 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_VF
), vf
) {
569 vf
.IndexedDrawCutIndexEnable
= pipeline
->primitive_restart
;
570 vf
.CutIndex
= cmd_buffer
->state
.restart_index
;
574 cmd_buffer
->state
.dirty
= 0;
577 void genX(CmdBindIndexBuffer
)(
578 VkCommandBuffer commandBuffer
,
581 VkIndexType indexType
)
583 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
584 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
586 static const uint32_t vk_to_gen_index_type
[] = {
587 [VK_INDEX_TYPE_UINT16
] = INDEX_WORD
,
588 [VK_INDEX_TYPE_UINT32
] = INDEX_DWORD
,
591 static const uint32_t restart_index_for_type
[] = {
592 [VK_INDEX_TYPE_UINT16
] = UINT16_MAX
,
593 [VK_INDEX_TYPE_UINT32
] = UINT32_MAX
,
596 cmd_buffer
->state
.restart_index
= restart_index_for_type
[indexType
];
598 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_INDEX_BUFFER
), ib
) {
599 ib
.IndexFormat
= vk_to_gen_index_type
[indexType
];
600 ib
.MemoryObjectControlState
= GENX(MOCS
);
601 ib
.BufferStartingAddress
=
602 (struct anv_address
) { buffer
->bo
, buffer
->offset
+ offset
};
603 ib
.BufferSize
= buffer
->size
- offset
;
606 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_INDEX_BUFFER
;
609 /* Set of stage bits for which are pipelined, i.e. they get queued by the
610 * command streamer for later execution.
612 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
613 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
614 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
615 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
616 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
617 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
618 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
619 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
620 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
621 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
622 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
623 VK_PIPELINE_STAGE_TRANSFER_BIT | \
624 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
625 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
626 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
628 void genX(CmdSetEvent
)(
629 VkCommandBuffer commandBuffer
,
631 VkPipelineStageFlags stageMask
)
633 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
634 ANV_FROM_HANDLE(anv_event
, event
, _event
);
636 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
637 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
638 pc
.StallAtPixelScoreboard
= true;
639 pc
.CommandStreamerStallEnable
= true;
642 pc
.DestinationAddressType
= DAT_PPGTT
,
643 pc
.PostSyncOperation
= WriteImmediateData
,
644 pc
.Address
= (struct anv_address
) {
645 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
648 pc
.ImmediateData
= VK_EVENT_SET
;
652 void genX(CmdResetEvent
)(
653 VkCommandBuffer commandBuffer
,
655 VkPipelineStageFlags stageMask
)
657 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
658 ANV_FROM_HANDLE(anv_event
, event
, _event
);
660 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
661 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
662 pc
.StallAtPixelScoreboard
= true;
663 pc
.CommandStreamerStallEnable
= true;
666 pc
.DestinationAddressType
= DAT_PPGTT
;
667 pc
.PostSyncOperation
= WriteImmediateData
;
668 pc
.Address
= (struct anv_address
) {
669 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
672 pc
.ImmediateData
= VK_EVENT_RESET
;
676 void genX(CmdWaitEvents
)(
677 VkCommandBuffer commandBuffer
,
679 const VkEvent
* pEvents
,
680 VkPipelineStageFlags srcStageMask
,
681 VkPipelineStageFlags destStageMask
,
682 uint32_t memoryBarrierCount
,
683 const VkMemoryBarrier
* pMemoryBarriers
,
684 uint32_t bufferMemoryBarrierCount
,
685 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
686 uint32_t imageMemoryBarrierCount
,
687 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
689 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
690 for (uint32_t i
= 0; i
< eventCount
; i
++) {
691 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
693 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
694 sem
.WaitMode
= PollingMode
,
695 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
696 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
697 sem
.SemaphoreAddress
= (struct anv_address
) {
698 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
704 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
705 false, /* byRegion */
706 memoryBarrierCount
, pMemoryBarriers
,
707 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
708 imageMemoryBarrierCount
, pImageMemoryBarriers
);