src/intel/vulkan/genX_blorp_exec.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "anv_private.h"
  27
  28 /* These are defined in anv_private.h and blorp_genX_exec.h */
  29 #undef __gen_address_type
  30 #undef __gen_user_data
  31 #undef __gen_combine_address
  32
  33 #include "common/gen_l3_config.h"
  34 #include "common/gen_sample_positions.h"
  35 #include "blorp/blorp_genX_exec.h"
  36
  37 static void *
  38 blorp_emit_dwords(struct blorp_batch *batch, unsigned n)
  39 {
  40    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
  41    return anv_batch_emit_dwords(&cmd_buffer->batch, n);
  42 }
  43
  44 static uint64_t
  45 blorp_emit_reloc(struct blorp_batch *batch,
  46                  void *location, struct blorp_address address, uint32_t delta)
  47 {
  48    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
  49    assert(cmd_buffer->batch.start <= location &&
  50           location < cmd_buffer->batch.end);
  51    return anv_batch_emit_reloc(&cmd_buffer->batch, location,
  52                                address.buffer, address.offset + delta);
  53 }
  54
  55 static void
  56 blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
  57                     struct blorp_address address, uint32_t delta)
  58 {
  59    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
  60    uint64_t address_u64 = 0;
  61    VkResult result =
  62       anv_reloc_list_add(&cmd_buffer->surface_relocs, &cmd_buffer->pool->alloc,
  63                          ss_offset, address.buffer, address.offset + delta,
  64                          &address_u64);
  65    if (result != VK_SUCCESS)
  66       anv_batch_set_error(&cmd_buffer->batch, result);
  67
  68    void *dest = anv_block_pool_map(
  69       &cmd_buffer->device->surface_state_pool.block_pool, ss_offset, 8);
  70    write_reloc(cmd_buffer->device, dest, address_u64, false);
  71 }
  72
  73 static uint64_t
  74 blorp_get_surface_address(struct blorp_batch *blorp_batch,
  75                           struct blorp_address address)
  76 {
  77    /* We'll let blorp_surface_reloc write the address. */
  78    return 0ull;
  79 }
  80
  81 #if GEN_GEN >= 7 && GEN_GEN < 10
  82 static struct blorp_address
  83 blorp_get_surface_base_address(struct blorp_batch *batch)
  84 {
  85    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
  86    return (struct blorp_address) {
  87       .buffer = cmd_buffer->device->surface_state_pool.block_pool.bo,
  88       .offset = 0,
  89    };
  90 }
  91 #endif
  92
  93 static void *
  94 blorp_alloc_dynamic_state(struct blorp_batch *batch,
  95                           uint32_t size,
  96                           uint32_t alignment,
  97                           uint32_t *offset)
  98 {
  99    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
 100
 101    struct anv_state state =
 102       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
 103
 104    *offset = state.offset;
 105    return state.map;
 106 }
 107
 108 static void
 109 blorp_alloc_binding_table(struct blorp_batch *batch, unsigned num_entries,
 110                           unsigned state_size, unsigned state_alignment,
 111                           uint32_t *bt_offset,
 112                           uint32_t *surface_offsets, void **surface_maps)
 113 {
 114    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
 115
 116    uint32_t state_offset;
 117    struct anv_state bt_state;
 118
 119    VkResult result =
 120       anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer, num_entries,
 121                                                &state_offset, &bt_state);
 122    if (result != VK_SUCCESS)
 123       return;
 124
 125    uint32_t *bt_map = bt_state.map;
 126    *bt_offset = bt_state.offset;
 127
 128    for (unsigned i = 0; i < num_entries; i++) {
 129       struct anv_state surface_state =
 130          anv_cmd_buffer_alloc_surface_state(cmd_buffer);
 131       bt_map[i] = surface_state.offset + state_offset;
 132       surface_offsets[i] = surface_state.offset;
 133       surface_maps[i] = surface_state.map;
 134    }
 135 }
 136
 137 static void *
 138 blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
 139                           struct blorp_address *addr)
 140 {
 141    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
 142    struct anv_state vb_state =
 143       anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 64);
 144
 145    *addr = (struct blorp_address) {
 146       .buffer = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
 147       .offset = vb_state.offset,
 148       .mocs = cmd_buffer->device->isl_dev.mocs.internal,
 149    };
 150
 151    return vb_state.map;
 152 }
 153
 154 static void
 155 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
 156                                            const struct blorp_address *addrs,
 157                                            uint32_t *sizes,
 158                                            unsigned num_vbs)
 159 {
 160    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
 161
 162    for (unsigned i = 0; i < num_vbs; i++) {
 163       struct anv_address anv_addr = {
 164          .bo = addrs[i].buffer,
 165          .offset = addrs[i].offset,
 166       };
 167       genX(cmd_buffer_set_binding_for_gen8_vb_flush)(cmd_buffer,
 168                                                      i, anv_addr, sizes[i]);
 169    }
 170
 171    genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
 172
 173    /* Technically, we should call this *after* 3DPRIMITIVE but it doesn't
 174     * really matter for blorp because we never call apply_pipe_flushes after
 175     * this point.
 176     */
 177    genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)(cmd_buffer, SEQUENTIAL,
 178                                                        (1 << num_vbs) - 1);
 179 }
 180
 181 UNUSED static struct blorp_address
 182 blorp_get_workaround_address(struct blorp_batch *batch)
 183 {
 184    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
 185
 186    return (struct blorp_address) {
 187       .buffer = cmd_buffer->device->workaround_address.bo,
 188       .offset = cmd_buffer->device->workaround_address.offset,
 189    };
 190 }
 191
 192 static void
 193 blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
 194 {
 195    /* We don't need to flush states anymore, since everything will be snooped.
 196     */
 197 }
 198
 199 static const struct gen_l3_config *
 200 blorp_get_l3_config(struct blorp_batch *batch)
 201 {
 202    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
 203    return cmd_buffer->state.current_l3_config;
 204 }
 205
 206 void
 207 genX(blorp_exec)(struct blorp_batch *batch,
 208                  const struct blorp_params *params)
 209 {
 210    struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
 211
 212    if (!cmd_buffer->state.current_l3_config) {
 213       const struct gen_l3_config *cfg =
 214          gen_get_default_l3_config(&cmd_buffer->device->info);
 215       genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
 216    }
 217
 218    const unsigned scale = params->fast_clear_op ? UINT_MAX : 1;
 219    genX(cmd_buffer_emit_hashing_mode)(cmd_buffer, params->x1 - params->x0,
 220                                       params->y1 - params->y0, scale);
 221
 222 #if GEN_GEN >= 11
 223    /* The PIPE_CONTROL command description says:
 224     *
 225     *    "Whenever a Binding Table Index (BTI) used by a Render Taget Message
 226     *     points to a different RENDER_SURFACE_STATE, SW must issue a Render
 227     *     Target Cache Flush by enabling this bit. When render target flush
 228     *     is set due to new association of BTI, PS Scoreboard Stall bit must
 229     *     be set in this packet."
 230     */
 231    cmd_buffer->state.pending_pipe_bits |=
 232       ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
 233       ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
 234 #endif
 235
 236 #if GEN_GEN == 7
 237    /* The MI_LOAD/STORE_REGISTER_MEM commands which BLORP uses to implement
 238     * indirect fast-clear colors can cause GPU hangs if we don't stall first.
 239     * See genX(cmd_buffer_mi_memcpy) for more details.
 240     */
 241    if (params->src.clear_color_addr.buffer ||
 242        params->dst.clear_color_addr.buffer)
 243       cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
 244 #endif
 245
 246    genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
 247
 248    genX(flush_pipeline_select_3d)(cmd_buffer);
 249
 250    genX(cmd_buffer_emit_gen7_depth_flush)(cmd_buffer);
 251
 252    /* BLORP doesn't do anything fancy with depth such as discards, so we want
 253     * the PMA fix off.  Also, off is always the safe option.
 254     */
 255    genX(cmd_buffer_enable_pma_fix)(cmd_buffer, false);
 256
 257    blorp_exec(batch, params);
 258
 259 #if GEN_GEN >= 11
 260    /* The PIPE_CONTROL command description says:
 261     *
 262     *    "Whenever a Binding Table Index (BTI) used by a Render Taget Message
 263     *     points to a different RENDER_SURFACE_STATE, SW must issue a Render
 264     *     Target Cache Flush by enabling this bit. When render target flush
 265     *     is set due to new association of BTI, PS Scoreboard Stall bit must
 266     *     be set in this packet."
 267     */
 268    cmd_buffer->state.pending_pipe_bits |=
 269       ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
 270       ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
 271 #endif
 272
 273    cmd_buffer->state.gfx.vb_dirty = ~0;
 274    cmd_buffer->state.gfx.dirty = ~0;
 275    cmd_buffer->state.push_constants_dirty = ~0;
 276 }