2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
38 * - GPR 14 for secondary command buffer returns
39 * - GPR 15 for conditional rendering
41 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
42 #define __gen_get_batch_dwords anv_batch_emit_dwords
43 #define __gen_address_offset anv_address_add
44 #include "common/gen_mi_builder.h"
46 static void genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
50 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
52 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
53 lri
.RegisterOffset
= reg
;
59 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
61 struct anv_device
*device
= cmd_buffer
->device
;
62 UNUSED
const struct gen_device_info
*devinfo
= &device
->info
;
63 uint32_t mocs
= device
->isl_dev
.mocs
.internal
;
65 /* If we are emitting a new state base address we probably need to re-emit
68 cmd_buffer
->state
.descriptors_dirty
|= ~0;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
82 pc
.TileCacheFlushEnable
= true;
85 /* GEN:BUG:1606662791:
87 * Software must program PIPE_CONTROL command with "HDC Pipeline
88 * Flush" prior to programming of the below two non-pipeline state :
89 * * STATE_BASE_ADDRESS
90 * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
92 if (devinfo
->revision
== 0 /* A0 */)
93 pc
.HDCPipelineFlushEnable
= true;
98 /* GEN:BUG:1607854226:
100 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
101 * mode by putting the pipeline temporarily in 3D mode.
103 uint32_t gen12_wa_pipeline
= cmd_buffer
->state
.current_pipeline
;
104 genX(flush_pipeline_select_3d
)(cmd_buffer
);
107 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
108 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
109 sba
.GeneralStateMOCS
= mocs
;
110 sba
.GeneralStateBaseAddressModifyEnable
= true;
112 sba
.StatelessDataPortAccessMOCS
= mocs
;
114 sba
.SurfaceStateBaseAddress
=
115 anv_cmd_buffer_surface_base_address(cmd_buffer
);
116 sba
.SurfaceStateMOCS
= mocs
;
117 sba
.SurfaceStateBaseAddressModifyEnable
= true;
119 sba
.DynamicStateBaseAddress
=
120 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
121 sba
.DynamicStateMOCS
= mocs
;
122 sba
.DynamicStateBaseAddressModifyEnable
= true;
124 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
125 sba
.IndirectObjectMOCS
= mocs
;
126 sba
.IndirectObjectBaseAddressModifyEnable
= true;
128 sba
.InstructionBaseAddress
=
129 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
130 sba
.InstructionMOCS
= mocs
;
131 sba
.InstructionBaseAddressModifyEnable
= true;
134 /* Broadwell requires that we specify a buffer size for a bunch of
135 * these fields. However, since we will be growing the BO's live, we
136 * just set them all to the maximum.
138 sba
.GeneralStateBufferSize
= 0xfffff;
139 sba
.IndirectObjectBufferSize
= 0xfffff;
140 if (device
->physical
->use_softpin
) {
141 /* With softpin, we use fixed addresses so we actually know how big
142 * our base addresses are.
144 sba
.DynamicStateBufferSize
= DYNAMIC_STATE_POOL_SIZE
/ 4096;
145 sba
.InstructionBufferSize
= INSTRUCTION_STATE_POOL_SIZE
/ 4096;
147 sba
.DynamicStateBufferSize
= 0xfffff;
148 sba
.InstructionBufferSize
= 0xfffff;
150 sba
.GeneralStateBufferSizeModifyEnable
= true;
151 sba
.IndirectObjectBufferSizeModifyEnable
= true;
152 sba
.DynamicStateBufferSizeModifyEnable
= true;
153 sba
.InstructionBuffersizeModifyEnable
= true;
155 /* On gen7, we have upper bounds instead. According to the docs,
156 * setting an upper bound of zero means that no bounds checking is
157 * performed so, in theory, we should be able to leave them zero.
158 * However, border color is broken and the GPU bounds-checks anyway.
159 * To avoid this and other potential problems, we may as well set it
162 sba
.GeneralStateAccessUpperBound
=
163 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
164 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
165 sba
.DynamicStateAccessUpperBound
=
166 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
167 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
168 sba
.InstructionAccessUpperBound
=
169 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
170 sba
.InstructionAccessUpperBoundModifyEnable
= true;
173 if (cmd_buffer
->device
->physical
->use_softpin
) {
174 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
175 .bo
= device
->surface_state_pool
.block_pool
.bo
,
178 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
180 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
181 sba
.BindlessSurfaceStateSize
= 0;
183 sba
.BindlessSurfaceStateMOCS
= mocs
;
184 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
187 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
188 sba
.BindlessSamplerStateMOCS
= mocs
;
189 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
190 sba
.BindlessSamplerStateBufferSize
= 0;
195 /* GEN:BUG:1607854226:
197 * Put the pipeline back into its current mode.
199 if (gen12_wa_pipeline
!= UINT32_MAX
)
200 genX(flush_pipeline_select
)(cmd_buffer
, gen12_wa_pipeline
);
203 /* After re-setting the surface state base address, we have to do some
204 * cache flusing so that the sampler engine will pick up the new
205 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
206 * Shared Function > 3D Sampler > State > State Caching (page 96):
208 * Coherency with system memory in the state cache, like the texture
209 * cache is handled partially by software. It is expected that the
210 * command stream or shader will issue Cache Flush operation or
211 * Cache_Flush sampler message to ensure that the L1 cache remains
212 * coherent with system memory.
216 * Whenever the value of the Dynamic_State_Base_Addr,
217 * Surface_State_Base_Addr are altered, the L1 state cache must be
218 * invalidated to ensure the new surface or sampler state is fetched
219 * from system memory.
221 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
222 * which, according the PIPE_CONTROL instruction documentation in the
225 * Setting this bit is independent of any other bit in this packet.
226 * This bit controls the invalidation of the L1 and L2 state caches
227 * at the top of the pipe i.e. at the parsing time.
229 * Unfortunately, experimentation seems to indicate that state cache
230 * invalidation through a PIPE_CONTROL does nothing whatsoever in
231 * regards to surface state and binding tables. In stead, it seems that
232 * invalidating the texture cache is what is actually needed.
234 * XXX: As far as we have been able to determine through
235 * experimentation, shows that flush the texture cache appears to be
236 * sufficient. The theory here is that all of the sampling/rendering
237 * units cache the binding table in the texture cache. However, we have
238 * yet to be able to actually confirm this.
240 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
241 pc
.TextureCacheInvalidationEnable
= true;
242 pc
.ConstantCacheInvalidationEnable
= true;
243 pc
.StateCacheInvalidationEnable
= true;
248 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
249 struct anv_state state
, struct anv_address addr
)
251 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
254 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
255 state
.offset
+ isl_dev
->ss
.addr_offset
,
256 addr
.bo
, addr
.offset
, NULL
);
257 if (result
!= VK_SUCCESS
)
258 anv_batch_set_error(&cmd_buffer
->batch
, result
);
262 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
263 struct anv_surface_state state
)
265 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
267 assert(!anv_address_is_null(state
.address
));
268 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
270 if (!anv_address_is_null(state
.aux_address
)) {
272 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
273 &cmd_buffer
->pool
->alloc
,
274 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
275 state
.aux_address
.bo
,
276 state
.aux_address
.offset
,
278 if (result
!= VK_SUCCESS
)
279 anv_batch_set_error(&cmd_buffer
->batch
, result
);
282 if (!anv_address_is_null(state
.clear_address
)) {
284 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
285 &cmd_buffer
->pool
->alloc
,
287 isl_dev
->ss
.clear_color_state_offset
,
288 state
.clear_address
.bo
,
289 state
.clear_address
.offset
,
291 if (result
!= VK_SUCCESS
)
292 anv_batch_set_error(&cmd_buffer
->batch
, result
);
297 isl_color_value_requires_conversion(union isl_color_value color
,
298 const struct isl_surf
*surf
,
299 const struct isl_view
*view
)
301 if (surf
->format
== view
->format
&& isl_swizzle_is_identity(view
->swizzle
))
304 uint32_t surf_pack
[4] = { 0, 0, 0, 0 };
305 isl_color_value_pack(&color
, surf
->format
, surf_pack
);
307 uint32_t view_pack
[4] = { 0, 0, 0, 0 };
308 union isl_color_value swiz_color
=
309 isl_color_value_swizzle_inv(color
, view
->swizzle
);
310 isl_color_value_pack(&swiz_color
, view
->format
, view_pack
);
312 return memcmp(surf_pack
, view_pack
, sizeof(surf_pack
)) != 0;
316 anv_can_fast_clear_color_view(struct anv_device
* device
,
317 struct anv_image_view
*iview
,
318 VkImageLayout layout
,
319 union isl_color_value clear_color
,
321 VkRect2D render_area
)
323 if (iview
->planes
[0].isl
.base_array_layer
>=
324 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
325 iview
->planes
[0].isl
.base_level
))
328 /* Start by getting the fast clear type. We use the first subpass
329 * layout here because we don't want to fast-clear if the first subpass
330 * to use the attachment can't handle fast-clears.
332 enum anv_fast_clear_type fast_clear_type
=
333 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
334 VK_IMAGE_ASPECT_COLOR_BIT
,
336 switch (fast_clear_type
) {
337 case ANV_FAST_CLEAR_NONE
:
339 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
340 if (!isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
))
343 case ANV_FAST_CLEAR_ANY
:
347 /* Potentially, we could do partial fast-clears but doing so has crazy
348 * alignment restrictions. It's easier to just restrict to full size
349 * fast clears for now.
351 if (render_area
.offset
.x
!= 0 ||
352 render_area
.offset
.y
!= 0 ||
353 render_area
.extent
.width
!= iview
->extent
.width
||
354 render_area
.extent
.height
!= iview
->extent
.height
)
357 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
359 !isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
))
362 /* If the clear color is one that would require non-trivial format
363 * conversion on resolve, we don't bother with the fast clear. This
364 * shouldn't be common as most clear colors are 0/1 and the most common
365 * format re-interpretation is for sRGB.
367 if (isl_color_value_requires_conversion(clear_color
,
368 &iview
->image
->planes
[0].surface
.isl
,
369 &iview
->planes
[0].isl
)) {
370 anv_perf_warn(device
, iview
,
371 "Cannot fast-clear to colors which would require "
372 "format conversion on resolve");
376 /* We only allow fast clears to the first slice of an image (level 0,
377 * layer 0) and only for the entire slice. This guarantees us that, at
378 * any given time, there is only one clear color on any given image at
379 * any given time. At the time of our testing (Jan 17, 2018), there
380 * were no known applications which would benefit from fast-clearing
381 * more than just the first slice.
383 if (iview
->planes
[0].isl
.base_level
> 0 ||
384 iview
->planes
[0].isl
.base_array_layer
> 0) {
385 anv_perf_warn(device
, iview
->image
,
386 "Rendering with multi-lod or multi-layer framebuffer "
387 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
388 "baseArrayLayer > 0. Not fast clearing.");
392 if (num_layers
> 1) {
393 anv_perf_warn(device
, iview
->image
,
394 "Rendering to a multi-layer framebuffer with "
395 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
402 anv_can_hiz_clear_ds_view(struct anv_device
*device
,
403 struct anv_image_view
*iview
,
404 VkImageLayout layout
,
405 VkImageAspectFlags clear_aspects
,
406 float depth_clear_value
,
407 VkRect2D render_area
)
409 /* We don't do any HiZ or depth fast-clears on gen7 yet */
413 /* If we're just clearing stencil, we can always HiZ clear */
414 if (!(clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
417 /* We must have depth in order to have HiZ */
418 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
421 const enum isl_aux_usage clear_aux_usage
=
422 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
423 VK_IMAGE_ASPECT_DEPTH_BIT
,
424 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
426 if (!blorp_can_hiz_clear_depth(&device
->info
,
427 &iview
->image
->planes
[0].surface
.isl
,
429 iview
->planes
[0].isl
.base_level
,
430 iview
->planes
[0].isl
.base_array_layer
,
431 render_area
.offset
.x
,
432 render_area
.offset
.y
,
433 render_area
.offset
.x
+
434 render_area
.extent
.width
,
435 render_area
.offset
.y
+
436 render_area
.extent
.height
))
439 if (depth_clear_value
!= ANV_HZ_FC_VAL
)
442 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a fast-cleared
443 * portion of a HiZ buffer. Testing has revealed that Gen8 only supports
444 * returning 0.0f. Gens prior to gen8 do not support this feature at all.
446 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
))
449 /* If we got here, then we can fast clear */
453 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
457 anv_image_init_aux_tt(struct anv_cmd_buffer
*cmd_buffer
,
458 const struct anv_image
*image
,
459 VkImageAspectFlagBits aspect
,
460 uint32_t base_level
, uint32_t level_count
,
461 uint32_t base_layer
, uint32_t layer_count
)
463 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
465 uint64_t base_address
=
466 anv_address_physical(image
->planes
[plane
].address
);
468 const struct isl_surf
*isl_surf
= &image
->planes
[plane
].surface
.isl
;
469 uint64_t format_bits
= gen_aux_map_format_bits_for_isl_surf(isl_surf
);
471 /* We're about to live-update the AUX-TT. We really don't want anyone else
472 * trying to read it while we're doing this. We could probably get away
473 * with not having this stall in some cases if we were really careful but
474 * it's better to play it safe. Full stall the GPU.
476 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
477 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
479 struct gen_mi_builder b
;
480 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
482 for (uint32_t a
= 0; a
< layer_count
; a
++) {
483 const uint32_t layer
= base_layer
+ a
;
485 uint64_t start_offset_B
= UINT64_MAX
, end_offset_B
= 0;
486 for (uint32_t l
= 0; l
< level_count
; l
++) {
487 const uint32_t level
= base_level
+ l
;
489 uint32_t logical_array_layer
, logical_z_offset_px
;
490 if (image
->type
== VK_IMAGE_TYPE_3D
) {
491 logical_array_layer
= 0;
493 /* If the given miplevel does not have this layer, then any higher
494 * miplevels won't either because miplevels only get smaller the
497 assert(layer
< image
->extent
.depth
);
498 if (layer
>= anv_minify(image
->extent
.depth
, level
))
500 logical_z_offset_px
= layer
;
502 assert(layer
< image
->array_size
);
503 logical_array_layer
= layer
;
504 logical_z_offset_px
= 0;
507 uint32_t slice_start_offset_B
, slice_end_offset_B
;
508 isl_surf_get_image_range_B_tile(isl_surf
, level
,
511 &slice_start_offset_B
,
512 &slice_end_offset_B
);
514 start_offset_B
= MIN2(start_offset_B
, slice_start_offset_B
);
515 end_offset_B
= MAX2(end_offset_B
, slice_end_offset_B
);
518 /* Aux operates 64K at a time */
519 start_offset_B
= align_down_u64(start_offset_B
, 64 * 1024);
520 end_offset_B
= align_u64(end_offset_B
, 64 * 1024);
522 for (uint64_t offset
= start_offset_B
;
523 offset
< end_offset_B
; offset
+= 64 * 1024) {
524 uint64_t address
= base_address
+ offset
;
526 uint64_t aux_entry_addr64
, *aux_entry_map
;
527 aux_entry_map
= gen_aux_map_get_entry(cmd_buffer
->device
->aux_map_ctx
,
528 address
, &aux_entry_addr64
);
530 assert(cmd_buffer
->device
->physical
->use_softpin
);
531 struct anv_address aux_entry_address
= {
533 .offset
= aux_entry_addr64
,
536 const uint64_t old_aux_entry
= READ_ONCE(*aux_entry_map
);
537 uint64_t new_aux_entry
=
538 (old_aux_entry
& GEN_AUX_MAP_ADDRESS_MASK
) | format_bits
;
540 if (isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
))
541 new_aux_entry
|= GEN_AUX_MAP_ENTRY_VALID_BIT
;
543 gen_mi_store(&b
, gen_mi_mem64(aux_entry_address
),
544 gen_mi_imm(new_aux_entry
));
548 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
550 #endif /* GEN_GEN == 12 */
552 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
553 * the initial layout is undefined, the HiZ buffer and depth buffer will
554 * represent the same data at the end of this operation.
557 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
558 const struct anv_image
*image
,
559 uint32_t base_layer
, uint32_t layer_count
,
560 VkImageLayout initial_layout
,
561 VkImageLayout final_layout
)
563 uint32_t depth_plane
=
564 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
565 if (image
->planes
[depth_plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
569 if ((initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
570 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) &&
571 cmd_buffer
->device
->physical
->has_implicit_ccs
&&
572 cmd_buffer
->device
->info
.has_aux_map
) {
573 anv_image_init_aux_tt(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
578 const enum isl_aux_state initial_state
=
579 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
580 VK_IMAGE_ASPECT_DEPTH_BIT
,
582 const enum isl_aux_state final_state
=
583 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
584 VK_IMAGE_ASPECT_DEPTH_BIT
,
587 const bool initial_depth_valid
=
588 isl_aux_state_has_valid_primary(initial_state
);
589 const bool initial_hiz_valid
=
590 isl_aux_state_has_valid_aux(initial_state
);
591 const bool final_needs_depth
=
592 isl_aux_state_has_valid_primary(final_state
);
593 const bool final_needs_hiz
=
594 isl_aux_state_has_valid_aux(final_state
);
596 /* Getting into the pass-through state for Depth is tricky and involves
597 * both a resolve and an ambiguate. We don't handle that state right now
598 * as anv_layout_to_aux_state never returns it.
600 assert(final_state
!= ISL_AUX_STATE_PASS_THROUGH
);
602 if (final_needs_depth
&& !initial_depth_valid
) {
603 assert(initial_hiz_valid
);
604 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
605 0, base_layer
, layer_count
, ISL_AUX_OP_FULL_RESOLVE
);
606 } else if (final_needs_hiz
&& !initial_hiz_valid
) {
607 assert(initial_depth_valid
);
608 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
609 0, base_layer
, layer_count
, ISL_AUX_OP_AMBIGUATE
);
614 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
616 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
617 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
||
618 layout
== VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
;
621 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
622 * the initial layout is undefined, the HiZ buffer and depth buffer will
623 * represent the same data at the end of this operation.
626 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
627 const struct anv_image
*image
,
628 uint32_t base_level
, uint32_t level_count
,
629 uint32_t base_layer
, uint32_t layer_count
,
630 VkImageLayout initial_layout
,
631 VkImageLayout final_layout
)
634 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
635 VK_IMAGE_ASPECT_STENCIL_BIT
);
637 /* On gen7, we have to store a texturable version of the stencil buffer in
638 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
639 * forth at strategic points. Stencil writes are only allowed in following
642 * - VK_IMAGE_LAYOUT_GENERAL
643 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
644 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
645 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
646 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
648 * For general, we have no nice opportunity to transition so we do the copy
649 * to the shadow unconditionally at the end of the subpass. For transfer
650 * destinations, we can update it as part of the transfer op. For the other
651 * layouts, we delay the copy until a transition into some other layout.
653 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
654 vk_image_layout_stencil_write_optimal(initial_layout
) &&
655 !vk_image_layout_stencil_write_optimal(final_layout
)) {
656 anv_image_copy_to_shadow(cmd_buffer
, image
,
657 VK_IMAGE_ASPECT_STENCIL_BIT
,
658 base_level
, level_count
,
659 base_layer
, layer_count
);
661 #endif /* GEN_GEN == 7 */
664 #define MI_PREDICATE_SRC0 0x2400
665 #define MI_PREDICATE_SRC1 0x2408
666 #define MI_PREDICATE_RESULT 0x2418
669 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
670 const struct anv_image
*image
,
671 VkImageAspectFlagBits aspect
,
673 uint32_t base_layer
, uint32_t layer_count
,
676 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
678 /* We only have compression tracking for CCS_E */
679 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
682 for (uint32_t a
= 0; a
< layer_count
; a
++) {
683 uint32_t layer
= base_layer
+ a
;
684 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
685 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
688 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
694 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
695 const struct anv_image
*image
,
696 VkImageAspectFlagBits aspect
,
697 enum anv_fast_clear_type fast_clear
)
699 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
700 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
702 sdi
.ImmediateData
= fast_clear
;
705 /* Whenever we have fast-clear, we consider that slice to be compressed.
706 * This makes building predicates much easier.
708 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
709 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
712 /* This is only really practical on haswell and above because it requires
713 * MI math in order to get it correct.
715 #if GEN_GEN >= 8 || GEN_IS_HASWELL
717 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
718 const struct anv_image
*image
,
719 VkImageAspectFlagBits aspect
,
720 uint32_t level
, uint32_t array_layer
,
721 enum isl_aux_op resolve_op
,
722 enum anv_fast_clear_type fast_clear_supported
)
724 struct gen_mi_builder b
;
725 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
727 const struct gen_mi_value fast_clear_type
=
728 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
731 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
732 /* In this case, we're doing a full resolve which means we want the
733 * resolve to happen if any compression (including fast-clears) is
736 * In order to simplify the logic a bit, we make the assumption that,
737 * if the first slice has been fast-cleared, it is also marked as
738 * compressed. See also set_image_fast_clear_state.
740 const struct gen_mi_value compression_state
=
741 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
743 level
, array_layer
));
744 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
746 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
748 if (level
== 0 && array_layer
== 0) {
749 /* If the predicate is true, we want to write 0 to the fast clear type
750 * and, if it's false, leave it alone. We can do this by writing
752 * clear_type = clear_type & ~predicate;
754 struct gen_mi_value new_fast_clear_type
=
755 gen_mi_iand(&b
, fast_clear_type
,
756 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
757 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
759 } else if (level
== 0 && array_layer
== 0) {
760 /* In this case, we are doing a partial resolve to get rid of fast-clear
761 * colors. We don't care about the compression state but we do care
762 * about how much fast clear is allowed by the final layout.
764 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
765 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
767 /* We need to compute (fast_clear_supported < image->fast_clear) */
768 struct gen_mi_value pred
=
769 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
770 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
771 gen_mi_value_ref(&b
, pred
));
773 /* If the predicate is true, we want to write 0 to the fast clear type
774 * and, if it's false, leave it alone. We can do this by writing
776 * clear_type = clear_type & ~predicate;
778 struct gen_mi_value new_fast_clear_type
=
779 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
780 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
782 /* In this case, we're trying to do a partial resolve on a slice that
783 * doesn't have clear color. There's nothing to do.
785 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
789 /* Set src1 to 0 and use a != condition */
790 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
792 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
793 mip
.LoadOperation
= LOAD_LOADINV
;
794 mip
.CombineOperation
= COMBINE_SET
;
795 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
798 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
802 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
803 const struct anv_image
*image
,
804 VkImageAspectFlagBits aspect
,
805 uint32_t level
, uint32_t array_layer
,
806 enum isl_aux_op resolve_op
,
807 enum anv_fast_clear_type fast_clear_supported
)
809 struct gen_mi_builder b
;
810 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
812 struct gen_mi_value fast_clear_type_mem
=
813 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
816 /* This only works for partial resolves and only when the clear color is
817 * all or nothing. On the upside, this emits less command streamer code
818 * and works on Ivybridge and Bay Trail.
820 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
821 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
823 /* We don't support fast clears on anything other than the first slice. */
824 if (level
> 0 || array_layer
> 0)
827 /* On gen8, we don't have a concept of default clear colors because we
828 * can't sample from CCS surfaces. It's enough to just load the fast clear
829 * state into the predicate register.
831 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
832 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
833 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
835 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
836 mip
.LoadOperation
= LOAD_LOADINV
;
837 mip
.CombineOperation
= COMBINE_SET
;
838 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
841 #endif /* GEN_GEN <= 8 */
844 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
845 const struct anv_image
*image
,
846 enum isl_format format
,
847 struct isl_swizzle swizzle
,
848 VkImageAspectFlagBits aspect
,
849 uint32_t level
, uint32_t array_layer
,
850 enum isl_aux_op resolve_op
,
851 enum anv_fast_clear_type fast_clear_supported
)
853 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
856 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
857 aspect
, level
, array_layer
,
858 resolve_op
, fast_clear_supported
);
859 #else /* GEN_GEN <= 8 */
860 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
861 aspect
, level
, array_layer
,
862 resolve_op
, fast_clear_supported
);
865 /* CCS_D only supports full resolves and BLORP will assert on us if we try
866 * to do a partial resolve on a CCS_D surface.
868 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
869 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_D
)
870 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
872 anv_image_ccs_op(cmd_buffer
, image
, format
, swizzle
, aspect
,
873 level
, array_layer
, 1, resolve_op
, NULL
, true);
877 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
878 const struct anv_image
*image
,
879 enum isl_format format
,
880 struct isl_swizzle swizzle
,
881 VkImageAspectFlagBits aspect
,
882 uint32_t array_layer
,
883 enum isl_aux_op resolve_op
,
884 enum anv_fast_clear_type fast_clear_supported
)
886 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
887 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
889 #if GEN_GEN >= 8 || GEN_IS_HASWELL
890 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
891 aspect
, 0, array_layer
,
892 resolve_op
, fast_clear_supported
);
894 anv_image_mcs_op(cmd_buffer
, image
, format
, swizzle
, aspect
,
895 array_layer
, 1, resolve_op
, NULL
, true);
897 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
902 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
903 const struct anv_image
*image
,
904 VkImageAspectFlagBits aspect
,
905 enum isl_aux_usage aux_usage
,
908 uint32_t layer_count
)
910 /* The aspect must be exactly one of the image aspects. */
911 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
913 /* The only compression types with more than just fast-clears are MCS,
914 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
915 * track the current fast-clear and compression state. This leaves us
916 * with just MCS and CCS_E.
918 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
919 aux_usage
!= ISL_AUX_USAGE_MCS
)
922 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
923 level
, base_layer
, layer_count
, true);
927 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
928 const struct anv_image
*image
,
929 VkImageAspectFlagBits aspect
)
931 assert(cmd_buffer
&& image
);
932 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
934 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
935 ANV_FAST_CLEAR_NONE
);
937 /* Initialize the struct fields that are accessed for fast-clears so that
938 * the HW restrictions on the field values are satisfied.
940 struct anv_address addr
=
941 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
944 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
945 const unsigned num_dwords
= GEN_GEN
>= 10 ?
946 isl_dev
->ss
.clear_color_state_size
/ 4 :
947 isl_dev
->ss
.clear_value_size
/ 4;
948 for (unsigned i
= 0; i
< num_dwords
; i
++) {
949 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
951 sdi
.Address
.offset
+= i
* 4;
952 sdi
.ImmediateData
= 0;
956 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
958 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
959 /* Pre-SKL, the dword containing the clear values also contains
960 * other fields, so we need to initialize those fields to match the
961 * values that would be in a color attachment.
963 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
964 ISL_CHANNEL_SELECT_GREEN
<< 22 |
965 ISL_CHANNEL_SELECT_BLUE
<< 19 |
966 ISL_CHANNEL_SELECT_ALPHA
<< 16;
967 } else if (GEN_GEN
== 7) {
968 /* On IVB, the dword containing the clear values also contains
969 * other fields that must be zero or can be zero.
971 sdi
.ImmediateData
= 0;
977 /* Copy the fast-clear value dword(s) between a surface state object and an
978 * image's fast clear state buffer.
981 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
982 struct anv_state surface_state
,
983 const struct anv_image
*image
,
984 VkImageAspectFlagBits aspect
,
985 bool copy_from_surface_state
)
987 assert(cmd_buffer
&& image
);
988 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
990 struct anv_address ss_clear_addr
= {
991 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
992 .offset
= surface_state
.offset
+
993 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
995 const struct anv_address entry_addr
=
996 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
997 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
1000 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
1001 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
1002 * in-flight when they are issued even if the memory touched is not
1003 * currently active for rendering. The weird bit is that it is not the
1004 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
1005 * rendering hangs such that the next stalling command after the
1006 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
1008 * It is unclear exactly why this hang occurs. Both MI commands come with
1009 * warnings about the 3D pipeline but that doesn't seem to fully explain
1010 * it. My (Jason's) best theory is that it has something to do with the
1011 * fact that we're using a GPU state register as our temporary and that
1012 * something with reading/writing it is causing problems.
1014 * In order to work around this issue, we emit a PIPE_CONTROL with the
1015 * command streamer stall bit set.
1017 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1018 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1021 struct gen_mi_builder b
;
1022 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
1024 if (copy_from_surface_state
) {
1025 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
1027 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
1029 /* Updating a surface state object may require that the state cache be
1030 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1033 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1034 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1035 * modified [...], the L1 state cache must be invalidated to ensure
1036 * the new surface or sampler state is fetched from system memory.
1038 * In testing, SKL doesn't actually seem to need this, but HSW does.
1040 cmd_buffer
->state
.pending_pipe_bits
|=
1041 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1046 * @brief Transitions a color buffer from one layout to another.
1048 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
1051 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
1052 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
1053 * this represents the maximum layers to transition at each
1054 * specified miplevel.
1057 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
1058 const struct anv_image
*image
,
1059 VkImageAspectFlagBits aspect
,
1060 const uint32_t base_level
, uint32_t level_count
,
1061 uint32_t base_layer
, uint32_t layer_count
,
1062 VkImageLayout initial_layout
,
1063 VkImageLayout final_layout
)
1065 struct anv_device
*device
= cmd_buffer
->device
;
1066 const struct gen_device_info
*devinfo
= &device
->info
;
1067 /* Validate the inputs. */
1069 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
1070 /* These values aren't supported for simplicity's sake. */
1071 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
1072 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
1073 /* Ensure the subresource range is valid. */
1074 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
1075 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
1076 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
1077 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
1078 assert(last_level_num
<= image
->levels
);
1079 /* The spec disallows these final layouts. */
1080 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
1081 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
1083 /* No work is necessary if the layout stays the same or if this subresource
1084 * range lacks auxiliary data.
1086 if (initial_layout
== final_layout
)
1089 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1091 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
1092 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
1093 /* This surface is a linear compressed image with a tiled shadow surface
1094 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
1095 * we need to ensure the shadow copy is up-to-date.
1097 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1098 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
1099 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1100 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
1102 anv_image_copy_to_shadow(cmd_buffer
, image
,
1103 VK_IMAGE_ASPECT_COLOR_BIT
,
1104 base_level
, level_count
,
1105 base_layer
, layer_count
);
1108 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1111 assert(image
->planes
[plane
].surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1113 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1114 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1116 if (device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
) {
1117 anv_image_init_aux_tt(cmd_buffer
, image
, aspect
,
1118 base_level
, level_count
,
1119 base_layer
, layer_count
);
1122 assert(!(device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
));
1125 /* A subresource in the undefined layout may have been aliased and
1126 * populated with any arrangement of bits. Therefore, we must initialize
1127 * the related aux buffer and clear buffer entry with desirable values.
1128 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1129 * images with VK_IMAGE_TILING_OPTIMAL.
1131 * Initialize the relevant clear buffer entries.
1133 if (base_level
== 0 && base_layer
== 0)
1134 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1136 /* Initialize the aux buffers to enable correct rendering. In order to
1137 * ensure that things such as storage images work correctly, aux buffers
1138 * need to be initialized to valid data.
1140 * Having an aux buffer with invalid data is a problem for two reasons:
1142 * 1) Having an invalid value in the buffer can confuse the hardware.
1143 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1144 * invalid and leads to the hardware doing strange things. It
1145 * doesn't hang as far as we can tell but rendering corruption can
1148 * 2) If this transition is into the GENERAL layout and we then use the
1149 * image as a storage image, then we must have the aux buffer in the
1150 * pass-through state so that, if we then go to texture from the
1151 * image, we get the results of our storage image writes and not the
1152 * fast clear color or other random data.
1154 * For CCS both of the problems above are real demonstrable issues. In
1155 * that case, the only thing we can do is to perform an ambiguate to
1156 * transition the aux surface into the pass-through state.
1158 * For MCS, (2) is never an issue because we don't support multisampled
1159 * storage images. In theory, issue (1) is a problem with MCS but we've
1160 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1161 * theory, be interpreted as something but we don't know that all bit
1162 * patterns are actually valid. For 2x and 8x, you could easily end up
1163 * with the MCS referring to an invalid plane because not all bits of
1164 * the MCS value are actually used. Even though we've never seen issues
1165 * in the wild, it's best to play it safe and initialize the MCS. We
1166 * can use a fast-clear for MCS because we only ever touch from render
1167 * and texture (no image load store).
1169 if (image
->samples
== 1) {
1170 for (uint32_t l
= 0; l
< level_count
; l
++) {
1171 const uint32_t level
= base_level
+ l
;
1173 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1174 if (base_layer
>= aux_layers
)
1175 break; /* We will only get fewer layers as level increases */
1176 uint32_t level_layer_count
=
1177 MIN2(layer_count
, aux_layers
- base_layer
);
1179 anv_image_ccs_op(cmd_buffer
, image
,
1180 image
->planes
[plane
].surface
.isl
.format
,
1181 ISL_SWIZZLE_IDENTITY
,
1182 aspect
, level
, base_layer
, level_layer_count
,
1183 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1185 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1186 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1187 level
, base_layer
, level_layer_count
,
1192 if (image
->samples
== 4 || image
->samples
== 16) {
1193 anv_perf_warn(cmd_buffer
->device
, image
,
1194 "Doing a potentially unnecessary fast-clear to "
1195 "define an MCS buffer.");
1198 assert(base_level
== 0 && level_count
== 1);
1199 anv_image_mcs_op(cmd_buffer
, image
,
1200 image
->planes
[plane
].surface
.isl
.format
,
1201 ISL_SWIZZLE_IDENTITY
,
1202 aspect
, base_layer
, layer_count
,
1203 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1208 const enum isl_aux_usage initial_aux_usage
=
1209 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, initial_layout
);
1210 const enum isl_aux_usage final_aux_usage
=
1211 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, final_layout
);
1213 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1214 * We can handle transitions between CCS_D/E to and from NONE. What we
1215 * don't yet handle is switching between CCS_E and CCS_D within a given
1216 * image. Doing so in a performant way requires more detailed aux state
1217 * tracking such as what is done in i965. For now, just assume that we
1218 * only have one type of compression.
1220 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1221 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1222 initial_aux_usage
== final_aux_usage
);
1224 /* If initial aux usage is NONE, there is nothing to resolve */
1225 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1228 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1230 /* If the initial layout supports more fast clear than the final layout
1231 * then we need at least a partial resolve.
1233 const enum anv_fast_clear_type initial_fast_clear
=
1234 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1235 const enum anv_fast_clear_type final_fast_clear
=
1236 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1237 if (final_fast_clear
< initial_fast_clear
)
1238 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1240 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1241 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1242 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1244 if (resolve_op
== ISL_AUX_OP_NONE
)
1247 /* Perform a resolve to synchronize data between the main and aux buffer.
1248 * Before we begin, we must satisfy the cache flushing requirement specified
1249 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1251 * Any transition from any value in {Clear, Render, Resolve} to a
1252 * different value in {Clear, Render, Resolve} requires end of pipe
1255 * We perform a flush of the write cache before and after the clear and
1256 * resolve operations to meet this requirement.
1258 * Unlike other drawing, fast clear operations are not properly
1259 * synchronized. The first PIPE_CONTROL here likely ensures that the
1260 * contents of the previous render or clear hit the render target before we
1261 * resolve and the second likely ensures that the resolve is complete before
1262 * we do any more rendering or clearing.
1264 cmd_buffer
->state
.pending_pipe_bits
|=
1265 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1267 for (uint32_t l
= 0; l
< level_count
; l
++) {
1268 uint32_t level
= base_level
+ l
;
1270 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1271 if (base_layer
>= aux_layers
)
1272 break; /* We will only get fewer layers as level increases */
1273 uint32_t level_layer_count
=
1274 MIN2(layer_count
, aux_layers
- base_layer
);
1276 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1277 uint32_t array_layer
= base_layer
+ a
;
1278 if (image
->samples
== 1) {
1279 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1280 image
->planes
[plane
].surface
.isl
.format
,
1281 ISL_SWIZZLE_IDENTITY
,
1282 aspect
, level
, array_layer
, resolve_op
,
1285 /* We only support fast-clear on the first layer so partial
1286 * resolves should not be used on other layers as they will use
1287 * the clear color stored in memory that is only valid for layer0.
1289 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1293 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1294 image
->planes
[plane
].surface
.isl
.format
,
1295 ISL_SWIZZLE_IDENTITY
,
1296 aspect
, array_layer
, resolve_op
,
1302 cmd_buffer
->state
.pending_pipe_bits
|=
1303 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1307 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1308 const struct anv_render_pass
*pass
,
1309 const struct anv_framebuffer
*framebuffer
,
1310 const VkRenderPassBeginInfo
*begin
)
1312 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1314 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1316 if (pass
->attachment_count
> 0) {
1317 state
->attachments
= vk_zalloc(&cmd_buffer
->pool
->alloc
,
1318 pass
->attachment_count
*
1319 sizeof(state
->attachments
[0]),
1320 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1321 if (state
->attachments
== NULL
) {
1322 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1323 return anv_batch_set_error(&cmd_buffer
->batch
,
1324 VK_ERROR_OUT_OF_HOST_MEMORY
);
1327 state
->attachments
= NULL
;
1330 const VkRenderPassAttachmentBeginInfoKHR
*attach_begin
=
1331 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1332 if (begin
&& !attach_begin
)
1333 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1335 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1336 if (attach_begin
&& attach_begin
->attachmentCount
!= 0) {
1337 assert(attach_begin
->attachmentCount
== pass
->attachment_count
);
1338 ANV_FROM_HANDLE(anv_image_view
, iview
, attach_begin
->pAttachments
[i
]);
1339 state
->attachments
[i
].image_view
= iview
;
1340 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1341 state
->attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1343 state
->attachments
[i
].image_view
= NULL
;
1348 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1349 const struct anv_render_pass_attachment
*pass_att
= &pass
->attachments
[i
];
1350 struct anv_attachment_state
*att_state
= &state
->attachments
[i
];
1351 VkImageAspectFlags att_aspects
= vk_format_aspects(pass_att
->format
);
1352 VkImageAspectFlags clear_aspects
= 0;
1353 VkImageAspectFlags load_aspects
= 0;
1355 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1356 /* color attachment */
1357 if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1358 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1359 } else if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1360 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1363 /* depthstencil attachment */
1364 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1365 if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1366 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1367 } else if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1368 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1371 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1372 if (pass_att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1373 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1374 } else if (pass_att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1375 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1380 att_state
->current_layout
= pass_att
->initial_layout
;
1381 att_state
->current_stencil_layout
= pass_att
->stencil_initial_layout
;
1382 att_state
->pending_clear_aspects
= clear_aspects
;
1383 att_state
->pending_load_aspects
= load_aspects
;
1385 att_state
->clear_value
= begin
->pClearValues
[i
];
1387 struct anv_image_view
*iview
= state
->attachments
[i
].image_view
;
1388 anv_assert(iview
->vk_format
== pass_att
->format
);
1390 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1391 att_state
->pending_clear_views
= (1 << num_layers
) - 1;
1393 /* This will be initialized after the first subpass transition. */
1394 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
1396 att_state
->fast_clear
= false;
1397 if (clear_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1398 assert(clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1399 att_state
->fast_clear
=
1400 anv_can_fast_clear_color_view(cmd_buffer
->device
, iview
,
1401 pass_att
->first_subpass_layout
,
1402 vk_to_isl_color(att_state
->clear_value
.color
),
1403 framebuffer
->layers
,
1405 } else if (clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1406 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1407 att_state
->fast_clear
=
1408 anv_can_hiz_clear_ds_view(cmd_buffer
->device
, iview
,
1409 pass_att
->first_subpass_layout
,
1411 att_state
->clear_value
.depthStencil
.depth
,
1421 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1424 genX(cmd_buffer_alloc_att_surf_states
)(struct anv_cmd_buffer
*cmd_buffer
,
1425 const struct anv_render_pass
*pass
,
1426 const struct anv_subpass
*subpass
)
1428 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1429 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1431 /* Reserve one for the NULL state. */
1432 unsigned num_states
= 1;
1433 for (uint32_t i
= 0; i
< subpass
->attachment_count
; i
++) {
1434 uint32_t att
= subpass
->attachments
[i
].attachment
;
1435 if (att
== VK_ATTACHMENT_UNUSED
)
1438 assert(att
< pass
->attachment_count
);
1439 if (!vk_format_is_color(pass
->attachments
[att
].format
))
1442 const VkImageUsageFlagBits att_usage
= subpass
->attachments
[i
].usage
;
1443 assert(util_bitcount(att_usage
) == 1);
1445 if (att_usage
== VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
||
1446 att_usage
== VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
1450 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1451 state
->attachment_states
=
1452 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1453 num_states
* ss_stride
, isl_dev
->ss
.align
);
1454 if (state
->attachment_states
.map
== NULL
) {
1455 return anv_batch_set_error(&cmd_buffer
->batch
,
1456 VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1459 struct anv_state next_state
= state
->attachment_states
;
1460 next_state
.alloc_size
= isl_dev
->ss
.size
;
1462 state
->null_surface_state
= next_state
;
1463 next_state
.offset
+= ss_stride
;
1464 next_state
.map
+= ss_stride
;
1466 for (uint32_t i
= 0; i
< subpass
->attachment_count
; i
++) {
1467 uint32_t att
= subpass
->attachments
[i
].attachment
;
1468 if (att
== VK_ATTACHMENT_UNUSED
)
1471 assert(att
< pass
->attachment_count
);
1472 if (!vk_format_is_color(pass
->attachments
[att
].format
))
1475 const VkImageUsageFlagBits att_usage
= subpass
->attachments
[i
].usage
;
1476 assert(util_bitcount(att_usage
) == 1);
1478 if (att_usage
== VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
1479 state
->attachments
[att
].color
.state
= next_state
;
1480 else if (att_usage
== VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
1481 state
->attachments
[att
].input
.state
= next_state
;
1485 state
->attachments
[att
].color
.state
= next_state
;
1486 next_state
.offset
+= ss_stride
;
1487 next_state
.map
+= ss_stride
;
1490 assert(next_state
.offset
== state
->attachment_states
.offset
+
1491 state
->attachment_states
.alloc_size
);
1497 genX(BeginCommandBuffer
)(
1498 VkCommandBuffer commandBuffer
,
1499 const VkCommandBufferBeginInfo
* pBeginInfo
)
1501 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1503 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1504 * command buffer's state. Otherwise, we must *reset* its state. In both
1505 * cases we reset it.
1507 * From the Vulkan 1.0 spec:
1509 * If a command buffer is in the executable state and the command buffer
1510 * was allocated from a command pool with the
1511 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1512 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1513 * as if vkResetCommandBuffer had been called with
1514 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1515 * the command buffer in the recording state.
1517 anv_cmd_buffer_reset(cmd_buffer
);
1519 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1521 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1522 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1524 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1526 /* We sometimes store vertex data in the dynamic state buffer for blorp
1527 * operations and our dynamic state stream may re-use data from previous
1528 * command buffers. In order to prevent stale cache data, we flush the VF
1529 * cache. We could do this on every blorp call but that's not really
1530 * needed as all of the data will get written by the CPU prior to the GPU
1531 * executing anything. The chances are fairly high that they will use
1532 * blorp at least once per primary command buffer so it shouldn't be
1535 * There is also a workaround on gen8 which requires us to invalidate the
1536 * VF cache occasionally. It's easier if we can assume we start with a
1537 * fresh cache (See also genX(cmd_buffer_set_binding_for_gen8_vb_flush).)
1539 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1541 /* Re-emit the aux table register in every command buffer. This way we're
1542 * ensured that we have the table even if this command buffer doesn't
1543 * initialize any images.
1545 if (cmd_buffer
->device
->info
.has_aux_map
)
1546 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
1548 /* We send an "Indirect State Pointers Disable" packet at
1549 * EndCommandBuffer, so all push contant packets are ignored during a
1550 * context restore. Documentation says after that command, we need to
1551 * emit push constants again before any rendering operation. So we
1552 * flag them dirty here to make sure they get emitted.
1554 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1556 VkResult result
= VK_SUCCESS
;
1557 if (cmd_buffer
->usage_flags
&
1558 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1559 assert(pBeginInfo
->pInheritanceInfo
);
1560 ANV_FROM_HANDLE(anv_render_pass
, pass
,
1561 pBeginInfo
->pInheritanceInfo
->renderPass
);
1562 struct anv_subpass
*subpass
=
1563 &pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1564 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
,
1565 pBeginInfo
->pInheritanceInfo
->framebuffer
);
1567 cmd_buffer
->state
.pass
= pass
;
1568 cmd_buffer
->state
.subpass
= subpass
;
1570 /* This is optional in the inheritance info. */
1571 cmd_buffer
->state
.framebuffer
= framebuffer
;
1573 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
,
1575 if (result
!= VK_SUCCESS
)
1578 result
= genX(cmd_buffer_alloc_att_surf_states
)(cmd_buffer
, pass
,
1580 if (result
!= VK_SUCCESS
)
1583 /* Record that HiZ is enabled if we can. */
1584 if (cmd_buffer
->state
.framebuffer
) {
1585 const struct anv_image_view
* const iview
=
1586 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1589 VkImageLayout layout
=
1590 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1592 enum isl_aux_usage aux_usage
=
1593 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1594 VK_IMAGE_ASPECT_DEPTH_BIT
,
1595 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
1598 cmd_buffer
->state
.hiz_enabled
= isl_aux_usage_has_hiz(aux_usage
);
1602 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1605 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1606 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1607 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1608 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1610 /* If secondary buffer supports conditional rendering
1611 * we should emit commands as if conditional rendering is enabled.
1613 cmd_buffer
->state
.conditional_render_enabled
=
1614 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1621 /* From the PRM, Volume 2a:
1623 * "Indirect State Pointers Disable
1625 * At the completion of the post-sync operation associated with this pipe
1626 * control packet, the indirect state pointers in the hardware are
1627 * considered invalid; the indirect pointers are not saved in the context.
1628 * If any new indirect state commands are executed in the command stream
1629 * while the pipe control is pending, the new indirect state commands are
1632 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1633 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1634 * commands are only considered as Indirect State Pointers. Once ISP is
1635 * issued in a context, SW must initialize by programming push constant
1636 * commands for all the shaders (at least to zero length) before attempting
1637 * any rendering operation for the same context."
1639 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1640 * even though they point to a BO that has been already unreferenced at
1641 * the end of the previous batch buffer. This has been fine so far since
1642 * we are protected by these scratch page (every address not covered by
1643 * a BO should be pointing to the scratch page). But on CNL, it is
1644 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1647 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1648 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1649 * context restore, so the mentioned hang doesn't happen. However,
1650 * software must program push constant commands for all stages prior to
1651 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1653 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1654 * constants have been loaded into the EUs prior to disable the push constants
1655 * so that it doesn't hang a previous 3DPRIMITIVE.
1658 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1660 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1661 pc
.StallAtPixelScoreboard
= true;
1662 pc
.CommandStreamerStallEnable
= true;
1664 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1665 pc
.IndirectStatePointersDisable
= true;
1666 pc
.CommandStreamerStallEnable
= true;
1671 genX(EndCommandBuffer
)(
1672 VkCommandBuffer commandBuffer
)
1674 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1676 if (anv_batch_has_error(&cmd_buffer
->batch
))
1677 return cmd_buffer
->batch
.status
;
1679 /* We want every command buffer to start with the PMA fix in a known state,
1680 * so we disable it at the end of the command buffer.
1682 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1684 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1686 emit_isp_disable(cmd_buffer
);
1688 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1694 genX(CmdExecuteCommands
)(
1695 VkCommandBuffer commandBuffer
,
1696 uint32_t commandBufferCount
,
1697 const VkCommandBuffer
* pCmdBuffers
)
1699 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1701 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1703 if (anv_batch_has_error(&primary
->batch
))
1706 /* The secondary command buffers will assume that the PMA fix is disabled
1707 * when they begin executing. Make sure this is true.
1709 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1711 /* The secondary command buffer doesn't know which textures etc. have been
1712 * flushed prior to their execution. Apply those flushes now.
1714 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1716 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1717 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1719 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1720 assert(!anv_batch_has_error(&secondary
->batch
));
1722 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1723 if (secondary
->state
.conditional_render_enabled
) {
1724 if (!primary
->state
.conditional_render_enabled
) {
1725 /* Secondary buffer is constructed as if it will be executed
1726 * with conditional rendering, we should satisfy this dependency
1727 * regardless of conditional rendering being enabled in primary.
1729 struct gen_mi_builder b
;
1730 gen_mi_builder_init(&b
, &primary
->batch
);
1731 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1732 gen_mi_imm(UINT64_MAX
));
1737 if (secondary
->usage_flags
&
1738 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1739 /* If we're continuing a render pass from the primary, we need to
1740 * copy the surface states for the current subpass into the storage
1741 * we allocated for them in BeginCommandBuffer.
1743 struct anv_bo
*ss_bo
=
1744 primary
->device
->surface_state_pool
.block_pool
.bo
;
1745 struct anv_state src_state
= primary
->state
.attachment_states
;
1746 struct anv_state dst_state
= secondary
->state
.attachment_states
;
1747 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1749 genX(cmd_buffer_so_memcpy
)(primary
,
1750 (struct anv_address
) {
1752 .offset
= dst_state
.offset
,
1754 (struct anv_address
) {
1756 .offset
= src_state
.offset
,
1758 src_state
.alloc_size
);
1761 anv_cmd_buffer_add_secondary(primary
, secondary
);
1763 assert(secondary
->perf_query_pool
== NULL
|| primary
->perf_query_pool
== NULL
||
1764 secondary
->perf_query_pool
== primary
->perf_query_pool
);
1765 if (secondary
->perf_query_pool
)
1766 primary
->perf_query_pool
= secondary
->perf_query_pool
;
1769 /* The secondary isn't counted in our VF cache tracking so we need to
1770 * invalidate the whole thing.
1772 if (GEN_GEN
>= 8 && GEN_GEN
<= 9) {
1773 primary
->state
.pending_pipe_bits
|=
1774 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1777 /* The secondary may have selected a different pipeline (3D or compute) and
1778 * may have changed the current L3$ configuration. Reset our tracking
1779 * variables to invalid values to ensure that we re-emit these in the case
1780 * where we do any draws or compute dispatches from the primary after the
1781 * secondary has returned.
1783 primary
->state
.current_pipeline
= UINT32_MAX
;
1784 primary
->state
.current_l3_config
= NULL
;
1785 primary
->state
.current_hash_scale
= 0;
1787 /* Each of the secondary command buffers will use its own state base
1788 * address. We need to re-emit state base address for the primary after
1789 * all of the secondaries are done.
1791 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1794 genX(cmd_buffer_emit_state_base_address
)(primary
);
1797 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1798 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1799 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1802 * Program the hardware to use the specified L3 configuration.
1805 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1806 const struct gen_l3_config
*cfg
)
1808 assert(cfg
|| GEN_GEN
>= 12);
1809 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1812 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1813 intel_logd("L3 config transition: ");
1814 gen_dump_l3_config(cfg
, stderr
);
1817 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1819 /* According to the hardware docs, the L3 partitioning can only be changed
1820 * while the pipeline is completely drained and the caches are flushed,
1821 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1823 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1824 pc
.DCFlushEnable
= true;
1825 pc
.PostSyncOperation
= NoWrite
;
1826 pc
.CommandStreamerStallEnable
= true;
1829 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1830 * invalidation of the relevant caches. Note that because RO invalidation
1831 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1832 * command is processed by the CS) we cannot combine it with the previous
1833 * stalling flush as the hardware documentation suggests, because that
1834 * would cause the CS to stall on previous rendering *after* RO
1835 * invalidation and wouldn't prevent the RO caches from being polluted by
1836 * concurrent rendering before the stall completes. This intentionally
1837 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1838 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1839 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1840 * already guarantee that there is no concurrent GPGPU kernel execution
1841 * (see SKL HSD 2132585).
1843 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1844 pc
.TextureCacheInvalidationEnable
= true;
1845 pc
.ConstantCacheInvalidationEnable
= true;
1846 pc
.InstructionCacheInvalidateEnable
= true;
1847 pc
.StateCacheInvalidationEnable
= true;
1848 pc
.PostSyncOperation
= NoWrite
;
1851 /* Now send a third stalling flush to make sure that invalidation is
1852 * complete when the L3 configuration registers are modified.
1854 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1855 pc
.DCFlushEnable
= true;
1856 pc
.PostSyncOperation
= NoWrite
;
1857 pc
.CommandStreamerStallEnable
= true;
1862 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1865 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1866 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1868 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1869 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1873 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1875 .SLMEnable
= has_slm
,
1878 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1879 * in L3CNTLREG register. The default setting of the bit is not the
1880 * desirable behavior.
1882 .ErrorDetectionBehaviorControl
= true,
1883 .UseFullWays
= true,
1885 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1886 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1887 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1888 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1890 /* Set up the L3 partitioning. */
1891 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1895 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1896 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1897 cfg
->n
[GEN_L3P_ALL
];
1898 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1899 cfg
->n
[GEN_L3P_ALL
];
1900 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1901 cfg
->n
[GEN_L3P_ALL
];
1903 assert(!cfg
->n
[GEN_L3P_ALL
]);
1905 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1906 * the matching space on the remaining banks has to be allocated to a
1907 * client (URB for all validated configurations) set to the
1908 * lower-bandwidth 2-bank address hashing mode.
1910 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1911 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1912 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1914 /* Minimum number of ways that can be allocated to the URB. */
1915 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1916 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1918 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1919 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1920 .ConvertDC_UC
= !has_dc
,
1921 .ConvertIS_UC
= !has_is
,
1922 .ConvertC_UC
= !has_c
,
1923 .ConvertT_UC
= !has_t
);
1925 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1926 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1927 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1929 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1930 .SLMEnable
= has_slm
,
1931 .URBLowBandwidth
= urb_low_bw
,
1932 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1934 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1936 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1937 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1939 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1940 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1941 .ISLowBandwidth
= 0,
1942 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1944 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1945 .TLowBandwidth
= 0);
1947 /* Set up the L3 partitioning. */
1948 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1949 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1950 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1953 if (cmd_buffer
->device
->physical
->cmd_parser_version
>= 4) {
1954 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1955 * them disabled to avoid crashing the system hard.
1957 uint32_t scratch1
, chicken3
;
1958 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1959 .L3AtomicDisable
= !has_dc
);
1960 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1961 .L3AtomicDisableMask
= true,
1962 .L3AtomicDisable
= !has_dc
);
1963 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1964 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1970 cmd_buffer
->state
.current_l3_config
= cfg
;
1974 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1976 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1977 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1979 if (cmd_buffer
->device
->physical
->always_flush_cache
)
1980 bits
|= ANV_PIPE_FLUSH_BITS
| ANV_PIPE_INVALIDATE_BITS
;
1983 * From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
1985 * Write synchronization is a special case of end-of-pipe
1986 * synchronization that requires that the render cache and/or depth
1987 * related caches are flushed to memory, where the data will become
1988 * globally visible. This type of synchronization is required prior to
1989 * SW (CPU) actually reading the result data from memory, or initiating
1990 * an operation that will use as a read surface (such as a texture
1991 * surface) a previous render target and/or depth/stencil buffer
1994 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
1996 * Exercising the write cache flush bits (Render Target Cache Flush
1997 * Enable, Depth Cache Flush Enable, DC Flush) in PIPE_CONTROL only
1998 * ensures the write caches are flushed and doesn't guarantee the data
1999 * is globally visible.
2001 * SW can track the completion of the end-of-pipe-synchronization by
2002 * using "Notify Enable" and "PostSync Operation - Write Immediate
2003 * Data" in the PIPE_CONTROL command.
2005 * In other words, flushes are pipelined while invalidations are handled
2006 * immediately. Therefore, if we're flushing anything then we need to
2007 * schedule an end-of-pipe sync before any invalidations can happen.
2009 if (bits
& ANV_PIPE_FLUSH_BITS
)
2010 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2013 /* HSD 1209978178: docs say that before programming the aux table:
2015 * "Driver must ensure that the engine is IDLE but ensure it doesn't
2016 * add extra flushes in the case it knows that the engine is already
2019 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
))
2020 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2022 /* If we're going to do an invalidate and we have a pending end-of-pipe
2023 * sync that has yet to be resolved, we do the end-of-pipe sync now.
2025 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
2026 (bits
& ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
)) {
2027 bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
2028 bits
&= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2031 if (GEN_GEN
>= 12 &&
2032 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
2033 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
2034 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
2037 * Unified Cache (Tile Cache Disabled):
2039 * When the Color and Depth (Z) streams are enabled to be cached in
2040 * the DC space of L2, Software must use "Render Target Cache Flush
2041 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
2042 * Flush" for getting the color and depth (Z) write data to be
2043 * globally observable. In this mode of operation it is not required
2044 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
2046 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2049 /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
2050 * invalidates the instruction cache
2052 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
))
2053 bits
|= ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2055 if ((GEN_GEN
>= 8 && GEN_GEN
<= 9) &&
2056 (bits
& ANV_PIPE_CS_STALL_BIT
) &&
2057 (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
)) {
2058 /* If we are doing a VF cache invalidate AND a CS stall (it must be
2059 * both) then we can reset our vertex cache tracking.
2061 memset(cmd_buffer
->state
.gfx
.vb_dirty_ranges
, 0,
2062 sizeof(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
2063 memset(&cmd_buffer
->state
.gfx
.ib_dirty_range
, 0,
2064 sizeof(cmd_buffer
->state
.gfx
.ib_dirty_range
));
2067 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2069 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2070 * programmed prior to programming a PIPECONTROL command with "LRI
2071 * Post Sync Operation" in GPGPU mode of operation (i.e when
2072 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2074 * The same text exists a few rows below for Post Sync Op.
2076 * On Gen12 this is GEN:BUG:1607156449.
2078 if (bits
& ANV_PIPE_POST_SYNC_BIT
) {
2079 if ((GEN_GEN
== 9 || (GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0 */)) &&
2080 cmd_buffer
->state
.current_pipeline
== GPGPU
)
2081 bits
|= ANV_PIPE_CS_STALL_BIT
;
2082 bits
&= ~ANV_PIPE_POST_SYNC_BIT
;
2085 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2086 ANV_PIPE_END_OF_PIPE_SYNC_BIT
)) {
2087 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2089 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2091 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2092 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2093 pipe
.RenderTargetCacheFlushEnable
=
2094 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2096 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
2097 * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
2100 pipe
.DepthStallEnable
=
2101 pipe
.DepthCacheFlushEnable
|| (bits
& ANV_PIPE_DEPTH_STALL_BIT
);
2103 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
2106 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
2107 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2109 /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":
2111 * "The most common action to perform upon reaching a
2112 * synchronization point is to write a value out to memory. An
2113 * immediate value (included with the synchronization command) may
2117 * From Broadwell PRM, volume 7, "End-of-Pipe Synchronization":
2119 * "In case the data flushed out by the render engine is to be
2120 * read back in to the render engine in coherent manner, then the
2121 * render engine has to wait for the fence completion before
2122 * accessing the flushed data. This can be achieved by following
2123 * means on various products: PIPE_CONTROL command with CS Stall
2124 * and the required write caches flushed with Post-Sync-Operation
2125 * as Write Immediate Data.
2128 * - Workload-1 (3D/GPGPU/MEDIA)
2129 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2130 * Immediate Data, Required Write Cache Flush bits set)
2131 * - Workload-2 (Can use the data produce or output by
2134 if (bits
& ANV_PIPE_END_OF_PIPE_SYNC_BIT
) {
2135 pipe
.CommandStreamerStallEnable
= true;
2136 pipe
.PostSyncOperation
= WriteImmediateData
;
2137 pipe
.Address
= cmd_buffer
->device
->workaround_address
;
2141 * According to the Broadwell documentation, any PIPE_CONTROL with the
2142 * "Command Streamer Stall" bit set must also have another bit set,
2143 * with five different options:
2145 * - Render Target Cache Flush
2146 * - Depth Cache Flush
2147 * - Stall at Pixel Scoreboard
2148 * - Post-Sync Operation
2152 * I chose "Stall at Pixel Scoreboard" since that's what we use in
2153 * mesa and it seems to work fine. The choice is fairly arbitrary.
2155 if (pipe
.CommandStreamerStallEnable
&&
2156 !pipe
.RenderTargetCacheFlushEnable
&&
2157 !pipe
.DepthCacheFlushEnable
&&
2158 !pipe
.StallAtPixelScoreboard
&&
2159 !pipe
.PostSyncOperation
&&
2160 !pipe
.DepthStallEnable
&&
2161 !pipe
.DCFlushEnable
)
2162 pipe
.StallAtPixelScoreboard
= true;
2165 /* If a render target flush was emitted, then we can toggle off the bit
2166 * saying that render target writes are ongoing.
2168 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
2169 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
2171 if (GEN_IS_HASWELL
) {
2172 /* Haswell needs addition work-arounds:
2174 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
2177 * PIPE_CONTROL command with the CS Stall and the required write
2178 * caches flushed with Post-SyncOperation as Write Immediate Data
2179 * followed by eight dummy MI_STORE_DATA_IMM (write to scratch
2184 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2185 * Immediate Data, Required Write Cache Flush bits set)
2186 * - MI_STORE_DATA_IMM (8 times) (Dummy data, Scratch Address)
2187 * - Workload-2 (Can use the data produce or output by
2190 * Unfortunately, both the PRMs and the internal docs are a bit
2191 * out-of-date in this regard. What the windows driver does (and
2192 * this appears to actually work) is to emit a register read from the
2193 * memory address written by the pipe control above.
2195 * What register we load into doesn't matter. We choose an indirect
2196 * rendering register because we know it always exists and it's one
2197 * of the first registers the command parser allows us to write. If
2198 * you don't have command parser support in your kernel (pre-4.2),
2199 * this will get turned into MI_NOOP and you won't get the
2200 * workaround. Unfortunately, there's just not much we can do in
2201 * that case. This register is perfectly safe to write since we
2202 * always re-load all of the indirect draw registers right before
2203 * 3DPRIMITIVE when needed anyway.
2205 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2206 lrm
.RegisterAddress
= 0x243C; /* GEN7_3DPRIM_START_INSTANCE */
2207 lrm
.MemoryAddress
= cmd_buffer
->device
->workaround_address
;
2211 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2212 ANV_PIPE_END_OF_PIPE_SYNC_BIT
);
2215 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
2216 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2218 * "If the VF Cache Invalidation Enable is set to a 1 in a
2219 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
2220 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
2221 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
2224 * This appears to hang Broadwell, so we restrict it to just gen9.
2226 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
2227 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
2229 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2230 pipe
.StateCacheInvalidationEnable
=
2231 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
2232 pipe
.ConstantCacheInvalidationEnable
=
2233 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2234 pipe
.VFCacheInvalidationEnable
=
2235 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2236 pipe
.TextureCacheInvalidationEnable
=
2237 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2238 pipe
.InstructionCacheInvalidateEnable
=
2239 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
2241 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2243 * "When VF Cache Invalidate is set “Post Sync Operation” must be
2244 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
2245 * “Write Timestamp”.
2247 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
2248 pipe
.PostSyncOperation
= WriteImmediateData
;
2249 pipe
.Address
= cmd_buffer
->device
->workaround_address
;
2254 if ((bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
) &&
2255 cmd_buffer
->device
->info
.has_aux_map
) {
2256 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2257 lri
.RegisterOffset
= GENX(GFX_CCS_AUX_INV_num
);
2263 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
2266 cmd_buffer
->state
.pending_pipe_bits
= bits
;
2269 void genX(CmdPipelineBarrier
)(
2270 VkCommandBuffer commandBuffer
,
2271 VkPipelineStageFlags srcStageMask
,
2272 VkPipelineStageFlags destStageMask
,
2274 uint32_t memoryBarrierCount
,
2275 const VkMemoryBarrier
* pMemoryBarriers
,
2276 uint32_t bufferMemoryBarrierCount
,
2277 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
2278 uint32_t imageMemoryBarrierCount
,
2279 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
2281 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2283 /* XXX: Right now, we're really dumb and just flush whatever categories
2284 * the app asks for. One of these days we may make this a bit better
2285 * but right now that's all the hardware allows for in most areas.
2287 VkAccessFlags src_flags
= 0;
2288 VkAccessFlags dst_flags
= 0;
2290 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
2291 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
2292 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
2295 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
2296 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
2297 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
2300 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
2301 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
2302 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
2303 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
2304 const VkImageSubresourceRange
*range
=
2305 &pImageMemoryBarriers
[i
].subresourceRange
;
2307 uint32_t base_layer
, layer_count
;
2308 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2310 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
2312 base_layer
= range
->baseArrayLayer
;
2313 layer_count
= anv_get_layerCount(image
, range
);
2316 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2317 transition_depth_buffer(cmd_buffer
, image
,
2318 base_layer
, layer_count
,
2319 pImageMemoryBarriers
[i
].oldLayout
,
2320 pImageMemoryBarriers
[i
].newLayout
);
2323 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
2324 transition_stencil_buffer(cmd_buffer
, image
,
2325 range
->baseMipLevel
,
2326 anv_get_levelCount(image
, range
),
2327 base_layer
, layer_count
,
2328 pImageMemoryBarriers
[i
].oldLayout
,
2329 pImageMemoryBarriers
[i
].newLayout
);
2332 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2333 VkImageAspectFlags color_aspects
=
2334 anv_image_expand_aspects(image
, range
->aspectMask
);
2335 uint32_t aspect_bit
;
2336 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
2337 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
2338 range
->baseMipLevel
,
2339 anv_get_levelCount(image
, range
),
2340 base_layer
, layer_count
,
2341 pImageMemoryBarriers
[i
].oldLayout
,
2342 pImageMemoryBarriers
[i
].newLayout
);
2347 cmd_buffer
->state
.pending_pipe_bits
|=
2348 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2349 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2353 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2355 VkShaderStageFlags stages
=
2356 cmd_buffer
->state
.gfx
.pipeline
->active_stages
;
2358 /* In order to avoid thrash, we assume that vertex and fragment stages
2359 * always exist. In the rare case where one is missing *and* the other
2360 * uses push concstants, this may be suboptimal. However, avoiding stalls
2361 * seems more important.
2363 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2365 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2369 const unsigned push_constant_kb
= 32;
2370 #elif GEN_IS_HASWELL
2371 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2373 const unsigned push_constant_kb
= 16;
2376 const unsigned num_stages
=
2377 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2378 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2380 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2381 * units of 2KB. Incidentally, these are the same platforms that have
2382 * 32KB worth of push constant space.
2384 if (push_constant_kb
== 32)
2385 size_per_stage
&= ~1u;
2387 uint32_t kb_used
= 0;
2388 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2389 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2390 anv_batch_emit(&cmd_buffer
->batch
,
2391 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2392 alloc
._3DCommandSubOpcode
= 18 + i
;
2393 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2394 alloc
.ConstantBufferSize
= push_size
;
2396 kb_used
+= push_size
;
2399 anv_batch_emit(&cmd_buffer
->batch
,
2400 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2401 alloc
.ConstantBufferOffset
= kb_used
;
2402 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2405 cmd_buffer
->state
.push_constant_stages
= stages
;
2407 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2409 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2410 * the next 3DPRIMITIVE command after programming the
2411 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2413 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2414 * pipeline setup, we need to dirty push constants.
2416 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2419 static struct anv_address
2420 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2421 struct anv_descriptor_set
*set
)
2424 /* This is a normal descriptor set */
2425 return (struct anv_address
) {
2426 .bo
= set
->pool
->bo
,
2427 .offset
= set
->desc_mem
.offset
,
2430 /* This is a push descriptor set. We have to flag it as used on the GPU
2431 * so that the next time we push descriptors, we grab a new memory.
2433 struct anv_push_descriptor_set
*push_set
=
2434 (struct anv_push_descriptor_set
*)set
;
2435 push_set
->set_used_on_gpu
= true;
2437 return (struct anv_address
) {
2438 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2439 .offset
= set
->desc_mem
.offset
,
2445 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2446 struct anv_cmd_pipeline_state
*pipe_state
,
2447 struct anv_shader_bin
*shader
,
2448 struct anv_state
*bt_state
)
2450 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2451 uint32_t state_offset
;
2453 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2454 if (map
->surface_count
== 0) {
2455 *bt_state
= (struct anv_state
) { 0, };
2459 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2462 uint32_t *bt_map
= bt_state
->map
;
2464 if (bt_state
->map
== NULL
)
2465 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2467 /* We only need to emit relocs if we're not using softpin. If we are using
2468 * softpin then we always keep all user-allocated memory objects resident.
2470 const bool need_client_mem_relocs
=
2471 !cmd_buffer
->device
->physical
->use_softpin
;
2473 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2474 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2476 struct anv_state surface_state
;
2478 switch (binding
->set
) {
2479 case ANV_DESCRIPTOR_SET_NULL
:
2483 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
:
2484 /* Color attachment binding */
2485 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2486 if (binding
->index
< subpass
->color_count
) {
2487 const unsigned att
=
2488 subpass
->color_attachments
[binding
->index
].attachment
;
2490 /* From the Vulkan 1.0.46 spec:
2492 * "If any color or depth/stencil attachments are
2493 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2496 if (att
== VK_ATTACHMENT_UNUSED
) {
2497 surface_state
= cmd_buffer
->state
.null_surface_state
;
2499 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2502 surface_state
= cmd_buffer
->state
.null_surface_state
;
2505 assert(surface_state
.map
);
2506 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2509 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
: {
2510 struct anv_state surface_state
=
2511 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2513 struct anv_address constant_data
= {
2514 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2515 .offset
= shader
->constant_data
.offset
,
2517 unsigned constant_data_size
= shader
->constant_data_size
;
2519 const enum isl_format format
=
2520 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2521 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2522 surface_state
, format
,
2523 constant_data
, constant_data_size
, 1);
2525 assert(surface_state
.map
);
2526 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2527 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2531 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
: {
2532 /* This is always the first binding for compute shaders */
2533 assert(shader
->stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2535 struct anv_state surface_state
=
2536 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2538 const enum isl_format format
=
2539 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2540 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2542 cmd_buffer
->state
.compute
.num_workgroups
,
2545 assert(surface_state
.map
);
2546 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2547 if (need_client_mem_relocs
) {
2548 add_surface_reloc(cmd_buffer
, surface_state
,
2549 cmd_buffer
->state
.compute
.num_workgroups
);
2554 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2555 /* This is a descriptor set buffer so the set index is actually
2556 * given by binding->binding. (Yes, that's confusing.)
2558 struct anv_descriptor_set
*set
=
2559 pipe_state
->descriptors
[binding
->index
];
2560 assert(set
->desc_mem
.alloc_size
);
2561 assert(set
->desc_surface_state
.alloc_size
);
2562 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2563 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2564 anv_descriptor_set_address(cmd_buffer
, set
));
2569 assert(binding
->set
< MAX_SETS
);
2570 const struct anv_descriptor
*desc
=
2571 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2573 switch (desc
->type
) {
2574 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2575 /* Nothing for us to do here */
2578 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2579 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2580 if (desc
->image_view
) {
2581 struct anv_surface_state sstate
=
2582 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2583 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2584 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2585 surface_state
= sstate
.state
;
2586 assert(surface_state
.alloc_size
);
2587 if (need_client_mem_relocs
)
2588 add_surface_state_relocs(cmd_buffer
, sstate
);
2590 surface_state
= cmd_buffer
->device
->null_surface_state
;
2594 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2595 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2596 assert(desc
->image_view
!= NULL
);
2597 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2598 /* For depth and stencil input attachments, we treat it like any
2599 * old texture that a user may have bound.
2601 assert(desc
->image_view
->n_planes
== 1);
2602 struct anv_surface_state sstate
=
2603 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2604 desc
->image_view
->planes
[0].general_sampler_surface_state
:
2605 desc
->image_view
->planes
[0].optimal_sampler_surface_state
;
2606 surface_state
= sstate
.state
;
2607 assert(surface_state
.alloc_size
);
2608 if (need_client_mem_relocs
)
2609 add_surface_state_relocs(cmd_buffer
, sstate
);
2611 /* For color input attachments, we create the surface state at
2612 * vkBeginRenderPass time so that we can include aux and clear
2613 * color information.
2615 assert(binding
->input_attachment_index
< subpass
->input_count
);
2616 const unsigned subpass_att
= binding
->input_attachment_index
;
2617 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2618 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2622 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2623 if (desc
->image_view
) {
2624 struct anv_surface_state sstate
= (binding
->write_only
)
2625 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2626 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2627 surface_state
= sstate
.state
;
2628 assert(surface_state
.alloc_size
);
2629 if (need_client_mem_relocs
)
2630 add_surface_state_relocs(cmd_buffer
, sstate
);
2632 surface_state
= cmd_buffer
->device
->null_surface_state
;
2637 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2638 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2639 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2640 if (desc
->buffer_view
) {
2641 surface_state
= desc
->buffer_view
->surface_state
;
2642 assert(surface_state
.alloc_size
);
2643 if (need_client_mem_relocs
) {
2644 add_surface_reloc(cmd_buffer
, surface_state
,
2645 desc
->buffer_view
->address
);
2648 surface_state
= cmd_buffer
->device
->null_surface_state
;
2652 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2653 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2655 /* Compute the offset within the buffer */
2656 struct anv_push_constants
*push
=
2657 &cmd_buffer
->state
.push_constants
[shader
->stage
];
2659 uint32_t dynamic_offset
=
2660 push
->dynamic_offsets
[binding
->dynamic_offset_index
];
2661 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2662 /* Clamp to the buffer size */
2663 offset
= MIN2(offset
, desc
->buffer
->size
);
2664 /* Clamp the range to the buffer size */
2665 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2667 /* Align the range for consistency */
2668 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
)
2669 range
= align_u32(range
, ANV_UBO_ALIGNMENT
);
2671 struct anv_address address
=
2672 anv_address_add(desc
->buffer
->address
, offset
);
2675 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2676 enum isl_format format
=
2677 anv_isl_format_for_descriptor_type(desc
->type
);
2679 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2680 format
, address
, range
, 1);
2681 if (need_client_mem_relocs
)
2682 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2684 surface_state
= cmd_buffer
->device
->null_surface_state
;
2689 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2690 if (desc
->buffer_view
) {
2691 surface_state
= (binding
->write_only
)
2692 ? desc
->buffer_view
->writeonly_storage_surface_state
2693 : desc
->buffer_view
->storage_surface_state
;
2694 assert(surface_state
.alloc_size
);
2695 if (need_client_mem_relocs
) {
2696 add_surface_reloc(cmd_buffer
, surface_state
,
2697 desc
->buffer_view
->address
);
2700 surface_state
= cmd_buffer
->device
->null_surface_state
;
2705 assert(!"Invalid descriptor type");
2708 assert(surface_state
.map
);
2709 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2719 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2720 struct anv_cmd_pipeline_state
*pipe_state
,
2721 struct anv_shader_bin
*shader
,
2722 struct anv_state
*state
)
2724 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2725 if (map
->sampler_count
== 0) {
2726 *state
= (struct anv_state
) { 0, };
2730 uint32_t size
= map
->sampler_count
* 16;
2731 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2733 if (state
->map
== NULL
)
2734 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2736 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2737 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2738 const struct anv_descriptor
*desc
=
2739 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2741 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2742 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2745 struct anv_sampler
*sampler
= desc
->sampler
;
2747 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2748 * happens to be zero.
2750 if (sampler
== NULL
)
2753 memcpy(state
->map
+ (s
* 16),
2754 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2761 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
,
2762 struct anv_cmd_pipeline_state
*pipe_state
,
2763 struct anv_shader_bin
**shaders
,
2764 uint32_t num_shaders
)
2766 const VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
;
2767 VkShaderStageFlags flushed
= 0;
2769 VkResult result
= VK_SUCCESS
;
2770 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2774 gl_shader_stage stage
= shaders
[i
]->stage
;
2775 VkShaderStageFlags vk_stage
= mesa_to_vk_shader_stage(stage
);
2776 if ((vk_stage
& dirty
) == 0)
2779 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2780 &cmd_buffer
->state
.samplers
[stage
]);
2781 if (result
!= VK_SUCCESS
)
2783 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2784 &cmd_buffer
->state
.binding_tables
[stage
]);
2785 if (result
!= VK_SUCCESS
)
2788 flushed
|= vk_stage
;
2791 if (result
!= VK_SUCCESS
) {
2792 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2794 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2795 if (result
!= VK_SUCCESS
)
2798 /* Re-emit state base addresses so we get the new surface state base
2799 * address before we start emitting binding tables etc.
2801 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2803 /* Re-emit all active binding tables */
2806 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2810 gl_shader_stage stage
= shaders
[i
]->stage
;
2812 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2813 &cmd_buffer
->state
.samplers
[stage
]);
2814 if (result
!= VK_SUCCESS
) {
2815 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2818 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2819 &cmd_buffer
->state
.binding_tables
[stage
]);
2820 if (result
!= VK_SUCCESS
) {
2821 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2825 flushed
|= mesa_to_vk_shader_stage(stage
);
2829 cmd_buffer
->state
.descriptors_dirty
&= ~flushed
;
2835 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2838 static const uint32_t sampler_state_opcodes
[] = {
2839 [MESA_SHADER_VERTEX
] = 43,
2840 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2841 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2842 [MESA_SHADER_GEOMETRY
] = 46,
2843 [MESA_SHADER_FRAGMENT
] = 47,
2844 [MESA_SHADER_COMPUTE
] = 0,
2847 static const uint32_t binding_table_opcodes
[] = {
2848 [MESA_SHADER_VERTEX
] = 38,
2849 [MESA_SHADER_TESS_CTRL
] = 39,
2850 [MESA_SHADER_TESS_EVAL
] = 40,
2851 [MESA_SHADER_GEOMETRY
] = 41,
2852 [MESA_SHADER_FRAGMENT
] = 42,
2853 [MESA_SHADER_COMPUTE
] = 0,
2856 anv_foreach_stage(s
, stages
) {
2857 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2858 assert(binding_table_opcodes
[s
] > 0);
2860 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2861 anv_batch_emit(&cmd_buffer
->batch
,
2862 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2863 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2864 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2868 /* Always emit binding table pointers if we're asked to, since on SKL
2869 * this is what flushes push constants. */
2870 anv_batch_emit(&cmd_buffer
->batch
,
2871 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2872 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2873 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2878 static struct anv_address
2879 get_push_range_address(struct anv_cmd_buffer
*cmd_buffer
,
2880 gl_shader_stage stage
,
2881 const struct anv_push_range
*range
)
2883 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2884 switch (range
->set
) {
2885 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2886 /* This is a descriptor set buffer so the set index is
2887 * actually given by binding->binding. (Yes, that's
2890 struct anv_descriptor_set
*set
=
2891 gfx_state
->base
.descriptors
[range
->index
];
2892 return anv_descriptor_set_address(cmd_buffer
, set
);
2895 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
: {
2896 struct anv_state state
=
2897 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2898 return (struct anv_address
) {
2899 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2900 .offset
= state
.offset
,
2905 assert(range
->set
< MAX_SETS
);
2906 struct anv_descriptor_set
*set
=
2907 gfx_state
->base
.descriptors
[range
->set
];
2908 const struct anv_descriptor
*desc
=
2909 &set
->descriptors
[range
->index
];
2911 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2912 if (desc
->buffer_view
)
2913 return desc
->buffer_view
->address
;
2915 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2917 struct anv_push_constants
*push
=
2918 &cmd_buffer
->state
.push_constants
[stage
];
2919 uint32_t dynamic_offset
=
2920 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2921 return anv_address_add(desc
->buffer
->address
,
2922 desc
->offset
+ dynamic_offset
);
2926 /* For NULL UBOs, we just return an address in the workaround BO. We do
2927 * writes to it for workarounds but always at the bottom. The higher
2928 * bytes should be all zeros.
2930 assert(range
->length
* 32 <= 2048);
2931 return (struct anv_address
) {
2932 .bo
= cmd_buffer
->device
->workaround_bo
,
2940 /** Returns the size in bytes of the bound buffer
2942 * The range is relative to the start of the buffer, not the start of the
2943 * range. The returned range may be smaller than
2945 * (range->start + range->length) * 32;
2948 get_push_range_bound_size(struct anv_cmd_buffer
*cmd_buffer
,
2949 gl_shader_stage stage
,
2950 const struct anv_push_range
*range
)
2952 assert(stage
!= MESA_SHADER_COMPUTE
);
2953 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2954 switch (range
->set
) {
2955 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2956 struct anv_descriptor_set
*set
=
2957 gfx_state
->base
.descriptors
[range
->index
];
2958 assert(range
->start
* 32 < set
->desc_mem
.alloc_size
);
2959 assert((range
->start
+ range
->length
) * 32 <= set
->desc_mem
.alloc_size
);
2960 return set
->desc_mem
.alloc_size
;
2963 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
:
2964 return (range
->start
+ range
->length
) * 32;
2967 assert(range
->set
< MAX_SETS
);
2968 struct anv_descriptor_set
*set
=
2969 gfx_state
->base
.descriptors
[range
->set
];
2970 const struct anv_descriptor
*desc
=
2971 &set
->descriptors
[range
->index
];
2973 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2974 if (!desc
->buffer_view
)
2977 if (range
->start
* 32 > desc
->buffer_view
->range
)
2980 return desc
->buffer_view
->range
;
2985 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2986 /* Compute the offset within the buffer */
2987 struct anv_push_constants
*push
=
2988 &cmd_buffer
->state
.push_constants
[stage
];
2989 uint32_t dynamic_offset
=
2990 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2991 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2992 /* Clamp to the buffer size */
2993 offset
= MIN2(offset
, desc
->buffer
->size
);
2994 /* Clamp the range to the buffer size */
2995 uint32_t bound_range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2997 /* Align the range for consistency */
2998 bound_range
= align_u32(bound_range
, ANV_UBO_ALIGNMENT
);
3007 cmd_buffer_emit_push_constant(struct anv_cmd_buffer
*cmd_buffer
,
3008 gl_shader_stage stage
,
3009 struct anv_address
*buffers
,
3010 unsigned buffer_count
)
3012 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3013 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3015 static const uint32_t push_constant_opcodes
[] = {
3016 [MESA_SHADER_VERTEX
] = 21,
3017 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3018 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3019 [MESA_SHADER_GEOMETRY
] = 22,
3020 [MESA_SHADER_FRAGMENT
] = 23,
3021 [MESA_SHADER_COMPUTE
] = 0,
3024 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3025 assert(push_constant_opcodes
[stage
] > 0);
3027 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
3028 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3030 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3031 const struct anv_pipeline_bind_map
*bind_map
=
3032 &pipeline
->shaders
[stage
]->bind_map
;
3035 /* This field exists since Gen8. However, the Broadwell PRM says:
3037 * "Constant Buffer Object Control State must be always programmed
3040 * This restriction does not exist on any newer platforms.
3042 * We only have one MOCS field for the whole packet, not one per
3043 * buffer. We could go out of our way here to walk over all of the
3044 * buffers and see if any of them are used externally and use the
3045 * external MOCS. However, the notion that someone would use the
3046 * same bit of memory for both scanout and a UBO is nuts. Let's not
3047 * bother and assume it's all internal.
3049 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3052 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3053 /* The Skylake PRM contains the following restriction:
3055 * "The driver must ensure The following case does not occur
3056 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3057 * buffer 3 read length equal to zero committed followed by a
3058 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3061 * To avoid this, we program the buffers in the highest slots.
3062 * This way, slot 0 is only used if slot 3 is also used.
3064 assert(buffer_count
<= 4);
3065 const unsigned shift
= 4 - buffer_count
;
3066 for (unsigned i
= 0; i
< buffer_count
; i
++) {
3067 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3069 /* At this point we only have non-empty ranges */
3070 assert(range
->length
> 0);
3072 /* For Ivy Bridge, make sure we only set the first range (actual
3075 assert((GEN_GEN
>= 8 || GEN_IS_HASWELL
) || i
== 0);
3077 c
.ConstantBody
.ReadLength
[i
+ shift
] = range
->length
;
3078 c
.ConstantBody
.Buffer
[i
+ shift
] =
3079 anv_address_add(buffers
[i
], range
->start
* 32);
3082 /* For Ivy Bridge, push constants are relative to dynamic state
3083 * base address and we only ever push actual push constants.
3085 if (bind_map
->push_ranges
[0].length
> 0) {
3086 assert(buffer_count
== 1);
3087 assert(bind_map
->push_ranges
[0].set
==
3088 ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
);
3089 assert(buffers
[0].bo
==
3090 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
);
3091 c
.ConstantBody
.ReadLength
[0] = bind_map
->push_ranges
[0].length
;
3092 c
.ConstantBody
.Buffer
[0].bo
= NULL
;
3093 c
.ConstantBody
.Buffer
[0].offset
= buffers
[0].offset
;
3095 assert(bind_map
->push_ranges
[1].length
== 0);
3096 assert(bind_map
->push_ranges
[2].length
== 0);
3097 assert(bind_map
->push_ranges
[3].length
== 0);
3105 cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer
*cmd_buffer
,
3106 uint32_t shader_mask
,
3107 struct anv_address
*buffers
,
3108 uint32_t buffer_count
)
3110 if (buffer_count
== 0) {
3111 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_ALL
), c
) {
3112 c
.ShaderUpdateEnable
= shader_mask
;
3113 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3118 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3119 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3121 static const uint32_t push_constant_opcodes
[] = {
3122 [MESA_SHADER_VERTEX
] = 21,
3123 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3124 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3125 [MESA_SHADER_GEOMETRY
] = 22,
3126 [MESA_SHADER_FRAGMENT
] = 23,
3127 [MESA_SHADER_COMPUTE
] = 0,
3130 gl_shader_stage stage
= vk_to_mesa_shader_stage(shader_mask
);
3131 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3132 assert(push_constant_opcodes
[stage
] > 0);
3134 const struct anv_pipeline_bind_map
*bind_map
=
3135 &pipeline
->shaders
[stage
]->bind_map
;
3138 const uint32_t buffer_mask
= (1 << buffer_count
) - 1;
3139 const uint32_t num_dwords
= 2 + 2 * buffer_count
;
3141 dw
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3142 GENX(3DSTATE_CONSTANT_ALL
),
3143 .ShaderUpdateEnable
= shader_mask
,
3144 .PointerBufferMask
= buffer_mask
,
3145 .MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
);
3147 for (int i
= 0; i
< buffer_count
; i
++) {
3148 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3149 GENX(3DSTATE_CONSTANT_ALL_DATA_pack
)(
3150 &cmd_buffer
->batch
, dw
+ 2 + i
* 2,
3151 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA
)) {
3152 .PointerToConstantBuffer
=
3153 anv_address_add(buffers
[i
], range
->start
* 32),
3154 .ConstantBufferReadLength
= range
->length
,
3161 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
3162 VkShaderStageFlags dirty_stages
)
3164 VkShaderStageFlags flushed
= 0;
3165 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3166 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3169 uint32_t nobuffer_stages
= 0;
3172 anv_foreach_stage(stage
, dirty_stages
) {
3173 unsigned buffer_count
= 0;
3174 flushed
|= mesa_to_vk_shader_stage(stage
);
3175 UNUSED
uint32_t max_push_range
= 0;
3177 struct anv_address buffers
[4] = {};
3178 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3179 const struct anv_pipeline_bind_map
*bind_map
=
3180 &pipeline
->shaders
[stage
]->bind_map
;
3181 struct anv_push_constants
*push
=
3182 &cmd_buffer
->state
.push_constants
[stage
];
3184 if (cmd_buffer
->device
->robust_buffer_access
) {
3185 push
->push_reg_mask
= 0;
3186 /* Start of the current range in the shader, relative to the start
3187 * of push constants in the shader.
3189 unsigned range_start_reg
= 0;
3190 for (unsigned i
= 0; i
< 4; i
++) {
3191 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3192 if (range
->length
== 0)
3195 unsigned bound_size
=
3196 get_push_range_bound_size(cmd_buffer
, stage
, range
);
3197 if (bound_size
>= range
->start
* 32) {
3198 unsigned bound_regs
=
3199 MIN2(DIV_ROUND_UP(bound_size
, 32) - range
->start
,
3201 assert(range_start_reg
+ bound_regs
<= 64);
3202 push
->push_reg_mask
|= BITFIELD64_RANGE(range_start_reg
,
3206 cmd_buffer
->state
.push_constants_dirty
|=
3207 mesa_to_vk_shader_stage(stage
);
3209 range_start_reg
+= range
->length
;
3213 /* We have to gather buffer addresses as a second step because the
3214 * loop above puts data into the push constant area and the call to
3215 * get_push_range_address is what locks our push constants and copies
3216 * them into the actual GPU buffer. If we did the two loops at the
3217 * same time, we'd risk only having some of the sizes in the push
3218 * constant buffer when we did the copy.
3220 for (unsigned i
= 0; i
< 4; i
++) {
3221 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3222 if (range
->length
== 0)
3225 buffers
[i
] = get_push_range_address(cmd_buffer
, stage
, range
);
3226 max_push_range
= MAX2(max_push_range
, range
->length
);
3230 /* We have at most 4 buffers but they should be tightly packed */
3231 for (unsigned i
= buffer_count
; i
< 4; i
++)
3232 assert(bind_map
->push_ranges
[i
].length
== 0);
3236 /* If this stage doesn't have any push constants, emit it later in a
3237 * single CONSTANT_ALL packet.
3239 if (buffer_count
== 0) {
3240 nobuffer_stages
|= 1 << stage
;
3244 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
3245 * contains only 5 bits, so we can only use it for buffers smaller than
3248 if (max_push_range
< 32) {
3249 cmd_buffer_emit_push_constant_all(cmd_buffer
, 1 << stage
,
3250 buffers
, buffer_count
);
3255 cmd_buffer_emit_push_constant(cmd_buffer
, stage
, buffers
, buffer_count
);
3259 if (nobuffer_stages
)
3260 cmd_buffer_emit_push_constant_all(cmd_buffer
, nobuffer_stages
, NULL
, 0);
3263 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
3267 genX(cmd_buffer_emit_clip
)(struct anv_cmd_buffer
*cmd_buffer
)
3269 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3271 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_PIPELINE
|
3272 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)) {
3273 uint32_t dwords
[GENX(3DSTATE_CLIP_length
)];
3275 cmd_buffer
->state
.gfx
.dynamic
.viewport
.count
> 0 ?
3276 cmd_buffer
->state
.gfx
.dynamic
.viewport
.count
- 1 : 0;
3278 struct GENX(3DSTATE_CLIP
) clip
= {
3279 GENX(3DSTATE_CLIP_header
),
3280 .MaximumVPIndex
= count
,
3282 GENX(3DSTATE_CLIP_pack
)(NULL
, dwords
, &clip
);
3283 anv_batch_emit_merge(&cmd_buffer
->batch
, dwords
,
3284 pipeline
->gen7
.clip
);
3289 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3291 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3294 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
3296 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
3298 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
3300 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3302 /* Apply any pending pipeline flushes we may have. We want to apply them
3303 * now because, if any of those flushes are for things like push constants,
3304 * the GPU will read the state at weird times.
3306 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3308 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
3309 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
3310 vb_emit
|= pipeline
->vb_used
;
3313 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
3314 const uint32_t num_dwords
= 1 + num_buffers
* 4;
3316 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3317 GENX(3DSTATE_VERTEX_BUFFERS
));
3319 for_each_bit(vb
, vb_emit
) {
3320 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
3321 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
3323 /* If dynamic, use stride/size from vertex binding, otherwise use
3324 * stride/size that was setup in the pipeline object.
3326 bool dynamic_stride
= cmd_buffer
->state
.gfx
.dynamic
.dyn_vbo_stride
;
3327 bool dynamic_size
= cmd_buffer
->state
.gfx
.dynamic
.dyn_vbo_size
;
3329 uint32_t stride
= dynamic_stride
?
3330 cmd_buffer
->state
.vertex_bindings
[vb
].stride
: pipeline
->vb
[vb
].stride
;
3331 uint32_t size
= dynamic_size
?
3332 cmd_buffer
->state
.vertex_bindings
[vb
].size
: buffer
->size
;
3334 struct GENX(VERTEX_BUFFER_STATE
) state
;
3336 state
= (struct GENX(VERTEX_BUFFER_STATE
)) {
3337 .VertexBufferIndex
= vb
,
3339 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
3341 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
3342 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
3344 .AddressModifyEnable
= true,
3345 .BufferPitch
= stride
,
3346 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
3347 .NullVertexBuffer
= offset
>= buffer
->size
,
3350 .BufferSize
= size
- offset
3352 .EndAddress
= anv_address_add(buffer
->address
, size
- 1),
3356 state
= (struct GENX(VERTEX_BUFFER_STATE
)) {
3357 .VertexBufferIndex
= vb
,
3358 .NullVertexBuffer
= true,
3362 #if GEN_GEN >= 8 && GEN_GEN <= 9
3363 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
, vb
,
3364 state
.BufferStartingAddress
,
3368 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
3373 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
3376 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
3377 /* We don't need any per-buffer dirty tracking because you're not
3378 * allowed to bind different XFB buffers while XFB is enabled.
3380 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3381 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
3382 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3384 sob
.SOBufferIndex
= idx
;
3386 sob
._3DCommandOpcode
= 0;
3387 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
3390 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
3391 sob
.SOBufferEnable
= true;
3392 sob
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
,
3393 sob
.StreamOffsetWriteEnable
= false;
3394 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
3396 /* Size is in DWords - 1 */
3397 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
3402 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
3404 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3408 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
3409 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
3411 /* If the pipeline changed, we may need to re-allocate push constant
3414 cmd_buffer_alloc_push_constants(cmd_buffer
);
3417 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
3418 cmd_buffer
->state
.gfx
.primitive_topology
= pipeline
->topology
;
3421 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
3422 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
3423 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
3425 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
3426 * stall needs to be sent just prior to any 3DSTATE_VS,
3427 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
3428 * 3DSTATE_BINDING_TABLE_POINTER_VS,
3429 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
3430 * PIPE_CONTROL needs to be sent before any combination of VS
3431 * associated 3DSTATE."
3433 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3434 pc
.DepthStallEnable
= true;
3435 pc
.PostSyncOperation
= WriteImmediateData
;
3436 pc
.Address
= cmd_buffer
->device
->workaround_address
;
3441 /* Render targets live in the same binding table as fragment descriptors */
3442 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
3443 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
3445 /* We emit the binding tables and sampler tables first, then emit push
3446 * constants and then finally emit binding table and sampler table
3447 * pointers. It has to happen in this order, since emitting the binding
3448 * tables may change the push constants (in case of storage images). After
3449 * emitting push constants, on SKL+ we have to emit the corresponding
3450 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
3453 if (cmd_buffer
->state
.descriptors_dirty
) {
3454 dirty
= flush_descriptor_sets(cmd_buffer
,
3455 &cmd_buffer
->state
.gfx
.base
,
3457 ARRAY_SIZE(pipeline
->shaders
));
3460 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
3461 /* Because we're pushing UBOs, we have to push whenever either
3462 * descriptors or push constants is dirty.
3464 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
3465 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
3466 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
3470 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
3472 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
) {
3473 genX(cmd_buffer_emit_clip
)(cmd_buffer
);
3474 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
3477 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
3478 ANV_CMD_DIRTY_PIPELINE
)) {
3479 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
3480 pipeline
->depth_clamp_enable
);
3483 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
3484 ANV_CMD_DIRTY_RENDER_TARGETS
))
3485 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
3487 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
3491 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
3492 struct anv_address addr
,
3493 uint32_t size
, uint32_t index
)
3495 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
3496 GENX(3DSTATE_VERTEX_BUFFERS
));
3498 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
3499 &(struct GENX(VERTEX_BUFFER_STATE
)) {
3500 .VertexBufferIndex
= index
,
3501 .AddressModifyEnable
= true,
3503 .MOCS
= addr
.bo
? anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
) : 0,
3504 .NullVertexBuffer
= size
== 0,
3506 .BufferStartingAddress
= addr
,
3509 .BufferStartingAddress
= addr
,
3510 .EndAddress
= anv_address_add(addr
, size
),
3514 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
,
3519 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
3520 struct anv_address addr
)
3522 emit_vertex_bo(cmd_buffer
, addr
, addr
.bo
? 8 : 0, ANV_SVGS_VB_INDEX
);
3526 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
3527 uint32_t base_vertex
, uint32_t base_instance
)
3529 if (base_vertex
== 0 && base_instance
== 0) {
3530 emit_base_vertex_instance_bo(cmd_buffer
, ANV_NULL_ADDRESS
);
3532 struct anv_state id_state
=
3533 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
3535 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
3536 ((uint32_t *)id_state
.map
)[1] = base_instance
;
3538 struct anv_address addr
= {
3539 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3540 .offset
= id_state
.offset
,
3543 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
3548 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
3550 struct anv_state state
=
3551 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
3553 ((uint32_t *)state
.map
)[0] = draw_index
;
3555 struct anv_address addr
= {
3556 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3557 .offset
= state
.offset
,
3560 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
3564 update_dirty_vbs_for_gen8_vb_flush(struct anv_cmd_buffer
*cmd_buffer
,
3565 uint32_t access_type
)
3567 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3568 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3570 uint64_t vb_used
= pipeline
->vb_used
;
3571 if (vs_prog_data
->uses_firstvertex
||
3572 vs_prog_data
->uses_baseinstance
)
3573 vb_used
|= 1ull << ANV_SVGS_VB_INDEX
;
3574 if (vs_prog_data
->uses_drawid
)
3575 vb_used
|= 1ull << ANV_DRAWID_VB_INDEX
;
3577 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(cmd_buffer
,
3578 access_type
== RANDOM
,
3583 VkCommandBuffer commandBuffer
,
3584 uint32_t vertexCount
,
3585 uint32_t instanceCount
,
3586 uint32_t firstVertex
,
3587 uint32_t firstInstance
)
3589 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3590 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3591 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3593 if (anv_batch_has_error(&cmd_buffer
->batch
))
3596 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3598 if (cmd_buffer
->state
.conditional_render_enabled
)
3599 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3601 if (vs_prog_data
->uses_firstvertex
||
3602 vs_prog_data
->uses_baseinstance
)
3603 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3604 if (vs_prog_data
->uses_drawid
)
3605 emit_draw_index(cmd_buffer
, 0);
3607 /* Emitting draw index or vertex index BOs may result in needing
3608 * additional VF cache flushes.
3610 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3612 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3613 * different views. We need to multiply instanceCount by the view count.
3615 if (!pipeline
->use_primitive_replication
)
3616 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3618 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3619 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3620 prim
.VertexAccessType
= SEQUENTIAL
;
3621 prim
.PrimitiveTopologyType
= cmd_buffer
->state
.gfx
.primitive_topology
;
3622 prim
.VertexCountPerInstance
= vertexCount
;
3623 prim
.StartVertexLocation
= firstVertex
;
3624 prim
.InstanceCount
= instanceCount
;
3625 prim
.StartInstanceLocation
= firstInstance
;
3626 prim
.BaseVertexLocation
= 0;
3629 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3632 void genX(CmdDrawIndexed
)(
3633 VkCommandBuffer commandBuffer
,
3634 uint32_t indexCount
,
3635 uint32_t instanceCount
,
3636 uint32_t firstIndex
,
3637 int32_t vertexOffset
,
3638 uint32_t firstInstance
)
3640 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3641 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3642 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3644 if (anv_batch_has_error(&cmd_buffer
->batch
))
3647 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3649 if (cmd_buffer
->state
.conditional_render_enabled
)
3650 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3652 if (vs_prog_data
->uses_firstvertex
||
3653 vs_prog_data
->uses_baseinstance
)
3654 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
3655 if (vs_prog_data
->uses_drawid
)
3656 emit_draw_index(cmd_buffer
, 0);
3658 /* Emitting draw index or vertex index BOs may result in needing
3659 * additional VF cache flushes.
3661 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3663 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3664 * different views. We need to multiply instanceCount by the view count.
3666 if (!pipeline
->use_primitive_replication
)
3667 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3669 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3670 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3671 prim
.VertexAccessType
= RANDOM
;
3672 prim
.PrimitiveTopologyType
= cmd_buffer
->state
.gfx
.primitive_topology
;
3673 prim
.VertexCountPerInstance
= indexCount
;
3674 prim
.StartVertexLocation
= firstIndex
;
3675 prim
.InstanceCount
= instanceCount
;
3676 prim
.StartInstanceLocation
= firstInstance
;
3677 prim
.BaseVertexLocation
= vertexOffset
;
3680 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3683 /* Auto-Draw / Indirect Registers */
3684 #define GEN7_3DPRIM_END_OFFSET 0x2420
3685 #define GEN7_3DPRIM_START_VERTEX 0x2430
3686 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3687 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3688 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3689 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3691 void genX(CmdDrawIndirectByteCountEXT
)(
3692 VkCommandBuffer commandBuffer
,
3693 uint32_t instanceCount
,
3694 uint32_t firstInstance
,
3695 VkBuffer counterBuffer
,
3696 VkDeviceSize counterBufferOffset
,
3697 uint32_t counterOffset
,
3698 uint32_t vertexStride
)
3700 #if GEN_IS_HASWELL || GEN_GEN >= 8
3701 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3702 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3703 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3704 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3706 /* firstVertex is always zero for this draw function */
3707 const uint32_t firstVertex
= 0;
3709 if (anv_batch_has_error(&cmd_buffer
->batch
))
3712 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3714 if (vs_prog_data
->uses_firstvertex
||
3715 vs_prog_data
->uses_baseinstance
)
3716 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3717 if (vs_prog_data
->uses_drawid
)
3718 emit_draw_index(cmd_buffer
, 0);
3720 /* Emitting draw index or vertex index BOs may result in needing
3721 * additional VF cache flushes.
3723 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3725 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3726 * different views. We need to multiply instanceCount by the view count.
3728 if (!pipeline
->use_primitive_replication
)
3729 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3731 struct gen_mi_builder b
;
3732 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3733 struct gen_mi_value count
=
3734 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3735 counterBufferOffset
));
3737 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3738 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3739 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3741 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3742 gen_mi_imm(firstVertex
));
3743 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3744 gen_mi_imm(instanceCount
));
3745 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3746 gen_mi_imm(firstInstance
));
3747 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3749 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3750 prim
.IndirectParameterEnable
= true;
3751 prim
.VertexAccessType
= SEQUENTIAL
;
3752 prim
.PrimitiveTopologyType
= cmd_buffer
->state
.gfx
.primitive_topology
;
3755 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3756 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3760 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3761 struct anv_address addr
,
3764 struct gen_mi_builder b
;
3765 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3767 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3768 gen_mi_mem32(anv_address_add(addr
, 0)));
3770 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3771 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3772 if (view_count
> 1) {
3773 #if GEN_IS_HASWELL || GEN_GEN >= 8
3774 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3776 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3777 "MI_MATH is not supported on Ivy Bridge");
3780 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3782 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3783 gen_mi_mem32(anv_address_add(addr
, 8)));
3786 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3787 gen_mi_mem32(anv_address_add(addr
, 12)));
3788 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3789 gen_mi_mem32(anv_address_add(addr
, 16)));
3791 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3792 gen_mi_mem32(anv_address_add(addr
, 12)));
3793 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3797 void genX(CmdDrawIndirect
)(
3798 VkCommandBuffer commandBuffer
,
3800 VkDeviceSize offset
,
3804 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3805 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3806 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3807 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3809 if (anv_batch_has_error(&cmd_buffer
->batch
))
3812 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3814 if (cmd_buffer
->state
.conditional_render_enabled
)
3815 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3817 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3818 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3820 if (vs_prog_data
->uses_firstvertex
||
3821 vs_prog_data
->uses_baseinstance
)
3822 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3823 if (vs_prog_data
->uses_drawid
)
3824 emit_draw_index(cmd_buffer
, i
);
3826 /* Emitting draw index or vertex index BOs may result in needing
3827 * additional VF cache flushes.
3829 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3831 load_indirect_parameters(cmd_buffer
, draw
, false);
3833 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3834 prim
.IndirectParameterEnable
= true;
3835 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3836 prim
.VertexAccessType
= SEQUENTIAL
;
3837 prim
.PrimitiveTopologyType
= cmd_buffer
->state
.gfx
.primitive_topology
;
3840 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3846 void genX(CmdDrawIndexedIndirect
)(
3847 VkCommandBuffer commandBuffer
,
3849 VkDeviceSize offset
,
3853 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3854 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3855 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3856 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3858 if (anv_batch_has_error(&cmd_buffer
->batch
))
3861 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3863 if (cmd_buffer
->state
.conditional_render_enabled
)
3864 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3866 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3867 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3869 /* TODO: We need to stomp base vertex to 0 somehow */
3870 if (vs_prog_data
->uses_firstvertex
||
3871 vs_prog_data
->uses_baseinstance
)
3872 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3873 if (vs_prog_data
->uses_drawid
)
3874 emit_draw_index(cmd_buffer
, i
);
3876 /* Emitting draw index or vertex index BOs may result in needing
3877 * additional VF cache flushes.
3879 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3881 load_indirect_parameters(cmd_buffer
, draw
, true);
3883 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3884 prim
.IndirectParameterEnable
= true;
3885 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3886 prim
.VertexAccessType
= RANDOM
;
3887 prim
.PrimitiveTopologyType
= cmd_buffer
->state
.gfx
.primitive_topology
;
3890 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3896 static struct gen_mi_value
3897 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3898 struct gen_mi_builder
*b
,
3899 struct anv_address count_address
,
3900 const bool conditional_render_enabled
)
3902 struct gen_mi_value ret
= gen_mi_imm(0);
3904 if (conditional_render_enabled
) {
3905 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3906 ret
= gen_mi_new_gpr(b
);
3907 gen_mi_store(b
, gen_mi_value_ref(b
, ret
), gen_mi_mem32(count_address
));
3910 /* Upload the current draw count from the draw parameters buffer to
3911 * MI_PREDICATE_SRC0.
3913 gen_mi_store(b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3914 gen_mi_mem32(count_address
));
3916 gen_mi_store(b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3923 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3924 struct gen_mi_builder
*b
,
3925 uint32_t draw_index
)
3927 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3928 gen_mi_store(b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3930 if (draw_index
== 0) {
3931 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3932 mip
.LoadOperation
= LOAD_LOADINV
;
3933 mip
.CombineOperation
= COMBINE_SET
;
3934 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3937 /* While draw_index < draw_count the predicate's result will be
3938 * (draw_index == draw_count) ^ TRUE = TRUE
3939 * When draw_index == draw_count the result is
3940 * (TRUE) ^ TRUE = FALSE
3941 * After this all results will be:
3942 * (FALSE) ^ FALSE = FALSE
3944 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3945 mip
.LoadOperation
= LOAD_LOAD
;
3946 mip
.CombineOperation
= COMBINE_XOR
;
3947 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3952 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3954 emit_draw_count_predicate_with_conditional_render(
3955 struct anv_cmd_buffer
*cmd_buffer
,
3956 struct gen_mi_builder
*b
,
3957 uint32_t draw_index
,
3958 struct gen_mi_value max
)
3960 struct gen_mi_value pred
= gen_mi_ult(b
, gen_mi_imm(draw_index
), max
);
3961 pred
= gen_mi_iand(b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3964 gen_mi_store(b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3966 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3967 * so we emit MI_PREDICATE to set it.
3970 gen_mi_store(b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3971 gen_mi_store(b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3973 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3974 mip
.LoadOperation
= LOAD_LOADINV
;
3975 mip
.CombineOperation
= COMBINE_SET
;
3976 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3982 void genX(CmdDrawIndirectCount
)(
3983 VkCommandBuffer commandBuffer
,
3985 VkDeviceSize offset
,
3986 VkBuffer _countBuffer
,
3987 VkDeviceSize countBufferOffset
,
3988 uint32_t maxDrawCount
,
3991 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3992 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3993 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3994 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3995 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
3996 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3998 if (anv_batch_has_error(&cmd_buffer
->batch
))
4001 genX(cmd_buffer_flush_state
)(cmd_buffer
);
4003 struct gen_mi_builder b
;
4004 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4005 struct anv_address count_address
=
4006 anv_address_add(count_buffer
->address
, countBufferOffset
);
4007 struct gen_mi_value max
=
4008 prepare_for_draw_count_predicate(cmd_buffer
, &b
, count_address
,
4009 cmd_state
->conditional_render_enabled
);
4011 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
4012 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
4014 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4015 if (cmd_state
->conditional_render_enabled
) {
4016 emit_draw_count_predicate_with_conditional_render(
4017 cmd_buffer
, &b
, i
, gen_mi_value_ref(&b
, max
));
4019 emit_draw_count_predicate(cmd_buffer
, &b
, i
);
4022 emit_draw_count_predicate(cmd_buffer
, &b
, i
);
4025 if (vs_prog_data
->uses_firstvertex
||
4026 vs_prog_data
->uses_baseinstance
)
4027 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
4028 if (vs_prog_data
->uses_drawid
)
4029 emit_draw_index(cmd_buffer
, i
);
4031 /* Emitting draw index or vertex index BOs may result in needing
4032 * additional VF cache flushes.
4034 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4036 load_indirect_parameters(cmd_buffer
, draw
, false);
4038 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
4039 prim
.IndirectParameterEnable
= true;
4040 prim
.PredicateEnable
= true;
4041 prim
.VertexAccessType
= SEQUENTIAL
;
4042 prim
.PrimitiveTopologyType
= cmd_buffer
->state
.gfx
.primitive_topology
;
4045 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
4050 gen_mi_value_unref(&b
, max
);
4053 void genX(CmdDrawIndexedIndirectCount
)(
4054 VkCommandBuffer commandBuffer
,
4056 VkDeviceSize offset
,
4057 VkBuffer _countBuffer
,
4058 VkDeviceSize countBufferOffset
,
4059 uint32_t maxDrawCount
,
4062 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4063 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
4064 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
4065 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4066 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
4067 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
4069 if (anv_batch_has_error(&cmd_buffer
->batch
))
4072 genX(cmd_buffer_flush_state
)(cmd_buffer
);
4074 struct gen_mi_builder b
;
4075 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4076 struct anv_address count_address
=
4077 anv_address_add(count_buffer
->address
, countBufferOffset
);
4078 struct gen_mi_value max
=
4079 prepare_for_draw_count_predicate(cmd_buffer
, &b
, count_address
,
4080 cmd_state
->conditional_render_enabled
);
4082 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
4083 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
4085 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4086 if (cmd_state
->conditional_render_enabled
) {
4087 emit_draw_count_predicate_with_conditional_render(
4088 cmd_buffer
, &b
, i
, gen_mi_value_ref(&b
, max
));
4090 emit_draw_count_predicate(cmd_buffer
, &b
, i
);
4093 emit_draw_count_predicate(cmd_buffer
, &b
, i
);
4096 /* TODO: We need to stomp base vertex to 0 somehow */
4097 if (vs_prog_data
->uses_firstvertex
||
4098 vs_prog_data
->uses_baseinstance
)
4099 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
4100 if (vs_prog_data
->uses_drawid
)
4101 emit_draw_index(cmd_buffer
, i
);
4103 /* Emitting draw index or vertex index BOs may result in needing
4104 * additional VF cache flushes.
4106 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4108 load_indirect_parameters(cmd_buffer
, draw
, true);
4110 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
4111 prim
.IndirectParameterEnable
= true;
4112 prim
.PredicateEnable
= true;
4113 prim
.VertexAccessType
= RANDOM
;
4114 prim
.PrimitiveTopologyType
= cmd_buffer
->state
.gfx
.primitive_topology
;
4117 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
4122 gen_mi_value_unref(&b
, max
);
4125 void genX(CmdBeginTransformFeedbackEXT
)(
4126 VkCommandBuffer commandBuffer
,
4127 uint32_t firstCounterBuffer
,
4128 uint32_t counterBufferCount
,
4129 const VkBuffer
* pCounterBuffers
,
4130 const VkDeviceSize
* pCounterBufferOffsets
)
4132 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4134 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4135 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4136 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4138 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4140 * "Ssoftware must ensure that no HW stream output operations can be in
4141 * process or otherwise pending at the point that the MI_LOAD/STORE
4142 * commands are processed. This will likely require a pipeline flush."
4144 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4145 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4147 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
4148 /* If we have a counter buffer, this is a resume so we need to load the
4149 * value into the streamout offset register. Otherwise, this is a begin
4150 * and we need to reset it to zero.
4152 if (pCounterBuffers
&&
4153 idx
>= firstCounterBuffer
&&
4154 idx
- firstCounterBuffer
< counterBufferCount
&&
4155 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
4156 uint32_t cb_idx
= idx
- firstCounterBuffer
;
4157 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4158 uint64_t offset
= pCounterBufferOffsets
?
4159 pCounterBufferOffsets
[cb_idx
] : 0;
4161 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4162 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4163 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4167 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4168 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4174 cmd_buffer
->state
.xfb_enabled
= true;
4175 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4178 void genX(CmdEndTransformFeedbackEXT
)(
4179 VkCommandBuffer commandBuffer
,
4180 uint32_t firstCounterBuffer
,
4181 uint32_t counterBufferCount
,
4182 const VkBuffer
* pCounterBuffers
,
4183 const VkDeviceSize
* pCounterBufferOffsets
)
4185 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4187 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4188 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4189 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4191 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4193 * "Ssoftware must ensure that no HW stream output operations can be in
4194 * process or otherwise pending at the point that the MI_LOAD/STORE
4195 * commands are processed. This will likely require a pipeline flush."
4197 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4198 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4200 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
4201 unsigned idx
= firstCounterBuffer
+ cb_idx
;
4203 /* If we have a counter buffer, this is a resume so we need to load the
4204 * value into the streamout offset register. Otherwise, this is a begin
4205 * and we need to reset it to zero.
4207 if (pCounterBuffers
&&
4208 cb_idx
< counterBufferCount
&&
4209 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
4210 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4211 uint64_t offset
= pCounterBufferOffsets
?
4212 pCounterBufferOffsets
[cb_idx
] : 0;
4214 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4215 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4217 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4222 cmd_buffer
->state
.xfb_enabled
= false;
4223 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4227 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
4229 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4231 assert(pipeline
->cs
);
4233 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
4235 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
4237 /* Apply any pending pipeline flushes we may have. We want to apply them
4238 * now because, if any of those flushes are for things like push constants,
4239 * the GPU will read the state at weird times.
4241 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4243 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
4244 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
4246 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4247 * the only bits that are changed are scoreboard related: Scoreboard
4248 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4249 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4252 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4253 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4255 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
4257 /* The workgroup size of the pipeline affects our push constant layout
4258 * so flag push constants as dirty if we change the pipeline.
4260 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4263 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
4264 cmd_buffer
->state
.compute
.pipeline_dirty
) {
4265 flush_descriptor_sets(cmd_buffer
,
4266 &cmd_buffer
->state
.compute
.base
,
4269 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4270 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
4271 .BindingTablePointer
=
4272 cmd_buffer
->state
.binding_tables
[MESA_SHADER_COMPUTE
].offset
,
4273 .SamplerStatePointer
=
4274 cmd_buffer
->state
.samplers
[MESA_SHADER_COMPUTE
].offset
,
4276 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
4278 struct anv_state state
=
4279 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
4280 pipeline
->interface_descriptor_data
,
4281 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
4284 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4285 anv_batch_emit(&cmd_buffer
->batch
,
4286 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
4287 mid
.InterfaceDescriptorTotalLength
= size
;
4288 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
4292 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
4293 struct anv_state push_state
=
4294 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
4296 if (push_state
.alloc_size
) {
4297 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4298 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
4299 curbe
.CURBEDataStartAddress
= push_state
.offset
;
4303 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
4306 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
4308 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4314 verify_cmd_parser(const struct anv_device
*device
,
4315 int required_version
,
4316 const char *function
)
4318 if (device
->physical
->cmd_parser_version
< required_version
) {
4319 return vk_errorf(device
, device
->physical
,
4320 VK_ERROR_FEATURE_NOT_PRESENT
,
4321 "cmd parser version %d is required for %s",
4322 required_version
, function
);
4331 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
4332 uint32_t baseGroupX
,
4333 uint32_t baseGroupY
,
4334 uint32_t baseGroupZ
)
4336 if (anv_batch_has_error(&cmd_buffer
->batch
))
4339 struct anv_push_constants
*push
=
4340 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
4341 if (push
->cs
.base_work_group_id
[0] != baseGroupX
||
4342 push
->cs
.base_work_group_id
[1] != baseGroupY
||
4343 push
->cs
.base_work_group_id
[2] != baseGroupZ
) {
4344 push
->cs
.base_work_group_id
[0] = baseGroupX
;
4345 push
->cs
.base_work_group_id
[1] = baseGroupY
;
4346 push
->cs
.base_work_group_id
[2] = baseGroupZ
;
4348 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4352 void genX(CmdDispatch
)(
4353 VkCommandBuffer commandBuffer
,
4358 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
4362 emit_gpgpu_walker(struct anv_cmd_buffer
*cmd_buffer
,
4363 const struct anv_compute_pipeline
*pipeline
, bool indirect
,
4364 const struct brw_cs_prog_data
*prog_data
,
4365 uint32_t groupCountX
, uint32_t groupCountY
,
4366 uint32_t groupCountZ
)
4368 bool predicate
= (GEN_GEN
<= 7 && indirect
) ||
4369 cmd_buffer
->state
.conditional_render_enabled
;
4370 const struct anv_cs_parameters cs_params
= anv_cs_parameters(pipeline
);
4372 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
4373 ggw
.IndirectParameterEnable
= indirect
;
4374 ggw
.PredicateEnable
= predicate
;
4375 ggw
.SIMDSize
= cs_params
.simd_size
/ 16;
4376 ggw
.ThreadDepthCounterMaximum
= 0;
4377 ggw
.ThreadHeightCounterMaximum
= 0;
4378 ggw
.ThreadWidthCounterMaximum
= cs_params
.threads
- 1;
4379 ggw
.ThreadGroupIDXDimension
= groupCountX
;
4380 ggw
.ThreadGroupIDYDimension
= groupCountY
;
4381 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
4382 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4383 ggw
.BottomExecutionMask
= 0xffffffff;
4386 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4389 void genX(CmdDispatchBase
)(
4390 VkCommandBuffer commandBuffer
,
4391 uint32_t baseGroupX
,
4392 uint32_t baseGroupY
,
4393 uint32_t baseGroupZ
,
4394 uint32_t groupCountX
,
4395 uint32_t groupCountY
,
4396 uint32_t groupCountZ
)
4398 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4399 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4400 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4402 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
4403 baseGroupY
, baseGroupZ
);
4405 if (anv_batch_has_error(&cmd_buffer
->batch
))
4408 if (prog_data
->uses_num_work_groups
) {
4409 struct anv_state state
=
4410 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
4411 uint32_t *sizes
= state
.map
;
4412 sizes
[0] = groupCountX
;
4413 sizes
[1] = groupCountY
;
4414 sizes
[2] = groupCountZ
;
4415 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
4416 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4417 .offset
= state
.offset
,
4420 /* The num_workgroups buffer goes in the binding table */
4421 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4424 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4426 if (cmd_buffer
->state
.conditional_render_enabled
)
4427 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4429 emit_gpgpu_walker(cmd_buffer
, pipeline
, false, prog_data
, groupCountX
,
4430 groupCountY
, groupCountZ
);
4433 #define GPGPU_DISPATCHDIMX 0x2500
4434 #define GPGPU_DISPATCHDIMY 0x2504
4435 #define GPGPU_DISPATCHDIMZ 0x2508
4437 void genX(CmdDispatchIndirect
)(
4438 VkCommandBuffer commandBuffer
,
4440 VkDeviceSize offset
)
4442 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4443 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
4444 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4445 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4446 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
4447 UNUSED
struct anv_batch
*batch
= &cmd_buffer
->batch
;
4449 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
4452 /* Linux 4.4 added command parser version 5 which allows the GPGPU
4453 * indirect dispatch registers to be written.
4455 if (verify_cmd_parser(cmd_buffer
->device
, 5,
4456 "vkCmdDispatchIndirect") != VK_SUCCESS
)
4460 if (prog_data
->uses_num_work_groups
) {
4461 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
4463 /* The num_workgroups buffer goes in the binding table */
4464 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4467 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4469 struct gen_mi_builder b
;
4470 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4472 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
4473 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
4474 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
4476 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
4477 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
4478 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
4481 /* predicate = (compute_dispatch_indirect_x_size == 0); */
4482 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
4483 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4484 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4485 mip
.LoadOperation
= LOAD_LOAD
;
4486 mip
.CombineOperation
= COMBINE_SET
;
4487 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4490 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
4491 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
4492 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4493 mip
.LoadOperation
= LOAD_LOAD
;
4494 mip
.CombineOperation
= COMBINE_OR
;
4495 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4498 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
4499 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
4500 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4501 mip
.LoadOperation
= LOAD_LOAD
;
4502 mip
.CombineOperation
= COMBINE_OR
;
4503 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4506 /* predicate = !predicate; */
4507 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4508 mip
.LoadOperation
= LOAD_LOADINV
;
4509 mip
.CombineOperation
= COMBINE_OR
;
4510 mip
.CompareOperation
= COMPARE_FALSE
;
4514 if (cmd_buffer
->state
.conditional_render_enabled
) {
4515 /* predicate &= !(conditional_rendering_predicate == 0); */
4516 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
4517 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4518 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4519 mip
.LoadOperation
= LOAD_LOADINV
;
4520 mip
.CombineOperation
= COMBINE_AND
;
4521 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4526 #else /* GEN_GEN > 7 */
4527 if (cmd_buffer
->state
.conditional_render_enabled
)
4528 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4531 emit_gpgpu_walker(cmd_buffer
, pipeline
, true, prog_data
, 0, 0, 0);
4535 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
4538 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4540 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
4543 #if GEN_GEN >= 8 && GEN_GEN < 10
4544 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
4546 * Software must clear the COLOR_CALC_STATE Valid field in
4547 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
4548 * with Pipeline Select set to GPGPU.
4550 * The internal hardware docs recommend the same workaround for Gen9
4553 if (pipeline
== GPGPU
)
4554 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
4558 if (pipeline
== _3D
) {
4559 /* There is a mid-object preemption workaround which requires you to
4560 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
4561 * even without preemption, we have issues with geometry flickering when
4562 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
4565 const uint32_t subslices
=
4566 MAX2(cmd_buffer
->device
->physical
->subslice_total
, 1);
4567 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4568 vfe
.MaximumNumberofThreads
=
4569 devinfo
->max_cs_threads
* subslices
- 1;
4570 vfe
.NumberofURBEntries
= 2;
4571 vfe
.URBEntryAllocationSize
= 2;
4574 /* We just emitted a dummy MEDIA_VFE_STATE so now that packet is
4575 * invalid. Set the compute pipeline to dirty to force a re-emit of the
4576 * pipeline in case we get back-to-back dispatch calls with the same
4577 * pipeline and a PIPELINE_SELECT in between.
4579 cmd_buffer
->state
.compute
.pipeline_dirty
= true;
4583 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
4584 * PIPELINE_SELECT [DevBWR+]":
4588 * Software must ensure all the write caches are flushed through a
4589 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
4590 * command to invalidate read only caches prior to programming
4591 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
4593 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4594 pc
.RenderTargetCacheFlushEnable
= true;
4595 pc
.DepthCacheFlushEnable
= true;
4596 pc
.DCFlushEnable
= true;
4597 pc
.PostSyncOperation
= NoWrite
;
4598 pc
.CommandStreamerStallEnable
= true;
4600 pc
.TileCacheFlushEnable
= true;
4602 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
4603 * set with any PIPE_CONTROL with Depth Flush Enable bit set.
4605 pc
.DepthStallEnable
= true;
4609 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4610 pc
.TextureCacheInvalidationEnable
= true;
4611 pc
.ConstantCacheInvalidationEnable
= true;
4612 pc
.StateCacheInvalidationEnable
= true;
4613 pc
.InstructionCacheInvalidateEnable
= true;
4614 pc
.PostSyncOperation
= NoWrite
;
4616 pc
.TileCacheFlushEnable
= true;
4620 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
4624 ps
.PipelineSelection
= pipeline
;
4628 if (devinfo
->is_geminilake
) {
4631 * "This chicken bit works around a hardware issue with barrier logic
4632 * encountered when switching between GPGPU and 3D pipelines. To
4633 * workaround the issue, this mode bit should be set after a pipeline
4637 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
4639 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
4640 : GLK_BARRIER_MODE_3D_HULL
,
4641 .GLKBarrierModeMask
= 1);
4642 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
4646 cmd_buffer
->state
.current_pipeline
= pipeline
;
4650 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
4652 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
4656 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
4658 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
4662 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
4667 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
4669 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
4670 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
4671 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
4672 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
4673 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
4674 * Depth Flush Bit set, followed by another pipelined depth stall
4675 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
4676 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
4677 * via a preceding MI_FLUSH)."
4679 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4680 pipe
.DepthStallEnable
= true;
4682 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4683 pipe
.DepthCacheFlushEnable
= true;
4685 pipe
.TileCacheFlushEnable
= true;
4688 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4689 pipe
.DepthStallEnable
= true;
4693 /* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
4695 * "The VF cache needs to be invalidated before binding and then using
4696 * Vertex Buffers that overlap with any previously bound Vertex Buffer
4697 * (at a 64B granularity) since the last invalidation. A VF cache
4698 * invalidate is performed by setting the "VF Cache Invalidation Enable"
4699 * bit in PIPE_CONTROL."
4701 * This is implemented by carefully tracking all vertex and index buffer
4702 * bindings and flushing if the cache ever ends up with a range in the cache
4703 * that would exceed 4 GiB. This is implemented in three parts:
4705 * 1. genX(cmd_buffer_set_binding_for_gen8_vb_flush)() which must be called
4706 * every time a 3DSTATE_VERTEX_BUFFER packet is emitted and informs the
4707 * tracking code of the new binding. If this new binding would cause
4708 * the cache to have a too-large range on the next draw call, a pipeline
4709 * stall and VF cache invalidate are added to pending_pipeline_bits.
4711 * 2. genX(cmd_buffer_apply_pipe_flushes)() resets the cache tracking to
4712 * empty whenever we emit a VF invalidate.
4714 * 3. genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)() must be called
4715 * after every 3DPRIMITIVE and copies the bound range into the dirty
4716 * range for each used buffer. This has to be a separate step because
4717 * we don't always re-bind all buffers and so 1. can't know which
4718 * buffers are actually bound.
4721 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4723 struct anv_address vb_address
,
4726 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4727 !cmd_buffer
->device
->physical
->use_softpin
)
4730 struct anv_vb_cache_range
*bound
, *dirty
;
4731 if (vb_index
== -1) {
4732 bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4733 dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4735 assert(vb_index
>= 0);
4736 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4737 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4738 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[vb_index
];
4739 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[vb_index
];
4748 assert(vb_address
.bo
&& (vb_address
.bo
->flags
& EXEC_OBJECT_PINNED
));
4749 bound
->start
= gen_48b_address(anv_address_physical(vb_address
));
4750 bound
->end
= bound
->start
+ vb_size
;
4751 assert(bound
->end
> bound
->start
); /* No overflow */
4753 /* Align everything to a cache line */
4754 bound
->start
&= ~(64ull - 1ull);
4755 bound
->end
= align_u64(bound
->end
, 64);
4757 /* Compute the dirty range */
4758 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4759 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4761 /* If our range is larger than 32 bits, we have to flush */
4762 assert(bound
->end
- bound
->start
<= (1ull << 32));
4763 if (dirty
->end
- dirty
->start
> (1ull << 32)) {
4764 cmd_buffer
->state
.pending_pipe_bits
|=
4765 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
4770 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4771 uint32_t access_type
,
4774 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4775 !cmd_buffer
->device
->physical
->use_softpin
)
4778 if (access_type
== RANDOM
) {
4779 /* We have an index buffer */
4780 struct anv_vb_cache_range
*bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4781 struct anv_vb_cache_range
*dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4783 if (bound
->end
> bound
->start
) {
4784 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4785 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4789 uint64_t mask
= vb_used
;
4791 int i
= u_bit_scan64(&mask
);
4793 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4794 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4796 struct anv_vb_cache_range
*bound
, *dirty
;
4797 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[i
];
4798 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[i
];
4800 if (bound
->end
> bound
->start
) {
4801 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4802 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4808 * Update the pixel hashing modes that determine the balancing of PS threads
4809 * across subslices and slices.
4811 * \param width Width bound of the rendering area (already scaled down if \p
4812 * scale is greater than 1).
4813 * \param height Height bound of the rendering area (already scaled down if \p
4814 * scale is greater than 1).
4815 * \param scale The number of framebuffer samples that could potentially be
4816 * affected by an individual channel of the PS thread. This is
4817 * typically one for single-sampled rendering, but for operations
4818 * like CCS resolves and fast clears a single PS invocation may
4819 * update a huge number of pixels, in which case a finer
4820 * balancing is desirable in order to maximally utilize the
4821 * bandwidth available. UINT_MAX can be used as shorthand for
4822 * "finest hashing mode available".
4825 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4826 unsigned width
, unsigned height
,
4830 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4831 const unsigned slice_hashing
[] = {
4832 /* Because all Gen9 platforms with more than one slice require
4833 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4834 * block is guaranteed to suffer from substantial imbalance, with one
4835 * subslice receiving twice as much work as the other two in the
4838 * The performance impact of that would be particularly severe when
4839 * three-way hashing is also in use for slice balancing (which is the
4840 * case for all Gen9 GT4 platforms), because one of the slices
4841 * receives one every three 16x16 blocks in either direction, which
4842 * is roughly the periodicity of the underlying subslice imbalance
4843 * pattern ("roughly" because in reality the hardware's
4844 * implementation of three-way hashing doesn't do exact modulo 3
4845 * arithmetic, which somewhat decreases the magnitude of this effect
4846 * in practice). This leads to a systematic subslice imbalance
4847 * within that slice regardless of the size of the primitive. The
4848 * 32x32 hashing mode guarantees that the subslice imbalance within a
4849 * single slice hashing block is minimal, largely eliminating this
4853 /* Finest slice hashing mode available. */
4856 const unsigned subslice_hashing
[] = {
4857 /* 16x16 would provide a slight cache locality benefit especially
4858 * visible in the sampler L1 cache efficiency of low-bandwidth
4859 * non-LLC platforms, but it comes at the cost of greater subslice
4860 * imbalance for primitives of dimensions approximately intermediate
4861 * between 16x4 and 16x16.
4864 /* Finest subslice hashing mode available. */
4867 /* Dimensions of the smallest hashing block of a given hashing mode. If
4868 * the rendering area is smaller than this there can't possibly be any
4869 * benefit from switching to this mode, so we optimize out the
4872 const unsigned min_size
[][2] = {
4876 const unsigned idx
= scale
> 1;
4878 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4879 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4882 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4883 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4884 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4885 .SubsliceHashing
= subslice_hashing
[idx
],
4886 .SubsliceHashingMask
= -1);
4888 cmd_buffer
->state
.pending_pipe_bits
|=
4889 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4890 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4892 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4894 cmd_buffer
->state
.current_hash_scale
= scale
;
4900 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4902 struct anv_device
*device
= cmd_buffer
->device
;
4903 const struct anv_image_view
*iview
=
4904 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4905 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4907 /* FIXME: Width and Height are wrong */
4909 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4911 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4912 device
->isl_dev
.ds
.size
/ 4);
4916 struct isl_depth_stencil_hiz_emit_info info
= { };
4919 info
.view
= &iview
->planes
[0].isl
;
4921 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4922 uint32_t depth_plane
=
4923 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4924 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4926 info
.depth_surf
= &surface
->isl
;
4928 info
.depth_address
=
4929 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4930 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4931 image
->planes
[depth_plane
].address
.bo
,
4932 image
->planes
[depth_plane
].address
.offset
+
4935 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4938 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4939 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4940 if (info
.hiz_usage
!= ISL_AUX_USAGE_NONE
) {
4941 assert(isl_aux_usage_has_hiz(info
.hiz_usage
));
4942 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4945 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4946 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4947 image
->planes
[depth_plane
].address
.bo
,
4948 image
->planes
[depth_plane
].address
.offset
+
4949 image
->planes
[depth_plane
].aux_surface
.offset
);
4951 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4955 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4956 uint32_t stencil_plane
=
4957 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4958 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4960 info
.stencil_surf
= &surface
->isl
;
4962 info
.stencil_address
=
4963 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4964 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4965 image
->planes
[stencil_plane
].address
.bo
,
4966 image
->planes
[stencil_plane
].address
.offset
+
4969 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4972 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4974 if (GEN_GEN
>= 12) {
4975 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
4976 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4978 /* GEN:BUG:1408224581
4980 * Workaround: Gen12LP Astep only An additional pipe control with
4981 * post-sync = store dword operation would be required.( w/a is to
4982 * have an additional pipe control after the stencil state whenever
4983 * the surface state bits of this state is changing).
4985 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4986 pc
.PostSyncOperation
= WriteImmediateData
;
4987 pc
.Address
= cmd_buffer
->device
->workaround_address
;
4990 cmd_buffer
->state
.hiz_enabled
= isl_aux_usage_has_hiz(info
.hiz_usage
);
4994 * This ANDs the view mask of the current subpass with the pending clear
4995 * views in the attachment to get the mask of views active in the subpass
4996 * that still need to be cleared.
4998 static inline uint32_t
4999 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
5000 const struct anv_attachment_state
*att_state
)
5002 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
5006 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
5007 const struct anv_attachment_state
*att_state
)
5009 if (!cmd_state
->subpass
->view_mask
)
5012 uint32_t pending_clear_mask
=
5013 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5015 return pending_clear_mask
& 1;
5019 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
5022 const uint32_t last_subpass_idx
=
5023 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
5024 const struct anv_subpass
*last_subpass
=
5025 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
5026 return last_subpass
== cmd_state
->subpass
;
5030 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
5031 uint32_t subpass_id
)
5033 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5034 struct anv_render_pass
*pass
= cmd_state
->pass
;
5035 struct anv_subpass
*subpass
= &pass
->subpasses
[subpass_id
];
5036 cmd_state
->subpass
= subpass
;
5038 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
5040 /* Our implementation of VK_KHR_multiview uses instancing to draw the
5041 * different views. If the client asks for instancing, we need to use the
5042 * Instance Data Step Rate to ensure that we repeat the client's
5043 * per-instance data once for each view. Since this bit is in
5044 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
5048 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
5050 /* It is possible to start a render pass with an old pipeline. Because the
5051 * render pass and subpass index are both baked into the pipeline, this is
5052 * highly unlikely. In order to do so, it requires that you have a render
5053 * pass with a single subpass and that you use that render pass twice
5054 * back-to-back and use the same pipeline at the start of the second render
5055 * pass as at the end of the first. In order to avoid unpredictable issues
5056 * with this edge case, we just dirty the pipeline at the start of every
5059 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
5061 /* Accumulate any subpass flushes that need to happen before the subpass */
5062 cmd_buffer
->state
.pending_pipe_bits
|=
5063 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
5065 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5066 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
5068 bool is_multiview
= subpass
->view_mask
!= 0;
5070 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5071 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5072 if (a
== VK_ATTACHMENT_UNUSED
)
5075 assert(a
< cmd_state
->pass
->attachment_count
);
5076 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5078 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5079 const struct anv_image
*image
= iview
->image
;
5081 VkImageLayout target_layout
= subpass
->attachments
[i
].layout
;
5082 VkImageLayout target_stencil_layout
=
5083 subpass
->attachments
[i
].stencil_layout
;
5085 uint32_t base_layer
, layer_count
;
5086 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5088 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5089 iview
->planes
[0].isl
.base_level
);
5091 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5092 layer_count
= fb
->layers
;
5095 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5096 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5097 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5098 iview
->planes
[0].isl
.base_level
, 1,
5099 base_layer
, layer_count
,
5100 att_state
->current_layout
, target_layout
);
5101 att_state
->aux_usage
=
5102 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
5103 VK_IMAGE_ASPECT_COLOR_BIT
,
5104 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
,
5108 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5109 transition_depth_buffer(cmd_buffer
, image
,
5110 base_layer
, layer_count
,
5111 att_state
->current_layout
, target_layout
);
5112 att_state
->aux_usage
=
5113 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
5114 VK_IMAGE_ASPECT_DEPTH_BIT
,
5115 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
5119 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5120 transition_stencil_buffer(cmd_buffer
, image
,
5121 iview
->planes
[0].isl
.base_level
, 1,
5122 base_layer
, layer_count
,
5123 att_state
->current_stencil_layout
,
5124 target_stencil_layout
);
5126 att_state
->current_layout
= target_layout
;
5127 att_state
->current_stencil_layout
= target_stencil_layout
;
5129 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
5130 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5132 /* Multi-planar images are not supported as attachments */
5133 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5134 assert(image
->n_planes
== 1);
5136 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
5137 uint32_t clear_layer_count
= fb
->layers
;
5139 if (att_state
->fast_clear
&&
5140 do_first_layer_clear(cmd_state
, att_state
)) {
5141 /* We only support fast-clears on the first layer */
5142 assert(iview
->planes
[0].isl
.base_level
== 0);
5143 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
5145 union isl_color_value clear_color
= {};
5146 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
5147 if (iview
->image
->samples
== 1) {
5148 anv_image_ccs_op(cmd_buffer
, image
,
5149 iview
->planes
[0].isl
.format
,
5150 iview
->planes
[0].isl
.swizzle
,
5151 VK_IMAGE_ASPECT_COLOR_BIT
,
5152 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5156 anv_image_mcs_op(cmd_buffer
, image
,
5157 iview
->planes
[0].isl
.format
,
5158 iview
->planes
[0].isl
.swizzle
,
5159 VK_IMAGE_ASPECT_COLOR_BIT
,
5160 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5165 clear_layer_count
--;
5167 att_state
->pending_clear_views
&= ~1;
5169 if (isl_color_value_is_zero(clear_color
,
5170 iview
->planes
[0].isl
.format
)) {
5171 /* This image has the auxiliary buffer enabled. We can mark the
5172 * subresource as not needing a resolve because the clear color
5173 * will match what's in every RENDER_SURFACE_STATE object when
5174 * it's being used for sampling.
5176 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5177 VK_IMAGE_ASPECT_COLOR_BIT
,
5178 ANV_FAST_CLEAR_DEFAULT_VALUE
);
5180 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5181 VK_IMAGE_ASPECT_COLOR_BIT
,
5182 ANV_FAST_CLEAR_ANY
);
5186 /* From the VkFramebufferCreateInfo spec:
5188 * "If the render pass uses multiview, then layers must be one and each
5189 * attachment requires a number of layers that is greater than the
5190 * maximum bit index set in the view mask in the subpasses in which it
5193 * So if multiview is active we ignore the number of layers in the
5194 * framebuffer and instead we honor the view mask from the subpass.
5197 assert(image
->n_planes
== 1);
5198 uint32_t pending_clear_mask
=
5199 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5202 for_each_bit(layer_idx
, pending_clear_mask
) {
5204 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5206 anv_image_clear_color(cmd_buffer
, image
,
5207 VK_IMAGE_ASPECT_COLOR_BIT
,
5208 att_state
->aux_usage
,
5209 iview
->planes
[0].isl
.format
,
5210 iview
->planes
[0].isl
.swizzle
,
5211 iview
->planes
[0].isl
.base_level
,
5214 vk_to_isl_color(att_state
->clear_value
.color
));
5217 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5218 } else if (clear_layer_count
> 0) {
5219 assert(image
->n_planes
== 1);
5220 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5221 att_state
->aux_usage
,
5222 iview
->planes
[0].isl
.format
,
5223 iview
->planes
[0].isl
.swizzle
,
5224 iview
->planes
[0].isl
.base_level
,
5225 base_clear_layer
, clear_layer_count
,
5227 vk_to_isl_color(att_state
->clear_value
.color
));
5229 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
5230 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
5231 if (att_state
->fast_clear
&& !is_multiview
) {
5232 /* We currently only support HiZ for single-LOD images */
5233 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5234 assert(isl_aux_usage_has_hiz(iview
->image
->planes
[0].aux_usage
));
5235 assert(iview
->planes
[0].isl
.base_level
== 0);
5238 anv_image_hiz_clear(cmd_buffer
, image
,
5239 att_state
->pending_clear_aspects
,
5240 iview
->planes
[0].isl
.base_level
,
5241 iview
->planes
[0].isl
.base_array_layer
,
5242 fb
->layers
, render_area
,
5243 att_state
->clear_value
.depthStencil
.stencil
);
5244 } else if (is_multiview
) {
5245 uint32_t pending_clear_mask
=
5246 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5249 for_each_bit(layer_idx
, pending_clear_mask
) {
5251 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5253 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5254 att_state
->pending_clear_aspects
,
5255 att_state
->aux_usage
,
5256 iview
->planes
[0].isl
.base_level
,
5259 att_state
->clear_value
.depthStencil
.depth
,
5260 att_state
->clear_value
.depthStencil
.stencil
);
5263 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5265 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5266 att_state
->pending_clear_aspects
,
5267 att_state
->aux_usage
,
5268 iview
->planes
[0].isl
.base_level
,
5269 iview
->planes
[0].isl
.base_array_layer
,
5270 fb
->layers
, render_area
,
5271 att_state
->clear_value
.depthStencil
.depth
,
5272 att_state
->clear_value
.depthStencil
.stencil
);
5275 assert(att_state
->pending_clear_aspects
== 0);
5278 /* If multiview is enabled, then we are only done clearing when we no
5279 * longer have pending layers to clear, or when we have processed the
5280 * last subpass that uses this attachment.
5282 if (!is_multiview
||
5283 att_state
->pending_clear_views
== 0 ||
5284 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
5285 att_state
->pending_clear_aspects
= 0;
5288 att_state
->pending_load_aspects
= 0;
5291 /* We've transitioned all our images possibly fast clearing them. Now we
5292 * can fill out the surface states that we will use as render targets
5293 * during actual subpass rendering.
5295 VkResult result
= genX(cmd_buffer_alloc_att_surf_states
)(cmd_buffer
,
5297 if (result
!= VK_SUCCESS
)
5300 isl_null_fill_state(&cmd_buffer
->device
->isl_dev
,
5301 cmd_state
->null_surface_state
.map
,
5302 isl_extent3d(fb
->width
, fb
->height
, fb
->layers
));
5304 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5305 const uint32_t att
= subpass
->attachments
[i
].attachment
;
5306 if (att
== VK_ATTACHMENT_UNUSED
)
5309 assert(att
< cmd_state
->pass
->attachment_count
);
5310 struct anv_render_pass_attachment
*pass_att
= &pass
->attachments
[att
];
5311 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
5312 struct anv_image_view
*iview
= att_state
->image_view
;
5314 if (!vk_format_is_color(pass_att
->format
))
5317 const VkImageUsageFlagBits att_usage
= subpass
->attachments
[i
].usage
;
5318 assert(util_bitcount(att_usage
) == 1);
5320 struct anv_surface_state
*surface_state
;
5321 isl_surf_usage_flags_t isl_surf_usage
;
5322 enum isl_aux_usage isl_aux_usage
;
5323 if (att_usage
== VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
5324 surface_state
= &att_state
->color
;
5325 isl_surf_usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
5326 isl_aux_usage
= att_state
->aux_usage
;
5327 } else if (att_usage
== VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
) {
5328 surface_state
= &att_state
->input
;
5329 isl_surf_usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
5331 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
5332 VK_IMAGE_ASPECT_COLOR_BIT
,
5333 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
,
5334 att_state
->current_layout
);
5339 /* We had better have a surface state when we get here */
5340 assert(surface_state
->state
.map
);
5342 union isl_color_value clear_color
= { .u32
= { 0, } };
5343 if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
&&
5344 att_state
->fast_clear
)
5345 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
5347 anv_image_fill_surface_state(cmd_buffer
->device
,
5349 VK_IMAGE_ASPECT_COLOR_BIT
,
5350 &iview
->planes
[0].isl
,
5358 add_surface_state_relocs(cmd_buffer
, *surface_state
);
5361 pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
&&
5362 iview
->image
->planes
[0].aux_usage
!= ISL_AUX_USAGE_NONE
&&
5363 iview
->planes
[0].isl
.base_level
== 0 &&
5364 iview
->planes
[0].isl
.base_array_layer
== 0) {
5365 genX(copy_fast_clear_dwords
)(cmd_buffer
, surface_state
->state
,
5367 VK_IMAGE_ASPECT_COLOR_BIT
,
5368 false /* copy to ss */);
5373 /* The PIPE_CONTROL command description says:
5375 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
5376 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
5377 * Target Cache Flush by enabling this bit. When render target flush
5378 * is set due to new association of BTI, PS Scoreboard Stall bit must
5379 * be set in this packet."
5381 cmd_buffer
->state
.pending_pipe_bits
|=
5382 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
|
5383 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
5387 /* GEN:BUG:14010455700
5389 * ISL will change some CHICKEN registers depending on the depth surface
5390 * format, along with emitting the depth and stencil packets. In that case,
5391 * we want to do a depth flush and stall, so the pipeline is not using these
5392 * settings while we change the registers.
5394 cmd_buffer
->state
.pending_pipe_bits
|=
5395 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
|
5396 ANV_PIPE_DEPTH_STALL_BIT
|
5397 ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
5398 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5401 cmd_buffer_emit_depth_stencil(cmd_buffer
);
5404 static enum blorp_filter
5405 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
5408 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
5409 return BLORP_FILTER_SAMPLE_0
;
5410 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
5411 return BLORP_FILTER_AVERAGE
;
5412 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
5413 return BLORP_FILTER_MIN_SAMPLE
;
5414 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
5415 return BLORP_FILTER_MAX_SAMPLE
;
5417 return BLORP_FILTER_NONE
;
5422 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
5424 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5425 struct anv_subpass
*subpass
= cmd_state
->subpass
;
5426 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
5427 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
5429 /* We are done with the previous subpass and all rendering directly to that
5430 * subpass is now complete. Zero out all the surface states so we don't
5431 * accidentally use them between now and the next subpass.
5433 for (uint32_t i
= 0; i
< cmd_state
->pass
->attachment_count
; ++i
) {
5434 memset(&cmd_state
->attachments
[i
].color
, 0,
5435 sizeof(cmd_state
->attachments
[i
].color
));
5436 memset(&cmd_state
->attachments
[i
].input
, 0,
5437 sizeof(cmd_state
->attachments
[i
].input
));
5439 cmd_state
->null_surface_state
= ANV_STATE_NULL
;
5440 cmd_state
->attachment_states
= ANV_STATE_NULL
;
5442 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5443 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5444 if (a
== VK_ATTACHMENT_UNUSED
)
5447 assert(a
< cmd_state
->pass
->attachment_count
);
5448 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5449 struct anv_image_view
*iview
= att_state
->image_view
;
5451 assert(util_bitcount(subpass
->attachments
[i
].usage
) == 1);
5452 if (subpass
->attachments
[i
].usage
==
5453 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
5454 /* We assume that if we're ending a subpass, we did do some rendering
5455 * so we may end up with compressed data.
5457 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5458 VK_IMAGE_ASPECT_COLOR_BIT
,
5459 att_state
->aux_usage
,
5460 iview
->planes
[0].isl
.base_level
,
5461 iview
->planes
[0].isl
.base_array_layer
,
5463 } else if (subpass
->attachments
[i
].usage
==
5464 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
5465 /* We may be writing depth or stencil so we need to mark the surface.
5466 * Unfortunately, there's no way to know at this point whether the
5467 * depth or stencil tests used will actually write to the surface.
5469 * Even though stencil may be plane 1, it always shares a base_level
5472 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
5473 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5474 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5475 VK_IMAGE_ASPECT_DEPTH_BIT
,
5476 att_state
->aux_usage
,
5477 ds_view
->base_level
,
5478 ds_view
->base_array_layer
,
5481 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5482 /* Even though stencil may be plane 1, it always shares a
5483 * base_level with depth.
5485 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5486 VK_IMAGE_ASPECT_STENCIL_BIT
,
5488 ds_view
->base_level
,
5489 ds_view
->base_array_layer
,
5495 if (subpass
->has_color_resolve
) {
5496 /* We are about to do some MSAA resolves. We need to flush so that the
5497 * result of writes to the MSAA color attachments show up in the sampler
5498 * when we blit to the single-sampled resolve target.
5500 cmd_buffer
->state
.pending_pipe_bits
|=
5501 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5502 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
5504 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
5505 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
5506 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
5508 if (dst_att
== VK_ATTACHMENT_UNUSED
)
5511 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5512 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5514 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5515 /* From the Vulkan 1.0 spec:
5517 * If the first use of an attachment in a render pass is as a
5518 * resolve attachment, then the loadOp is effectively ignored
5519 * as the resolve is guaranteed to overwrite all pixels in the
5522 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5525 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5526 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5528 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5530 enum isl_aux_usage src_aux_usage
=
5531 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
5532 enum isl_aux_usage dst_aux_usage
=
5533 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
5535 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
5536 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
5538 anv_image_msaa_resolve(cmd_buffer
,
5539 src_iview
->image
, src_aux_usage
,
5540 src_iview
->planes
[0].isl
.base_level
,
5541 src_iview
->planes
[0].isl
.base_array_layer
,
5542 dst_iview
->image
, dst_aux_usage
,
5543 dst_iview
->planes
[0].isl
.base_level
,
5544 dst_iview
->planes
[0].isl
.base_array_layer
,
5545 VK_IMAGE_ASPECT_COLOR_BIT
,
5546 render_area
.offset
.x
, render_area
.offset
.y
,
5547 render_area
.offset
.x
, render_area
.offset
.y
,
5548 render_area
.extent
.width
,
5549 render_area
.extent
.height
,
5550 fb
->layers
, BLORP_FILTER_NONE
);
5554 if (subpass
->ds_resolve_attachment
) {
5555 /* We are about to do some MSAA resolves. We need to flush so that the
5556 * result of writes to the MSAA depth attachments show up in the sampler
5557 * when we blit to the single-sampled resolve target.
5559 cmd_buffer
->state
.pending_pipe_bits
|=
5560 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5561 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
5563 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
5564 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
5566 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5567 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5569 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5570 /* From the Vulkan 1.0 spec:
5572 * If the first use of an attachment in a render pass is as a
5573 * resolve attachment, then the loadOp is effectively ignored
5574 * as the resolve is guaranteed to overwrite all pixels in the
5577 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5580 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5581 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5583 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5585 struct anv_attachment_state
*src_state
=
5586 &cmd_state
->attachments
[src_att
];
5587 struct anv_attachment_state
*dst_state
=
5588 &cmd_state
->attachments
[dst_att
];
5590 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
5591 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5593 /* MSAA resolves sample from the source attachment. Transition the
5594 * depth attachment first to get rid of any HiZ that we may not be
5597 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
5598 src_iview
->planes
[0].isl
.base_array_layer
,
5600 src_state
->current_layout
,
5601 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5602 src_state
->aux_usage
=
5603 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
5604 VK_IMAGE_ASPECT_DEPTH_BIT
,
5605 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
,
5606 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5607 src_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5609 /* MSAA resolves write to the resolve attachment as if it were any
5610 * other transfer op. Transition the resolve attachment accordingly.
5612 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
5614 /* If our render area is the entire size of the image, we're going to
5615 * blow it all away so we can claim the initial layout is UNDEFINED
5616 * and we'll get a HiZ ambiguate instead of a resolve.
5618 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
5619 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
5620 render_area
.extent
.width
== dst_iview
->extent
.width
&&
5621 render_area
.extent
.height
== dst_iview
->extent
.height
)
5622 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
5624 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
5625 dst_iview
->planes
[0].isl
.base_array_layer
,
5628 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5629 dst_state
->aux_usage
=
5630 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
5631 VK_IMAGE_ASPECT_DEPTH_BIT
,
5632 VK_IMAGE_USAGE_TRANSFER_DST_BIT
,
5633 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5634 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5636 enum blorp_filter filter
=
5637 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
5639 anv_image_msaa_resolve(cmd_buffer
,
5640 src_iview
->image
, src_state
->aux_usage
,
5641 src_iview
->planes
[0].isl
.base_level
,
5642 src_iview
->planes
[0].isl
.base_array_layer
,
5643 dst_iview
->image
, dst_state
->aux_usage
,
5644 dst_iview
->planes
[0].isl
.base_level
,
5645 dst_iview
->planes
[0].isl
.base_array_layer
,
5646 VK_IMAGE_ASPECT_DEPTH_BIT
,
5647 render_area
.offset
.x
, render_area
.offset
.y
,
5648 render_area
.offset
.x
, render_area
.offset
.y
,
5649 render_area
.extent
.width
,
5650 render_area
.extent
.height
,
5651 fb
->layers
, filter
);
5654 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
5655 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5657 src_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5658 dst_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5660 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
5661 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
5663 enum blorp_filter filter
=
5664 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
5666 anv_image_msaa_resolve(cmd_buffer
,
5667 src_iview
->image
, src_aux_usage
,
5668 src_iview
->planes
[0].isl
.base_level
,
5669 src_iview
->planes
[0].isl
.base_array_layer
,
5670 dst_iview
->image
, dst_aux_usage
,
5671 dst_iview
->planes
[0].isl
.base_level
,
5672 dst_iview
->planes
[0].isl
.base_array_layer
,
5673 VK_IMAGE_ASPECT_STENCIL_BIT
,
5674 render_area
.offset
.x
, render_area
.offset
.y
,
5675 render_area
.offset
.x
, render_area
.offset
.y
,
5676 render_area
.extent
.width
,
5677 render_area
.extent
.height
,
5678 fb
->layers
, filter
);
5683 /* On gen7, we have to store a texturable version of the stencil buffer in
5684 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
5685 * forth at strategic points. Stencil writes are only allowed in following
5688 * - VK_IMAGE_LAYOUT_GENERAL
5689 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
5690 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
5691 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
5692 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
5694 * For general, we have no nice opportunity to transition so we do the copy
5695 * to the shadow unconditionally at the end of the subpass. For transfer
5696 * destinations, we can update it as part of the transfer op. For the other
5697 * layouts, we delay the copy until a transition into some other layout.
5699 if (subpass
->depth_stencil_attachment
) {
5700 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
5701 assert(a
!= VK_ATTACHMENT_UNUSED
);
5703 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5704 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
5705 const struct anv_image
*image
= iview
->image
;
5707 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5708 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
5709 VK_IMAGE_ASPECT_STENCIL_BIT
);
5711 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
5712 att_state
->current_stencil_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5713 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
5714 anv_image_copy_to_shadow(cmd_buffer
, image
,
5715 VK_IMAGE_ASPECT_STENCIL_BIT
,
5716 iview
->planes
[plane
].isl
.base_level
, 1,
5717 iview
->planes
[plane
].isl
.base_array_layer
,
5722 #endif /* GEN_GEN == 7 */
5724 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5725 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5726 if (a
== VK_ATTACHMENT_UNUSED
)
5729 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
5732 assert(a
< cmd_state
->pass
->attachment_count
);
5733 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5734 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5735 const struct anv_image
*image
= iview
->image
;
5737 /* Transition the image into the final layout for this render pass */
5738 VkImageLayout target_layout
=
5739 cmd_state
->pass
->attachments
[a
].final_layout
;
5740 VkImageLayout target_stencil_layout
=
5741 cmd_state
->pass
->attachments
[a
].stencil_final_layout
;
5743 uint32_t base_layer
, layer_count
;
5744 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5746 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5747 iview
->planes
[0].isl
.base_level
);
5749 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5750 layer_count
= fb
->layers
;
5753 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5754 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5755 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5756 iview
->planes
[0].isl
.base_level
, 1,
5757 base_layer
, layer_count
,
5758 att_state
->current_layout
, target_layout
);
5761 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5762 transition_depth_buffer(cmd_buffer
, image
,
5763 base_layer
, layer_count
,
5764 att_state
->current_layout
, target_layout
);
5767 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5768 transition_stencil_buffer(cmd_buffer
, image
,
5769 iview
->planes
[0].isl
.base_level
, 1,
5770 base_layer
, layer_count
,
5771 att_state
->current_stencil_layout
,
5772 target_stencil_layout
);
5776 /* Accumulate any subpass flushes that need to happen after the subpass.
5777 * Yes, they do get accumulated twice in the NextSubpass case but since
5778 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
5779 * ORing the bits in twice so it's harmless.
5781 cmd_buffer
->state
.pending_pipe_bits
|=
5782 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
5785 void genX(CmdBeginRenderPass
)(
5786 VkCommandBuffer commandBuffer
,
5787 const VkRenderPassBeginInfo
* pRenderPassBegin
,
5788 VkSubpassContents contents
)
5790 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5791 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
5792 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
5795 cmd_buffer
->state
.framebuffer
= framebuffer
;
5796 cmd_buffer
->state
.pass
= pass
;
5797 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
5799 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
,
5802 if (result
!= VK_SUCCESS
) {
5803 assert(anv_batch_has_error(&cmd_buffer
->batch
));
5807 genX(flush_pipeline_select_3d
)(cmd_buffer
);
5809 cmd_buffer_begin_subpass(cmd_buffer
, 0);
5812 void genX(CmdBeginRenderPass2
)(
5813 VkCommandBuffer commandBuffer
,
5814 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
5815 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
5817 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
5818 pSubpassBeginInfo
->contents
);
5821 void genX(CmdNextSubpass
)(
5822 VkCommandBuffer commandBuffer
,
5823 VkSubpassContents contents
)
5825 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5827 if (anv_batch_has_error(&cmd_buffer
->batch
))
5830 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
5832 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
5833 cmd_buffer_end_subpass(cmd_buffer
);
5834 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
5837 void genX(CmdNextSubpass2
)(
5838 VkCommandBuffer commandBuffer
,
5839 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
5840 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5842 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
5845 void genX(CmdEndRenderPass
)(
5846 VkCommandBuffer commandBuffer
)
5848 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5850 if (anv_batch_has_error(&cmd_buffer
->batch
))
5853 cmd_buffer_end_subpass(cmd_buffer
);
5855 cmd_buffer
->state
.hiz_enabled
= false;
5858 anv_dump_add_attachments(cmd_buffer
);
5861 /* Remove references to render pass specific state. This enables us to
5862 * detect whether or not we're in a renderpass.
5864 cmd_buffer
->state
.framebuffer
= NULL
;
5865 cmd_buffer
->state
.pass
= NULL
;
5866 cmd_buffer
->state
.subpass
= NULL
;
5869 void genX(CmdEndRenderPass2
)(
5870 VkCommandBuffer commandBuffer
,
5871 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5873 genX(CmdEndRenderPass
)(commandBuffer
);
5877 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5879 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5880 struct gen_mi_builder b
;
5881 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5883 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5884 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5885 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5887 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5888 mip
.LoadOperation
= LOAD_LOADINV
;
5889 mip
.CombineOperation
= COMBINE_SET
;
5890 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5895 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5896 void genX(CmdBeginConditionalRenderingEXT
)(
5897 VkCommandBuffer commandBuffer
,
5898 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5900 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5901 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5902 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5903 struct anv_address value_address
=
5904 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5906 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5907 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5909 cmd_state
->conditional_render_enabled
= true;
5911 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5913 struct gen_mi_builder b
;
5914 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5916 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5918 * If the value of the predicate in buffer memory changes
5919 * while conditional rendering is active, the rendering commands
5920 * may be discarded in an implementation-dependent way.
5921 * Some implementations may latch the value of the predicate
5922 * upon beginning conditional rendering while others
5923 * may read it before every rendering command.
5925 * So it's perfectly fine to read a value from the buffer once.
5927 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5929 /* Precompute predicate result, it is necessary to support secondary
5930 * command buffers since it is unknown if conditional rendering is
5931 * inverted when populating them.
5933 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5934 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5935 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5938 void genX(CmdEndConditionalRenderingEXT
)(
5939 VkCommandBuffer commandBuffer
)
5941 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5942 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5944 cmd_state
->conditional_render_enabled
= false;
5948 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5949 * command streamer for later execution.
5951 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5952 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5953 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5954 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5955 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5956 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5957 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5958 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5959 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5960 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5961 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5962 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5963 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5964 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5965 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5967 void genX(CmdSetEvent
)(
5968 VkCommandBuffer commandBuffer
,
5970 VkPipelineStageFlags stageMask
)
5972 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5973 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5975 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5976 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5978 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5979 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5980 pc
.StallAtPixelScoreboard
= true;
5981 pc
.CommandStreamerStallEnable
= true;
5984 pc
.DestinationAddressType
= DAT_PPGTT
,
5985 pc
.PostSyncOperation
= WriteImmediateData
,
5986 pc
.Address
= (struct anv_address
) {
5987 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5990 pc
.ImmediateData
= VK_EVENT_SET
;
5994 void genX(CmdResetEvent
)(
5995 VkCommandBuffer commandBuffer
,
5997 VkPipelineStageFlags stageMask
)
5999 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6000 ANV_FROM_HANDLE(anv_event
, event
, _event
);
6002 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
6003 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
6005 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
6006 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
6007 pc
.StallAtPixelScoreboard
= true;
6008 pc
.CommandStreamerStallEnable
= true;
6011 pc
.DestinationAddressType
= DAT_PPGTT
;
6012 pc
.PostSyncOperation
= WriteImmediateData
;
6013 pc
.Address
= (struct anv_address
) {
6014 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
6017 pc
.ImmediateData
= VK_EVENT_RESET
;
6021 void genX(CmdWaitEvents
)(
6022 VkCommandBuffer commandBuffer
,
6023 uint32_t eventCount
,
6024 const VkEvent
* pEvents
,
6025 VkPipelineStageFlags srcStageMask
,
6026 VkPipelineStageFlags destStageMask
,
6027 uint32_t memoryBarrierCount
,
6028 const VkMemoryBarrier
* pMemoryBarriers
,
6029 uint32_t bufferMemoryBarrierCount
,
6030 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
6031 uint32_t imageMemoryBarrierCount
,
6032 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
6035 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6037 for (uint32_t i
= 0; i
< eventCount
; i
++) {
6038 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
6040 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
6041 sem
.WaitMode
= PollingMode
,
6042 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
6043 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
6044 sem
.SemaphoreAddress
= (struct anv_address
) {
6045 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
6051 anv_finishme("Implement events on gen7");
6054 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
6055 false, /* byRegion */
6056 memoryBarrierCount
, pMemoryBarriers
,
6057 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
6058 imageMemoryBarrierCount
, pImageMemoryBarriers
);
6061 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
6062 VkCommandBuffer commandBuffer
,
6063 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
6065 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6067 switch (pOverrideInfo
->type
) {
6068 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
6072 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
6073 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
6074 .MediaInstructionDisable
= pOverrideInfo
->enable
,
6075 ._3DRenderingInstructionDisableMask
= true,
6076 .MediaInstructionDisableMask
= true);
6077 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
6079 anv_pack_struct(&dw
, GENX(INSTPM
),
6080 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
6081 .MediaInstructionDisable
= pOverrideInfo
->enable
,
6082 ._3DRenderingInstructionDisableMask
= true,
6083 .MediaInstructionDisableMask
= true);
6084 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
6089 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
6090 if (pOverrideInfo
->enable
) {
6091 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
6092 cmd_buffer
->state
.pending_pipe_bits
|=
6093 ANV_PIPE_FLUSH_BITS
|
6094 ANV_PIPE_INVALIDATE_BITS
;
6095 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
6100 unreachable("Invalid override");
6106 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
6107 VkCommandBuffer commandBuffer
,
6108 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
6110 /* TODO: Waiting on the register to write, might depend on generation. */