anv: move push constant allocation tracking into gfx pipeline state
[mesa.git] / src / intel / vulkan / genX_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26
27 #include "anv_private.h"
28 #include "vk_format_info.h"
29 #include "vk_util.h"
30 #include "util/fast_idiv_by_const.h"
31
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
36
37 /* We reserve :
38 * - GPR 14 for secondary command buffer returns
39 * - GPR 15 for conditional rendering
40 */
41 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
42 #define __gen_get_batch_dwords anv_batch_emit_dwords
43 #define __gen_address_offset anv_address_add
44 #include "common/gen_mi_builder.h"
45
46 static void genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
47 uint32_t pipeline);
48
49 static void
50 emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
51 {
52 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
53 lri.RegisterOffset = reg;
54 lri.DataDWord = imm;
55 }
56 }
57
58 void
59 genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
60 {
61 struct anv_device *device = cmd_buffer->device;
62 UNUSED const struct gen_device_info *devinfo = &device->info;
63 uint32_t mocs = device->isl_dev.mocs.internal;
64
65 /* If we are emitting a new state base address we probably need to re-emit
66 * binding tables.
67 */
68 cmd_buffer->state.descriptors_dirty |= ~0;
69
70 /* Emit a render target cache flush.
71 *
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
76 */
77 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
78 pc.DCFlushEnable = true;
79 pc.RenderTargetCacheFlushEnable = true;
80 pc.CommandStreamerStallEnable = true;
81 #if GEN_GEN >= 12
82 pc.TileCacheFlushEnable = true;
83 #endif
84 #if GEN_GEN == 12
85 /* GEN:BUG:1606662791:
86 *
87 * Software must program PIPE_CONTROL command with "HDC Pipeline
88 * Flush" prior to programming of the below two non-pipeline state :
89 * * STATE_BASE_ADDRESS
90 * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
91 */
92 if (devinfo->revision == 0 /* A0 */)
93 pc.HDCPipelineFlushEnable = true;
94 #endif
95 }
96
97 #if GEN_GEN == 12
98 /* GEN:BUG:1607854226:
99 *
100 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
101 * mode by putting the pipeline temporarily in 3D mode.
102 */
103 uint32_t gen12_wa_pipeline = cmd_buffer->state.current_pipeline;
104 genX(flush_pipeline_select_3d)(cmd_buffer);
105 #endif
106
107 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
108 sba.GeneralStateBaseAddress = (struct anv_address) { NULL, 0 };
109 sba.GeneralStateMOCS = mocs;
110 sba.GeneralStateBaseAddressModifyEnable = true;
111
112 sba.StatelessDataPortAccessMOCS = mocs;
113
114 sba.SurfaceStateBaseAddress =
115 anv_cmd_buffer_surface_base_address(cmd_buffer);
116 sba.SurfaceStateMOCS = mocs;
117 sba.SurfaceStateBaseAddressModifyEnable = true;
118
119 sba.DynamicStateBaseAddress =
120 (struct anv_address) { device->dynamic_state_pool.block_pool.bo, 0 };
121 sba.DynamicStateMOCS = mocs;
122 sba.DynamicStateBaseAddressModifyEnable = true;
123
124 sba.IndirectObjectBaseAddress = (struct anv_address) { NULL, 0 };
125 sba.IndirectObjectMOCS = mocs;
126 sba.IndirectObjectBaseAddressModifyEnable = true;
127
128 sba.InstructionBaseAddress =
129 (struct anv_address) { device->instruction_state_pool.block_pool.bo, 0 };
130 sba.InstructionMOCS = mocs;
131 sba.InstructionBaseAddressModifyEnable = true;
132
133 # if (GEN_GEN >= 8)
134 /* Broadwell requires that we specify a buffer size for a bunch of
135 * these fields. However, since we will be growing the BO's live, we
136 * just set them all to the maximum.
137 */
138 sba.GeneralStateBufferSize = 0xfffff;
139 sba.IndirectObjectBufferSize = 0xfffff;
140 if (device->physical->use_softpin) {
141 /* With softpin, we use fixed addresses so we actually know how big
142 * our base addresses are.
143 */
144 sba.DynamicStateBufferSize = DYNAMIC_STATE_POOL_SIZE / 4096;
145 sba.InstructionBufferSize = INSTRUCTION_STATE_POOL_SIZE / 4096;
146 } else {
147 sba.DynamicStateBufferSize = 0xfffff;
148 sba.InstructionBufferSize = 0xfffff;
149 }
150 sba.GeneralStateBufferSizeModifyEnable = true;
151 sba.IndirectObjectBufferSizeModifyEnable = true;
152 sba.DynamicStateBufferSizeModifyEnable = true;
153 sba.InstructionBuffersizeModifyEnable = true;
154 # else
155 /* On gen7, we have upper bounds instead. According to the docs,
156 * setting an upper bound of zero means that no bounds checking is
157 * performed so, in theory, we should be able to leave them zero.
158 * However, border color is broken and the GPU bounds-checks anyway.
159 * To avoid this and other potential problems, we may as well set it
160 * for everything.
161 */
162 sba.GeneralStateAccessUpperBound =
163 (struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
164 sba.GeneralStateAccessUpperBoundModifyEnable = true;
165 sba.DynamicStateAccessUpperBound =
166 (struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
167 sba.DynamicStateAccessUpperBoundModifyEnable = true;
168 sba.InstructionAccessUpperBound =
169 (struct anv_address) { .bo = NULL, .offset = 0xfffff000 };
170 sba.InstructionAccessUpperBoundModifyEnable = true;
171 # endif
172 # if (GEN_GEN >= 9)
173 if (cmd_buffer->device->physical->use_softpin) {
174 sba.BindlessSurfaceStateBaseAddress = (struct anv_address) {
175 .bo = device->surface_state_pool.block_pool.bo,
176 .offset = 0,
177 };
178 sba.BindlessSurfaceStateSize = (1 << 20) - 1;
179 } else {
180 sba.BindlessSurfaceStateBaseAddress = ANV_NULL_ADDRESS;
181 sba.BindlessSurfaceStateSize = 0;
182 }
183 sba.BindlessSurfaceStateMOCS = mocs;
184 sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
185 # endif
186 # if (GEN_GEN >= 10)
187 sba.BindlessSamplerStateBaseAddress = (struct anv_address) { NULL, 0 };
188 sba.BindlessSamplerStateMOCS = mocs;
189 sba.BindlessSamplerStateBaseAddressModifyEnable = true;
190 sba.BindlessSamplerStateBufferSize = 0;
191 # endif
192 }
193
194 #if GEN_GEN == 12
195 /* GEN:BUG:1607854226:
196 *
197 * Put the pipeline back into its current mode.
198 */
199 if (gen12_wa_pipeline != UINT32_MAX)
200 genX(flush_pipeline_select)(cmd_buffer, gen12_wa_pipeline);
201 #endif
202
203 /* After re-setting the surface state base address, we have to do some
204 * cache flusing so that the sampler engine will pick up the new
205 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
206 * Shared Function > 3D Sampler > State > State Caching (page 96):
207 *
208 * Coherency with system memory in the state cache, like the texture
209 * cache is handled partially by software. It is expected that the
210 * command stream or shader will issue Cache Flush operation or
211 * Cache_Flush sampler message to ensure that the L1 cache remains
212 * coherent with system memory.
213 *
214 * [...]
215 *
216 * Whenever the value of the Dynamic_State_Base_Addr,
217 * Surface_State_Base_Addr are altered, the L1 state cache must be
218 * invalidated to ensure the new surface or sampler state is fetched
219 * from system memory.
220 *
221 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
222 * which, according the PIPE_CONTROL instruction documentation in the
223 * Broadwell PRM:
224 *
225 * Setting this bit is independent of any other bit in this packet.
226 * This bit controls the invalidation of the L1 and L2 state caches
227 * at the top of the pipe i.e. at the parsing time.
228 *
229 * Unfortunately, experimentation seems to indicate that state cache
230 * invalidation through a PIPE_CONTROL does nothing whatsoever in
231 * regards to surface state and binding tables. In stead, it seems that
232 * invalidating the texture cache is what is actually needed.
233 *
234 * XXX: As far as we have been able to determine through
235 * experimentation, shows that flush the texture cache appears to be
236 * sufficient. The theory here is that all of the sampling/rendering
237 * units cache the binding table in the texture cache. However, we have
238 * yet to be able to actually confirm this.
239 */
240 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
241 pc.TextureCacheInvalidationEnable = true;
242 pc.ConstantCacheInvalidationEnable = true;
243 pc.StateCacheInvalidationEnable = true;
244 }
245 }
246
247 static void
248 add_surface_reloc(struct anv_cmd_buffer *cmd_buffer,
249 struct anv_state state, struct anv_address addr)
250 {
251 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
252
253 VkResult result =
254 anv_reloc_list_add(&cmd_buffer->surface_relocs, &cmd_buffer->pool->alloc,
255 state.offset + isl_dev->ss.addr_offset,
256 addr.bo, addr.offset, NULL);
257 if (result != VK_SUCCESS)
258 anv_batch_set_error(&cmd_buffer->batch, result);
259 }
260
261 static void
262 add_surface_state_relocs(struct anv_cmd_buffer *cmd_buffer,
263 struct anv_surface_state state)
264 {
265 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
266
267 assert(!anv_address_is_null(state.address));
268 add_surface_reloc(cmd_buffer, state.state, state.address);
269
270 if (!anv_address_is_null(state.aux_address)) {
271 VkResult result =
272 anv_reloc_list_add(&cmd_buffer->surface_relocs,
273 &cmd_buffer->pool->alloc,
274 state.state.offset + isl_dev->ss.aux_addr_offset,
275 state.aux_address.bo,
276 state.aux_address.offset,
277 NULL);
278 if (result != VK_SUCCESS)
279 anv_batch_set_error(&cmd_buffer->batch, result);
280 }
281
282 if (!anv_address_is_null(state.clear_address)) {
283 VkResult result =
284 anv_reloc_list_add(&cmd_buffer->surface_relocs,
285 &cmd_buffer->pool->alloc,
286 state.state.offset +
287 isl_dev->ss.clear_color_state_offset,
288 state.clear_address.bo,
289 state.clear_address.offset,
290 NULL);
291 if (result != VK_SUCCESS)
292 anv_batch_set_error(&cmd_buffer->batch, result);
293 }
294 }
295
296 static bool
297 isl_color_value_requires_conversion(union isl_color_value color,
298 const struct isl_surf *surf,
299 const struct isl_view *view)
300 {
301 if (surf->format == view->format && isl_swizzle_is_identity(view->swizzle))
302 return false;
303
304 uint32_t surf_pack[4] = { 0, 0, 0, 0 };
305 isl_color_value_pack(&color, surf->format, surf_pack);
306
307 uint32_t view_pack[4] = { 0, 0, 0, 0 };
308 union isl_color_value swiz_color =
309 isl_color_value_swizzle_inv(color, view->swizzle);
310 isl_color_value_pack(&swiz_color, view->format, view_pack);
311
312 return memcmp(surf_pack, view_pack, sizeof(surf_pack)) != 0;
313 }
314
315 static bool
316 anv_can_fast_clear_color_view(struct anv_device * device,
317 struct anv_image_view *iview,
318 VkImageLayout layout,
319 union isl_color_value clear_color,
320 uint32_t num_layers,
321 VkRect2D render_area)
322 {
323 if (iview->planes[0].isl.base_array_layer >=
324 anv_image_aux_layers(iview->image, VK_IMAGE_ASPECT_COLOR_BIT,
325 iview->planes[0].isl.base_level))
326 return false;
327
328 /* Start by getting the fast clear type. We use the first subpass
329 * layout here because we don't want to fast-clear if the first subpass
330 * to use the attachment can't handle fast-clears.
331 */
332 enum anv_fast_clear_type fast_clear_type =
333 anv_layout_to_fast_clear_type(&device->info, iview->image,
334 VK_IMAGE_ASPECT_COLOR_BIT,
335 layout);
336 switch (fast_clear_type) {
337 case ANV_FAST_CLEAR_NONE:
338 return false;
339 case ANV_FAST_CLEAR_DEFAULT_VALUE:
340 if (!isl_color_value_is_zero(clear_color, iview->planes[0].isl.format))
341 return false;
342 break;
343 case ANV_FAST_CLEAR_ANY:
344 break;
345 }
346
347 /* Potentially, we could do partial fast-clears but doing so has crazy
348 * alignment restrictions. It's easier to just restrict to full size
349 * fast clears for now.
350 */
351 if (render_area.offset.x != 0 ||
352 render_area.offset.y != 0 ||
353 render_area.extent.width != iview->extent.width ||
354 render_area.extent.height != iview->extent.height)
355 return false;
356
357 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
358 if (GEN_GEN <= 8 &&
359 !isl_color_value_is_zero_one(clear_color, iview->planes[0].isl.format))
360 return false;
361
362 /* If the clear color is one that would require non-trivial format
363 * conversion on resolve, we don't bother with the fast clear. This
364 * shouldn't be common as most clear colors are 0/1 and the most common
365 * format re-interpretation is for sRGB.
366 */
367 if (isl_color_value_requires_conversion(clear_color,
368 &iview->image->planes[0].surface.isl,
369 &iview->planes[0].isl)) {
370 anv_perf_warn(device, iview,
371 "Cannot fast-clear to colors which would require "
372 "format conversion on resolve");
373 return false;
374 }
375
376 /* We only allow fast clears to the first slice of an image (level 0,
377 * layer 0) and only for the entire slice. This guarantees us that, at
378 * any given time, there is only one clear color on any given image at
379 * any given time. At the time of our testing (Jan 17, 2018), there
380 * were no known applications which would benefit from fast-clearing
381 * more than just the first slice.
382 */
383 if (iview->planes[0].isl.base_level > 0 ||
384 iview->planes[0].isl.base_array_layer > 0) {
385 anv_perf_warn(device, iview->image,
386 "Rendering with multi-lod or multi-layer framebuffer "
387 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
388 "baseArrayLayer > 0. Not fast clearing.");
389 return false;
390 }
391
392 if (num_layers > 1) {
393 anv_perf_warn(device, iview->image,
394 "Rendering to a multi-layer framebuffer with "
395 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
396 }
397
398 return true;
399 }
400
401 static bool
402 anv_can_hiz_clear_ds_view(struct anv_device *device,
403 struct anv_image_view *iview,
404 VkImageLayout layout,
405 VkImageAspectFlags clear_aspects,
406 float depth_clear_value,
407 VkRect2D render_area)
408 {
409 /* We don't do any HiZ or depth fast-clears on gen7 yet */
410 if (GEN_GEN == 7)
411 return false;
412
413 /* If we're just clearing stencil, we can always HiZ clear */
414 if (!(clear_aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
415 return true;
416
417 /* We must have depth in order to have HiZ */
418 if (!(iview->image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
419 return false;
420
421 const enum isl_aux_usage clear_aux_usage =
422 anv_layout_to_aux_usage(&device->info, iview->image,
423 VK_IMAGE_ASPECT_DEPTH_BIT,
424 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT,
425 layout);
426 if (!blorp_can_hiz_clear_depth(&device->info,
427 &iview->image->planes[0].surface.isl,
428 clear_aux_usage,
429 iview->planes[0].isl.base_level,
430 iview->planes[0].isl.base_array_layer,
431 render_area.offset.x,
432 render_area.offset.y,
433 render_area.offset.x +
434 render_area.extent.width,
435 render_area.offset.y +
436 render_area.extent.height))
437 return false;
438
439 if (depth_clear_value != ANV_HZ_FC_VAL)
440 return false;
441
442 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a fast-cleared
443 * portion of a HiZ buffer. Testing has revealed that Gen8 only supports
444 * returning 0.0f. Gens prior to gen8 do not support this feature at all.
445 */
446 if (GEN_GEN == 8 && anv_can_sample_with_hiz(&device->info, iview->image))
447 return false;
448
449 /* If we got here, then we can fast clear */
450 return true;
451 }
452
453 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
454
455 #if GEN_GEN == 12
456 static void
457 anv_image_init_aux_tt(struct anv_cmd_buffer *cmd_buffer,
458 const struct anv_image *image,
459 VkImageAspectFlagBits aspect,
460 uint32_t base_level, uint32_t level_count,
461 uint32_t base_layer, uint32_t layer_count)
462 {
463 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
464
465 uint64_t base_address =
466 anv_address_physical(image->planes[plane].address);
467
468 const struct isl_surf *isl_surf = &image->planes[plane].surface.isl;
469 uint64_t format_bits = gen_aux_map_format_bits_for_isl_surf(isl_surf);
470
471 /* We're about to live-update the AUX-TT. We really don't want anyone else
472 * trying to read it while we're doing this. We could probably get away
473 * with not having this stall in some cases if we were really careful but
474 * it's better to play it safe. Full stall the GPU.
475 */
476 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_END_OF_PIPE_SYNC_BIT;
477 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
478
479 struct gen_mi_builder b;
480 gen_mi_builder_init(&b, &cmd_buffer->batch);
481
482 for (uint32_t a = 0; a < layer_count; a++) {
483 const uint32_t layer = base_layer + a;
484
485 uint64_t start_offset_B = UINT64_MAX, end_offset_B = 0;
486 for (uint32_t l = 0; l < level_count; l++) {
487 const uint32_t level = base_level + l;
488
489 uint32_t logical_array_layer, logical_z_offset_px;
490 if (image->type == VK_IMAGE_TYPE_3D) {
491 logical_array_layer = 0;
492
493 /* If the given miplevel does not have this layer, then any higher
494 * miplevels won't either because miplevels only get smaller the
495 * higher the LOD.
496 */
497 assert(layer < image->extent.depth);
498 if (layer >= anv_minify(image->extent.depth, level))
499 break;
500 logical_z_offset_px = layer;
501 } else {
502 assert(layer < image->array_size);
503 logical_array_layer = layer;
504 logical_z_offset_px = 0;
505 }
506
507 uint32_t slice_start_offset_B, slice_end_offset_B;
508 isl_surf_get_image_range_B_tile(isl_surf, level,
509 logical_array_layer,
510 logical_z_offset_px,
511 &slice_start_offset_B,
512 &slice_end_offset_B);
513
514 start_offset_B = MIN2(start_offset_B, slice_start_offset_B);
515 end_offset_B = MAX2(end_offset_B, slice_end_offset_B);
516 }
517
518 /* Aux operates 64K at a time */
519 start_offset_B = align_down_u64(start_offset_B, 64 * 1024);
520 end_offset_B = align_u64(end_offset_B, 64 * 1024);
521
522 for (uint64_t offset = start_offset_B;
523 offset < end_offset_B; offset += 64 * 1024) {
524 uint64_t address = base_address + offset;
525
526 uint64_t aux_entry_addr64, *aux_entry_map;
527 aux_entry_map = gen_aux_map_get_entry(cmd_buffer->device->aux_map_ctx,
528 address, &aux_entry_addr64);
529
530 assert(cmd_buffer->device->physical->use_softpin);
531 struct anv_address aux_entry_address = {
532 .bo = NULL,
533 .offset = aux_entry_addr64,
534 };
535
536 const uint64_t old_aux_entry = READ_ONCE(*aux_entry_map);
537 uint64_t new_aux_entry =
538 (old_aux_entry & GEN_AUX_MAP_ADDRESS_MASK) | format_bits;
539
540 if (isl_aux_usage_has_ccs(image->planes[plane].aux_usage))
541 new_aux_entry |= GEN_AUX_MAP_ENTRY_VALID_BIT;
542
543 gen_mi_store(&b, gen_mi_mem64(aux_entry_address),
544 gen_mi_imm(new_aux_entry));
545 }
546 }
547
548 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT;
549 }
550 #endif /* GEN_GEN == 12 */
551
552 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
553 * the initial layout is undefined, the HiZ buffer and depth buffer will
554 * represent the same data at the end of this operation.
555 */
556 static void
557 transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
558 const struct anv_image *image,
559 uint32_t base_layer, uint32_t layer_count,
560 VkImageLayout initial_layout,
561 VkImageLayout final_layout)
562 {
563 uint32_t depth_plane =
564 anv_image_aspect_to_plane(image->aspects, VK_IMAGE_ASPECT_DEPTH_BIT);
565 if (image->planes[depth_plane].aux_usage == ISL_AUX_USAGE_NONE)
566 return;
567
568 #if GEN_GEN == 12
569 if ((initial_layout == VK_IMAGE_LAYOUT_UNDEFINED ||
570 initial_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) &&
571 cmd_buffer->device->physical->has_implicit_ccs &&
572 cmd_buffer->device->info.has_aux_map) {
573 anv_image_init_aux_tt(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
574 0, 1, 0, 1);
575 }
576 #endif
577
578 const enum isl_aux_state initial_state =
579 anv_layout_to_aux_state(&cmd_buffer->device->info, image,
580 VK_IMAGE_ASPECT_DEPTH_BIT,
581 initial_layout);
582 const enum isl_aux_state final_state =
583 anv_layout_to_aux_state(&cmd_buffer->device->info, image,
584 VK_IMAGE_ASPECT_DEPTH_BIT,
585 final_layout);
586
587 const bool initial_depth_valid =
588 isl_aux_state_has_valid_primary(initial_state);
589 const bool initial_hiz_valid =
590 isl_aux_state_has_valid_aux(initial_state);
591 const bool final_needs_depth =
592 isl_aux_state_has_valid_primary(final_state);
593 const bool final_needs_hiz =
594 isl_aux_state_has_valid_aux(final_state);
595
596 /* Getting into the pass-through state for Depth is tricky and involves
597 * both a resolve and an ambiguate. We don't handle that state right now
598 * as anv_layout_to_aux_state never returns it.
599 */
600 assert(final_state != ISL_AUX_STATE_PASS_THROUGH);
601
602 if (final_needs_depth && !initial_depth_valid) {
603 assert(initial_hiz_valid);
604 anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
605 0, base_layer, layer_count, ISL_AUX_OP_FULL_RESOLVE);
606 } else if (final_needs_hiz && !initial_hiz_valid) {
607 assert(initial_depth_valid);
608 anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
609 0, base_layer, layer_count, ISL_AUX_OP_AMBIGUATE);
610 }
611 }
612
613 static inline bool
614 vk_image_layout_stencil_write_optimal(VkImageLayout layout)
615 {
616 return layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
617 layout == VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL ||
618 layout == VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR;
619 }
620
621 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
622 * the initial layout is undefined, the HiZ buffer and depth buffer will
623 * represent the same data at the end of this operation.
624 */
625 static void
626 transition_stencil_buffer(struct anv_cmd_buffer *cmd_buffer,
627 const struct anv_image *image,
628 uint32_t base_level, uint32_t level_count,
629 uint32_t base_layer, uint32_t layer_count,
630 VkImageLayout initial_layout,
631 VkImageLayout final_layout)
632 {
633 #if GEN_GEN == 7
634 uint32_t plane = anv_image_aspect_to_plane(image->aspects,
635 VK_IMAGE_ASPECT_STENCIL_BIT);
636
637 /* On gen7, we have to store a texturable version of the stencil buffer in
638 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
639 * forth at strategic points. Stencil writes are only allowed in following
640 * layouts:
641 *
642 * - VK_IMAGE_LAYOUT_GENERAL
643 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
644 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
645 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
646 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
647 *
648 * For general, we have no nice opportunity to transition so we do the copy
649 * to the shadow unconditionally at the end of the subpass. For transfer
650 * destinations, we can update it as part of the transfer op. For the other
651 * layouts, we delay the copy until a transition into some other layout.
652 */
653 if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
654 vk_image_layout_stencil_write_optimal(initial_layout) &&
655 !vk_image_layout_stencil_write_optimal(final_layout)) {
656 anv_image_copy_to_shadow(cmd_buffer, image,
657 VK_IMAGE_ASPECT_STENCIL_BIT,
658 base_level, level_count,
659 base_layer, layer_count);
660 }
661 #endif /* GEN_GEN == 7 */
662 }
663
664 #define MI_PREDICATE_SRC0 0x2400
665 #define MI_PREDICATE_SRC1 0x2408
666 #define MI_PREDICATE_RESULT 0x2418
667
668 static void
669 set_image_compressed_bit(struct anv_cmd_buffer *cmd_buffer,
670 const struct anv_image *image,
671 VkImageAspectFlagBits aspect,
672 uint32_t level,
673 uint32_t base_layer, uint32_t layer_count,
674 bool compressed)
675 {
676 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
677
678 /* We only have compression tracking for CCS_E */
679 if (image->planes[plane].aux_usage != ISL_AUX_USAGE_CCS_E)
680 return;
681
682 for (uint32_t a = 0; a < layer_count; a++) {
683 uint32_t layer = base_layer + a;
684 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
685 sdi.Address = anv_image_get_compression_state_addr(cmd_buffer->device,
686 image, aspect,
687 level, layer);
688 sdi.ImmediateData = compressed ? UINT32_MAX : 0;
689 }
690 }
691 }
692
693 static void
694 set_image_fast_clear_state(struct anv_cmd_buffer *cmd_buffer,
695 const struct anv_image *image,
696 VkImageAspectFlagBits aspect,
697 enum anv_fast_clear_type fast_clear)
698 {
699 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
700 sdi.Address = anv_image_get_fast_clear_type_addr(cmd_buffer->device,
701 image, aspect);
702 sdi.ImmediateData = fast_clear;
703 }
704
705 /* Whenever we have fast-clear, we consider that slice to be compressed.
706 * This makes building predicates much easier.
707 */
708 if (fast_clear != ANV_FAST_CLEAR_NONE)
709 set_image_compressed_bit(cmd_buffer, image, aspect, 0, 0, 1, true);
710 }
711
712 /* This is only really practical on haswell and above because it requires
713 * MI math in order to get it correct.
714 */
715 #if GEN_GEN >= 8 || GEN_IS_HASWELL
716 static void
717 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
718 const struct anv_image *image,
719 VkImageAspectFlagBits aspect,
720 uint32_t level, uint32_t array_layer,
721 enum isl_aux_op resolve_op,
722 enum anv_fast_clear_type fast_clear_supported)
723 {
724 struct gen_mi_builder b;
725 gen_mi_builder_init(&b, &cmd_buffer->batch);
726
727 const struct gen_mi_value fast_clear_type =
728 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer->device,
729 image, aspect));
730
731 if (resolve_op == ISL_AUX_OP_FULL_RESOLVE) {
732 /* In this case, we're doing a full resolve which means we want the
733 * resolve to happen if any compression (including fast-clears) is
734 * present.
735 *
736 * In order to simplify the logic a bit, we make the assumption that,
737 * if the first slice has been fast-cleared, it is also marked as
738 * compressed. See also set_image_fast_clear_state.
739 */
740 const struct gen_mi_value compression_state =
741 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer->device,
742 image, aspect,
743 level, array_layer));
744 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
745 compression_state);
746 gen_mi_store(&b, compression_state, gen_mi_imm(0));
747
748 if (level == 0 && array_layer == 0) {
749 /* If the predicate is true, we want to write 0 to the fast clear type
750 * and, if it's false, leave it alone. We can do this by writing
751 *
752 * clear_type = clear_type & ~predicate;
753 */
754 struct gen_mi_value new_fast_clear_type =
755 gen_mi_iand(&b, fast_clear_type,
756 gen_mi_inot(&b, gen_mi_reg64(MI_PREDICATE_SRC0)));
757 gen_mi_store(&b, fast_clear_type, new_fast_clear_type);
758 }
759 } else if (level == 0 && array_layer == 0) {
760 /* In this case, we are doing a partial resolve to get rid of fast-clear
761 * colors. We don't care about the compression state but we do care
762 * about how much fast clear is allowed by the final layout.
763 */
764 assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
765 assert(fast_clear_supported < ANV_FAST_CLEAR_ANY);
766
767 /* We need to compute (fast_clear_supported < image->fast_clear) */
768 struct gen_mi_value pred =
769 gen_mi_ult(&b, gen_mi_imm(fast_clear_supported), fast_clear_type);
770 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
771 gen_mi_value_ref(&b, pred));
772
773 /* If the predicate is true, we want to write 0 to the fast clear type
774 * and, if it's false, leave it alone. We can do this by writing
775 *
776 * clear_type = clear_type & ~predicate;
777 */
778 struct gen_mi_value new_fast_clear_type =
779 gen_mi_iand(&b, fast_clear_type, gen_mi_inot(&b, pred));
780 gen_mi_store(&b, fast_clear_type, new_fast_clear_type);
781 } else {
782 /* In this case, we're trying to do a partial resolve on a slice that
783 * doesn't have clear color. There's nothing to do.
784 */
785 assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
786 return;
787 }
788
789 /* Set src1 to 0 and use a != condition */
790 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
791
792 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
793 mip.LoadOperation = LOAD_LOADINV;
794 mip.CombineOperation = COMBINE_SET;
795 mip.CompareOperation = COMPARE_SRCS_EQUAL;
796 }
797 }
798 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
799
800 #if GEN_GEN <= 8
801 static void
802 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
803 const struct anv_image *image,
804 VkImageAspectFlagBits aspect,
805 uint32_t level, uint32_t array_layer,
806 enum isl_aux_op resolve_op,
807 enum anv_fast_clear_type fast_clear_supported)
808 {
809 struct gen_mi_builder b;
810 gen_mi_builder_init(&b, &cmd_buffer->batch);
811
812 struct gen_mi_value fast_clear_type_mem =
813 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer->device,
814 image, aspect));
815
816 /* This only works for partial resolves and only when the clear color is
817 * all or nothing. On the upside, this emits less command streamer code
818 * and works on Ivybridge and Bay Trail.
819 */
820 assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
821 assert(fast_clear_supported != ANV_FAST_CLEAR_ANY);
822
823 /* We don't support fast clears on anything other than the first slice. */
824 if (level > 0 || array_layer > 0)
825 return;
826
827 /* On gen8, we don't have a concept of default clear colors because we
828 * can't sample from CCS surfaces. It's enough to just load the fast clear
829 * state into the predicate register.
830 */
831 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), fast_clear_type_mem);
832 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0));
833 gen_mi_store(&b, fast_clear_type_mem, gen_mi_imm(0));
834
835 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
836 mip.LoadOperation = LOAD_LOADINV;
837 mip.CombineOperation = COMBINE_SET;
838 mip.CompareOperation = COMPARE_SRCS_EQUAL;
839 }
840 }
841 #endif /* GEN_GEN <= 8 */
842
843 static void
844 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer *cmd_buffer,
845 const struct anv_image *image,
846 enum isl_format format,
847 struct isl_swizzle swizzle,
848 VkImageAspectFlagBits aspect,
849 uint32_t level, uint32_t array_layer,
850 enum isl_aux_op resolve_op,
851 enum anv_fast_clear_type fast_clear_supported)
852 {
853 const uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
854
855 #if GEN_GEN >= 9
856 anv_cmd_compute_resolve_predicate(cmd_buffer, image,
857 aspect, level, array_layer,
858 resolve_op, fast_clear_supported);
859 #else /* GEN_GEN <= 8 */
860 anv_cmd_simple_resolve_predicate(cmd_buffer, image,
861 aspect, level, array_layer,
862 resolve_op, fast_clear_supported);
863 #endif
864
865 /* CCS_D only supports full resolves and BLORP will assert on us if we try
866 * to do a partial resolve on a CCS_D surface.
867 */
868 if (resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE &&
869 image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_D)
870 resolve_op = ISL_AUX_OP_FULL_RESOLVE;
871
872 anv_image_ccs_op(cmd_buffer, image, format, swizzle, aspect,
873 level, array_layer, 1, resolve_op, NULL, true);
874 }
875
876 static void
877 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer *cmd_buffer,
878 const struct anv_image *image,
879 enum isl_format format,
880 struct isl_swizzle swizzle,
881 VkImageAspectFlagBits aspect,
882 uint32_t array_layer,
883 enum isl_aux_op resolve_op,
884 enum anv_fast_clear_type fast_clear_supported)
885 {
886 assert(aspect == VK_IMAGE_ASPECT_COLOR_BIT);
887 assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
888
889 #if GEN_GEN >= 8 || GEN_IS_HASWELL
890 anv_cmd_compute_resolve_predicate(cmd_buffer, image,
891 aspect, 0, array_layer,
892 resolve_op, fast_clear_supported);
893
894 anv_image_mcs_op(cmd_buffer, image, format, swizzle, aspect,
895 array_layer, 1, resolve_op, NULL, true);
896 #else
897 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
898 #endif
899 }
900
901 void
902 genX(cmd_buffer_mark_image_written)(struct anv_cmd_buffer *cmd_buffer,
903 const struct anv_image *image,
904 VkImageAspectFlagBits aspect,
905 enum isl_aux_usage aux_usage,
906 uint32_t level,
907 uint32_t base_layer,
908 uint32_t layer_count)
909 {
910 /* The aspect must be exactly one of the image aspects. */
911 assert(util_bitcount(aspect) == 1 && (aspect & image->aspects));
912
913 /* The only compression types with more than just fast-clears are MCS,
914 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
915 * track the current fast-clear and compression state. This leaves us
916 * with just MCS and CCS_E.
917 */
918 if (aux_usage != ISL_AUX_USAGE_CCS_E &&
919 aux_usage != ISL_AUX_USAGE_MCS)
920 return;
921
922 set_image_compressed_bit(cmd_buffer, image, aspect,
923 level, base_layer, layer_count, true);
924 }
925
926 static void
927 init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer,
928 const struct anv_image *image,
929 VkImageAspectFlagBits aspect)
930 {
931 assert(cmd_buffer && image);
932 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
933
934 set_image_fast_clear_state(cmd_buffer, image, aspect,
935 ANV_FAST_CLEAR_NONE);
936
937 /* Initialize the struct fields that are accessed for fast-clears so that
938 * the HW restrictions on the field values are satisfied.
939 */
940 struct anv_address addr =
941 anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
942
943 if (GEN_GEN >= 9) {
944 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
945 const unsigned num_dwords = GEN_GEN >= 10 ?
946 isl_dev->ss.clear_color_state_size / 4 :
947 isl_dev->ss.clear_value_size / 4;
948 for (unsigned i = 0; i < num_dwords; i++) {
949 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
950 sdi.Address = addr;
951 sdi.Address.offset += i * 4;
952 sdi.ImmediateData = 0;
953 }
954 }
955 } else {
956 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
957 sdi.Address = addr;
958 if (GEN_GEN >= 8 || GEN_IS_HASWELL) {
959 /* Pre-SKL, the dword containing the clear values also contains
960 * other fields, so we need to initialize those fields to match the
961 * values that would be in a color attachment.
962 */
963 sdi.ImmediateData = ISL_CHANNEL_SELECT_RED << 25 |
964 ISL_CHANNEL_SELECT_GREEN << 22 |
965 ISL_CHANNEL_SELECT_BLUE << 19 |
966 ISL_CHANNEL_SELECT_ALPHA << 16;
967 } else if (GEN_GEN == 7) {
968 /* On IVB, the dword containing the clear values also contains
969 * other fields that must be zero or can be zero.
970 */
971 sdi.ImmediateData = 0;
972 }
973 }
974 }
975 }
976
977 /* Copy the fast-clear value dword(s) between a surface state object and an
978 * image's fast clear state buffer.
979 */
980 static void
981 genX(copy_fast_clear_dwords)(struct anv_cmd_buffer *cmd_buffer,
982 struct anv_state surface_state,
983 const struct anv_image *image,
984 VkImageAspectFlagBits aspect,
985 bool copy_from_surface_state)
986 {
987 assert(cmd_buffer && image);
988 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
989
990 struct anv_address ss_clear_addr = {
991 .bo = cmd_buffer->device->surface_state_pool.block_pool.bo,
992 .offset = surface_state.offset +
993 cmd_buffer->device->isl_dev.ss.clear_value_offset,
994 };
995 const struct anv_address entry_addr =
996 anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
997 unsigned copy_size = cmd_buffer->device->isl_dev.ss.clear_value_size;
998
999 #if GEN_GEN == 7
1000 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
1001 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
1002 * in-flight when they are issued even if the memory touched is not
1003 * currently active for rendering. The weird bit is that it is not the
1004 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
1005 * rendering hangs such that the next stalling command after the
1006 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
1007 *
1008 * It is unclear exactly why this hang occurs. Both MI commands come with
1009 * warnings about the 3D pipeline but that doesn't seem to fully explain
1010 * it. My (Jason's) best theory is that it has something to do with the
1011 * fact that we're using a GPU state register as our temporary and that
1012 * something with reading/writing it is causing problems.
1013 *
1014 * In order to work around this issue, we emit a PIPE_CONTROL with the
1015 * command streamer stall bit set.
1016 */
1017 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
1018 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
1019 #endif
1020
1021 struct gen_mi_builder b;
1022 gen_mi_builder_init(&b, &cmd_buffer->batch);
1023
1024 if (copy_from_surface_state) {
1025 gen_mi_memcpy(&b, entry_addr, ss_clear_addr, copy_size);
1026 } else {
1027 gen_mi_memcpy(&b, ss_clear_addr, entry_addr, copy_size);
1028
1029 /* Updating a surface state object may require that the state cache be
1030 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1031 * Caching:
1032 *
1033 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1034 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1035 * modified [...], the L1 state cache must be invalidated to ensure
1036 * the new surface or sampler state is fetched from system memory.
1037 *
1038 * In testing, SKL doesn't actually seem to need this, but HSW does.
1039 */
1040 cmd_buffer->state.pending_pipe_bits |=
1041 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
1042 }
1043 }
1044
1045 /**
1046 * @brief Transitions a color buffer from one layout to another.
1047 *
1048 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
1049 * more information.
1050 *
1051 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
1052 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
1053 * this represents the maximum layers to transition at each
1054 * specified miplevel.
1055 */
1056 static void
1057 transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
1058 const struct anv_image *image,
1059 VkImageAspectFlagBits aspect,
1060 const uint32_t base_level, uint32_t level_count,
1061 uint32_t base_layer, uint32_t layer_count,
1062 VkImageLayout initial_layout,
1063 VkImageLayout final_layout)
1064 {
1065 struct anv_device *device = cmd_buffer->device;
1066 const struct gen_device_info *devinfo = &device->info;
1067 /* Validate the inputs. */
1068 assert(cmd_buffer);
1069 assert(image && image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
1070 /* These values aren't supported for simplicity's sake. */
1071 assert(level_count != VK_REMAINING_MIP_LEVELS &&
1072 layer_count != VK_REMAINING_ARRAY_LAYERS);
1073 /* Ensure the subresource range is valid. */
1074 UNUSED uint64_t last_level_num = base_level + level_count;
1075 const uint32_t max_depth = anv_minify(image->extent.depth, base_level);
1076 UNUSED const uint32_t image_layers = MAX2(image->array_size, max_depth);
1077 assert((uint64_t)base_layer + layer_count <= image_layers);
1078 assert(last_level_num <= image->levels);
1079 /* The spec disallows these final layouts. */
1080 assert(final_layout != VK_IMAGE_LAYOUT_UNDEFINED &&
1081 final_layout != VK_IMAGE_LAYOUT_PREINITIALIZED);
1082
1083 /* No work is necessary if the layout stays the same or if this subresource
1084 * range lacks auxiliary data.
1085 */
1086 if (initial_layout == final_layout)
1087 return;
1088
1089 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1090
1091 if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
1092 final_layout == VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL) {
1093 /* This surface is a linear compressed image with a tiled shadow surface
1094 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
1095 * we need to ensure the shadow copy is up-to-date.
1096 */
1097 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1098 assert(image->planes[plane].surface.isl.tiling == ISL_TILING_LINEAR);
1099 assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR);
1100 assert(isl_format_is_compressed(image->planes[plane].surface.isl.format));
1101 assert(plane == 0);
1102 anv_image_copy_to_shadow(cmd_buffer, image,
1103 VK_IMAGE_ASPECT_COLOR_BIT,
1104 base_level, level_count,
1105 base_layer, layer_count);
1106 }
1107
1108 if (base_layer >= anv_image_aux_layers(image, aspect, base_level))
1109 return;
1110
1111 assert(image->planes[plane].surface.isl.tiling != ISL_TILING_LINEAR);
1112
1113 if (initial_layout == VK_IMAGE_LAYOUT_UNDEFINED ||
1114 initial_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
1115 #if GEN_GEN == 12
1116 if (device->physical->has_implicit_ccs && devinfo->has_aux_map) {
1117 anv_image_init_aux_tt(cmd_buffer, image, aspect,
1118 base_level, level_count,
1119 base_layer, layer_count);
1120 }
1121 #else
1122 assert(!(device->physical->has_implicit_ccs && devinfo->has_aux_map));
1123 #endif
1124
1125 /* A subresource in the undefined layout may have been aliased and
1126 * populated with any arrangement of bits. Therefore, we must initialize
1127 * the related aux buffer and clear buffer entry with desirable values.
1128 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1129 * images with VK_IMAGE_TILING_OPTIMAL.
1130 *
1131 * Initialize the relevant clear buffer entries.
1132 */
1133 if (base_level == 0 && base_layer == 0)
1134 init_fast_clear_color(cmd_buffer, image, aspect);
1135
1136 /* Initialize the aux buffers to enable correct rendering. In order to
1137 * ensure that things such as storage images work correctly, aux buffers
1138 * need to be initialized to valid data.
1139 *
1140 * Having an aux buffer with invalid data is a problem for two reasons:
1141 *
1142 * 1) Having an invalid value in the buffer can confuse the hardware.
1143 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1144 * invalid and leads to the hardware doing strange things. It
1145 * doesn't hang as far as we can tell but rendering corruption can
1146 * occur.
1147 *
1148 * 2) If this transition is into the GENERAL layout and we then use the
1149 * image as a storage image, then we must have the aux buffer in the
1150 * pass-through state so that, if we then go to texture from the
1151 * image, we get the results of our storage image writes and not the
1152 * fast clear color or other random data.
1153 *
1154 * For CCS both of the problems above are real demonstrable issues. In
1155 * that case, the only thing we can do is to perform an ambiguate to
1156 * transition the aux surface into the pass-through state.
1157 *
1158 * For MCS, (2) is never an issue because we don't support multisampled
1159 * storage images. In theory, issue (1) is a problem with MCS but we've
1160 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1161 * theory, be interpreted as something but we don't know that all bit
1162 * patterns are actually valid. For 2x and 8x, you could easily end up
1163 * with the MCS referring to an invalid plane because not all bits of
1164 * the MCS value are actually used. Even though we've never seen issues
1165 * in the wild, it's best to play it safe and initialize the MCS. We
1166 * can use a fast-clear for MCS because we only ever touch from render
1167 * and texture (no image load store).
1168 */
1169 if (image->samples == 1) {
1170 for (uint32_t l = 0; l < level_count; l++) {
1171 const uint32_t level = base_level + l;
1172
1173 uint32_t aux_layers = anv_image_aux_layers(image, aspect, level);
1174 if (base_layer >= aux_layers)
1175 break; /* We will only get fewer layers as level increases */
1176 uint32_t level_layer_count =
1177 MIN2(layer_count, aux_layers - base_layer);
1178
1179 anv_image_ccs_op(cmd_buffer, image,
1180 image->planes[plane].surface.isl.format,
1181 ISL_SWIZZLE_IDENTITY,
1182 aspect, level, base_layer, level_layer_count,
1183 ISL_AUX_OP_AMBIGUATE, NULL, false);
1184
1185 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) {
1186 set_image_compressed_bit(cmd_buffer, image, aspect,
1187 level, base_layer, level_layer_count,
1188 false);
1189 }
1190 }
1191 } else {
1192 if (image->samples == 4 || image->samples == 16) {
1193 anv_perf_warn(cmd_buffer->device, image,
1194 "Doing a potentially unnecessary fast-clear to "
1195 "define an MCS buffer.");
1196 }
1197
1198 assert(base_level == 0 && level_count == 1);
1199 anv_image_mcs_op(cmd_buffer, image,
1200 image->planes[plane].surface.isl.format,
1201 ISL_SWIZZLE_IDENTITY,
1202 aspect, base_layer, layer_count,
1203 ISL_AUX_OP_FAST_CLEAR, NULL, false);
1204 }
1205 return;
1206 }
1207
1208 const enum isl_aux_usage initial_aux_usage =
1209 anv_layout_to_aux_usage(devinfo, image, aspect, 0, initial_layout);
1210 const enum isl_aux_usage final_aux_usage =
1211 anv_layout_to_aux_usage(devinfo, image, aspect, 0, final_layout);
1212
1213 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1214 * We can handle transitions between CCS_D/E to and from NONE. What we
1215 * don't yet handle is switching between CCS_E and CCS_D within a given
1216 * image. Doing so in a performant way requires more detailed aux state
1217 * tracking such as what is done in i965. For now, just assume that we
1218 * only have one type of compression.
1219 */
1220 assert(initial_aux_usage == ISL_AUX_USAGE_NONE ||
1221 final_aux_usage == ISL_AUX_USAGE_NONE ||
1222 initial_aux_usage == final_aux_usage);
1223
1224 /* If initial aux usage is NONE, there is nothing to resolve */
1225 if (initial_aux_usage == ISL_AUX_USAGE_NONE)
1226 return;
1227
1228 enum isl_aux_op resolve_op = ISL_AUX_OP_NONE;
1229
1230 /* If the initial layout supports more fast clear than the final layout
1231 * then we need at least a partial resolve.
1232 */
1233 const enum anv_fast_clear_type initial_fast_clear =
1234 anv_layout_to_fast_clear_type(devinfo, image, aspect, initial_layout);
1235 const enum anv_fast_clear_type final_fast_clear =
1236 anv_layout_to_fast_clear_type(devinfo, image, aspect, final_layout);
1237 if (final_fast_clear < initial_fast_clear)
1238 resolve_op = ISL_AUX_OP_PARTIAL_RESOLVE;
1239
1240 if (initial_aux_usage == ISL_AUX_USAGE_CCS_E &&
1241 final_aux_usage != ISL_AUX_USAGE_CCS_E)
1242 resolve_op = ISL_AUX_OP_FULL_RESOLVE;
1243
1244 if (resolve_op == ISL_AUX_OP_NONE)
1245 return;
1246
1247 /* Perform a resolve to synchronize data between the main and aux buffer.
1248 * Before we begin, we must satisfy the cache flushing requirement specified
1249 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1250 *
1251 * Any transition from any value in {Clear, Render, Resolve} to a
1252 * different value in {Clear, Render, Resolve} requires end of pipe
1253 * synchronization.
1254 *
1255 * We perform a flush of the write cache before and after the clear and
1256 * resolve operations to meet this requirement.
1257 *
1258 * Unlike other drawing, fast clear operations are not properly
1259 * synchronized. The first PIPE_CONTROL here likely ensures that the
1260 * contents of the previous render or clear hit the render target before we
1261 * resolve and the second likely ensures that the resolve is complete before
1262 * we do any more rendering or clearing.
1263 */
1264 cmd_buffer->state.pending_pipe_bits |=
1265 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
1266
1267 for (uint32_t l = 0; l < level_count; l++) {
1268 uint32_t level = base_level + l;
1269
1270 uint32_t aux_layers = anv_image_aux_layers(image, aspect, level);
1271 if (base_layer >= aux_layers)
1272 break; /* We will only get fewer layers as level increases */
1273 uint32_t level_layer_count =
1274 MIN2(layer_count, aux_layers - base_layer);
1275
1276 for (uint32_t a = 0; a < level_layer_count; a++) {
1277 uint32_t array_layer = base_layer + a;
1278 if (image->samples == 1) {
1279 anv_cmd_predicated_ccs_resolve(cmd_buffer, image,
1280 image->planes[plane].surface.isl.format,
1281 ISL_SWIZZLE_IDENTITY,
1282 aspect, level, array_layer, resolve_op,
1283 final_fast_clear);
1284 } else {
1285 /* We only support fast-clear on the first layer so partial
1286 * resolves should not be used on other layers as they will use
1287 * the clear color stored in memory that is only valid for layer0.
1288 */
1289 if (resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE &&
1290 array_layer != 0)
1291 continue;
1292
1293 anv_cmd_predicated_mcs_resolve(cmd_buffer, image,
1294 image->planes[plane].surface.isl.format,
1295 ISL_SWIZZLE_IDENTITY,
1296 aspect, array_layer, resolve_op,
1297 final_fast_clear);
1298 }
1299 }
1300 }
1301
1302 cmd_buffer->state.pending_pipe_bits |=
1303 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
1304 }
1305
1306 static VkResult
1307 genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer *cmd_buffer,
1308 const struct anv_render_pass *pass,
1309 const struct anv_framebuffer *framebuffer,
1310 const VkRenderPassBeginInfo *begin)
1311 {
1312 struct anv_cmd_state *state = &cmd_buffer->state;
1313
1314 vk_free(&cmd_buffer->pool->alloc, state->attachments);
1315
1316 if (pass->attachment_count > 0) {
1317 state->attachments = vk_zalloc(&cmd_buffer->pool->alloc,
1318 pass->attachment_count *
1319 sizeof(state->attachments[0]),
1320 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1321 if (state->attachments == NULL) {
1322 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1323 return anv_batch_set_error(&cmd_buffer->batch,
1324 VK_ERROR_OUT_OF_HOST_MEMORY);
1325 }
1326 } else {
1327 state->attachments = NULL;
1328 }
1329
1330 const VkRenderPassAttachmentBeginInfoKHR *attach_begin =
1331 vk_find_struct_const(begin, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR);
1332 if (begin && !attach_begin)
1333 assert(pass->attachment_count == framebuffer->attachment_count);
1334
1335 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1336 if (attach_begin && attach_begin->attachmentCount != 0) {
1337 assert(attach_begin->attachmentCount == pass->attachment_count);
1338 ANV_FROM_HANDLE(anv_image_view, iview, attach_begin->pAttachments[i]);
1339 state->attachments[i].image_view = iview;
1340 } else if (framebuffer && i < framebuffer->attachment_count) {
1341 state->attachments[i].image_view = framebuffer->attachments[i];
1342 } else {
1343 state->attachments[i].image_view = NULL;
1344 }
1345 }
1346
1347 if (begin) {
1348 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1349 const struct anv_render_pass_attachment *pass_att = &pass->attachments[i];
1350 struct anv_attachment_state *att_state = &state->attachments[i];
1351 VkImageAspectFlags att_aspects = vk_format_aspects(pass_att->format);
1352 VkImageAspectFlags clear_aspects = 0;
1353 VkImageAspectFlags load_aspects = 0;
1354
1355 if (att_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
1356 /* color attachment */
1357 if (pass_att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1358 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1359 } else if (pass_att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
1360 load_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1361 }
1362 } else {
1363 /* depthstencil attachment */
1364 if (att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
1365 if (pass_att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1366 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1367 } else if (pass_att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
1368 load_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1369 }
1370 }
1371 if (att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1372 if (pass_att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1373 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1374 } else if (pass_att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
1375 load_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1376 }
1377 }
1378 }
1379
1380 att_state->current_layout = pass_att->initial_layout;
1381 att_state->current_stencil_layout = pass_att->stencil_initial_layout;
1382 att_state->pending_clear_aspects = clear_aspects;
1383 att_state->pending_load_aspects = load_aspects;
1384 if (clear_aspects)
1385 att_state->clear_value = begin->pClearValues[i];
1386
1387 struct anv_image_view *iview = state->attachments[i].image_view;
1388 anv_assert(iview->vk_format == pass_att->format);
1389
1390 const uint32_t num_layers = iview->planes[0].isl.array_len;
1391 att_state->pending_clear_views = (1 << num_layers) - 1;
1392
1393 /* This will be initialized after the first subpass transition. */
1394 att_state->aux_usage = ISL_AUX_USAGE_NONE;
1395
1396 att_state->fast_clear = false;
1397 if (clear_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
1398 assert(clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1399 att_state->fast_clear =
1400 anv_can_fast_clear_color_view(cmd_buffer->device, iview,
1401 pass_att->first_subpass_layout,
1402 vk_to_isl_color(att_state->clear_value.color),
1403 framebuffer->layers,
1404 begin->renderArea);
1405 } else if (clear_aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
1406 VK_IMAGE_ASPECT_STENCIL_BIT)) {
1407 att_state->fast_clear =
1408 anv_can_hiz_clear_ds_view(cmd_buffer->device, iview,
1409 pass_att->first_subpass_layout,
1410 clear_aspects,
1411 att_state->clear_value.depthStencil.depth,
1412 begin->renderArea);
1413 }
1414 }
1415 }
1416
1417 return VK_SUCCESS;
1418 }
1419
1420 /**
1421 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1422 */
1423 static VkResult
1424 genX(cmd_buffer_alloc_att_surf_states)(struct anv_cmd_buffer *cmd_buffer,
1425 const struct anv_render_pass *pass,
1426 const struct anv_subpass *subpass)
1427 {
1428 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
1429 struct anv_cmd_state *state = &cmd_buffer->state;
1430
1431 /* Reserve one for the NULL state. */
1432 unsigned num_states = 1;
1433 for (uint32_t i = 0; i < subpass->attachment_count; i++) {
1434 uint32_t att = subpass->attachments[i].attachment;
1435 if (att == VK_ATTACHMENT_UNUSED)
1436 continue;
1437
1438 assert(att < pass->attachment_count);
1439 if (!vk_format_is_color(pass->attachments[att].format))
1440 continue;
1441
1442 const VkImageUsageFlagBits att_usage = subpass->attachments[i].usage;
1443 assert(util_bitcount(att_usage) == 1);
1444
1445 if (att_usage == VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT ||
1446 att_usage == VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)
1447 num_states++;
1448 }
1449
1450 const uint32_t ss_stride = align_u32(isl_dev->ss.size, isl_dev->ss.align);
1451 state->attachment_states =
1452 anv_state_stream_alloc(&cmd_buffer->surface_state_stream,
1453 num_states * ss_stride, isl_dev->ss.align);
1454 if (state->attachment_states.map == NULL) {
1455 return anv_batch_set_error(&cmd_buffer->batch,
1456 VK_ERROR_OUT_OF_DEVICE_MEMORY);
1457 }
1458
1459 struct anv_state next_state = state->attachment_states;
1460 next_state.alloc_size = isl_dev->ss.size;
1461
1462 state->null_surface_state = next_state;
1463 next_state.offset += ss_stride;
1464 next_state.map += ss_stride;
1465
1466 for (uint32_t i = 0; i < subpass->attachment_count; i++) {
1467 uint32_t att = subpass->attachments[i].attachment;
1468 if (att == VK_ATTACHMENT_UNUSED)
1469 continue;
1470
1471 assert(att < pass->attachment_count);
1472 if (!vk_format_is_color(pass->attachments[att].format))
1473 continue;
1474
1475 const VkImageUsageFlagBits att_usage = subpass->attachments[i].usage;
1476 assert(util_bitcount(att_usage) == 1);
1477
1478 if (att_usage == VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT)
1479 state->attachments[att].color.state = next_state;
1480 else if (att_usage == VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)
1481 state->attachments[att].input.state = next_state;
1482 else
1483 continue;
1484
1485 state->attachments[att].color.state = next_state;
1486 next_state.offset += ss_stride;
1487 next_state.map += ss_stride;
1488 }
1489
1490 assert(next_state.offset == state->attachment_states.offset +
1491 state->attachment_states.alloc_size);
1492
1493 return VK_SUCCESS;
1494 }
1495
1496 VkResult
1497 genX(BeginCommandBuffer)(
1498 VkCommandBuffer commandBuffer,
1499 const VkCommandBufferBeginInfo* pBeginInfo)
1500 {
1501 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1502
1503 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1504 * command buffer's state. Otherwise, we must *reset* its state. In both
1505 * cases we reset it.
1506 *
1507 * From the Vulkan 1.0 spec:
1508 *
1509 * If a command buffer is in the executable state and the command buffer
1510 * was allocated from a command pool with the
1511 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1512 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1513 * as if vkResetCommandBuffer had been called with
1514 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1515 * the command buffer in the recording state.
1516 */
1517 anv_cmd_buffer_reset(cmd_buffer);
1518
1519 cmd_buffer->usage_flags = pBeginInfo->flags;
1520
1521 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY ||
1522 !(cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT));
1523
1524 genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
1525
1526 /* We sometimes store vertex data in the dynamic state buffer for blorp
1527 * operations and our dynamic state stream may re-use data from previous
1528 * command buffers. In order to prevent stale cache data, we flush the VF
1529 * cache. We could do this on every blorp call but that's not really
1530 * needed as all of the data will get written by the CPU prior to the GPU
1531 * executing anything. The chances are fairly high that they will use
1532 * blorp at least once per primary command buffer so it shouldn't be
1533 * wasted.
1534 *
1535 * There is also a workaround on gen8 which requires us to invalidate the
1536 * VF cache occasionally. It's easier if we can assume we start with a
1537 * fresh cache (See also genX(cmd_buffer_set_binding_for_gen8_vb_flush).)
1538 */
1539 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1540
1541 /* Re-emit the aux table register in every command buffer. This way we're
1542 * ensured that we have the table even if this command buffer doesn't
1543 * initialize any images.
1544 */
1545 if (cmd_buffer->device->info.has_aux_map)
1546 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT;
1547
1548 /* We send an "Indirect State Pointers Disable" packet at
1549 * EndCommandBuffer, so all push contant packets are ignored during a
1550 * context restore. Documentation says after that command, we need to
1551 * emit push constants again before any rendering operation. So we
1552 * flag them dirty here to make sure they get emitted.
1553 */
1554 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
1555
1556 VkResult result = VK_SUCCESS;
1557 if (cmd_buffer->usage_flags &
1558 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1559 assert(pBeginInfo->pInheritanceInfo);
1560 ANV_FROM_HANDLE(anv_render_pass, pass,
1561 pBeginInfo->pInheritanceInfo->renderPass);
1562 struct anv_subpass *subpass =
1563 &pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1564 ANV_FROM_HANDLE(anv_framebuffer, framebuffer,
1565 pBeginInfo->pInheritanceInfo->framebuffer);
1566
1567 cmd_buffer->state.pass = pass;
1568 cmd_buffer->state.subpass = subpass;
1569
1570 /* This is optional in the inheritance info. */
1571 cmd_buffer->state.framebuffer = framebuffer;
1572
1573 result = genX(cmd_buffer_setup_attachments)(cmd_buffer, pass,
1574 framebuffer, NULL);
1575 if (result != VK_SUCCESS)
1576 return result;
1577
1578 result = genX(cmd_buffer_alloc_att_surf_states)(cmd_buffer, pass,
1579 subpass);
1580 if (result != VK_SUCCESS)
1581 return result;
1582
1583 /* Record that HiZ is enabled if we can. */
1584 if (cmd_buffer->state.framebuffer) {
1585 const struct anv_image_view * const iview =
1586 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
1587
1588 if (iview) {
1589 VkImageLayout layout =
1590 cmd_buffer->state.subpass->depth_stencil_attachment->layout;
1591
1592 enum isl_aux_usage aux_usage =
1593 anv_layout_to_aux_usage(&cmd_buffer->device->info, iview->image,
1594 VK_IMAGE_ASPECT_DEPTH_BIT,
1595 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT,
1596 layout);
1597
1598 cmd_buffer->state.hiz_enabled = isl_aux_usage_has_hiz(aux_usage);
1599 }
1600 }
1601
1602 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
1603 }
1604
1605 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1606 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) {
1607 const VkCommandBufferInheritanceConditionalRenderingInfoEXT *conditional_rendering_info =
1608 vk_find_struct_const(pBeginInfo->pInheritanceInfo->pNext, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT);
1609
1610 /* If secondary buffer supports conditional rendering
1611 * we should emit commands as if conditional rendering is enabled.
1612 */
1613 cmd_buffer->state.conditional_render_enabled =
1614 conditional_rendering_info && conditional_rendering_info->conditionalRenderingEnable;
1615 }
1616 #endif
1617
1618 return result;
1619 }
1620
1621 /* From the PRM, Volume 2a:
1622 *
1623 * "Indirect State Pointers Disable
1624 *
1625 * At the completion of the post-sync operation associated with this pipe
1626 * control packet, the indirect state pointers in the hardware are
1627 * considered invalid; the indirect pointers are not saved in the context.
1628 * If any new indirect state commands are executed in the command stream
1629 * while the pipe control is pending, the new indirect state commands are
1630 * preserved.
1631 *
1632 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1633 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1634 * commands are only considered as Indirect State Pointers. Once ISP is
1635 * issued in a context, SW must initialize by programming push constant
1636 * commands for all the shaders (at least to zero length) before attempting
1637 * any rendering operation for the same context."
1638 *
1639 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1640 * even though they point to a BO that has been already unreferenced at
1641 * the end of the previous batch buffer. This has been fine so far since
1642 * we are protected by these scratch page (every address not covered by
1643 * a BO should be pointing to the scratch page). But on CNL, it is
1644 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1645 * instruction.
1646 *
1647 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1648 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1649 * context restore, so the mentioned hang doesn't happen. However,
1650 * software must program push constant commands for all stages prior to
1651 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1652 *
1653 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1654 * constants have been loaded into the EUs prior to disable the push constants
1655 * so that it doesn't hang a previous 3DPRIMITIVE.
1656 */
1657 static void
1658 emit_isp_disable(struct anv_cmd_buffer *cmd_buffer)
1659 {
1660 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1661 pc.StallAtPixelScoreboard = true;
1662 pc.CommandStreamerStallEnable = true;
1663 }
1664 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1665 pc.IndirectStatePointersDisable = true;
1666 pc.CommandStreamerStallEnable = true;
1667 }
1668 }
1669
1670 VkResult
1671 genX(EndCommandBuffer)(
1672 VkCommandBuffer commandBuffer)
1673 {
1674 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1675
1676 if (anv_batch_has_error(&cmd_buffer->batch))
1677 return cmd_buffer->batch.status;
1678
1679 /* We want every command buffer to start with the PMA fix in a known state,
1680 * so we disable it at the end of the command buffer.
1681 */
1682 genX(cmd_buffer_enable_pma_fix)(cmd_buffer, false);
1683
1684 genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
1685
1686 emit_isp_disable(cmd_buffer);
1687
1688 anv_cmd_buffer_end_batch_buffer(cmd_buffer);
1689
1690 return VK_SUCCESS;
1691 }
1692
1693 void
1694 genX(CmdExecuteCommands)(
1695 VkCommandBuffer commandBuffer,
1696 uint32_t commandBufferCount,
1697 const VkCommandBuffer* pCmdBuffers)
1698 {
1699 ANV_FROM_HANDLE(anv_cmd_buffer, primary, commandBuffer);
1700
1701 assert(primary->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1702
1703 if (anv_batch_has_error(&primary->batch))
1704 return;
1705
1706 /* The secondary command buffers will assume that the PMA fix is disabled
1707 * when they begin executing. Make sure this is true.
1708 */
1709 genX(cmd_buffer_enable_pma_fix)(primary, false);
1710
1711 /* The secondary command buffer doesn't know which textures etc. have been
1712 * flushed prior to their execution. Apply those flushes now.
1713 */
1714 genX(cmd_buffer_apply_pipe_flushes)(primary);
1715
1716 for (uint32_t i = 0; i < commandBufferCount; i++) {
1717 ANV_FROM_HANDLE(anv_cmd_buffer, secondary, pCmdBuffers[i]);
1718
1719 assert(secondary->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY);
1720 assert(!anv_batch_has_error(&secondary->batch));
1721
1722 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1723 if (secondary->state.conditional_render_enabled) {
1724 if (!primary->state.conditional_render_enabled) {
1725 /* Secondary buffer is constructed as if it will be executed
1726 * with conditional rendering, we should satisfy this dependency
1727 * regardless of conditional rendering being enabled in primary.
1728 */
1729 struct gen_mi_builder b;
1730 gen_mi_builder_init(&b, &primary->batch);
1731 gen_mi_store(&b, gen_mi_reg64(ANV_PREDICATE_RESULT_REG),
1732 gen_mi_imm(UINT64_MAX));
1733 }
1734 }
1735 #endif
1736
1737 if (secondary->usage_flags &
1738 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1739 /* If we're continuing a render pass from the primary, we need to
1740 * copy the surface states for the current subpass into the storage
1741 * we allocated for them in BeginCommandBuffer.
1742 */
1743 struct anv_bo *ss_bo =
1744 primary->device->surface_state_pool.block_pool.bo;
1745 struct anv_state src_state = primary->state.attachment_states;
1746 struct anv_state dst_state = secondary->state.attachment_states;
1747 assert(src_state.alloc_size == dst_state.alloc_size);
1748
1749 genX(cmd_buffer_so_memcpy)(primary,
1750 (struct anv_address) {
1751 .bo = ss_bo,
1752 .offset = dst_state.offset,
1753 },
1754 (struct anv_address) {
1755 .bo = ss_bo,
1756 .offset = src_state.offset,
1757 },
1758 src_state.alloc_size);
1759 }
1760
1761 anv_cmd_buffer_add_secondary(primary, secondary);
1762
1763 assert(secondary->perf_query_pool == NULL || primary->perf_query_pool == NULL ||
1764 secondary->perf_query_pool == primary->perf_query_pool);
1765 if (secondary->perf_query_pool)
1766 primary->perf_query_pool = secondary->perf_query_pool;
1767 }
1768
1769 /* The secondary isn't counted in our VF cache tracking so we need to
1770 * invalidate the whole thing.
1771 */
1772 if (GEN_GEN >= 8 && GEN_GEN <= 9) {
1773 primary->state.pending_pipe_bits |=
1774 ANV_PIPE_CS_STALL_BIT | ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1775 }
1776
1777 /* The secondary may have selected a different pipeline (3D or compute) and
1778 * may have changed the current L3$ configuration. Reset our tracking
1779 * variables to invalid values to ensure that we re-emit these in the case
1780 * where we do any draws or compute dispatches from the primary after the
1781 * secondary has returned.
1782 */
1783 primary->state.current_pipeline = UINT32_MAX;
1784 primary->state.current_l3_config = NULL;
1785 primary->state.current_hash_scale = 0;
1786
1787 /* Each of the secondary command buffers will use its own state base
1788 * address. We need to re-emit state base address for the primary after
1789 * all of the secondaries are done.
1790 *
1791 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1792 * address calls?
1793 */
1794 genX(cmd_buffer_emit_state_base_address)(primary);
1795 }
1796
1797 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1798 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1799 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1800
1801 /**
1802 * Program the hardware to use the specified L3 configuration.
1803 */
1804 void
1805 genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
1806 const struct gen_l3_config *cfg)
1807 {
1808 assert(cfg || GEN_GEN >= 12);
1809 if (cfg == cmd_buffer->state.current_l3_config)
1810 return;
1811
1812 if (unlikely(INTEL_DEBUG & DEBUG_L3)) {
1813 intel_logd("L3 config transition: ");
1814 gen_dump_l3_config(cfg, stderr);
1815 }
1816
1817 UNUSED const bool has_slm = cfg->n[GEN_L3P_SLM];
1818
1819 /* According to the hardware docs, the L3 partitioning can only be changed
1820 * while the pipeline is completely drained and the caches are flushed,
1821 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1822 */
1823 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1824 pc.DCFlushEnable = true;
1825 pc.PostSyncOperation = NoWrite;
1826 pc.CommandStreamerStallEnable = true;
1827 }
1828
1829 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1830 * invalidation of the relevant caches. Note that because RO invalidation
1831 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1832 * command is processed by the CS) we cannot combine it with the previous
1833 * stalling flush as the hardware documentation suggests, because that
1834 * would cause the CS to stall on previous rendering *after* RO
1835 * invalidation and wouldn't prevent the RO caches from being polluted by
1836 * concurrent rendering before the stall completes. This intentionally
1837 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1838 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1839 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1840 * already guarantee that there is no concurrent GPGPU kernel execution
1841 * (see SKL HSD 2132585).
1842 */
1843 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1844 pc.TextureCacheInvalidationEnable = true;
1845 pc.ConstantCacheInvalidationEnable = true;
1846 pc.InstructionCacheInvalidateEnable = true;
1847 pc.StateCacheInvalidationEnable = true;
1848 pc.PostSyncOperation = NoWrite;
1849 }
1850
1851 /* Now send a third stalling flush to make sure that invalidation is
1852 * complete when the L3 configuration registers are modified.
1853 */
1854 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1855 pc.DCFlushEnable = true;
1856 pc.PostSyncOperation = NoWrite;
1857 pc.CommandStreamerStallEnable = true;
1858 }
1859
1860 #if GEN_GEN >= 8
1861
1862 assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
1863
1864 #if GEN_GEN >= 12
1865 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1866 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1867 #else
1868 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1869 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1870 #endif
1871
1872 uint32_t l3cr;
1873 anv_pack_struct(&l3cr, L3_ALLOCATION_REG,
1874 #if GEN_GEN < 11
1875 .SLMEnable = has_slm,
1876 #endif
1877 #if GEN_GEN == 11
1878 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1879 * in L3CNTLREG register. The default setting of the bit is not the
1880 * desirable behavior.
1881 */
1882 .ErrorDetectionBehaviorControl = true,
1883 .UseFullWays = true,
1884 #endif
1885 .URBAllocation = cfg->n[GEN_L3P_URB],
1886 .ROAllocation = cfg->n[GEN_L3P_RO],
1887 .DCAllocation = cfg->n[GEN_L3P_DC],
1888 .AllAllocation = cfg->n[GEN_L3P_ALL]);
1889
1890 /* Set up the L3 partitioning. */
1891 emit_lri(&cmd_buffer->batch, L3_ALLOCATION_REG_num, l3cr);
1892
1893 #else
1894
1895 const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
1896 const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
1897 cfg->n[GEN_L3P_ALL];
1898 const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] ||
1899 cfg->n[GEN_L3P_ALL];
1900 const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] ||
1901 cfg->n[GEN_L3P_ALL];
1902
1903 assert(!cfg->n[GEN_L3P_ALL]);
1904
1905 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1906 * the matching space on the remaining banks has to be allocated to a
1907 * client (URB for all validated configurations) set to the
1908 * lower-bandwidth 2-bank address hashing mode.
1909 */
1910 const struct gen_device_info *devinfo = &cmd_buffer->device->info;
1911 const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
1912 assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
1913
1914 /* Minimum number of ways that can be allocated to the URB. */
1915 const unsigned n0_urb = devinfo->is_baytrail ? 32 : 0;
1916 assert(cfg->n[GEN_L3P_URB] >= n0_urb);
1917
1918 uint32_t l3sqcr1, l3cr2, l3cr3;
1919 anv_pack_struct(&l3sqcr1, GENX(L3SQCREG1),
1920 .ConvertDC_UC = !has_dc,
1921 .ConvertIS_UC = !has_is,
1922 .ConvertC_UC = !has_c,
1923 .ConvertT_UC = !has_t);
1924 l3sqcr1 |=
1925 GEN_IS_HASWELL ? HSW_L3SQCREG1_SQGHPCI_DEFAULT :
1926 devinfo->is_baytrail ? VLV_L3SQCREG1_SQGHPCI_DEFAULT :
1927 IVB_L3SQCREG1_SQGHPCI_DEFAULT;
1928
1929 anv_pack_struct(&l3cr2, GENX(L3CNTLREG2),
1930 .SLMEnable = has_slm,
1931 .URBLowBandwidth = urb_low_bw,
1932 .URBAllocation = cfg->n[GEN_L3P_URB] - n0_urb,
1933 #if !GEN_IS_HASWELL
1934 .ALLAllocation = cfg->n[GEN_L3P_ALL],
1935 #endif
1936 .ROAllocation = cfg->n[GEN_L3P_RO],
1937 .DCAllocation = cfg->n[GEN_L3P_DC]);
1938
1939 anv_pack_struct(&l3cr3, GENX(L3CNTLREG3),
1940 .ISAllocation = cfg->n[GEN_L3P_IS],
1941 .ISLowBandwidth = 0,
1942 .CAllocation = cfg->n[GEN_L3P_C],
1943 .CLowBandwidth = 0,
1944 .TAllocation = cfg->n[GEN_L3P_T],
1945 .TLowBandwidth = 0);
1946
1947 /* Set up the L3 partitioning. */
1948 emit_lri(&cmd_buffer->batch, GENX(L3SQCREG1_num), l3sqcr1);
1949 emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG2_num), l3cr2);
1950 emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG3_num), l3cr3);
1951
1952 #if GEN_IS_HASWELL
1953 if (cmd_buffer->device->physical->cmd_parser_version >= 4) {
1954 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1955 * them disabled to avoid crashing the system hard.
1956 */
1957 uint32_t scratch1, chicken3;
1958 anv_pack_struct(&scratch1, GENX(SCRATCH1),
1959 .L3AtomicDisable = !has_dc);
1960 anv_pack_struct(&chicken3, GENX(CHICKEN3),
1961 .L3AtomicDisableMask = true,
1962 .L3AtomicDisable = !has_dc);
1963 emit_lri(&cmd_buffer->batch, GENX(SCRATCH1_num), scratch1);
1964 emit_lri(&cmd_buffer->batch, GENX(CHICKEN3_num), chicken3);
1965 }
1966 #endif
1967
1968 #endif
1969
1970 cmd_buffer->state.current_l3_config = cfg;
1971 }
1972
1973 void
1974 genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
1975 {
1976 UNUSED const struct gen_device_info *devinfo = &cmd_buffer->device->info;
1977 enum anv_pipe_bits bits = cmd_buffer->state.pending_pipe_bits;
1978
1979 if (cmd_buffer->device->physical->always_flush_cache)
1980 bits |= ANV_PIPE_FLUSH_BITS | ANV_PIPE_INVALIDATE_BITS;
1981
1982 /*
1983 * From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
1984 *
1985 * Write synchronization is a special case of end-of-pipe
1986 * synchronization that requires that the render cache and/or depth
1987 * related caches are flushed to memory, where the data will become
1988 * globally visible. This type of synchronization is required prior to
1989 * SW (CPU) actually reading the result data from memory, or initiating
1990 * an operation that will use as a read surface (such as a texture
1991 * surface) a previous render target and/or depth/stencil buffer
1992 *
1993 *
1994 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
1995 *
1996 * Exercising the write cache flush bits (Render Target Cache Flush
1997 * Enable, Depth Cache Flush Enable, DC Flush) in PIPE_CONTROL only
1998 * ensures the write caches are flushed and doesn't guarantee the data
1999 * is globally visible.
2000 *
2001 * SW can track the completion of the end-of-pipe-synchronization by
2002 * using "Notify Enable" and "PostSync Operation - Write Immediate
2003 * Data" in the PIPE_CONTROL command.
2004 *
2005 * In other words, flushes are pipelined while invalidations are handled
2006 * immediately. Therefore, if we're flushing anything then we need to
2007 * schedule an end-of-pipe sync before any invalidations can happen.
2008 */
2009 if (bits & ANV_PIPE_FLUSH_BITS)
2010 bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
2011
2012
2013 /* HSD 1209978178: docs say that before programming the aux table:
2014 *
2015 * "Driver must ensure that the engine is IDLE but ensure it doesn't
2016 * add extra flushes in the case it knows that the engine is already
2017 * IDLE."
2018 */
2019 if (GEN_GEN == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT))
2020 bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
2021
2022 /* If we're going to do an invalidate and we have a pending end-of-pipe
2023 * sync that has yet to be resolved, we do the end-of-pipe sync now.
2024 */
2025 if ((bits & ANV_PIPE_INVALIDATE_BITS) &&
2026 (bits & ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT)) {
2027 bits |= ANV_PIPE_END_OF_PIPE_SYNC_BIT;
2028 bits &= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
2029 }
2030
2031 if (GEN_GEN >= 12 &&
2032 ((bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT) ||
2033 (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT))) {
2034 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
2035 * Enable):
2036 *
2037 * Unified Cache (Tile Cache Disabled):
2038 *
2039 * When the Color and Depth (Z) streams are enabled to be cached in
2040 * the DC space of L2, Software must use "Render Target Cache Flush
2041 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
2042 * Flush" for getting the color and depth (Z) write data to be
2043 * globally observable. In this mode of operation it is not required
2044 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
2045 */
2046 bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
2047 }
2048
2049 /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
2050 * invalidates the instruction cache
2051 */
2052 if (GEN_GEN == 12 && (bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT))
2053 bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
2054
2055 if ((GEN_GEN >= 8 && GEN_GEN <= 9) &&
2056 (bits & ANV_PIPE_CS_STALL_BIT) &&
2057 (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) {
2058 /* If we are doing a VF cache invalidate AND a CS stall (it must be
2059 * both) then we can reset our vertex cache tracking.
2060 */
2061 memset(cmd_buffer->state.gfx.vb_dirty_ranges, 0,
2062 sizeof(cmd_buffer->state.gfx.vb_dirty_ranges));
2063 memset(&cmd_buffer->state.gfx.ib_dirty_range, 0,
2064 sizeof(cmd_buffer->state.gfx.ib_dirty_range));
2065 }
2066
2067 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2068 *
2069 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2070 * programmed prior to programming a PIPECONTROL command with "LRI
2071 * Post Sync Operation" in GPGPU mode of operation (i.e when
2072 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2073 *
2074 * The same text exists a few rows below for Post Sync Op.
2075 *
2076 * On Gen12 this is GEN:BUG:1607156449.
2077 */
2078 if (bits & ANV_PIPE_POST_SYNC_BIT) {
2079 if ((GEN_GEN == 9 || (GEN_GEN == 12 && devinfo->revision == 0 /* A0 */)) &&
2080 cmd_buffer->state.current_pipeline == GPGPU)
2081 bits |= ANV_PIPE_CS_STALL_BIT;
2082 bits &= ~ANV_PIPE_POST_SYNC_BIT;
2083 }
2084
2085 if (bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_CS_STALL_BIT |
2086 ANV_PIPE_END_OF_PIPE_SYNC_BIT)) {
2087 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
2088 #if GEN_GEN >= 12
2089 pipe.TileCacheFlushEnable = bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT;
2090 #endif
2091 pipe.DepthCacheFlushEnable = bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2092 pipe.DCFlushEnable = bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT;
2093 pipe.RenderTargetCacheFlushEnable =
2094 bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2095
2096 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
2097 * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
2098 */
2099 #if GEN_GEN >= 12
2100 pipe.DepthStallEnable =
2101 pipe.DepthCacheFlushEnable || (bits & ANV_PIPE_DEPTH_STALL_BIT);
2102 #else
2103 pipe.DepthStallEnable = bits & ANV_PIPE_DEPTH_STALL_BIT;
2104 #endif
2105
2106 pipe.CommandStreamerStallEnable = bits & ANV_PIPE_CS_STALL_BIT;
2107 pipe.StallAtPixelScoreboard = bits & ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
2108
2109 /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":
2110 *
2111 * "The most common action to perform upon reaching a
2112 * synchronization point is to write a value out to memory. An
2113 * immediate value (included with the synchronization command) may
2114 * be written."
2115 *
2116 *
2117 * From Broadwell PRM, volume 7, "End-of-Pipe Synchronization":
2118 *
2119 * "In case the data flushed out by the render engine is to be
2120 * read back in to the render engine in coherent manner, then the
2121 * render engine has to wait for the fence completion before
2122 * accessing the flushed data. This can be achieved by following
2123 * means on various products: PIPE_CONTROL command with CS Stall
2124 * and the required write caches flushed with Post-Sync-Operation
2125 * as Write Immediate Data.
2126 *
2127 * Example:
2128 * - Workload-1 (3D/GPGPU/MEDIA)
2129 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2130 * Immediate Data, Required Write Cache Flush bits set)
2131 * - Workload-2 (Can use the data produce or output by
2132 * Workload-1)
2133 */
2134 if (bits & ANV_PIPE_END_OF_PIPE_SYNC_BIT) {
2135 pipe.CommandStreamerStallEnable = true;
2136 pipe.PostSyncOperation = WriteImmediateData;
2137 pipe.Address = cmd_buffer->device->workaround_address;
2138 }
2139
2140 /*
2141 * According to the Broadwell documentation, any PIPE_CONTROL with the
2142 * "Command Streamer Stall" bit set must also have another bit set,
2143 * with five different options:
2144 *
2145 * - Render Target Cache Flush
2146 * - Depth Cache Flush
2147 * - Stall at Pixel Scoreboard
2148 * - Post-Sync Operation
2149 * - Depth Stall
2150 * - DC Flush Enable
2151 *
2152 * I chose "Stall at Pixel Scoreboard" since that's what we use in
2153 * mesa and it seems to work fine. The choice is fairly arbitrary.
2154 */
2155 if (pipe.CommandStreamerStallEnable &&
2156 !pipe.RenderTargetCacheFlushEnable &&
2157 !pipe.DepthCacheFlushEnable &&
2158 !pipe.StallAtPixelScoreboard &&
2159 !pipe.PostSyncOperation &&
2160 !pipe.DepthStallEnable &&
2161 !pipe.DCFlushEnable)
2162 pipe.StallAtPixelScoreboard = true;
2163 }
2164
2165 /* If a render target flush was emitted, then we can toggle off the bit
2166 * saying that render target writes are ongoing.
2167 */
2168 if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
2169 bits &= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES);
2170
2171 if (GEN_IS_HASWELL) {
2172 /* Haswell needs addition work-arounds:
2173 *
2174 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
2175 *
2176 * Option 1:
2177 * PIPE_CONTROL command with the CS Stall and the required write
2178 * caches flushed with Post-SyncOperation as Write Immediate Data
2179 * followed by eight dummy MI_STORE_DATA_IMM (write to scratch
2180 * spce) commands.
2181 *
2182 * Example:
2183 * - Workload-1
2184 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2185 * Immediate Data, Required Write Cache Flush bits set)
2186 * - MI_STORE_DATA_IMM (8 times) (Dummy data, Scratch Address)
2187 * - Workload-2 (Can use the data produce or output by
2188 * Workload-1)
2189 *
2190 * Unfortunately, both the PRMs and the internal docs are a bit
2191 * out-of-date in this regard. What the windows driver does (and
2192 * this appears to actually work) is to emit a register read from the
2193 * memory address written by the pipe control above.
2194 *
2195 * What register we load into doesn't matter. We choose an indirect
2196 * rendering register because we know it always exists and it's one
2197 * of the first registers the command parser allows us to write. If
2198 * you don't have command parser support in your kernel (pre-4.2),
2199 * this will get turned into MI_NOOP and you won't get the
2200 * workaround. Unfortunately, there's just not much we can do in
2201 * that case. This register is perfectly safe to write since we
2202 * always re-load all of the indirect draw registers right before
2203 * 3DPRIMITIVE when needed anyway.
2204 */
2205 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
2206 lrm.RegisterAddress = 0x243C; /* GEN7_3DPRIM_START_INSTANCE */
2207 lrm.MemoryAddress = cmd_buffer->device->workaround_address;
2208 }
2209 }
2210
2211 bits &= ~(ANV_PIPE_FLUSH_BITS | ANV_PIPE_CS_STALL_BIT |
2212 ANV_PIPE_END_OF_PIPE_SYNC_BIT);
2213 }
2214
2215 if (bits & ANV_PIPE_INVALIDATE_BITS) {
2216 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2217 *
2218 * "If the VF Cache Invalidation Enable is set to a 1 in a
2219 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
2220 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
2221 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
2222 * a 1."
2223 *
2224 * This appears to hang Broadwell, so we restrict it to just gen9.
2225 */
2226 if (GEN_GEN == 9 && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT))
2227 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe);
2228
2229 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) {
2230 pipe.StateCacheInvalidationEnable =
2231 bits & ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
2232 pipe.ConstantCacheInvalidationEnable =
2233 bits & ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2234 pipe.VFCacheInvalidationEnable =
2235 bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2236 pipe.TextureCacheInvalidationEnable =
2237 bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2238 pipe.InstructionCacheInvalidateEnable =
2239 bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT;
2240
2241 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2242 *
2243 * "When VF Cache Invalidate is set “Post Sync Operation” must be
2244 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
2245 * “Write Timestamp”.
2246 */
2247 if (GEN_GEN == 9 && pipe.VFCacheInvalidationEnable) {
2248 pipe.PostSyncOperation = WriteImmediateData;
2249 pipe.Address = cmd_buffer->device->workaround_address;
2250 }
2251 }
2252
2253 #if GEN_GEN == 12
2254 if ((bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) &&
2255 cmd_buffer->device->info.has_aux_map) {
2256 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
2257 lri.RegisterOffset = GENX(GFX_CCS_AUX_INV_num);
2258 lri.DataDWord = 1;
2259 }
2260 }
2261 #endif
2262
2263 bits &= ~ANV_PIPE_INVALIDATE_BITS;
2264 }
2265
2266 cmd_buffer->state.pending_pipe_bits = bits;
2267 }
2268
2269 void genX(CmdPipelineBarrier)(
2270 VkCommandBuffer commandBuffer,
2271 VkPipelineStageFlags srcStageMask,
2272 VkPipelineStageFlags destStageMask,
2273 VkBool32 byRegion,
2274 uint32_t memoryBarrierCount,
2275 const VkMemoryBarrier* pMemoryBarriers,
2276 uint32_t bufferMemoryBarrierCount,
2277 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
2278 uint32_t imageMemoryBarrierCount,
2279 const VkImageMemoryBarrier* pImageMemoryBarriers)
2280 {
2281 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
2282
2283 /* XXX: Right now, we're really dumb and just flush whatever categories
2284 * the app asks for. One of these days we may make this a bit better
2285 * but right now that's all the hardware allows for in most areas.
2286 */
2287 VkAccessFlags src_flags = 0;
2288 VkAccessFlags dst_flags = 0;
2289
2290 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
2291 src_flags |= pMemoryBarriers[i].srcAccessMask;
2292 dst_flags |= pMemoryBarriers[i].dstAccessMask;
2293 }
2294
2295 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
2296 src_flags |= pBufferMemoryBarriers[i].srcAccessMask;
2297 dst_flags |= pBufferMemoryBarriers[i].dstAccessMask;
2298 }
2299
2300 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
2301 src_flags |= pImageMemoryBarriers[i].srcAccessMask;
2302 dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
2303 ANV_FROM_HANDLE(anv_image, image, pImageMemoryBarriers[i].image);
2304 const VkImageSubresourceRange *range =
2305 &pImageMemoryBarriers[i].subresourceRange;
2306
2307 uint32_t base_layer, layer_count;
2308 if (image->type == VK_IMAGE_TYPE_3D) {
2309 base_layer = 0;
2310 layer_count = anv_minify(image->extent.depth, range->baseMipLevel);
2311 } else {
2312 base_layer = range->baseArrayLayer;
2313 layer_count = anv_get_layerCount(image, range);
2314 }
2315
2316 if (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT) {
2317 transition_depth_buffer(cmd_buffer, image,
2318 base_layer, layer_count,
2319 pImageMemoryBarriers[i].oldLayout,
2320 pImageMemoryBarriers[i].newLayout);
2321 }
2322
2323 if (range->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT) {
2324 transition_stencil_buffer(cmd_buffer, image,
2325 range->baseMipLevel,
2326 anv_get_levelCount(image, range),
2327 base_layer, layer_count,
2328 pImageMemoryBarriers[i].oldLayout,
2329 pImageMemoryBarriers[i].newLayout);
2330 }
2331
2332 if (range->aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2333 VkImageAspectFlags color_aspects =
2334 anv_image_expand_aspects(image, range->aspectMask);
2335 uint32_t aspect_bit;
2336 anv_foreach_image_aspect_bit(aspect_bit, image, color_aspects) {
2337 transition_color_buffer(cmd_buffer, image, 1UL << aspect_bit,
2338 range->baseMipLevel,
2339 anv_get_levelCount(image, range),
2340 base_layer, layer_count,
2341 pImageMemoryBarriers[i].oldLayout,
2342 pImageMemoryBarriers[i].newLayout);
2343 }
2344 }
2345 }
2346
2347 cmd_buffer->state.pending_pipe_bits |=
2348 anv_pipe_flush_bits_for_access_flags(src_flags) |
2349 anv_pipe_invalidate_bits_for_access_flags(dst_flags);
2350 }
2351
2352 static void
2353 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer *cmd_buffer)
2354 {
2355 VkShaderStageFlags stages =
2356 cmd_buffer->state.gfx.pipeline->active_stages;
2357
2358 /* In order to avoid thrash, we assume that vertex and fragment stages
2359 * always exist. In the rare case where one is missing *and* the other
2360 * uses push concstants, this may be suboptimal. However, avoiding stalls
2361 * seems more important.
2362 */
2363 stages |= VK_SHADER_STAGE_FRAGMENT_BIT | VK_SHADER_STAGE_VERTEX_BIT;
2364
2365 if (stages == cmd_buffer->state.gfx.push_constant_stages)
2366 return;
2367
2368 #if GEN_GEN >= 8
2369 const unsigned push_constant_kb = 32;
2370 #elif GEN_IS_HASWELL
2371 const unsigned push_constant_kb = cmd_buffer->device->info.gt == 3 ? 32 : 16;
2372 #else
2373 const unsigned push_constant_kb = 16;
2374 #endif
2375
2376 const unsigned num_stages =
2377 util_bitcount(stages & VK_SHADER_STAGE_ALL_GRAPHICS);
2378 unsigned size_per_stage = push_constant_kb / num_stages;
2379
2380 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2381 * units of 2KB. Incidentally, these are the same platforms that have
2382 * 32KB worth of push constant space.
2383 */
2384 if (push_constant_kb == 32)
2385 size_per_stage &= ~1u;
2386
2387 uint32_t kb_used = 0;
2388 for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
2389 unsigned push_size = (stages & (1 << i)) ? size_per_stage : 0;
2390 anv_batch_emit(&cmd_buffer->batch,
2391 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
2392 alloc._3DCommandSubOpcode = 18 + i;
2393 alloc.ConstantBufferOffset = (push_size > 0) ? kb_used : 0;
2394 alloc.ConstantBufferSize = push_size;
2395 }
2396 kb_used += push_size;
2397 }
2398
2399 anv_batch_emit(&cmd_buffer->batch,
2400 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS), alloc) {
2401 alloc.ConstantBufferOffset = kb_used;
2402 alloc.ConstantBufferSize = push_constant_kb - kb_used;
2403 }
2404
2405 cmd_buffer->state.gfx.push_constant_stages = stages;
2406
2407 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2408 *
2409 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2410 * the next 3DPRIMITIVE command after programming the
2411 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2412 *
2413 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2414 * pipeline setup, we need to dirty push constants.
2415 */
2416 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
2417 }
2418
2419 static struct anv_address
2420 anv_descriptor_set_address(struct anv_cmd_buffer *cmd_buffer,
2421 struct anv_descriptor_set *set)
2422 {
2423 if (set->pool) {
2424 /* This is a normal descriptor set */
2425 return (struct anv_address) {
2426 .bo = set->pool->bo,
2427 .offset = set->desc_mem.offset,
2428 };
2429 } else {
2430 /* This is a push descriptor set. We have to flag it as used on the GPU
2431 * so that the next time we push descriptors, we grab a new memory.
2432 */
2433 struct anv_push_descriptor_set *push_set =
2434 (struct anv_push_descriptor_set *)set;
2435 push_set->set_used_on_gpu = true;
2436
2437 return (struct anv_address) {
2438 .bo = cmd_buffer->dynamic_state_stream.state_pool->block_pool.bo,
2439 .offset = set->desc_mem.offset,
2440 };
2441 }
2442 }
2443
2444 static VkResult
2445 emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
2446 struct anv_cmd_pipeline_state *pipe_state,
2447 struct anv_shader_bin *shader,
2448 struct anv_state *bt_state)
2449 {
2450 struct anv_subpass *subpass = cmd_buffer->state.subpass;
2451 uint32_t state_offset;
2452
2453 struct anv_pipeline_bind_map *map = &shader->bind_map;
2454 if (map->surface_count == 0) {
2455 *bt_state = (struct anv_state) { 0, };
2456 return VK_SUCCESS;
2457 }
2458
2459 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer,
2460 map->surface_count,
2461 &state_offset);
2462 uint32_t *bt_map = bt_state->map;
2463
2464 if (bt_state->map == NULL)
2465 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2466
2467 /* We only need to emit relocs if we're not using softpin. If we are using
2468 * softpin then we always keep all user-allocated memory objects resident.
2469 */
2470 const bool need_client_mem_relocs =
2471 !cmd_buffer->device->physical->use_softpin;
2472
2473 for (uint32_t s = 0; s < map->surface_count; s++) {
2474 struct anv_pipeline_binding *binding = &map->surface_to_descriptor[s];
2475
2476 struct anv_state surface_state;
2477
2478 switch (binding->set) {
2479 case ANV_DESCRIPTOR_SET_NULL:
2480 bt_map[s] = 0;
2481 break;
2482
2483 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS:
2484 /* Color attachment binding */
2485 assert(shader->stage == MESA_SHADER_FRAGMENT);
2486 if (binding->index < subpass->color_count) {
2487 const unsigned att =
2488 subpass->color_attachments[binding->index].attachment;
2489
2490 /* From the Vulkan 1.0.46 spec:
2491 *
2492 * "If any color or depth/stencil attachments are
2493 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2494 * attachments."
2495 */
2496 if (att == VK_ATTACHMENT_UNUSED) {
2497 surface_state = cmd_buffer->state.null_surface_state;
2498 } else {
2499 surface_state = cmd_buffer->state.attachments[att].color.state;
2500 }
2501 } else {
2502 surface_state = cmd_buffer->state.null_surface_state;
2503 }
2504
2505 assert(surface_state.map);
2506 bt_map[s] = surface_state.offset + state_offset;
2507 break;
2508
2509 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS: {
2510 struct anv_state surface_state =
2511 anv_cmd_buffer_alloc_surface_state(cmd_buffer);
2512
2513 struct anv_address constant_data = {
2514 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
2515 .offset = shader->constant_data.offset,
2516 };
2517 unsigned constant_data_size = shader->constant_data_size;
2518
2519 const enum isl_format format =
2520 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER);
2521 anv_fill_buffer_surface_state(cmd_buffer->device,
2522 surface_state, format,
2523 constant_data, constant_data_size, 1);
2524
2525 assert(surface_state.map);
2526 bt_map[s] = surface_state.offset + state_offset;
2527 add_surface_reloc(cmd_buffer, surface_state, constant_data);
2528 break;
2529 }
2530
2531 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS: {
2532 /* This is always the first binding for compute shaders */
2533 assert(shader->stage == MESA_SHADER_COMPUTE && s == 0);
2534
2535 struct anv_state surface_state =
2536 anv_cmd_buffer_alloc_surface_state(cmd_buffer);
2537
2538 const enum isl_format format =
2539 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER);
2540 anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
2541 format,
2542 cmd_buffer->state.compute.num_workgroups,
2543 12, 1);
2544
2545 assert(surface_state.map);
2546 bt_map[s] = surface_state.offset + state_offset;
2547 if (need_client_mem_relocs) {
2548 add_surface_reloc(cmd_buffer, surface_state,
2549 cmd_buffer->state.compute.num_workgroups);
2550 }
2551 break;
2552 }
2553
2554 case ANV_DESCRIPTOR_SET_DESCRIPTORS: {
2555 /* This is a descriptor set buffer so the set index is actually
2556 * given by binding->binding. (Yes, that's confusing.)
2557 */
2558 struct anv_descriptor_set *set =
2559 pipe_state->descriptors[binding->index];
2560 assert(set->desc_mem.alloc_size);
2561 assert(set->desc_surface_state.alloc_size);
2562 bt_map[s] = set->desc_surface_state.offset + state_offset;
2563 add_surface_reloc(cmd_buffer, set->desc_surface_state,
2564 anv_descriptor_set_address(cmd_buffer, set));
2565 break;
2566 }
2567
2568 default: {
2569 assert(binding->set < MAX_SETS);
2570 const struct anv_descriptor *desc =
2571 &pipe_state->descriptors[binding->set]->descriptors[binding->index];
2572
2573 switch (desc->type) {
2574 case VK_DESCRIPTOR_TYPE_SAMPLER:
2575 /* Nothing for us to do here */
2576 continue;
2577
2578 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
2579 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE: {
2580 if (desc->image_view) {
2581 struct anv_surface_state sstate =
2582 (desc->layout == VK_IMAGE_LAYOUT_GENERAL) ?
2583 desc->image_view->planes[binding->plane].general_sampler_surface_state :
2584 desc->image_view->planes[binding->plane].optimal_sampler_surface_state;
2585 surface_state = sstate.state;
2586 assert(surface_state.alloc_size);
2587 if (need_client_mem_relocs)
2588 add_surface_state_relocs(cmd_buffer, sstate);
2589 } else {
2590 surface_state = cmd_buffer->device->null_surface_state;
2591 }
2592 break;
2593 }
2594 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
2595 assert(shader->stage == MESA_SHADER_FRAGMENT);
2596 assert(desc->image_view != NULL);
2597 if ((desc->image_view->aspect_mask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0) {
2598 /* For depth and stencil input attachments, we treat it like any
2599 * old texture that a user may have bound.
2600 */
2601 assert(desc->image_view->n_planes == 1);
2602 struct anv_surface_state sstate =
2603 (desc->layout == VK_IMAGE_LAYOUT_GENERAL) ?
2604 desc->image_view->planes[0].general_sampler_surface_state :
2605 desc->image_view->planes[0].optimal_sampler_surface_state;
2606 surface_state = sstate.state;
2607 assert(surface_state.alloc_size);
2608 if (need_client_mem_relocs)
2609 add_surface_state_relocs(cmd_buffer, sstate);
2610 } else {
2611 /* For color input attachments, we create the surface state at
2612 * vkBeginRenderPass time so that we can include aux and clear
2613 * color information.
2614 */
2615 assert(binding->input_attachment_index < subpass->input_count);
2616 const unsigned subpass_att = binding->input_attachment_index;
2617 const unsigned att = subpass->input_attachments[subpass_att].attachment;
2618 surface_state = cmd_buffer->state.attachments[att].input.state;
2619 }
2620 break;
2621
2622 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE: {
2623 if (desc->image_view) {
2624 struct anv_surface_state sstate = (binding->write_only)
2625 ? desc->image_view->planes[binding->plane].writeonly_storage_surface_state
2626 : desc->image_view->planes[binding->plane].storage_surface_state;
2627 surface_state = sstate.state;
2628 assert(surface_state.alloc_size);
2629 if (need_client_mem_relocs)
2630 add_surface_state_relocs(cmd_buffer, sstate);
2631 } else {
2632 surface_state = cmd_buffer->device->null_surface_state;
2633 }
2634 break;
2635 }
2636
2637 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
2638 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
2639 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
2640 if (desc->buffer_view) {
2641 surface_state = desc->buffer_view->surface_state;
2642 assert(surface_state.alloc_size);
2643 if (need_client_mem_relocs) {
2644 add_surface_reloc(cmd_buffer, surface_state,
2645 desc->buffer_view->address);
2646 }
2647 } else {
2648 surface_state = cmd_buffer->device->null_surface_state;
2649 }
2650 break;
2651
2652 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
2653 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: {
2654 if (desc->buffer) {
2655 /* Compute the offset within the buffer */
2656 struct anv_push_constants *push =
2657 &cmd_buffer->state.push_constants[shader->stage];
2658
2659 uint32_t dynamic_offset =
2660 push->dynamic_offsets[binding->dynamic_offset_index];
2661 uint64_t offset = desc->offset + dynamic_offset;
2662 /* Clamp to the buffer size */
2663 offset = MIN2(offset, desc->buffer->size);
2664 /* Clamp the range to the buffer size */
2665 uint32_t range = MIN2(desc->range, desc->buffer->size - offset);
2666
2667 /* Align the range for consistency */
2668 if (desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC)
2669 range = align_u32(range, ANV_UBO_ALIGNMENT);
2670
2671 struct anv_address address =
2672 anv_address_add(desc->buffer->address, offset);
2673
2674 surface_state =
2675 anv_state_stream_alloc(&cmd_buffer->surface_state_stream, 64, 64);
2676 enum isl_format format =
2677 anv_isl_format_for_descriptor_type(desc->type);
2678
2679 anv_fill_buffer_surface_state(cmd_buffer->device, surface_state,
2680 format, address, range, 1);
2681 if (need_client_mem_relocs)
2682 add_surface_reloc(cmd_buffer, surface_state, address);
2683 } else {
2684 surface_state = cmd_buffer->device->null_surface_state;
2685 }
2686 break;
2687 }
2688
2689 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
2690 if (desc->buffer_view) {
2691 surface_state = (binding->write_only)
2692 ? desc->buffer_view->writeonly_storage_surface_state
2693 : desc->buffer_view->storage_surface_state;
2694 assert(surface_state.alloc_size);
2695 if (need_client_mem_relocs) {
2696 add_surface_reloc(cmd_buffer, surface_state,
2697 desc->buffer_view->address);
2698 }
2699 } else {
2700 surface_state = cmd_buffer->device->null_surface_state;
2701 }
2702 break;
2703
2704 default:
2705 assert(!"Invalid descriptor type");
2706 continue;
2707 }
2708 assert(surface_state.map);
2709 bt_map[s] = surface_state.offset + state_offset;
2710 break;
2711 }
2712 }
2713 }
2714
2715 return VK_SUCCESS;
2716 }
2717
2718 static VkResult
2719 emit_samplers(struct anv_cmd_buffer *cmd_buffer,
2720 struct anv_cmd_pipeline_state *pipe_state,
2721 struct anv_shader_bin *shader,
2722 struct anv_state *state)
2723 {
2724 struct anv_pipeline_bind_map *map = &shader->bind_map;
2725 if (map->sampler_count == 0) {
2726 *state = (struct anv_state) { 0, };
2727 return VK_SUCCESS;
2728 }
2729
2730 uint32_t size = map->sampler_count * 16;
2731 *state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 32);
2732
2733 if (state->map == NULL)
2734 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2735
2736 for (uint32_t s = 0; s < map->sampler_count; s++) {
2737 struct anv_pipeline_binding *binding = &map->sampler_to_descriptor[s];
2738 const struct anv_descriptor *desc =
2739 &pipe_state->descriptors[binding->set]->descriptors[binding->index];
2740
2741 if (desc->type != VK_DESCRIPTOR_TYPE_SAMPLER &&
2742 desc->type != VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
2743 continue;
2744
2745 struct anv_sampler *sampler = desc->sampler;
2746
2747 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2748 * happens to be zero.
2749 */
2750 if (sampler == NULL)
2751 continue;
2752
2753 memcpy(state->map + (s * 16),
2754 sampler->state[binding->plane], sizeof(sampler->state[0]));
2755 }
2756
2757 return VK_SUCCESS;
2758 }
2759
2760 static uint32_t
2761 flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer,
2762 struct anv_cmd_pipeline_state *pipe_state,
2763 struct anv_shader_bin **shaders,
2764 uint32_t num_shaders)
2765 {
2766 const VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty;
2767 VkShaderStageFlags flushed = 0;
2768
2769 VkResult result = VK_SUCCESS;
2770 for (uint32_t i = 0; i < num_shaders; i++) {
2771 if (!shaders[i])
2772 continue;
2773
2774 gl_shader_stage stage = shaders[i]->stage;
2775 VkShaderStageFlags vk_stage = mesa_to_vk_shader_stage(stage);
2776 if ((vk_stage & dirty) == 0)
2777 continue;
2778
2779 result = emit_samplers(cmd_buffer, pipe_state, shaders[i],
2780 &cmd_buffer->state.samplers[stage]);
2781 if (result != VK_SUCCESS)
2782 break;
2783 result = emit_binding_table(cmd_buffer, pipe_state, shaders[i],
2784 &cmd_buffer->state.binding_tables[stage]);
2785 if (result != VK_SUCCESS)
2786 break;
2787
2788 flushed |= vk_stage;
2789 }
2790
2791 if (result != VK_SUCCESS) {
2792 assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
2793
2794 result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
2795 if (result != VK_SUCCESS)
2796 return 0;
2797
2798 /* Re-emit state base addresses so we get the new surface state base
2799 * address before we start emitting binding tables etc.
2800 */
2801 genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
2802
2803 /* Re-emit all active binding tables */
2804 flushed = 0;
2805
2806 for (uint32_t i = 0; i < num_shaders; i++) {
2807 if (!shaders[i])
2808 continue;
2809
2810 gl_shader_stage stage = shaders[i]->stage;
2811
2812 result = emit_samplers(cmd_buffer, pipe_state, shaders[i],
2813 &cmd_buffer->state.samplers[stage]);
2814 if (result != VK_SUCCESS) {
2815 anv_batch_set_error(&cmd_buffer->batch, result);
2816 return 0;
2817 }
2818 result = emit_binding_table(cmd_buffer, pipe_state, shaders[i],
2819 &cmd_buffer->state.binding_tables[stage]);
2820 if (result != VK_SUCCESS) {
2821 anv_batch_set_error(&cmd_buffer->batch, result);
2822 return 0;
2823 }
2824
2825 flushed |= mesa_to_vk_shader_stage(stage);
2826 }
2827 }
2828
2829 cmd_buffer->state.descriptors_dirty &= ~flushed;
2830
2831 return flushed;
2832 }
2833
2834 static void
2835 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
2836 uint32_t stages)
2837 {
2838 static const uint32_t sampler_state_opcodes[] = {
2839 [MESA_SHADER_VERTEX] = 43,
2840 [MESA_SHADER_TESS_CTRL] = 44, /* HS */
2841 [MESA_SHADER_TESS_EVAL] = 45, /* DS */
2842 [MESA_SHADER_GEOMETRY] = 46,
2843 [MESA_SHADER_FRAGMENT] = 47,
2844 [MESA_SHADER_COMPUTE] = 0,
2845 };
2846
2847 static const uint32_t binding_table_opcodes[] = {
2848 [MESA_SHADER_VERTEX] = 38,
2849 [MESA_SHADER_TESS_CTRL] = 39,
2850 [MESA_SHADER_TESS_EVAL] = 40,
2851 [MESA_SHADER_GEOMETRY] = 41,
2852 [MESA_SHADER_FRAGMENT] = 42,
2853 [MESA_SHADER_COMPUTE] = 0,
2854 };
2855
2856 anv_foreach_stage(s, stages) {
2857 assert(s < ARRAY_SIZE(binding_table_opcodes));
2858 assert(binding_table_opcodes[s] > 0);
2859
2860 if (cmd_buffer->state.samplers[s].alloc_size > 0) {
2861 anv_batch_emit(&cmd_buffer->batch,
2862 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ssp) {
2863 ssp._3DCommandSubOpcode = sampler_state_opcodes[s];
2864 ssp.PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset;
2865 }
2866 }
2867
2868 /* Always emit binding table pointers if we're asked to, since on SKL
2869 * this is what flushes push constants. */
2870 anv_batch_emit(&cmd_buffer->batch,
2871 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), btp) {
2872 btp._3DCommandSubOpcode = binding_table_opcodes[s];
2873 btp.PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset;
2874 }
2875 }
2876 }
2877
2878 static struct anv_address
2879 get_push_range_address(struct anv_cmd_buffer *cmd_buffer,
2880 gl_shader_stage stage,
2881 const struct anv_push_range *range)
2882 {
2883 const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
2884 switch (range->set) {
2885 case ANV_DESCRIPTOR_SET_DESCRIPTORS: {
2886 /* This is a descriptor set buffer so the set index is
2887 * actually given by binding->binding. (Yes, that's
2888 * confusing.)
2889 */
2890 struct anv_descriptor_set *set =
2891 gfx_state->base.descriptors[range->index];
2892 return anv_descriptor_set_address(cmd_buffer, set);
2893 }
2894
2895 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS: {
2896 struct anv_state state =
2897 anv_cmd_buffer_push_constants(cmd_buffer, stage);
2898 return (struct anv_address) {
2899 .bo = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
2900 .offset = state.offset,
2901 };
2902 }
2903
2904 default: {
2905 assert(range->set < MAX_SETS);
2906 struct anv_descriptor_set *set =
2907 gfx_state->base.descriptors[range->set];
2908 const struct anv_descriptor *desc =
2909 &set->descriptors[range->index];
2910
2911 if (desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
2912 if (desc->buffer_view)
2913 return desc->buffer_view->address;
2914 } else {
2915 assert(desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC);
2916 if (desc->buffer) {
2917 struct anv_push_constants *push =
2918 &cmd_buffer->state.push_constants[stage];
2919 uint32_t dynamic_offset =
2920 push->dynamic_offsets[range->dynamic_offset_index];
2921 return anv_address_add(desc->buffer->address,
2922 desc->offset + dynamic_offset);
2923 }
2924 }
2925
2926 /* For NULL UBOs, we just return an address in the workaround BO. We do
2927 * writes to it for workarounds but always at the bottom. The higher
2928 * bytes should be all zeros.
2929 */
2930 assert(range->length * 32 <= 2048);
2931 return (struct anv_address) {
2932 .bo = cmd_buffer->device->workaround_bo,
2933 .offset = 1024,
2934 };
2935 }
2936 }
2937 }
2938
2939
2940 /** Returns the size in bytes of the bound buffer
2941 *
2942 * The range is relative to the start of the buffer, not the start of the
2943 * range. The returned range may be smaller than
2944 *
2945 * (range->start + range->length) * 32;
2946 */
2947 static uint32_t
2948 get_push_range_bound_size(struct anv_cmd_buffer *cmd_buffer,
2949 gl_shader_stage stage,
2950 const struct anv_push_range *range)
2951 {
2952 assert(stage != MESA_SHADER_COMPUTE);
2953 const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
2954 switch (range->set) {
2955 case ANV_DESCRIPTOR_SET_DESCRIPTORS: {
2956 struct anv_descriptor_set *set =
2957 gfx_state->base.descriptors[range->index];
2958 assert(range->start * 32 < set->desc_mem.alloc_size);
2959 assert((range->start + range->length) * 32 <= set->desc_mem.alloc_size);
2960 return set->desc_mem.alloc_size;
2961 }
2962
2963 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS:
2964 return (range->start + range->length) * 32;
2965
2966 default: {
2967 assert(range->set < MAX_SETS);
2968 struct anv_descriptor_set *set =
2969 gfx_state->base.descriptors[range->set];
2970 const struct anv_descriptor *desc =
2971 &set->descriptors[range->index];
2972
2973 if (desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER) {
2974 if (!desc->buffer_view)
2975 return 0;
2976
2977 if (range->start * 32 > desc->buffer_view->range)
2978 return 0;
2979
2980 return desc->buffer_view->range;
2981 } else {
2982 if (!desc->buffer)
2983 return 0;
2984
2985 assert(desc->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC);
2986 /* Compute the offset within the buffer */
2987 struct anv_push_constants *push =
2988 &cmd_buffer->state.push_constants[stage];
2989 uint32_t dynamic_offset =
2990 push->dynamic_offsets[range->dynamic_offset_index];
2991 uint64_t offset = desc->offset + dynamic_offset;
2992 /* Clamp to the buffer size */
2993 offset = MIN2(offset, desc->buffer->size);
2994 /* Clamp the range to the buffer size */
2995 uint32_t bound_range = MIN2(desc->range, desc->buffer->size - offset);
2996
2997 /* Align the range for consistency */
2998 bound_range = align_u32(bound_range, ANV_UBO_ALIGNMENT);
2999
3000 return bound_range;
3001 }
3002 }
3003 }
3004 }
3005
3006 static void
3007 cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer,
3008 gl_shader_stage stage,
3009 struct anv_address *buffers,
3010 unsigned buffer_count)
3011 {
3012 const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
3013 const struct anv_graphics_pipeline *pipeline = gfx_state->pipeline;
3014
3015 static const uint32_t push_constant_opcodes[] = {
3016 [MESA_SHADER_VERTEX] = 21,
3017 [MESA_SHADER_TESS_CTRL] = 25, /* HS */
3018 [MESA_SHADER_TESS_EVAL] = 26, /* DS */
3019 [MESA_SHADER_GEOMETRY] = 22,
3020 [MESA_SHADER_FRAGMENT] = 23,
3021 [MESA_SHADER_COMPUTE] = 0,
3022 };
3023
3024 assert(stage < ARRAY_SIZE(push_constant_opcodes));
3025 assert(push_constant_opcodes[stage] > 0);
3026
3027 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS), c) {
3028 c._3DCommandSubOpcode = push_constant_opcodes[stage];
3029
3030 if (anv_pipeline_has_stage(pipeline, stage)) {
3031 const struct anv_pipeline_bind_map *bind_map =
3032 &pipeline->shaders[stage]->bind_map;
3033
3034 #if GEN_GEN >= 9
3035 /* This field exists since Gen8. However, the Broadwell PRM says:
3036 *
3037 * "Constant Buffer Object Control State must be always programmed
3038 * to zero."
3039 *
3040 * This restriction does not exist on any newer platforms.
3041 *
3042 * We only have one MOCS field for the whole packet, not one per
3043 * buffer. We could go out of our way here to walk over all of the
3044 * buffers and see if any of them are used externally and use the
3045 * external MOCS. However, the notion that someone would use the
3046 * same bit of memory for both scanout and a UBO is nuts. Let's not
3047 * bother and assume it's all internal.
3048 */
3049 c.MOCS = cmd_buffer->device->isl_dev.mocs.internal;
3050 #endif
3051
3052 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3053 /* The Skylake PRM contains the following restriction:
3054 *
3055 * "The driver must ensure The following case does not occur
3056 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3057 * buffer 3 read length equal to zero committed followed by a
3058 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3059 * zero committed."
3060 *
3061 * To avoid this, we program the buffers in the highest slots.
3062 * This way, slot 0 is only used if slot 3 is also used.
3063 */
3064 assert(buffer_count <= 4);
3065 const unsigned shift = 4 - buffer_count;
3066 for (unsigned i = 0; i < buffer_count; i++) {
3067 const struct anv_push_range *range = &bind_map->push_ranges[i];
3068
3069 /* At this point we only have non-empty ranges */
3070 assert(range->length > 0);
3071
3072 /* For Ivy Bridge, make sure we only set the first range (actual
3073 * push constants)
3074 */
3075 assert((GEN_GEN >= 8 || GEN_IS_HASWELL) || i == 0);
3076
3077 c.ConstantBody.ReadLength[i + shift] = range->length;
3078 c.ConstantBody.Buffer[i + shift] =
3079 anv_address_add(buffers[i], range->start * 32);
3080 }
3081 #else
3082 /* For Ivy Bridge, push constants are relative to dynamic state
3083 * base address and we only ever push actual push constants.
3084 */
3085 if (bind_map->push_ranges[0].length > 0) {
3086 assert(buffer_count == 1);
3087 assert(bind_map->push_ranges[0].set ==
3088 ANV_DESCRIPTOR_SET_PUSH_CONSTANTS);
3089 assert(buffers[0].bo ==
3090 cmd_buffer->device->dynamic_state_pool.block_pool.bo);
3091 c.ConstantBody.ReadLength[0] = bind_map->push_ranges[0].length;
3092 c.ConstantBody.Buffer[0].bo = NULL;
3093 c.ConstantBody.Buffer[0].offset = buffers[0].offset;
3094 }
3095 assert(bind_map->push_ranges[1].length == 0);
3096 assert(bind_map->push_ranges[2].length == 0);
3097 assert(bind_map->push_ranges[3].length == 0);
3098 #endif
3099 }
3100 }
3101 }
3102
3103 #if GEN_GEN >= 12
3104 static void
3105 cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer *cmd_buffer,
3106 uint32_t shader_mask,
3107 struct anv_address *buffers,
3108 uint32_t buffer_count)
3109 {
3110 if (buffer_count == 0) {
3111 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_ALL), c) {
3112 c.ShaderUpdateEnable = shader_mask;
3113 c.MOCS = cmd_buffer->device->isl_dev.mocs.internal;
3114 }
3115 return;
3116 }
3117
3118 const struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
3119 const struct anv_graphics_pipeline *pipeline = gfx_state->pipeline;
3120
3121 static const uint32_t push_constant_opcodes[] = {
3122 [MESA_SHADER_VERTEX] = 21,
3123 [MESA_SHADER_TESS_CTRL] = 25, /* HS */
3124 [MESA_SHADER_TESS_EVAL] = 26, /* DS */
3125 [MESA_SHADER_GEOMETRY] = 22,
3126 [MESA_SHADER_FRAGMENT] = 23,
3127 [MESA_SHADER_COMPUTE] = 0,
3128 };
3129
3130 gl_shader_stage stage = vk_to_mesa_shader_stage(shader_mask);
3131 assert(stage < ARRAY_SIZE(push_constant_opcodes));
3132 assert(push_constant_opcodes[stage] > 0);
3133
3134 const struct anv_pipeline_bind_map *bind_map =
3135 &pipeline->shaders[stage]->bind_map;
3136
3137 uint32_t *dw;
3138 const uint32_t buffer_mask = (1 << buffer_count) - 1;
3139 const uint32_t num_dwords = 2 + 2 * buffer_count;
3140
3141 dw = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
3142 GENX(3DSTATE_CONSTANT_ALL),
3143 .ShaderUpdateEnable = shader_mask,
3144 .PointerBufferMask = buffer_mask,
3145 .MOCS = cmd_buffer->device->isl_dev.mocs.internal);
3146
3147 for (int i = 0; i < buffer_count; i++) {
3148 const struct anv_push_range *range = &bind_map->push_ranges[i];
3149 GENX(3DSTATE_CONSTANT_ALL_DATA_pack)(
3150 &cmd_buffer->batch, dw + 2 + i * 2,
3151 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA)) {
3152 .PointerToConstantBuffer =
3153 anv_address_add(buffers[i], range->start * 32),
3154 .ConstantBufferReadLength = range->length,
3155 });
3156 }
3157 }
3158 #endif
3159