2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
,
37 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
83 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
84 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
85 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
86 sba
.GeneralStateBaseAddressModifyEnable
= true;
88 sba
.SurfaceStateBaseAddress
=
89 anv_cmd_buffer_surface_base_address(cmd_buffer
);
90 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
91 sba
.SurfaceStateBaseAddressModifyEnable
= true;
93 sba
.DynamicStateBaseAddress
=
94 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
95 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
96 sba
.DynamicStateBaseAddressModifyEnable
= true;
98 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
99 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
100 sba
.IndirectObjectBaseAddressModifyEnable
= true;
102 sba
.InstructionBaseAddress
=
103 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
104 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
105 sba
.InstructionBaseAddressModifyEnable
= true;
108 /* Broadwell requires that we specify a buffer size for a bunch of
109 * these fields. However, since we will be growing the BO's live, we
110 * just set them all to the maximum.
112 sba
.GeneralStateBufferSize
= 0xfffff;
113 sba
.GeneralStateBufferSizeModifyEnable
= true;
114 sba
.DynamicStateBufferSize
= 0xfffff;
115 sba
.DynamicStateBufferSizeModifyEnable
= true;
116 sba
.IndirectObjectBufferSize
= 0xfffff;
117 sba
.IndirectObjectBufferSizeModifyEnable
= true;
118 sba
.InstructionBufferSize
= 0xfffff;
119 sba
.InstructionBuffersizeModifyEnable
= true;
123 /* After re-setting the surface state base address, we have to do some
124 * cache flusing so that the sampler engine will pick up the new
125 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
126 * Shared Function > 3D Sampler > State > State Caching (page 96):
128 * Coherency with system memory in the state cache, like the texture
129 * cache is handled partially by software. It is expected that the
130 * command stream or shader will issue Cache Flush operation or
131 * Cache_Flush sampler message to ensure that the L1 cache remains
132 * coherent with system memory.
136 * Whenever the value of the Dynamic_State_Base_Addr,
137 * Surface_State_Base_Addr are altered, the L1 state cache must be
138 * invalidated to ensure the new surface or sampler state is fetched
139 * from system memory.
141 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
142 * which, according the PIPE_CONTROL instruction documentation in the
145 * Setting this bit is independent of any other bit in this packet.
146 * This bit controls the invalidation of the L1 and L2 state caches
147 * at the top of the pipe i.e. at the parsing time.
149 * Unfortunately, experimentation seems to indicate that state cache
150 * invalidation through a PIPE_CONTROL does nothing whatsoever in
151 * regards to surface state and binding tables. In stead, it seems that
152 * invalidating the texture cache is what is actually needed.
154 * XXX: As far as we have been able to determine through
155 * experimentation, shows that flush the texture cache appears to be
156 * sufficient. The theory here is that all of the sampling/rendering
157 * units cache the binding table in the texture cache. However, we have
158 * yet to be able to actually confirm this.
160 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
161 pc
.TextureCacheInvalidationEnable
= true;
162 pc
.ConstantCacheInvalidationEnable
= true;
163 pc
.StateCacheInvalidationEnable
= true;
168 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
169 struct anv_state state
,
170 struct anv_bo
*bo
, uint32_t offset
)
172 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
175 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
176 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
177 if (result
!= VK_SUCCESS
)
178 anv_batch_set_error(&cmd_buffer
->batch
, result
);
182 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
183 const struct anv_image_view
*image_view
,
184 const uint32_t plane
,
185 struct anv_surface_state state
)
187 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
188 const struct anv_image
*image
= image_view
->image
;
189 uint32_t image_plane
= image_view
->planes
[plane
].image_plane
;
191 add_surface_state_reloc(cmd_buffer
, state
.state
,
192 image
->planes
[image_plane
].bo
, state
.address
);
194 if (state
.aux_address
) {
196 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
197 &cmd_buffer
->pool
->alloc
,
198 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
199 image
->planes
[image_plane
].bo
, state
.aux_address
);
200 if (result
!= VK_SUCCESS
)
201 anv_batch_set_error(&cmd_buffer
->batch
, result
);
204 if (state
.clear_address
) {
206 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
207 &cmd_buffer
->pool
->alloc
,
209 isl_dev
->ss
.clear_color_state_offset
,
210 image
->planes
[image_plane
].bo
, state
.clear_address
);
211 if (result
!= VK_SUCCESS
)
212 anv_batch_set_error(&cmd_buffer
->batch
, result
);
217 color_attachment_compute_aux_usage(struct anv_device
* device
,
218 struct anv_cmd_state
* cmd_state
,
219 uint32_t att
, VkRect2D render_area
,
220 union isl_color_value
*fast_clear_color
)
222 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
223 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
225 assert(iview
->n_planes
== 1);
227 if (iview
->planes
[0].isl
.base_array_layer
>=
228 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
229 iview
->planes
[0].isl
.base_level
)) {
230 /* There is no aux buffer which corresponds to the level and layer(s)
233 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
234 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
235 att_state
->fast_clear
= false;
239 att_state
->aux_usage
=
240 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
241 VK_IMAGE_ASPECT_COLOR_BIT
,
242 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
244 /* If we don't have aux, then we should have returned early in the layer
245 * check above. If we got here, we must have something.
247 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
249 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
250 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
251 att_state
->input_aux_usage
= att_state
->aux_usage
;
253 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
255 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
256 * setting is only allowed if Surface Format supported for Fast
257 * Clear. In addition, if the surface is bound to the sampling
258 * engine, Surface Format must be supported for Render Target
259 * Compression for surfaces bound to the sampling engine."
261 * In other words, we can only sample from a fast-cleared image if it
262 * also supports color compression.
264 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
265 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
267 /* While fast-clear resolves and partial resolves are fairly cheap in the
268 * case where you render to most of the pixels, full resolves are not
269 * because they potentially involve reading and writing the entire
270 * framebuffer. If we can't texture with CCS_E, we should leave it off and
271 * limit ourselves to fast clears.
273 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
274 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
275 anv_perf_warn(device
->instance
, iview
->image
,
276 "Not temporarily enabling CCS_E.");
279 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
283 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
284 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
286 union isl_color_value clear_color
= {};
287 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
289 att_state
->clear_color_is_zero_one
=
290 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
291 att_state
->clear_color_is_zero
=
292 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
294 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
295 /* Start by getting the fast clear type. We use the first subpass
296 * layout here because we don't want to fast-clear if the first subpass
297 * to use the attachment can't handle fast-clears.
299 enum anv_fast_clear_type fast_clear_type
=
300 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
301 VK_IMAGE_ASPECT_COLOR_BIT
,
302 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
303 switch (fast_clear_type
) {
304 case ANV_FAST_CLEAR_NONE
:
305 att_state
->fast_clear
= false;
307 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
308 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
310 case ANV_FAST_CLEAR_ANY
:
311 att_state
->fast_clear
= true;
315 /* Potentially, we could do partial fast-clears but doing so has crazy
316 * alignment restrictions. It's easier to just restrict to full size
317 * fast clears for now.
319 if (render_area
.offset
.x
!= 0 ||
320 render_area
.offset
.y
!= 0 ||
321 render_area
.extent
.width
!= iview
->extent
.width
||
322 render_area
.extent
.height
!= iview
->extent
.height
)
323 att_state
->fast_clear
= false;
325 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
326 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
327 att_state
->fast_clear
= false;
329 /* We only allow fast clears to the first slice of an image (level 0,
330 * layer 0) and only for the entire slice. This guarantees us that, at
331 * any given time, there is only one clear color on any given image at
332 * any given time. At the time of our testing (Jan 17, 2018), there
333 * were no known applications which would benefit from fast-clearing
334 * more than just the first slice.
336 if (att_state
->fast_clear
&&
337 (iview
->planes
[0].isl
.base_level
> 0 ||
338 iview
->planes
[0].isl
.base_array_layer
> 0)) {
339 anv_perf_warn(device
->instance
, iview
->image
,
340 "Rendering with multi-lod or multi-layer framebuffer "
341 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
342 "baseArrayLayer > 0. Not fast clearing.");
343 att_state
->fast_clear
= false;
344 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
345 anv_perf_warn(device
->instance
, iview
->image
,
346 "Rendering to a multi-layer framebuffer with "
347 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
350 if (att_state
->fast_clear
)
351 *fast_clear_color
= clear_color
;
353 att_state
->fast_clear
= false;
358 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
359 struct anv_cmd_state
*cmd_state
,
360 uint32_t att
, VkRect2D render_area
)
362 struct anv_render_pass_attachment
*pass_att
=
363 &cmd_state
->pass
->attachments
[att
];
364 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
365 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
367 /* These will be initialized after the first subpass transition. */
368 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
369 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
372 /* We don't do any HiZ or depth fast-clears on gen7 yet */
373 att_state
->fast_clear
= false;
377 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
378 /* If we're just clearing stencil, we can always HiZ clear */
379 att_state
->fast_clear
= true;
383 /* Default to false for now */
384 att_state
->fast_clear
= false;
386 /* We must have depth in order to have HiZ */
387 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
390 const enum isl_aux_usage first_subpass_aux_usage
=
391 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
392 VK_IMAGE_ASPECT_DEPTH_BIT
,
393 pass_att
->first_subpass_layout
);
394 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
397 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
398 iview
->planes
[0].isl
.format
,
399 iview
->image
->samples
,
400 render_area
.offset
.x
,
401 render_area
.offset
.y
,
402 render_area
.offset
.x
+
403 render_area
.extent
.width
,
404 render_area
.offset
.y
+
405 render_area
.extent
.height
))
408 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
411 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
412 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
413 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
414 * only supports returning 0.0f. Gens prior to gen8 do not support this
420 /* If we got here, then we can fast clear */
421 att_state
->fast_clear
= true;
425 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
427 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
430 /* We only allocate input attachment states for color surfaces. Compression
431 * is not yet enabled for depth textures and stencil doesn't allow
432 * compression so we can just use the texture surface state from the view.
434 return vk_format_is_color(att
->format
);
437 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
438 * the initial layout is undefined, the HiZ buffer and depth buffer will
439 * represent the same data at the end of this operation.
442 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
443 const struct anv_image
*image
,
444 VkImageLayout initial_layout
,
445 VkImageLayout final_layout
)
447 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
448 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
449 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
450 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
451 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
452 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
454 enum isl_aux_op hiz_op
;
455 if (hiz_enabled
&& !enable_hiz
) {
456 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
457 } else if (!hiz_enabled
&& enable_hiz
) {
458 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
460 assert(hiz_enabled
== enable_hiz
);
461 /* If the same buffer will be used, no resolves are necessary. */
462 hiz_op
= ISL_AUX_OP_NONE
;
465 if (hiz_op
!= ISL_AUX_OP_NONE
)
466 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
470 #define MI_PREDICATE_SRC0 0x2400
471 #define MI_PREDICATE_SRC1 0x2408
474 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
475 const struct anv_image
*image
,
476 VkImageAspectFlagBits aspect
,
478 uint32_t base_layer
, uint32_t layer_count
,
481 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
483 /* We only have compression tracking for CCS_E */
484 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
487 for (uint32_t a
= 0; a
< layer_count
; a
++) {
488 uint32_t layer
= base_layer
+ a
;
489 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
490 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
493 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
499 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
500 const struct anv_image
*image
,
501 VkImageAspectFlagBits aspect
,
502 enum anv_fast_clear_type fast_clear
)
504 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
505 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
507 sdi
.ImmediateData
= fast_clear
;
510 /* Whenever we have fast-clear, we consider that slice to be compressed.
511 * This makes building predicates much easier.
513 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
514 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
517 #if GEN_IS_HASWELL || GEN_GEN >= 8
518 static inline uint32_t
519 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
521 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
523 .Operand1
= operand1
,
524 .Operand2
= operand2
,
528 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
534 #define CS_GPR(n) (0x2600 + (n) * 8)
536 /* This is only really practical on haswell and above because it requires
537 * MI math in order to get it correct.
539 #if GEN_GEN >= 8 || GEN_IS_HASWELL
541 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
542 const struct anv_image
*image
,
543 VkImageAspectFlagBits aspect
,
544 uint32_t level
, uint32_t array_layer
,
545 enum isl_aux_op resolve_op
,
546 enum anv_fast_clear_type fast_clear_supported
)
548 struct anv_address fast_clear_type_addr
=
549 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
551 /* Name some registers */
552 const int image_fc_reg
= MI_ALU_REG0
;
553 const int fc_imm_reg
= MI_ALU_REG1
;
554 const int pred_reg
= MI_ALU_REG2
;
558 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
559 /* In this case, we're doing a full resolve which means we want the
560 * resolve to happen if any compression (including fast-clears) is
563 * In order to simplify the logic a bit, we make the assumption that,
564 * if the first slice has been fast-cleared, it is also marked as
565 * compressed. See also set_image_fast_clear_state.
567 struct anv_address compression_state_addr
=
568 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
569 aspect
, level
, array_layer
);
570 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
571 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
572 lrm
.MemoryAddress
= compression_state_addr
;
574 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
575 sdi
.Address
= compression_state_addr
;
576 sdi
.ImmediateData
= 0;
579 if (level
== 0 && array_layer
== 0) {
580 /* If the predicate is true, we want to write 0 to the fast clear type
581 * and, if it's false, leave it alone. We can do this by writing
583 * clear_type = clear_type & ~predicate;
585 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
586 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
587 lrm
.MemoryAddress
= fast_clear_type_addr
;
589 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
590 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
591 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
594 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
595 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
596 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
597 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
598 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
600 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
601 srm
.MemoryAddress
= fast_clear_type_addr
;
602 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
605 } else if (level
== 0 && array_layer
== 0) {
606 /* In this case, we are doing a partial resolve to get rid of fast-clear
607 * colors. We don't care about the compression state but we do care
608 * about how much fast clear is allowed by the final layout.
610 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
611 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
613 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
614 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
615 lrm
.MemoryAddress
= fast_clear_type_addr
;
617 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
619 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
620 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
622 /* We need to compute (fast_clear_supported < image->fast_clear).
623 * We do this by subtracting and storing the carry bit.
625 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
626 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
627 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
628 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
629 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
631 /* Store the predicate */
632 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
634 /* If the predicate is true, we want to write 0 to the fast clear type
635 * and, if it's false, leave it alone. We can do this by writing
637 * clear_type = clear_type & ~predicate;
639 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
640 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
641 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
642 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
643 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
645 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
646 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
647 srm
.MemoryAddress
= fast_clear_type_addr
;
650 /* In this case, we're trying to do a partial resolve on a slice that
651 * doesn't have clear color. There's nothing to do.
653 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
657 /* We use the first half of src0 for the actual predicate. Set the second
658 * half of src0 and all of src1 to 0 as the predicate operation will be
659 * doing an implicit src0 != src1.
661 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
662 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
663 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
665 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
666 mip
.LoadOperation
= LOAD_LOADINV
;
667 mip
.CombineOperation
= COMBINE_SET
;
668 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
671 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
675 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
676 const struct anv_image
*image
,
677 VkImageAspectFlagBits aspect
,
678 uint32_t level
, uint32_t array_layer
,
679 enum isl_aux_op resolve_op
,
680 enum anv_fast_clear_type fast_clear_supported
)
682 struct anv_address fast_clear_type_addr
=
683 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
685 /* This only works for partial resolves and only when the clear color is
686 * all or nothing. On the upside, this emits less command streamer code
687 * and works on Ivybridge and Bay Trail.
689 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
690 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
692 /* We don't support fast clears on anything other than the first slice. */
693 if (level
> 0 || array_layer
> 0)
696 /* On gen8, we don't have a concept of default clear colors because we
697 * can't sample from CCS surfaces. It's enough to just load the fast clear
698 * state into the predicate register.
700 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
701 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
702 lrm
.MemoryAddress
= fast_clear_type_addr
;
704 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
705 sdi
.Address
= fast_clear_type_addr
;
706 sdi
.ImmediateData
= 0;
709 /* We use the first half of src0 for the actual predicate. Set the second
710 * half of src0 and all of src1 to 0 as the predicate operation will be
711 * doing an implicit src0 != src1.
713 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
714 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
715 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
717 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
718 mip
.LoadOperation
= LOAD_LOADINV
;
719 mip
.CombineOperation
= COMBINE_SET
;
720 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
723 #endif /* GEN_GEN <= 8 */
726 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
727 const struct anv_image
*image
,
728 VkImageAspectFlagBits aspect
,
729 uint32_t level
, uint32_t array_layer
,
730 enum isl_aux_op resolve_op
,
731 enum anv_fast_clear_type fast_clear_supported
)
733 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
736 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
737 aspect
, level
, array_layer
,
738 resolve_op
, fast_clear_supported
);
739 #else /* GEN_GEN <= 8 */
740 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
741 aspect
, level
, array_layer
,
742 resolve_op
, fast_clear_supported
);
745 /* CCS_D only supports full resolves and BLORP will assert on us if we try
746 * to do a partial resolve on a CCS_D surface.
748 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
749 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
750 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
752 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
753 array_layer
, 1, resolve_op
, true);
757 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
758 const struct anv_image
*image
,
759 VkImageAspectFlagBits aspect
,
760 uint32_t array_layer
,
761 enum isl_aux_op resolve_op
,
762 enum anv_fast_clear_type fast_clear_supported
)
764 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
765 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
767 #if GEN_GEN >= 8 || GEN_IS_HASWELL
768 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
769 aspect
, 0, array_layer
,
770 resolve_op
, fast_clear_supported
);
772 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
773 array_layer
, 1, resolve_op
, true);
775 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
780 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
781 const struct anv_image
*image
,
782 VkImageAspectFlagBits aspect
,
783 enum isl_aux_usage aux_usage
,
786 uint32_t layer_count
)
788 /* The aspect must be exactly one of the image aspects. */
789 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
791 /* The only compression types with more than just fast-clears are MCS,
792 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
793 * track the current fast-clear and compression state. This leaves us
794 * with just MCS and CCS_E.
796 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
797 aux_usage
!= ISL_AUX_USAGE_MCS
)
800 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
801 level
, base_layer
, layer_count
, true);
805 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
806 const struct anv_image
*image
,
807 VkImageAspectFlagBits aspect
)
809 assert(cmd_buffer
&& image
);
810 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
812 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
813 ANV_FAST_CLEAR_NONE
);
815 /* The fast clear value dword(s) will be copied into a surface state object.
816 * Ensure that the restrictions of the fields in the dword(s) are followed.
818 * CCS buffers on SKL+ can have any value set for the clear colors.
820 if (image
->samples
== 1 && GEN_GEN
>= 9)
823 /* Other combinations of auxiliary buffers and platforms require specific
824 * values in the clear value dword(s).
826 struct anv_address addr
=
827 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
830 for (unsigned i
= 0; i
< 4; i
++) {
831 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
833 sdi
.Address
.offset
+= i
* 4;
834 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
835 assert(image
->samples
> 1);
836 sdi
.ImmediateData
= 0;
840 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
842 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
843 /* Pre-SKL, the dword containing the clear values also contains
844 * other fields, so we need to initialize those fields to match the
845 * values that would be in a color attachment.
847 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
848 ISL_CHANNEL_SELECT_GREEN
<< 22 |
849 ISL_CHANNEL_SELECT_BLUE
<< 19 |
850 ISL_CHANNEL_SELECT_ALPHA
<< 16;
851 } else if (GEN_GEN
== 7) {
852 /* On IVB, the dword containing the clear values also contains
853 * other fields that must be zero or can be zero.
855 sdi
.ImmediateData
= 0;
861 /* Copy the fast-clear value dword(s) between a surface state object and an
862 * image's fast clear state buffer.
865 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
866 struct anv_state surface_state
,
867 const struct anv_image
*image
,
868 VkImageAspectFlagBits aspect
,
869 bool copy_from_surface_state
)
871 assert(cmd_buffer
&& image
);
872 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
874 struct anv_bo
*ss_bo
=
875 &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
;
876 uint32_t ss_clear_offset
= surface_state
.offset
+
877 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
;
878 const struct anv_address entry_addr
=
879 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
880 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
882 if (copy_from_surface_state
) {
883 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
.bo
, entry_addr
.offset
,
884 ss_bo
, ss_clear_offset
, copy_size
);
886 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_bo
, ss_clear_offset
,
887 entry_addr
.bo
, entry_addr
.offset
, copy_size
);
889 /* Updating a surface state object may require that the state cache be
890 * invalidated. From the SKL PRM, Shared Functions -> State -> State
893 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
894 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
895 * modified [...], the L1 state cache must be invalidated to ensure
896 * the new surface or sampler state is fetched from system memory.
898 * In testing, SKL doesn't actually seem to need this, but HSW does.
900 cmd_buffer
->state
.pending_pipe_bits
|=
901 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
906 * @brief Transitions a color buffer from one layout to another.
908 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
911 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
912 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
913 * this represents the maximum layers to transition at each
914 * specified miplevel.
917 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
918 const struct anv_image
*image
,
919 VkImageAspectFlagBits aspect
,
920 const uint32_t base_level
, uint32_t level_count
,
921 uint32_t base_layer
, uint32_t layer_count
,
922 VkImageLayout initial_layout
,
923 VkImageLayout final_layout
)
925 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
926 /* Validate the inputs. */
928 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
929 /* These values aren't supported for simplicity's sake. */
930 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
931 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
932 /* Ensure the subresource range is valid. */
933 uint64_t last_level_num
= base_level
+ level_count
;
934 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
935 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
936 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
937 assert(last_level_num
<= image
->levels
);
938 /* The spec disallows these final layouts. */
939 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
940 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
942 /* No work is necessary if the layout stays the same or if this subresource
943 * range lacks auxiliary data.
945 if (initial_layout
== final_layout
)
948 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
950 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
951 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
952 /* This surface is a linear compressed image with a tiled shadow surface
953 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
954 * we need to ensure the shadow copy is up-to-date.
956 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
957 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
958 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
959 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
961 anv_image_copy_to_shadow(cmd_buffer
, image
,
962 base_level
, level_count
,
963 base_layer
, layer_count
);
966 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
969 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
971 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
972 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
973 /* A subresource in the undefined layout may have been aliased and
974 * populated with any arrangement of bits. Therefore, we must initialize
975 * the related aux buffer and clear buffer entry with desirable values.
976 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
977 * images with VK_IMAGE_TILING_OPTIMAL.
979 * Initialize the relevant clear buffer entries.
981 if (base_level
== 0 && base_layer
== 0)
982 init_fast_clear_color(cmd_buffer
, image
, aspect
);
984 /* Initialize the aux buffers to enable correct rendering. In order to
985 * ensure that things such as storage images work correctly, aux buffers
986 * need to be initialized to valid data.
988 * Having an aux buffer with invalid data is a problem for two reasons:
990 * 1) Having an invalid value in the buffer can confuse the hardware.
991 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
992 * invalid and leads to the hardware doing strange things. It
993 * doesn't hang as far as we can tell but rendering corruption can
996 * 2) If this transition is into the GENERAL layout and we then use the
997 * image as a storage image, then we must have the aux buffer in the
998 * pass-through state so that, if we then go to texture from the
999 * image, we get the results of our storage image writes and not the
1000 * fast clear color or other random data.
1002 * For CCS both of the problems above are real demonstrable issues. In
1003 * that case, the only thing we can do is to perform an ambiguate to
1004 * transition the aux surface into the pass-through state.
1006 * For MCS, (2) is never an issue because we don't support multisampled
1007 * storage images. In theory, issue (1) is a problem with MCS but we've
1008 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1009 * theory, be interpreted as something but we don't know that all bit
1010 * patterns are actually valid. For 2x and 8x, you could easily end up
1011 * with the MCS referring to an invalid plane because not all bits of
1012 * the MCS value are actually used. Even though we've never seen issues
1013 * in the wild, it's best to play it safe and initialize the MCS. We
1014 * can use a fast-clear for MCS because we only ever touch from render
1015 * and texture (no image load store).
1017 if (image
->samples
== 1) {
1018 for (uint32_t l
= 0; l
< level_count
; l
++) {
1019 const uint32_t level
= base_level
+ l
;
1021 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1022 if (base_layer
>= aux_layers
)
1023 break; /* We will only get fewer layers as level increases */
1024 uint32_t level_layer_count
=
1025 MIN2(layer_count
, aux_layers
- base_layer
);
1027 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
1028 base_layer
, level_layer_count
,
1029 ISL_AUX_OP_AMBIGUATE
, false);
1031 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1032 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1033 level
, base_layer
, level_layer_count
,
1038 if (image
->samples
== 4 || image
->samples
== 16) {
1039 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1040 "Doing a potentially unnecessary fast-clear to "
1041 "define an MCS buffer.");
1044 assert(base_level
== 0 && level_count
== 1);
1045 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
1046 base_layer
, layer_count
,
1047 ISL_AUX_OP_FAST_CLEAR
, false);
1052 const enum isl_aux_usage initial_aux_usage
=
1053 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1054 const enum isl_aux_usage final_aux_usage
=
1055 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1057 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1058 * We can handle transitions between CCS_D/E to and from NONE. What we
1059 * don't yet handle is switching between CCS_E and CCS_D within a given
1060 * image. Doing so in a performant way requires more detailed aux state
1061 * tracking such as what is done in i965. For now, just assume that we
1062 * only have one type of compression.
1064 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1065 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1066 initial_aux_usage
== final_aux_usage
);
1068 /* If initial aux usage is NONE, there is nothing to resolve */
1069 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1072 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1074 /* If the initial layout supports more fast clear than the final layout
1075 * then we need at least a partial resolve.
1077 const enum anv_fast_clear_type initial_fast_clear
=
1078 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1079 const enum anv_fast_clear_type final_fast_clear
=
1080 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1081 if (final_fast_clear
< initial_fast_clear
)
1082 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1084 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1085 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1086 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1088 if (resolve_op
== ISL_AUX_OP_NONE
)
1091 /* Perform a resolve to synchronize data between the main and aux buffer.
1092 * Before we begin, we must satisfy the cache flushing requirement specified
1093 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1095 * Any transition from any value in {Clear, Render, Resolve} to a
1096 * different value in {Clear, Render, Resolve} requires end of pipe
1099 * We perform a flush of the write cache before and after the clear and
1100 * resolve operations to meet this requirement.
1102 * Unlike other drawing, fast clear operations are not properly
1103 * synchronized. The first PIPE_CONTROL here likely ensures that the
1104 * contents of the previous render or clear hit the render target before we
1105 * resolve and the second likely ensures that the resolve is complete before
1106 * we do any more rendering or clearing.
1108 cmd_buffer
->state
.pending_pipe_bits
|=
1109 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1111 for (uint32_t l
= 0; l
< level_count
; l
++) {
1112 uint32_t level
= base_level
+ l
;
1114 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1115 if (base_layer
>= aux_layers
)
1116 break; /* We will only get fewer layers as level increases */
1117 uint32_t level_layer_count
=
1118 MIN2(layer_count
, aux_layers
- base_layer
);
1120 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1121 uint32_t array_layer
= base_layer
+ a
;
1122 if (image
->samples
== 1) {
1123 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
, aspect
,
1124 level
, array_layer
, resolve_op
,
1127 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
, aspect
,
1128 array_layer
, resolve_op
,
1134 cmd_buffer
->state
.pending_pipe_bits
|=
1135 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1139 update_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
1140 const struct anv_attachment_state
*att_state
,
1141 const struct anv_image_view
*iview
)
1143 assert(GEN_GEN
>= 10);
1144 assert(iview
->image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1146 struct anv_address clear_address
=
1147 anv_image_get_clear_color_addr(cmd_buffer
->device
, iview
->image
,
1148 VK_IMAGE_ASPECT_COLOR_BIT
);
1149 union isl_color_value clear_color
;
1150 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
1152 /* Clear values are stored at the same bo as the aux surface, right
1153 * after the surface.
1155 for (int i
= 0; i
< 4; i
++) {
1156 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1157 sdi
.Address
= (struct anv_address
) {
1158 .bo
= clear_address
.bo
,
1159 .offset
= clear_address
.offset
+ i
* 4,
1161 sdi
.ImmediateData
= clear_color
.u32
[i
];
1167 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1170 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1171 struct anv_render_pass
*pass
,
1172 const VkRenderPassBeginInfo
*begin
)
1174 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1175 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1177 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1179 if (pass
->attachment_count
> 0) {
1180 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1181 pass
->attachment_count
*
1182 sizeof(state
->attachments
[0]),
1183 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1184 if (state
->attachments
== NULL
) {
1185 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1186 return anv_batch_set_error(&cmd_buffer
->batch
,
1187 VK_ERROR_OUT_OF_HOST_MEMORY
);
1190 state
->attachments
= NULL
;
1193 /* Reserve one for the NULL state. */
1194 unsigned num_states
= 1;
1195 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1196 if (vk_format_is_color(pass
->attachments
[i
].format
))
1199 if (need_input_attachment_state(&pass
->attachments
[i
]))
1203 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1204 state
->render_pass_states
=
1205 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1206 num_states
* ss_stride
, isl_dev
->ss
.align
);
1208 struct anv_state next_state
= state
->render_pass_states
;
1209 next_state
.alloc_size
= isl_dev
->ss
.size
;
1211 state
->null_surface_state
= next_state
;
1212 next_state
.offset
+= ss_stride
;
1213 next_state
.map
+= ss_stride
;
1215 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1216 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1217 state
->attachments
[i
].color
.state
= next_state
;
1218 next_state
.offset
+= ss_stride
;
1219 next_state
.map
+= ss_stride
;
1222 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1223 state
->attachments
[i
].input
.state
= next_state
;
1224 next_state
.offset
+= ss_stride
;
1225 next_state
.map
+= ss_stride
;
1228 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1229 state
->render_pass_states
.alloc_size
);
1232 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1233 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1235 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1236 isl_extent3d(framebuffer
->width
,
1237 framebuffer
->height
,
1238 framebuffer
->layers
));
1240 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1241 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1242 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1243 VkImageAspectFlags clear_aspects
= 0;
1244 VkImageAspectFlags load_aspects
= 0;
1246 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1247 /* color attachment */
1248 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1249 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1250 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1251 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1254 /* depthstencil attachment */
1255 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1256 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1257 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1258 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1259 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1262 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1263 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1264 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1265 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1266 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1271 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1272 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1273 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1275 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1277 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1278 anv_assert(iview
->vk_format
== att
->format
);
1279 anv_assert(iview
->n_planes
== 1);
1281 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1282 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1284 union isl_color_value clear_color
= { .u32
= { 0, } };
1285 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1286 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1287 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1288 state
, i
, begin
->renderArea
,
1291 anv_image_fill_surface_state(cmd_buffer
->device
,
1293 VK_IMAGE_ASPECT_COLOR_BIT
,
1294 &iview
->planes
[0].isl
,
1295 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1296 state
->attachments
[i
].aux_usage
,
1299 &state
->attachments
[i
].color
,
1302 add_image_view_relocs(cmd_buffer
, iview
, 0,
1303 state
->attachments
[i
].color
);
1305 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1310 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1311 anv_image_fill_surface_state(cmd_buffer
->device
,
1313 VK_IMAGE_ASPECT_COLOR_BIT
,
1314 &iview
->planes
[0].isl
,
1315 ISL_SURF_USAGE_TEXTURE_BIT
,
1316 state
->attachments
[i
].input_aux_usage
,
1319 &state
->attachments
[i
].input
,
1322 add_image_view_relocs(cmd_buffer
, iview
, 0,
1323 state
->attachments
[i
].input
);
1332 genX(BeginCommandBuffer
)(
1333 VkCommandBuffer commandBuffer
,
1334 const VkCommandBufferBeginInfo
* pBeginInfo
)
1336 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1338 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1339 * command buffer's state. Otherwise, we must *reset* its state. In both
1340 * cases we reset it.
1342 * From the Vulkan 1.0 spec:
1344 * If a command buffer is in the executable state and the command buffer
1345 * was allocated from a command pool with the
1346 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1347 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1348 * as if vkResetCommandBuffer had been called with
1349 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1350 * the command buffer in the recording state.
1352 anv_cmd_buffer_reset(cmd_buffer
);
1354 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1356 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1357 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1359 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1361 /* We sometimes store vertex data in the dynamic state buffer for blorp
1362 * operations and our dynamic state stream may re-use data from previous
1363 * command buffers. In order to prevent stale cache data, we flush the VF
1364 * cache. We could do this on every blorp call but that's not really
1365 * needed as all of the data will get written by the CPU prior to the GPU
1366 * executing anything. The chances are fairly high that they will use
1367 * blorp at least once per primary command buffer so it shouldn't be
1370 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1371 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1373 /* We send an "Indirect State Pointers Disable" packet at
1374 * EndCommandBuffer, so all push contant packets are ignored during a
1375 * context restore. Documentation says after that command, we need to
1376 * emit push constants again before any rendering operation. So we
1377 * flag them dirty here to make sure they get emitted.
1379 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1381 VkResult result
= VK_SUCCESS
;
1382 if (cmd_buffer
->usage_flags
&
1383 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1384 assert(pBeginInfo
->pInheritanceInfo
);
1385 cmd_buffer
->state
.pass
=
1386 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1387 cmd_buffer
->state
.subpass
=
1388 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1390 /* This is optional in the inheritance info. */
1391 cmd_buffer
->state
.framebuffer
=
1392 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1394 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1395 cmd_buffer
->state
.pass
, NULL
);
1397 /* Record that HiZ is enabled if we can. */
1398 if (cmd_buffer
->state
.framebuffer
) {
1399 const struct anv_image_view
* const iview
=
1400 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1403 VkImageLayout layout
=
1404 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.layout
;
1406 enum isl_aux_usage aux_usage
=
1407 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1408 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1410 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1414 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1420 /* From the PRM, Volume 2a:
1422 * "Indirect State Pointers Disable
1424 * At the completion of the post-sync operation associated with this pipe
1425 * control packet, the indirect state pointers in the hardware are
1426 * considered invalid; the indirect pointers are not saved in the context.
1427 * If any new indirect state commands are executed in the command stream
1428 * while the pipe control is pending, the new indirect state commands are
1431 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1432 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1433 * commands are only considered as Indirect State Pointers. Once ISP is
1434 * issued in a context, SW must initialize by programming push constant
1435 * commands for all the shaders (at least to zero length) before attempting
1436 * any rendering operation for the same context."
1438 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1439 * even though they point to a BO that has been already unreferenced at
1440 * the end of the previous batch buffer. This has been fine so far since
1441 * we are protected by these scratch page (every address not covered by
1442 * a BO should be pointing to the scratch page). But on CNL, it is
1443 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1446 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1447 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1448 * context restore, so the mentioned hang doesn't happen. However,
1449 * software must program push constant commands for all stages prior to
1450 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1453 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1455 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1456 pc
.IndirectStatePointersDisable
= true;
1457 pc
.CommandStreamerStallEnable
= true;
1462 genX(EndCommandBuffer
)(
1463 VkCommandBuffer commandBuffer
)
1465 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1467 if (anv_batch_has_error(&cmd_buffer
->batch
))
1468 return cmd_buffer
->batch
.status
;
1470 /* We want every command buffer to start with the PMA fix in a known state,
1471 * so we disable it at the end of the command buffer.
1473 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1475 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1477 emit_isp_disable(cmd_buffer
);
1479 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1485 genX(CmdExecuteCommands
)(
1486 VkCommandBuffer commandBuffer
,
1487 uint32_t commandBufferCount
,
1488 const VkCommandBuffer
* pCmdBuffers
)
1490 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1492 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1494 if (anv_batch_has_error(&primary
->batch
))
1497 /* The secondary command buffers will assume that the PMA fix is disabled
1498 * when they begin executing. Make sure this is true.
1500 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1502 /* The secondary command buffer doesn't know which textures etc. have been
1503 * flushed prior to their execution. Apply those flushes now.
1505 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1507 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1508 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1510 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1511 assert(!anv_batch_has_error(&secondary
->batch
));
1513 if (secondary
->usage_flags
&
1514 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1515 /* If we're continuing a render pass from the primary, we need to
1516 * copy the surface states for the current subpass into the storage
1517 * we allocated for them in BeginCommandBuffer.
1519 struct anv_bo
*ss_bo
=
1520 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1521 struct anv_state src_state
= primary
->state
.render_pass_states
;
1522 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1523 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1525 genX(cmd_buffer_so_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
1526 ss_bo
, src_state
.offset
,
1527 src_state
.alloc_size
);
1530 anv_cmd_buffer_add_secondary(primary
, secondary
);
1533 /* The secondary may have selected a different pipeline (3D or compute) and
1534 * may have changed the current L3$ configuration. Reset our tracking
1535 * variables to invalid values to ensure that we re-emit these in the case
1536 * where we do any draws or compute dispatches from the primary after the
1537 * secondary has returned.
1539 primary
->state
.current_pipeline
= UINT32_MAX
;
1540 primary
->state
.current_l3_config
= NULL
;
1542 /* Each of the secondary command buffers will use its own state base
1543 * address. We need to re-emit state base address for the primary after
1544 * all of the secondaries are done.
1546 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1549 genX(cmd_buffer_emit_state_base_address
)(primary
);
1552 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1553 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1554 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1557 * Program the hardware to use the specified L3 configuration.
1560 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1561 const struct gen_l3_config
*cfg
)
1564 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1567 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1568 intel_logd("L3 config transition: ");
1569 gen_dump_l3_config(cfg
, stderr
);
1572 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1574 /* According to the hardware docs, the L3 partitioning can only be changed
1575 * while the pipeline is completely drained and the caches are flushed,
1576 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1578 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1579 pc
.DCFlushEnable
= true;
1580 pc
.PostSyncOperation
= NoWrite
;
1581 pc
.CommandStreamerStallEnable
= true;
1584 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1585 * invalidation of the relevant caches. Note that because RO invalidation
1586 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1587 * command is processed by the CS) we cannot combine it with the previous
1588 * stalling flush as the hardware documentation suggests, because that
1589 * would cause the CS to stall on previous rendering *after* RO
1590 * invalidation and wouldn't prevent the RO caches from being polluted by
1591 * concurrent rendering before the stall completes. This intentionally
1592 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1593 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1594 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1595 * already guarantee that there is no concurrent GPGPU kernel execution
1596 * (see SKL HSD 2132585).
1598 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1599 pc
.TextureCacheInvalidationEnable
= true;
1600 pc
.ConstantCacheInvalidationEnable
= true;
1601 pc
.InstructionCacheInvalidateEnable
= true;
1602 pc
.StateCacheInvalidationEnable
= true;
1603 pc
.PostSyncOperation
= NoWrite
;
1606 /* Now send a third stalling flush to make sure that invalidation is
1607 * complete when the L3 configuration registers are modified.
1609 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1610 pc
.DCFlushEnable
= true;
1611 pc
.PostSyncOperation
= NoWrite
;
1612 pc
.CommandStreamerStallEnable
= true;
1617 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1620 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1621 .SLMEnable
= has_slm
,
1622 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1623 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1624 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1625 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1627 /* Set up the L3 partitioning. */
1628 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1632 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1633 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1634 cfg
->n
[GEN_L3P_ALL
];
1635 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1636 cfg
->n
[GEN_L3P_ALL
];
1637 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1638 cfg
->n
[GEN_L3P_ALL
];
1640 assert(!cfg
->n
[GEN_L3P_ALL
]);
1642 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1643 * the matching space on the remaining banks has to be allocated to a
1644 * client (URB for all validated configurations) set to the
1645 * lower-bandwidth 2-bank address hashing mode.
1647 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1648 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1649 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1651 /* Minimum number of ways that can be allocated to the URB. */
1652 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1653 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1655 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1656 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1657 .ConvertDC_UC
= !has_dc
,
1658 .ConvertIS_UC
= !has_is
,
1659 .ConvertC_UC
= !has_c
,
1660 .ConvertT_UC
= !has_t
);
1662 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1663 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1664 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1666 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1667 .SLMEnable
= has_slm
,
1668 .URBLowBandwidth
= urb_low_bw
,
1669 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1671 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1673 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1674 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1676 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1677 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1678 .ISLowBandwidth
= 0,
1679 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1681 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1682 .TLowBandwidth
= 0);
1684 /* Set up the L3 partitioning. */
1685 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1686 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1687 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1690 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1691 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1692 * them disabled to avoid crashing the system hard.
1694 uint32_t scratch1
, chicken3
;
1695 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1696 .L3AtomicDisable
= !has_dc
);
1697 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1698 .L3AtomicDisableMask
= true,
1699 .L3AtomicDisable
= !has_dc
);
1700 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1701 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1707 cmd_buffer
->state
.current_l3_config
= cfg
;
1711 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1713 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1715 /* Flushes are pipelined while invalidations are handled immediately.
1716 * Therefore, if we're flushing anything then we need to schedule a stall
1717 * before any invalidations can happen.
1719 if (bits
& ANV_PIPE_FLUSH_BITS
)
1720 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1722 /* If we're going to do an invalidate and we have a pending CS stall that
1723 * has yet to be resolved, we do the CS stall now.
1725 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1726 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1727 bits
|= ANV_PIPE_CS_STALL_BIT
;
1728 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1731 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1732 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1733 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1734 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1735 pipe
.RenderTargetCacheFlushEnable
=
1736 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1738 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1739 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1740 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1743 * According to the Broadwell documentation, any PIPE_CONTROL with the
1744 * "Command Streamer Stall" bit set must also have another bit set,
1745 * with five different options:
1747 * - Render Target Cache Flush
1748 * - Depth Cache Flush
1749 * - Stall at Pixel Scoreboard
1750 * - Post-Sync Operation
1754 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1755 * mesa and it seems to work fine. The choice is fairly arbitrary.
1757 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1758 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1759 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1760 pipe
.StallAtPixelScoreboard
= true;
1763 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1766 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1767 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1768 pipe
.StateCacheInvalidationEnable
=
1769 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1770 pipe
.ConstantCacheInvalidationEnable
=
1771 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1772 pipe
.VFCacheInvalidationEnable
=
1773 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1774 pipe
.TextureCacheInvalidationEnable
=
1775 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1776 pipe
.InstructionCacheInvalidateEnable
=
1777 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1780 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1783 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1786 void genX(CmdPipelineBarrier
)(
1787 VkCommandBuffer commandBuffer
,
1788 VkPipelineStageFlags srcStageMask
,
1789 VkPipelineStageFlags destStageMask
,
1791 uint32_t memoryBarrierCount
,
1792 const VkMemoryBarrier
* pMemoryBarriers
,
1793 uint32_t bufferMemoryBarrierCount
,
1794 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1795 uint32_t imageMemoryBarrierCount
,
1796 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1798 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1800 /* XXX: Right now, we're really dumb and just flush whatever categories
1801 * the app asks for. One of these days we may make this a bit better
1802 * but right now that's all the hardware allows for in most areas.
1804 VkAccessFlags src_flags
= 0;
1805 VkAccessFlags dst_flags
= 0;
1807 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1808 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1809 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1812 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1813 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1814 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1817 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1818 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1819 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1820 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1821 const VkImageSubresourceRange
*range
=
1822 &pImageMemoryBarriers
[i
].subresourceRange
;
1824 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1825 transition_depth_buffer(cmd_buffer
, image
,
1826 pImageMemoryBarriers
[i
].oldLayout
,
1827 pImageMemoryBarriers
[i
].newLayout
);
1828 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1829 VkImageAspectFlags color_aspects
=
1830 anv_image_expand_aspects(image
, range
->aspectMask
);
1831 uint32_t aspect_bit
;
1833 uint32_t base_layer
, layer_count
;
1834 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1836 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1838 base_layer
= range
->baseArrayLayer
;
1839 layer_count
= anv_get_layerCount(image
, range
);
1842 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1843 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1844 range
->baseMipLevel
,
1845 anv_get_levelCount(image
, range
),
1846 base_layer
, layer_count
,
1847 pImageMemoryBarriers
[i
].oldLayout
,
1848 pImageMemoryBarriers
[i
].newLayout
);
1853 cmd_buffer
->state
.pending_pipe_bits
|=
1854 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1855 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1859 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1861 VkShaderStageFlags stages
=
1862 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1864 /* In order to avoid thrash, we assume that vertex and fragment stages
1865 * always exist. In the rare case where one is missing *and* the other
1866 * uses push concstants, this may be suboptimal. However, avoiding stalls
1867 * seems more important.
1869 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1871 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1875 const unsigned push_constant_kb
= 32;
1876 #elif GEN_IS_HASWELL
1877 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1879 const unsigned push_constant_kb
= 16;
1882 const unsigned num_stages
=
1883 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1884 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1886 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1887 * units of 2KB. Incidentally, these are the same platforms that have
1888 * 32KB worth of push constant space.
1890 if (push_constant_kb
== 32)
1891 size_per_stage
&= ~1u;
1893 uint32_t kb_used
= 0;
1894 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1895 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1896 anv_batch_emit(&cmd_buffer
->batch
,
1897 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1898 alloc
._3DCommandSubOpcode
= 18 + i
;
1899 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1900 alloc
.ConstantBufferSize
= push_size
;
1902 kb_used
+= push_size
;
1905 anv_batch_emit(&cmd_buffer
->batch
,
1906 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1907 alloc
.ConstantBufferOffset
= kb_used
;
1908 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1911 cmd_buffer
->state
.push_constant_stages
= stages
;
1913 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1915 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1916 * the next 3DPRIMITIVE command after programming the
1917 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1919 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1920 * pipeline setup, we need to dirty push constants.
1922 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1925 static const struct anv_descriptor
*
1926 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1927 const struct anv_pipeline_binding
*binding
)
1929 assert(binding
->set
< MAX_SETS
);
1930 const struct anv_descriptor_set
*set
=
1931 pipe_state
->descriptors
[binding
->set
];
1932 const uint32_t offset
=
1933 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1934 return &set
->descriptors
[offset
+ binding
->index
];
1938 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1939 const struct anv_pipeline_binding
*binding
)
1941 assert(binding
->set
< MAX_SETS
);
1942 const struct anv_descriptor_set
*set
=
1943 pipe_state
->descriptors
[binding
->set
];
1945 uint32_t dynamic_offset_idx
=
1946 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1947 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1950 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1954 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1955 gl_shader_stage stage
,
1956 struct anv_state
*bt_state
)
1958 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1959 struct anv_cmd_pipeline_state
*pipe_state
;
1960 struct anv_pipeline
*pipeline
;
1961 uint32_t bias
, state_offset
;
1964 case MESA_SHADER_COMPUTE
:
1965 pipe_state
= &cmd_buffer
->state
.compute
.base
;
1969 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
1973 pipeline
= pipe_state
->pipeline
;
1975 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1976 *bt_state
= (struct anv_state
) { 0, };
1980 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1981 if (bias
+ map
->surface_count
== 0) {
1982 *bt_state
= (struct anv_state
) { 0, };
1986 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1987 bias
+ map
->surface_count
,
1989 uint32_t *bt_map
= bt_state
->map
;
1991 if (bt_state
->map
== NULL
)
1992 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1994 if (stage
== MESA_SHADER_COMPUTE
&&
1995 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
1996 struct anv_bo
*bo
= cmd_buffer
->state
.compute
.num_workgroups
.bo
;
1997 uint32_t bo_offset
= cmd_buffer
->state
.compute
.num_workgroups
.offset
;
1999 struct anv_state surface_state
;
2001 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2003 const enum isl_format format
=
2004 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2005 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2006 format
, bo_offset
, 12, 1);
2008 bt_map
[0] = surface_state
.offset
+ state_offset
;
2009 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
2012 if (map
->surface_count
== 0)
2015 if (map
->image_count
> 0) {
2017 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
2018 if (result
!= VK_SUCCESS
)
2021 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2025 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2026 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2028 struct anv_state surface_state
;
2030 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2031 /* Color attachment binding */
2032 assert(stage
== MESA_SHADER_FRAGMENT
);
2033 assert(binding
->binding
== 0);
2034 if (binding
->index
< subpass
->color_count
) {
2035 const unsigned att
=
2036 subpass
->color_attachments
[binding
->index
].attachment
;
2038 /* From the Vulkan 1.0.46 spec:
2040 * "If any color or depth/stencil attachments are
2041 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2044 if (att
== VK_ATTACHMENT_UNUSED
) {
2045 surface_state
= cmd_buffer
->state
.null_surface_state
;
2047 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2050 surface_state
= cmd_buffer
->state
.null_surface_state
;
2053 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2057 const struct anv_descriptor
*desc
=
2058 anv_descriptor_for_binding(pipe_state
, binding
);
2060 switch (desc
->type
) {
2061 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2062 /* Nothing for us to do here */
2065 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2066 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2067 struct anv_surface_state sstate
=
2068 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2069 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2070 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2071 surface_state
= sstate
.state
;
2072 assert(surface_state
.alloc_size
);
2073 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
2074 binding
->plane
, sstate
);
2077 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2078 assert(stage
== MESA_SHADER_FRAGMENT
);
2079 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2080 /* For depth and stencil input attachments, we treat it like any
2081 * old texture that a user may have bound.
2083 struct anv_surface_state sstate
=
2084 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2085 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2086 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2087 surface_state
= sstate
.state
;
2088 assert(surface_state
.alloc_size
);
2089 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
2090 binding
->plane
, sstate
);
2092 /* For color input attachments, we create the surface state at
2093 * vkBeginRenderPass time so that we can include aux and clear
2094 * color information.
2096 assert(binding
->input_attachment_index
< subpass
->input_count
);
2097 const unsigned subpass_att
= binding
->input_attachment_index
;
2098 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2099 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2103 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2104 struct anv_surface_state sstate
= (binding
->write_only
)
2105 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2106 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2107 surface_state
= sstate
.state
;
2108 assert(surface_state
.alloc_size
);
2109 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
2110 binding
->plane
, sstate
);
2112 struct brw_image_param
*image_param
=
2113 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2115 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2116 image_param
->surface_idx
= bias
+ s
;
2120 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2121 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2122 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2123 surface_state
= desc
->buffer_view
->surface_state
;
2124 assert(surface_state
.alloc_size
);
2125 add_surface_state_reloc(cmd_buffer
, surface_state
,
2126 desc
->buffer_view
->bo
,
2127 desc
->buffer_view
->offset
);
2130 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2131 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2132 /* Compute the offset within the buffer */
2133 uint32_t dynamic_offset
=
2134 dynamic_offset_for_binding(pipe_state
, binding
);
2135 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2136 /* Clamp to the buffer size */
2137 offset
= MIN2(offset
, desc
->buffer
->size
);
2138 /* Clamp the range to the buffer size */
2139 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2142 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2143 enum isl_format format
=
2144 anv_isl_format_for_descriptor_type(desc
->type
);
2146 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2147 format
, offset
, range
, 1);
2148 add_surface_state_reloc(cmd_buffer
, surface_state
,
2150 desc
->buffer
->offset
+ offset
);
2154 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2155 surface_state
= (binding
->write_only
)
2156 ? desc
->buffer_view
->writeonly_storage_surface_state
2157 : desc
->buffer_view
->storage_surface_state
;
2158 assert(surface_state
.alloc_size
);
2159 add_surface_state_reloc(cmd_buffer
, surface_state
,
2160 desc
->buffer_view
->bo
,
2161 desc
->buffer_view
->offset
);
2163 struct brw_image_param
*image_param
=
2164 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2166 *image_param
= desc
->buffer_view
->storage_image_param
;
2167 image_param
->surface_idx
= bias
+ s
;
2171 assert(!"Invalid descriptor type");
2175 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2177 assert(image
== map
->image_count
);
2180 anv_state_flush(cmd_buffer
->device
, *bt_state
);
2183 /* The PIPE_CONTROL command description says:
2185 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2186 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2187 * Target Cache Flush by enabling this bit. When render target flush
2188 * is set due to new association of BTI, PS Scoreboard Stall bit must
2189 * be set in this packet."
2191 * FINISHME: Currently we shuffle around the surface states in the binding
2192 * table based on if they are getting used or not. So, we've to do below
2193 * pipe control flush for every binding table upload. Make changes so
2194 * that we do it only when we modify render target surface states.
2196 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2197 pc
.RenderTargetCacheFlushEnable
= true;
2198 pc
.StallAtPixelScoreboard
= true;
2206 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2207 gl_shader_stage stage
,
2208 struct anv_state
*state
)
2210 struct anv_cmd_pipeline_state
*pipe_state
=
2211 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2212 &cmd_buffer
->state
.gfx
.base
;
2213 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2215 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2216 *state
= (struct anv_state
) { 0, };
2220 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2221 if (map
->sampler_count
== 0) {
2222 *state
= (struct anv_state
) { 0, };
2226 uint32_t size
= map
->sampler_count
* 16;
2227 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2229 if (state
->map
== NULL
)
2230 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2232 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2233 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2234 const struct anv_descriptor
*desc
=
2235 anv_descriptor_for_binding(pipe_state
, binding
);
2237 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2238 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2241 struct anv_sampler
*sampler
= desc
->sampler
;
2243 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2244 * happens to be zero.
2246 if (sampler
== NULL
)
2249 memcpy(state
->map
+ (s
* 16),
2250 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2253 anv_state_flush(cmd_buffer
->device
, *state
);
2259 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2261 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2263 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2264 pipeline
->active_stages
;
2266 VkResult result
= VK_SUCCESS
;
2267 anv_foreach_stage(s
, dirty
) {
2268 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2269 if (result
!= VK_SUCCESS
)
2271 result
= emit_binding_table(cmd_buffer
, s
,
2272 &cmd_buffer
->state
.binding_tables
[s
]);
2273 if (result
!= VK_SUCCESS
)
2277 if (result
!= VK_SUCCESS
) {
2278 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2280 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2281 if (result
!= VK_SUCCESS
)
2284 /* Re-emit state base addresses so we get the new surface state base
2285 * address before we start emitting binding tables etc.
2287 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2289 /* Re-emit all active binding tables */
2290 dirty
|= pipeline
->active_stages
;
2291 anv_foreach_stage(s
, dirty
) {
2292 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2293 if (result
!= VK_SUCCESS
) {
2294 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2297 result
= emit_binding_table(cmd_buffer
, s
,
2298 &cmd_buffer
->state
.binding_tables
[s
]);
2299 if (result
!= VK_SUCCESS
) {
2300 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2306 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2312 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2315 static const uint32_t sampler_state_opcodes
[] = {
2316 [MESA_SHADER_VERTEX
] = 43,
2317 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2318 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2319 [MESA_SHADER_GEOMETRY
] = 46,
2320 [MESA_SHADER_FRAGMENT
] = 47,
2321 [MESA_SHADER_COMPUTE
] = 0,
2324 static const uint32_t binding_table_opcodes
[] = {
2325 [MESA_SHADER_VERTEX
] = 38,
2326 [MESA_SHADER_TESS_CTRL
] = 39,
2327 [MESA_SHADER_TESS_EVAL
] = 40,
2328 [MESA_SHADER_GEOMETRY
] = 41,
2329 [MESA_SHADER_FRAGMENT
] = 42,
2330 [MESA_SHADER_COMPUTE
] = 0,
2333 anv_foreach_stage(s
, stages
) {
2334 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2335 assert(binding_table_opcodes
[s
] > 0);
2337 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2338 anv_batch_emit(&cmd_buffer
->batch
,
2339 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2340 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2341 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2345 /* Always emit binding table pointers if we're asked to, since on SKL
2346 * this is what flushes push constants. */
2347 anv_batch_emit(&cmd_buffer
->batch
,
2348 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2349 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2350 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2356 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2357 VkShaderStageFlags dirty_stages
)
2359 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2360 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2362 static const uint32_t push_constant_opcodes
[] = {
2363 [MESA_SHADER_VERTEX
] = 21,
2364 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2365 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2366 [MESA_SHADER_GEOMETRY
] = 22,
2367 [MESA_SHADER_FRAGMENT
] = 23,
2368 [MESA_SHADER_COMPUTE
] = 0,
2371 VkShaderStageFlags flushed
= 0;
2373 anv_foreach_stage(stage
, dirty_stages
) {
2374 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2375 assert(push_constant_opcodes
[stage
] > 0);
2377 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2378 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2380 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2381 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2382 const struct brw_stage_prog_data
*prog_data
=
2383 pipeline
->shaders
[stage
]->prog_data
;
2384 const struct anv_pipeline_bind_map
*bind_map
=
2385 &pipeline
->shaders
[stage
]->bind_map
;
2387 /* The Skylake PRM contains the following restriction:
2389 * "The driver must ensure The following case does not occur
2390 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2391 * buffer 3 read length equal to zero committed followed by a
2392 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2395 * To avoid this, we program the buffers in the highest slots.
2396 * This way, slot 0 is only used if slot 3 is also used.
2400 for (int i
= 3; i
>= 0; i
--) {
2401 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2402 if (range
->length
== 0)
2405 const unsigned surface
=
2406 prog_data
->binding_table
.ubo_start
+ range
->block
;
2408 assert(surface
<= bind_map
->surface_count
);
2409 const struct anv_pipeline_binding
*binding
=
2410 &bind_map
->surface_to_descriptor
[surface
];
2412 const struct anv_descriptor
*desc
=
2413 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2415 struct anv_address read_addr
;
2417 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2418 read_len
= MIN2(range
->length
,
2419 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2420 read_addr
= (struct anv_address
) {
2421 .bo
= desc
->buffer_view
->bo
,
2422 .offset
= desc
->buffer_view
->offset
+
2426 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2428 uint32_t dynamic_offset
=
2429 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2430 uint32_t buf_offset
=
2431 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2432 uint32_t buf_range
=
2433 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2435 read_len
= MIN2(range
->length
,
2436 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2437 read_addr
= (struct anv_address
) {
2438 .bo
= desc
->buffer
->bo
,
2439 .offset
= desc
->buffer
->offset
+ buf_offset
+
2445 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2446 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2451 struct anv_state state
=
2452 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2454 if (state
.alloc_size
> 0) {
2455 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2456 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2457 .offset
= state
.offset
,
2459 c
.ConstantBody
.ReadLength
[n
] =
2460 DIV_ROUND_UP(state
.alloc_size
, 32);
2463 /* For Ivy Bridge, the push constants packets have a different
2464 * rule that would require us to iterate in the other direction
2465 * and possibly mess around with dynamic state base address.
2466 * Don't bother; just emit regular push constants at n = 0.
2468 struct anv_state state
=
2469 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2471 if (state
.alloc_size
> 0) {
2472 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2473 c
.ConstantBody
.ReadLength
[0] =
2474 DIV_ROUND_UP(state
.alloc_size
, 32);
2480 flushed
|= mesa_to_vk_shader_stage(stage
);
2483 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2487 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2489 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2492 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2494 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2496 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2498 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2501 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2502 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2504 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2505 GENX(3DSTATE_VERTEX_BUFFERS
));
2507 for_each_bit(vb
, vb_emit
) {
2508 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2509 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2511 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2512 .VertexBufferIndex
= vb
,
2515 .MemoryObjectControlState
= GENX(MOCS
),
2517 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
2518 /* Our implementation of VK_KHR_multiview uses instancing to draw
2519 * the different views. If the client asks for instancing, we
2520 * need to use the Instance Data Step Rate to ensure that we
2521 * repeat the client's per-instance data once for each view.
2523 .InstanceDataStepRate
= anv_subpass_view_count(pipeline
->subpass
),
2524 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2527 .AddressModifyEnable
= true,
2528 .BufferPitch
= pipeline
->binding_stride
[vb
],
2529 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
2532 .BufferSize
= buffer
->size
- offset
2534 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
2538 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2543 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2545 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2546 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2548 /* The exact descriptor layout is pulled from the pipeline, so we need
2549 * to re-emit binding tables on every pipeline change.
2551 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2553 /* If the pipeline changed, we may need to re-allocate push constant
2556 cmd_buffer_alloc_push_constants(cmd_buffer
);
2560 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2561 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2562 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2564 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2565 * stall needs to be sent just prior to any 3DSTATE_VS,
2566 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2567 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2568 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2569 * PIPE_CONTROL needs to be sent before any combination of VS
2570 * associated 3DSTATE."
2572 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2573 pc
.DepthStallEnable
= true;
2574 pc
.PostSyncOperation
= WriteImmediateData
;
2576 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2581 /* Render targets live in the same binding table as fragment descriptors */
2582 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2583 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2585 /* We emit the binding tables and sampler tables first, then emit push
2586 * constants and then finally emit binding table and sampler table
2587 * pointers. It has to happen in this order, since emitting the binding
2588 * tables may change the push constants (in case of storage images). After
2589 * emitting push constants, on SKL+ we have to emit the corresponding
2590 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2593 if (cmd_buffer
->state
.descriptors_dirty
)
2594 dirty
= flush_descriptor_sets(cmd_buffer
);
2596 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2597 /* Because we're pushing UBOs, we have to push whenever either
2598 * descriptors or push constants is dirty.
2600 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2601 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2602 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2606 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2608 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2609 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2611 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2612 ANV_CMD_DIRTY_PIPELINE
)) {
2613 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2614 pipeline
->depth_clamp_enable
);
2617 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
2618 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2620 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2622 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2626 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2627 struct anv_bo
*bo
, uint32_t offset
,
2628 uint32_t size
, uint32_t index
)
2630 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2631 GENX(3DSTATE_VERTEX_BUFFERS
));
2633 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2634 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2635 .VertexBufferIndex
= index
,
2636 .AddressModifyEnable
= true,
2639 .MemoryObjectControlState
= GENX(MOCS
),
2640 .BufferStartingAddress
= { bo
, offset
},
2643 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2644 .BufferStartingAddress
= { bo
, offset
},
2645 .EndAddress
= { bo
, offset
+ size
},
2651 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2652 struct anv_bo
*bo
, uint32_t offset
)
2654 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
2658 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2659 uint32_t base_vertex
, uint32_t base_instance
)
2661 struct anv_state id_state
=
2662 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2664 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2665 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2667 anv_state_flush(cmd_buffer
->device
, id_state
);
2669 emit_base_vertex_instance_bo(cmd_buffer
,
2670 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
, id_state
.offset
);
2674 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2676 struct anv_state state
=
2677 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2679 ((uint32_t *)state
.map
)[0] = draw_index
;
2681 anv_state_flush(cmd_buffer
->device
, state
);
2683 emit_vertex_bo(cmd_buffer
,
2684 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2685 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
2689 VkCommandBuffer commandBuffer
,
2690 uint32_t vertexCount
,
2691 uint32_t instanceCount
,
2692 uint32_t firstVertex
,
2693 uint32_t firstInstance
)
2695 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2696 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2697 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2699 if (anv_batch_has_error(&cmd_buffer
->batch
))
2702 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2704 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2705 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2706 if (vs_prog_data
->uses_drawid
)
2707 emit_draw_index(cmd_buffer
, 0);
2709 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2710 * different views. We need to multiply instanceCount by the view count.
2712 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2714 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2715 prim
.VertexAccessType
= SEQUENTIAL
;
2716 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2717 prim
.VertexCountPerInstance
= vertexCount
;
2718 prim
.StartVertexLocation
= firstVertex
;
2719 prim
.InstanceCount
= instanceCount
;
2720 prim
.StartInstanceLocation
= firstInstance
;
2721 prim
.BaseVertexLocation
= 0;
2725 void genX(CmdDrawIndexed
)(
2726 VkCommandBuffer commandBuffer
,
2727 uint32_t indexCount
,
2728 uint32_t instanceCount
,
2729 uint32_t firstIndex
,
2730 int32_t vertexOffset
,
2731 uint32_t firstInstance
)
2733 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2734 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2735 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2737 if (anv_batch_has_error(&cmd_buffer
->batch
))
2740 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2742 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2743 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2744 if (vs_prog_data
->uses_drawid
)
2745 emit_draw_index(cmd_buffer
, 0);
2747 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2748 * different views. We need to multiply instanceCount by the view count.
2750 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2752 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2753 prim
.VertexAccessType
= RANDOM
;
2754 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2755 prim
.VertexCountPerInstance
= indexCount
;
2756 prim
.StartVertexLocation
= firstIndex
;
2757 prim
.InstanceCount
= instanceCount
;
2758 prim
.StartInstanceLocation
= firstInstance
;
2759 prim
.BaseVertexLocation
= vertexOffset
;
2763 /* Auto-Draw / Indirect Registers */
2764 #define GEN7_3DPRIM_END_OFFSET 0x2420
2765 #define GEN7_3DPRIM_START_VERTEX 0x2430
2766 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2767 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2768 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2769 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2771 /* MI_MATH only exists on Haswell+ */
2772 #if GEN_IS_HASWELL || GEN_GEN >= 8
2774 /* Emit dwords to multiply GPR0 by N */
2776 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2778 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2780 #define append_alu(opcode, operand1, operand2) \
2781 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2784 unsigned top_bit
= 31 - __builtin_clz(N
);
2785 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2786 /* We get our initial data in GPR0 and we write the final data out to
2787 * GPR0 but we use GPR1 as our scratch register.
2789 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2790 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2792 /* Shift the current value left by 1 */
2793 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2794 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2795 append_alu(MI_ALU_ADD
, 0, 0);
2798 /* Store ACCU to R1 and add R0 to R1 */
2799 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2800 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2801 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2802 append_alu(MI_ALU_ADD
, 0, 0);
2805 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2812 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2814 uint32_t num_dwords
;
2815 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2817 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2818 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2821 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2824 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2825 struct anv_buffer
*buffer
, uint64_t offset
,
2828 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2829 struct anv_bo
*bo
= buffer
->bo
;
2830 uint32_t bo_offset
= buffer
->offset
+ offset
;
2832 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
2834 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2835 if (view_count
> 1) {
2836 #if GEN_IS_HASWELL || GEN_GEN >= 8
2837 emit_lrm(batch
, CS_GPR(0), bo
, bo_offset
+ 4);
2838 emit_mul_gpr0(batch
, view_count
);
2839 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2841 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2842 "MI_MATH is not supported on Ivy Bridge");
2843 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2846 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2849 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
2852 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
2853 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
2855 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
2856 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2860 void genX(CmdDrawIndirect
)(
2861 VkCommandBuffer commandBuffer
,
2863 VkDeviceSize offset
,
2867 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2868 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2869 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2870 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2872 if (anv_batch_has_error(&cmd_buffer
->batch
))
2875 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2877 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2878 struct anv_bo
*bo
= buffer
->bo
;
2879 uint32_t bo_offset
= buffer
->offset
+ offset
;
2881 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2882 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
2883 if (vs_prog_data
->uses_drawid
)
2884 emit_draw_index(cmd_buffer
, i
);
2886 load_indirect_parameters(cmd_buffer
, buffer
, offset
, false);
2888 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2889 prim
.IndirectParameterEnable
= true;
2890 prim
.VertexAccessType
= SEQUENTIAL
;
2891 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2898 void genX(CmdDrawIndexedIndirect
)(
2899 VkCommandBuffer commandBuffer
,
2901 VkDeviceSize offset
,
2905 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2906 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2907 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2908 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2910 if (anv_batch_has_error(&cmd_buffer
->batch
))
2913 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2915 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2916 struct anv_bo
*bo
= buffer
->bo
;
2917 uint32_t bo_offset
= buffer
->offset
+ offset
;
2919 /* TODO: We need to stomp base vertex to 0 somehow */
2920 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2921 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
2922 if (vs_prog_data
->uses_drawid
)
2923 emit_draw_index(cmd_buffer
, i
);
2925 load_indirect_parameters(cmd_buffer
, buffer
, offset
, true);
2927 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2928 prim
.IndirectParameterEnable
= true;
2929 prim
.VertexAccessType
= RANDOM
;
2930 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2938 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2940 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2941 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2944 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2945 if (result
!= VK_SUCCESS
) {
2946 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2948 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2949 if (result
!= VK_SUCCESS
)
2952 /* Re-emit state base addresses so we get the new surface state base
2953 * address before we start emitting binding tables etc.
2955 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2957 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2958 if (result
!= VK_SUCCESS
) {
2959 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2964 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
2965 if (result
!= VK_SUCCESS
) {
2966 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2970 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
2971 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2972 .BindingTablePointer
= surfaces
.offset
,
2973 .SamplerStatePointer
= samplers
.offset
,
2975 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
2977 struct anv_state state
=
2978 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
2979 pipeline
->interface_descriptor_data
,
2980 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
2983 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
2984 anv_batch_emit(&cmd_buffer
->batch
,
2985 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
2986 mid
.InterfaceDescriptorTotalLength
= size
;
2987 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
2994 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2996 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2997 MAYBE_UNUSED VkResult result
;
2999 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3001 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3003 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3005 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3006 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3008 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3009 * the only bits that are changed are scoreboard related: Scoreboard
3010 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3011 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3014 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3015 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3017 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3020 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3021 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3022 /* FIXME: figure out descriptors for gen7 */
3023 result
= flush_compute_descriptor_set(cmd_buffer
);
3024 if (result
!= VK_SUCCESS
)
3027 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3030 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3031 struct anv_state push_state
=
3032 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3034 if (push_state
.alloc_size
) {
3035 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3036 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3037 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3042 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3044 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3050 verify_cmd_parser(const struct anv_device
*device
,
3051 int required_version
,
3052 const char *function
)
3054 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3055 return vk_errorf(device
->instance
, device
->instance
,
3056 VK_ERROR_FEATURE_NOT_PRESENT
,
3057 "cmd parser version %d is required for %s",
3058 required_version
, function
);
3067 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3068 uint32_t baseGroupX
,
3069 uint32_t baseGroupY
,
3070 uint32_t baseGroupZ
)
3072 if (anv_batch_has_error(&cmd_buffer
->batch
))
3076 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3077 base_work_group_id
);
3078 if (result
!= VK_SUCCESS
) {
3079 cmd_buffer
->batch
.status
= result
;
3083 struct anv_push_constants
*push
=
3084 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3085 if (push
->base_work_group_id
[0] != baseGroupX
||
3086 push
->base_work_group_id
[1] != baseGroupY
||
3087 push
->base_work_group_id
[2] != baseGroupZ
) {
3088 push
->base_work_group_id
[0] = baseGroupX
;
3089 push
->base_work_group_id
[1] = baseGroupY
;
3090 push
->base_work_group_id
[2] = baseGroupZ
;
3092 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3096 void genX(CmdDispatch
)(
3097 VkCommandBuffer commandBuffer
,
3102 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3105 void genX(CmdDispatchBase
)(
3106 VkCommandBuffer commandBuffer
,
3107 uint32_t baseGroupX
,
3108 uint32_t baseGroupY
,
3109 uint32_t baseGroupZ
,
3110 uint32_t groupCountX
,
3111 uint32_t groupCountY
,
3112 uint32_t groupCountZ
)
3114 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3115 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3116 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3118 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3119 baseGroupY
, baseGroupZ
);
3121 if (anv_batch_has_error(&cmd_buffer
->batch
))
3124 if (prog_data
->uses_num_work_groups
) {
3125 struct anv_state state
=
3126 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3127 uint32_t *sizes
= state
.map
;
3128 sizes
[0] = groupCountX
;
3129 sizes
[1] = groupCountY
;
3130 sizes
[2] = groupCountZ
;
3131 anv_state_flush(cmd_buffer
->device
, state
);
3132 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3133 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3134 .offset
= state
.offset
,
3138 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3140 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3141 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3142 ggw
.ThreadDepthCounterMaximum
= 0;
3143 ggw
.ThreadHeightCounterMaximum
= 0;
3144 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3145 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3146 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3147 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3148 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3149 ggw
.BottomExecutionMask
= 0xffffffff;
3152 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3155 #define GPGPU_DISPATCHDIMX 0x2500
3156 #define GPGPU_DISPATCHDIMY 0x2504
3157 #define GPGPU_DISPATCHDIMZ 0x2508
3159 void genX(CmdDispatchIndirect
)(
3160 VkCommandBuffer commandBuffer
,
3162 VkDeviceSize offset
)
3164 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3165 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3166 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3167 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3168 struct anv_bo
*bo
= buffer
->bo
;
3169 uint32_t bo_offset
= buffer
->offset
+ offset
;
3170 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3172 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3175 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3176 * indirect dispatch registers to be written.
3178 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3179 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3183 if (prog_data
->uses_num_work_groups
) {
3184 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3186 .offset
= bo_offset
,
3190 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3192 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
3193 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
3194 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
3197 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3198 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3199 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3200 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3202 /* Load compute_dispatch_indirect_x_size into SRC0 */
3203 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
3205 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3206 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3207 mip
.LoadOperation
= LOAD_LOAD
;
3208 mip
.CombineOperation
= COMBINE_SET
;
3209 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3212 /* Load compute_dispatch_indirect_y_size into SRC0 */
3213 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
3215 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3216 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3217 mip
.LoadOperation
= LOAD_LOAD
;
3218 mip
.CombineOperation
= COMBINE_OR
;
3219 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3222 /* Load compute_dispatch_indirect_z_size into SRC0 */
3223 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
3225 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3226 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3227 mip
.LoadOperation
= LOAD_LOAD
;
3228 mip
.CombineOperation
= COMBINE_OR
;
3229 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3232 /* predicate = !predicate; */
3233 #define COMPARE_FALSE 1
3234 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3235 mip
.LoadOperation
= LOAD_LOADINV
;
3236 mip
.CombineOperation
= COMBINE_OR
;
3237 mip
.CompareOperation
= COMPARE_FALSE
;
3241 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3242 ggw
.IndirectParameterEnable
= true;
3243 ggw
.PredicateEnable
= GEN_GEN
<= 7;
3244 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3245 ggw
.ThreadDepthCounterMaximum
= 0;
3246 ggw
.ThreadHeightCounterMaximum
= 0;
3247 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3248 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3249 ggw
.BottomExecutionMask
= 0xffffffff;
3252 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3256 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3259 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3261 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3264 #if GEN_GEN >= 8 && GEN_GEN < 10
3265 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3267 * Software must clear the COLOR_CALC_STATE Valid field in
3268 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3269 * with Pipeline Select set to GPGPU.
3271 * The internal hardware docs recommend the same workaround for Gen9
3274 if (pipeline
== GPGPU
)
3275 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3278 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3279 * PIPELINE_SELECT [DevBWR+]":
3283 * Software must ensure all the write caches are flushed through a
3284 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3285 * command to invalidate read only caches prior to programming
3286 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3288 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3289 pc
.RenderTargetCacheFlushEnable
= true;
3290 pc
.DepthCacheFlushEnable
= true;
3291 pc
.DCFlushEnable
= true;
3292 pc
.PostSyncOperation
= NoWrite
;
3293 pc
.CommandStreamerStallEnable
= true;
3296 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3297 pc
.TextureCacheInvalidationEnable
= true;
3298 pc
.ConstantCacheInvalidationEnable
= true;
3299 pc
.StateCacheInvalidationEnable
= true;
3300 pc
.InstructionCacheInvalidateEnable
= true;
3301 pc
.PostSyncOperation
= NoWrite
;
3304 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3308 ps
.PipelineSelection
= pipeline
;
3312 if (devinfo
->is_geminilake
) {
3315 * "This chicken bit works around a hardware issue with barrier logic
3316 * encountered when switching between GPGPU and 3D pipelines. To
3317 * workaround the issue, this mode bit should be set after a pipeline
3321 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3323 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3324 : GLK_BARRIER_MODE_3D_HULL
,
3325 .GLKBarrierModeMask
= 1);
3326 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3330 cmd_buffer
->state
.current_pipeline
= pipeline
;
3334 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3336 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3340 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3342 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3346 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3351 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3353 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3354 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3355 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3356 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3357 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3358 * Depth Flush Bit set, followed by another pipelined depth stall
3359 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3360 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3361 * via a preceding MI_FLUSH)."
3363 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3364 pipe
.DepthStallEnable
= true;
3366 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3367 pipe
.DepthCacheFlushEnable
= true;
3369 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3370 pipe
.DepthStallEnable
= true;
3375 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3377 struct anv_device
*device
= cmd_buffer
->device
;
3378 const struct anv_image_view
*iview
=
3379 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3380 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3382 /* FIXME: Width and Height are wrong */
3384 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3386 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3387 device
->isl_dev
.ds
.size
/ 4);
3391 struct isl_depth_stencil_hiz_emit_info info
= {
3392 .mocs
= device
->default_mocs
,
3396 info
.view
= &iview
->planes
[0].isl
;
3398 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3399 uint32_t depth_plane
=
3400 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3401 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3403 info
.depth_surf
= &surface
->isl
;
3405 info
.depth_address
=
3406 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3407 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3408 image
->planes
[depth_plane
].bo
,
3409 image
->planes
[depth_plane
].bo_offset
+
3413 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.attachment
;
3414 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3415 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3416 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3419 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3420 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3421 image
->planes
[depth_plane
].bo
,
3422 image
->planes
[depth_plane
].bo_offset
+
3423 image
->planes
[depth_plane
].aux_surface
.offset
);
3425 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3429 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3430 uint32_t stencil_plane
=
3431 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3432 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3434 info
.stencil_surf
= &surface
->isl
;
3436 info
.stencil_address
=
3437 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3438 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3439 image
->planes
[stencil_plane
].bo
,
3440 image
->planes
[stencil_plane
].bo_offset
+ surface
->offset
);
3443 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3445 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3449 * This ANDs the view mask of the current subpass with the pending clear
3450 * views in the attachment to get the mask of views active in the subpass
3451 * that still need to be cleared.
3453 static inline uint32_t
3454 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3455 const struct anv_attachment_state
*att_state
)
3457 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3461 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3462 const struct anv_attachment_state
*att_state
)
3464 if (!cmd_state
->subpass
->view_mask
)
3467 uint32_t pending_clear_mask
=
3468 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3470 return pending_clear_mask
& 1;
3474 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3477 const uint32_t last_subpass_idx
=
3478 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3479 const struct anv_subpass
*last_subpass
=
3480 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3481 return last_subpass
== cmd_state
->subpass
;
3485 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3486 uint32_t subpass_id
)
3488 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3489 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3490 cmd_state
->subpass
= subpass
;
3492 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3494 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3495 * different views. If the client asks for instancing, we need to use the
3496 * Instance Data Step Rate to ensure that we repeat the client's
3497 * per-instance data once for each view. Since this bit is in
3498 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3502 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3504 /* It is possible to start a render pass with an old pipeline. Because the
3505 * render pass and subpass index are both baked into the pipeline, this is
3506 * highly unlikely. In order to do so, it requires that you have a render
3507 * pass with a single subpass and that you use that render pass twice
3508 * back-to-back and use the same pipeline at the start of the second render
3509 * pass as at the end of the first. In order to avoid unpredictable issues
3510 * with this edge case, we just dirty the pipeline at the start of every
3513 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3515 /* Accumulate any subpass flushes that need to happen before the subpass */
3516 cmd_buffer
->state
.pending_pipe_bits
|=
3517 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3519 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3520 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3522 bool is_multiview
= subpass
->view_mask
!= 0;
3524 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3525 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3526 if (a
== VK_ATTACHMENT_UNUSED
)
3529 assert(a
< cmd_state
->pass
->attachment_count
);
3530 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3532 struct anv_image_view
*iview
= fb
->attachments
[a
];
3533 const struct anv_image
*image
= iview
->image
;
3535 /* A resolve is necessary before use as an input attachment if the clear
3536 * color or auxiliary buffer usage isn't supported by the sampler.
3538 const bool input_needs_resolve
=
3539 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3540 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3542 VkImageLayout target_layout
;
3543 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3544 !input_needs_resolve
) {
3545 /* Layout transitions before the final only help to enable sampling
3546 * as an input attachment. If the input attachment supports sampling
3547 * using the auxiliary surface, we can skip such transitions by
3548 * making the target layout one that is CCS-aware.
3550 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3552 target_layout
= subpass
->attachments
[i
].layout
;
3555 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3556 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3558 uint32_t base_layer
, layer_count
;
3559 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3561 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3562 iview
->planes
[0].isl
.base_level
);
3564 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3565 layer_count
= fb
->layers
;
3568 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3569 iview
->planes
[0].isl
.base_level
, 1,
3570 base_layer
, layer_count
,
3571 att_state
->current_layout
, target_layout
);
3572 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3573 transition_depth_buffer(cmd_buffer
, image
,
3574 att_state
->current_layout
, target_layout
);
3575 att_state
->aux_usage
=
3576 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3577 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3579 att_state
->current_layout
= target_layout
;
3581 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3582 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3584 /* Multi-planar images are not supported as attachments */
3585 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3586 assert(image
->n_planes
== 1);
3588 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
3589 uint32_t clear_layer_count
= fb
->layers
;
3591 if (att_state
->fast_clear
&&
3592 do_first_layer_clear(cmd_state
, att_state
)) {
3593 /* We only support fast-clears on the first layer */
3594 assert(iview
->planes
[0].isl
.base_level
== 0);
3595 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3597 if (iview
->image
->samples
== 1) {
3598 anv_image_ccs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3599 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
, false);
3601 anv_image_mcs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3602 0, 1, ISL_AUX_OP_FAST_CLEAR
, false);
3605 clear_layer_count
--;
3607 att_state
->pending_clear_views
&= ~1;
3610 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3611 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3612 true /* copy from ss */);
3614 update_fast_clear_color(cmd_buffer
, att_state
, iview
);
3617 if (att_state
->clear_color_is_zero
) {
3618 /* This image has the auxiliary buffer enabled. We can mark the
3619 * subresource as not needing a resolve because the clear color
3620 * will match what's in every RENDER_SURFACE_STATE object when
3621 * it's being used for sampling.
3623 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3624 VK_IMAGE_ASPECT_COLOR_BIT
,
3625 ANV_FAST_CLEAR_DEFAULT_VALUE
);
3627 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3628 VK_IMAGE_ASPECT_COLOR_BIT
,
3629 ANV_FAST_CLEAR_ANY
);
3633 /* From the VkFramebufferCreateInfo spec:
3635 * "If the render pass uses multiview, then layers must be one and each
3636 * attachment requires a number of layers that is greater than the
3637 * maximum bit index set in the view mask in the subpasses in which it
3640 * So if multiview is active we ignore the number of layers in the
3641 * framebuffer and instead we honor the view mask from the subpass.
3644 assert(image
->n_planes
== 1);
3645 uint32_t pending_clear_mask
=
3646 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3649 for_each_bit(layer_idx
, pending_clear_mask
) {
3651 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3653 anv_image_clear_color(cmd_buffer
, image
,
3654 VK_IMAGE_ASPECT_COLOR_BIT
,
3655 att_state
->aux_usage
,
3656 iview
->planes
[0].isl
.format
,
3657 iview
->planes
[0].isl
.swizzle
,
3658 iview
->planes
[0].isl
.base_level
,
3661 vk_to_isl_color(att_state
->clear_value
.color
));
3664 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3665 } else if (clear_layer_count
> 0) {
3666 assert(image
->n_planes
== 1);
3667 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3668 att_state
->aux_usage
,
3669 iview
->planes
[0].isl
.format
,
3670 iview
->planes
[0].isl
.swizzle
,
3671 iview
->planes
[0].isl
.base_level
,
3672 base_clear_layer
, clear_layer_count
,
3674 vk_to_isl_color(att_state
->clear_value
.color
));
3676 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
3677 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3678 if (att_state
->fast_clear
&& !is_multiview
) {
3679 /* We currently only support HiZ for single-layer images */
3680 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3681 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
3682 assert(iview
->planes
[0].isl
.base_level
== 0);
3683 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3684 assert(fb
->layers
== 1);
3687 anv_image_hiz_clear(cmd_buffer
, image
,
3688 att_state
->pending_clear_aspects
,
3689 iview
->planes
[0].isl
.base_level
,
3690 iview
->planes
[0].isl
.base_array_layer
,
3691 fb
->layers
, render_area
,
3692 att_state
->clear_value
.depthStencil
.stencil
);
3693 } else if (is_multiview
) {
3694 uint32_t pending_clear_mask
=
3695 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3698 for_each_bit(layer_idx
, pending_clear_mask
) {
3700 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3702 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3703 att_state
->pending_clear_aspects
,
3704 att_state
->aux_usage
,
3705 iview
->planes
[0].isl
.base_level
,
3708 att_state
->clear_value
.depthStencil
.depth
,
3709 att_state
->clear_value
.depthStencil
.stencil
);
3712 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3714 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3715 att_state
->pending_clear_aspects
,
3716 att_state
->aux_usage
,
3717 iview
->planes
[0].isl
.base_level
,
3718 iview
->planes
[0].isl
.base_array_layer
,
3719 fb
->layers
, render_area
,
3720 att_state
->clear_value
.depthStencil
.depth
,
3721 att_state
->clear_value
.depthStencil
.stencil
);
3724 assert(att_state
->pending_clear_aspects
== 0);
3728 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
3729 image
->planes
[0].aux_surface
.isl
.size
> 0 &&
3730 iview
->planes
[0].isl
.base_level
== 0 &&
3731 iview
->planes
[0].isl
.base_array_layer
== 0) {
3732 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
3733 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3734 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3735 false /* copy to ss */);
3738 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
3739 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3740 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3741 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3742 false /* copy to ss */);
3746 if (subpass
->attachments
[i
].usage
==
3747 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
3748 /* We assume that if we're starting a subpass, we're going to do some
3749 * rendering so we may end up with compressed data.
3751 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
3752 VK_IMAGE_ASPECT_COLOR_BIT
,
3753 att_state
->aux_usage
,
3754 iview
->planes
[0].isl
.base_level
,
3755 iview
->planes
[0].isl
.base_array_layer
,
3757 } else if (subpass
->attachments
[i
].usage
==
3758 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
3759 /* We may be writing depth or stencil so we need to mark the surface.
3760 * Unfortunately, there's no way to know at this point whether the
3761 * depth or stencil tests used will actually write to the surface.
3763 * Even though stencil may be plane 1, it always shares a base_level
3766 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
3767 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3768 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3769 VK_IMAGE_ASPECT_DEPTH_BIT
,
3770 att_state
->aux_usage
,
3771 ds_view
->base_level
,
3772 ds_view
->base_array_layer
,
3775 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
3776 /* Even though stencil may be plane 1, it always shares a
3777 * base_level with depth.
3779 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3780 VK_IMAGE_ASPECT_STENCIL_BIT
,
3782 ds_view
->base_level
,
3783 ds_view
->base_array_layer
,
3788 /* If multiview is enabled, then we are only done clearing when we no
3789 * longer have pending layers to clear, or when we have processed the
3790 * last subpass that uses this attachment.
3792 if (!is_multiview
||
3793 att_state
->pending_clear_views
== 0 ||
3794 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
3795 att_state
->pending_clear_aspects
= 0;
3798 att_state
->pending_load_aspects
= 0;
3801 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3805 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
3807 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3808 struct anv_subpass
*subpass
= cmd_state
->subpass
;
3809 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3811 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3813 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3814 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3815 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3816 if (a
== VK_ATTACHMENT_UNUSED
)
3819 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3822 assert(a
< cmd_state
->pass
->attachment_count
);
3823 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3824 struct anv_image_view
*iview
= fb
->attachments
[a
];
3825 const struct anv_image
*image
= iview
->image
;
3827 /* Transition the image into the final layout for this render pass */
3828 VkImageLayout target_layout
=
3829 cmd_state
->pass
->attachments
[a
].final_layout
;
3831 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3832 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3834 uint32_t base_layer
, layer_count
;
3835 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3837 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3838 iview
->planes
[0].isl
.base_level
);
3840 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3841 layer_count
= fb
->layers
;
3844 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3845 iview
->planes
[0].isl
.base_level
, 1,
3846 base_layer
, layer_count
,
3847 att_state
->current_layout
, target_layout
);
3848 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3849 transition_depth_buffer(cmd_buffer
, image
,
3850 att_state
->current_layout
, target_layout
);
3854 /* Accumulate any subpass flushes that need to happen after the subpass.
3855 * Yes, they do get accumulated twice in the NextSubpass case but since
3856 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
3857 * ORing the bits in twice so it's harmless.
3859 cmd_buffer
->state
.pending_pipe_bits
|=
3860 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
3863 void genX(CmdBeginRenderPass
)(
3864 VkCommandBuffer commandBuffer
,
3865 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3866 VkSubpassContents contents
)
3868 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3869 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3870 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3872 cmd_buffer
->state
.framebuffer
= framebuffer
;
3873 cmd_buffer
->state
.pass
= pass
;
3874 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3876 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3878 /* If we failed to setup the attachments we should not try to go further */
3879 if (result
!= VK_SUCCESS
) {
3880 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3884 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3886 cmd_buffer_begin_subpass(cmd_buffer
, 0);
3889 void genX(CmdNextSubpass
)(
3890 VkCommandBuffer commandBuffer
,
3891 VkSubpassContents contents
)
3893 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3895 if (anv_batch_has_error(&cmd_buffer
->batch
))
3898 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3900 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
3901 cmd_buffer_end_subpass(cmd_buffer
);
3902 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3905 void genX(CmdEndRenderPass
)(
3906 VkCommandBuffer commandBuffer
)
3908 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3910 if (anv_batch_has_error(&cmd_buffer
->batch
))
3913 cmd_buffer_end_subpass(cmd_buffer
);
3915 cmd_buffer
->state
.hiz_enabled
= false;
3918 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
3921 /* Remove references to render pass specific state. This enables us to
3922 * detect whether or not we're in a renderpass.
3924 cmd_buffer
->state
.framebuffer
= NULL
;
3925 cmd_buffer
->state
.pass
= NULL
;
3926 cmd_buffer
->state
.subpass
= NULL
;