2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
,
37 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* If we are emitting a new state base address we probably need to re-emit
73 cmd_buffer
->state
.descriptors_dirty
|= ~0;
75 /* Emit a render target cache flush.
77 * This isn't documented anywhere in the PRM. However, it seems to be
78 * necessary prior to changing the surface state base adress. Without
79 * this, we get GPU hangs when using multi-level command buffers which
80 * clear depth, reset state base address, and then go render stuff.
82 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
83 pc
.DCFlushEnable
= true;
84 pc
.RenderTargetCacheFlushEnable
= true;
85 pc
.CommandStreamerStallEnable
= true;
88 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
89 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
90 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
91 sba
.GeneralStateBaseAddressModifyEnable
= true;
93 sba
.SurfaceStateBaseAddress
=
94 anv_cmd_buffer_surface_base_address(cmd_buffer
);
95 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
96 sba
.SurfaceStateBaseAddressModifyEnable
= true;
98 sba
.DynamicStateBaseAddress
=
99 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
100 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
101 sba
.DynamicStateBaseAddressModifyEnable
= true;
103 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
104 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
105 sba
.IndirectObjectBaseAddressModifyEnable
= true;
107 sba
.InstructionBaseAddress
=
108 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
109 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
110 sba
.InstructionBaseAddressModifyEnable
= true;
113 /* Broadwell requires that we specify a buffer size for a bunch of
114 * these fields. However, since we will be growing the BO's live, we
115 * just set them all to the maximum.
117 sba
.GeneralStateBufferSize
= 0xfffff;
118 sba
.GeneralStateBufferSizeModifyEnable
= true;
119 sba
.DynamicStateBufferSize
= 0xfffff;
120 sba
.DynamicStateBufferSizeModifyEnable
= true;
121 sba
.IndirectObjectBufferSize
= 0xfffff;
122 sba
.IndirectObjectBufferSizeModifyEnable
= true;
123 sba
.InstructionBufferSize
= 0xfffff;
124 sba
.InstructionBuffersizeModifyEnable
= true;
128 /* After re-setting the surface state base address, we have to do some
129 * cache flusing so that the sampler engine will pick up the new
130 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
131 * Shared Function > 3D Sampler > State > State Caching (page 96):
133 * Coherency with system memory in the state cache, like the texture
134 * cache is handled partially by software. It is expected that the
135 * command stream or shader will issue Cache Flush operation or
136 * Cache_Flush sampler message to ensure that the L1 cache remains
137 * coherent with system memory.
141 * Whenever the value of the Dynamic_State_Base_Addr,
142 * Surface_State_Base_Addr are altered, the L1 state cache must be
143 * invalidated to ensure the new surface or sampler state is fetched
144 * from system memory.
146 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
147 * which, according the PIPE_CONTROL instruction documentation in the
150 * Setting this bit is independent of any other bit in this packet.
151 * This bit controls the invalidation of the L1 and L2 state caches
152 * at the top of the pipe i.e. at the parsing time.
154 * Unfortunately, experimentation seems to indicate that state cache
155 * invalidation through a PIPE_CONTROL does nothing whatsoever in
156 * regards to surface state and binding tables. In stead, it seems that
157 * invalidating the texture cache is what is actually needed.
159 * XXX: As far as we have been able to determine through
160 * experimentation, shows that flush the texture cache appears to be
161 * sufficient. The theory here is that all of the sampling/rendering
162 * units cache the binding table in the texture cache. However, we have
163 * yet to be able to actually confirm this.
165 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
166 pc
.TextureCacheInvalidationEnable
= true;
167 pc
.ConstantCacheInvalidationEnable
= true;
168 pc
.StateCacheInvalidationEnable
= true;
173 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
174 struct anv_state state
, struct anv_address addr
)
176 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
179 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
180 state
.offset
+ isl_dev
->ss
.addr_offset
,
181 addr
.bo
, addr
.offset
);
182 if (result
!= VK_SUCCESS
)
183 anv_batch_set_error(&cmd_buffer
->batch
, result
);
187 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
188 struct anv_surface_state state
)
190 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
192 assert(!anv_address_is_null(state
.address
));
193 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
195 if (!anv_address_is_null(state
.aux_address
)) {
197 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
198 &cmd_buffer
->pool
->alloc
,
199 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
200 state
.aux_address
.bo
, state
.aux_address
.offset
);
201 if (result
!= VK_SUCCESS
)
202 anv_batch_set_error(&cmd_buffer
->batch
, result
);
205 if (!anv_address_is_null(state
.clear_address
)) {
207 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
208 &cmd_buffer
->pool
->alloc
,
210 isl_dev
->ss
.clear_color_state_offset
,
211 state
.clear_address
.bo
, state
.clear_address
.offset
);
212 if (result
!= VK_SUCCESS
)
213 anv_batch_set_error(&cmd_buffer
->batch
, result
);
218 color_attachment_compute_aux_usage(struct anv_device
* device
,
219 struct anv_cmd_state
* cmd_state
,
220 uint32_t att
, VkRect2D render_area
,
221 union isl_color_value
*fast_clear_color
)
223 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
224 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
226 assert(iview
->n_planes
== 1);
228 if (iview
->planes
[0].isl
.base_array_layer
>=
229 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
230 iview
->planes
[0].isl
.base_level
)) {
231 /* There is no aux buffer which corresponds to the level and layer(s)
234 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
235 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
236 att_state
->fast_clear
= false;
240 att_state
->aux_usage
=
241 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
242 VK_IMAGE_ASPECT_COLOR_BIT
,
243 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
245 /* If we don't have aux, then we should have returned early in the layer
246 * check above. If we got here, we must have something.
248 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
250 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
251 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
252 att_state
->input_aux_usage
= att_state
->aux_usage
;
254 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
256 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
257 * setting is only allowed if Surface Format supported for Fast
258 * Clear. In addition, if the surface is bound to the sampling
259 * engine, Surface Format must be supported for Render Target
260 * Compression for surfaces bound to the sampling engine."
262 * In other words, we can only sample from a fast-cleared image if it
263 * also supports color compression.
265 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
266 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
268 /* While fast-clear resolves and partial resolves are fairly cheap in the
269 * case where you render to most of the pixels, full resolves are not
270 * because they potentially involve reading and writing the entire
271 * framebuffer. If we can't texture with CCS_E, we should leave it off and
272 * limit ourselves to fast clears.
274 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
275 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
276 anv_perf_warn(device
->instance
, iview
->image
,
277 "Not temporarily enabling CCS_E.");
280 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
284 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
285 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
287 union isl_color_value clear_color
= {};
288 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
290 att_state
->clear_color_is_zero_one
=
291 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
292 att_state
->clear_color_is_zero
=
293 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
295 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
296 /* Start by getting the fast clear type. We use the first subpass
297 * layout here because we don't want to fast-clear if the first subpass
298 * to use the attachment can't handle fast-clears.
300 enum anv_fast_clear_type fast_clear_type
=
301 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
302 VK_IMAGE_ASPECT_COLOR_BIT
,
303 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
304 switch (fast_clear_type
) {
305 case ANV_FAST_CLEAR_NONE
:
306 att_state
->fast_clear
= false;
308 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
309 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
311 case ANV_FAST_CLEAR_ANY
:
312 att_state
->fast_clear
= true;
316 /* Potentially, we could do partial fast-clears but doing so has crazy
317 * alignment restrictions. It's easier to just restrict to full size
318 * fast clears for now.
320 if (render_area
.offset
.x
!= 0 ||
321 render_area
.offset
.y
!= 0 ||
322 render_area
.extent
.width
!= iview
->extent
.width
||
323 render_area
.extent
.height
!= iview
->extent
.height
)
324 att_state
->fast_clear
= false;
326 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
327 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
328 att_state
->fast_clear
= false;
330 /* We only allow fast clears to the first slice of an image (level 0,
331 * layer 0) and only for the entire slice. This guarantees us that, at
332 * any given time, there is only one clear color on any given image at
333 * any given time. At the time of our testing (Jan 17, 2018), there
334 * were no known applications which would benefit from fast-clearing
335 * more than just the first slice.
337 if (att_state
->fast_clear
&&
338 (iview
->planes
[0].isl
.base_level
> 0 ||
339 iview
->planes
[0].isl
.base_array_layer
> 0)) {
340 anv_perf_warn(device
->instance
, iview
->image
,
341 "Rendering with multi-lod or multi-layer framebuffer "
342 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
343 "baseArrayLayer > 0. Not fast clearing.");
344 att_state
->fast_clear
= false;
345 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
346 anv_perf_warn(device
->instance
, iview
->image
,
347 "Rendering to a multi-layer framebuffer with "
348 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
351 if (att_state
->fast_clear
)
352 *fast_clear_color
= clear_color
;
354 att_state
->fast_clear
= false;
359 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
360 struct anv_cmd_state
*cmd_state
,
361 uint32_t att
, VkRect2D render_area
)
363 struct anv_render_pass_attachment
*pass_att
=
364 &cmd_state
->pass
->attachments
[att
];
365 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
366 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
368 /* These will be initialized after the first subpass transition. */
369 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
370 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
373 /* We don't do any HiZ or depth fast-clears on gen7 yet */
374 att_state
->fast_clear
= false;
378 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
379 /* If we're just clearing stencil, we can always HiZ clear */
380 att_state
->fast_clear
= true;
384 /* Default to false for now */
385 att_state
->fast_clear
= false;
387 /* We must have depth in order to have HiZ */
388 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
391 const enum isl_aux_usage first_subpass_aux_usage
=
392 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
393 VK_IMAGE_ASPECT_DEPTH_BIT
,
394 pass_att
->first_subpass_layout
);
395 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
398 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
399 iview
->planes
[0].isl
.format
,
400 iview
->image
->samples
,
401 render_area
.offset
.x
,
402 render_area
.offset
.y
,
403 render_area
.offset
.x
+
404 render_area
.extent
.width
,
405 render_area
.offset
.y
+
406 render_area
.extent
.height
))
409 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
412 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
413 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
414 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
415 * only supports returning 0.0f. Gens prior to gen8 do not support this
421 /* If we got here, then we can fast clear */
422 att_state
->fast_clear
= true;
426 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
428 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
431 /* We only allocate input attachment states for color surfaces. Compression
432 * is not yet enabled for depth textures and stencil doesn't allow
433 * compression so we can just use the texture surface state from the view.
435 return vk_format_is_color(att
->format
);
438 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
439 * the initial layout is undefined, the HiZ buffer and depth buffer will
440 * represent the same data at the end of this operation.
443 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
444 const struct anv_image
*image
,
445 VkImageLayout initial_layout
,
446 VkImageLayout final_layout
)
448 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
449 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
450 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
451 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
452 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
453 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
455 enum isl_aux_op hiz_op
;
456 if (hiz_enabled
&& !enable_hiz
) {
457 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
458 } else if (!hiz_enabled
&& enable_hiz
) {
459 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
461 assert(hiz_enabled
== enable_hiz
);
462 /* If the same buffer will be used, no resolves are necessary. */
463 hiz_op
= ISL_AUX_OP_NONE
;
466 if (hiz_op
!= ISL_AUX_OP_NONE
)
467 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
471 #define MI_PREDICATE_SRC0 0x2400
472 #define MI_PREDICATE_SRC1 0x2408
475 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
476 const struct anv_image
*image
,
477 VkImageAspectFlagBits aspect
,
479 uint32_t base_layer
, uint32_t layer_count
,
482 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
484 /* We only have compression tracking for CCS_E */
485 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
488 for (uint32_t a
= 0; a
< layer_count
; a
++) {
489 uint32_t layer
= base_layer
+ a
;
490 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
491 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
494 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
500 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
501 const struct anv_image
*image
,
502 VkImageAspectFlagBits aspect
,
503 enum anv_fast_clear_type fast_clear
)
505 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
506 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
508 sdi
.ImmediateData
= fast_clear
;
511 /* Whenever we have fast-clear, we consider that slice to be compressed.
512 * This makes building predicates much easier.
514 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
515 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
518 #if GEN_IS_HASWELL || GEN_GEN >= 8
519 static inline uint32_t
520 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
522 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
524 .Operand1
= operand1
,
525 .Operand2
= operand2
,
529 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
535 #define CS_GPR(n) (0x2600 + (n) * 8)
537 /* This is only really practical on haswell and above because it requires
538 * MI math in order to get it correct.
540 #if GEN_GEN >= 8 || GEN_IS_HASWELL
542 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
543 const struct anv_image
*image
,
544 VkImageAspectFlagBits aspect
,
545 uint32_t level
, uint32_t array_layer
,
546 enum isl_aux_op resolve_op
,
547 enum anv_fast_clear_type fast_clear_supported
)
549 struct anv_address fast_clear_type_addr
=
550 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
552 /* Name some registers */
553 const int image_fc_reg
= MI_ALU_REG0
;
554 const int fc_imm_reg
= MI_ALU_REG1
;
555 const int pred_reg
= MI_ALU_REG2
;
559 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
560 /* In this case, we're doing a full resolve which means we want the
561 * resolve to happen if any compression (including fast-clears) is
564 * In order to simplify the logic a bit, we make the assumption that,
565 * if the first slice has been fast-cleared, it is also marked as
566 * compressed. See also set_image_fast_clear_state.
568 struct anv_address compression_state_addr
=
569 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
570 aspect
, level
, array_layer
);
571 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
572 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
573 lrm
.MemoryAddress
= compression_state_addr
;
575 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
576 sdi
.Address
= compression_state_addr
;
577 sdi
.ImmediateData
= 0;
580 if (level
== 0 && array_layer
== 0) {
581 /* If the predicate is true, we want to write 0 to the fast clear type
582 * and, if it's false, leave it alone. We can do this by writing
584 * clear_type = clear_type & ~predicate;
586 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
587 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
588 lrm
.MemoryAddress
= fast_clear_type_addr
;
590 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
591 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
592 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
595 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
596 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
597 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
598 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
599 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
601 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
602 srm
.MemoryAddress
= fast_clear_type_addr
;
603 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
606 } else if (level
== 0 && array_layer
== 0) {
607 /* In this case, we are doing a partial resolve to get rid of fast-clear
608 * colors. We don't care about the compression state but we do care
609 * about how much fast clear is allowed by the final layout.
611 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
612 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
614 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
615 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
616 lrm
.MemoryAddress
= fast_clear_type_addr
;
618 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
620 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
621 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
623 /* We need to compute (fast_clear_supported < image->fast_clear).
624 * We do this by subtracting and storing the carry bit.
626 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
627 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
628 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
629 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
630 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
632 /* Store the predicate */
633 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
635 /* If the predicate is true, we want to write 0 to the fast clear type
636 * and, if it's false, leave it alone. We can do this by writing
638 * clear_type = clear_type & ~predicate;
640 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
641 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
642 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
643 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
644 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
646 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
647 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
648 srm
.MemoryAddress
= fast_clear_type_addr
;
651 /* In this case, we're trying to do a partial resolve on a slice that
652 * doesn't have clear color. There's nothing to do.
654 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
658 /* We use the first half of src0 for the actual predicate. Set the second
659 * half of src0 and all of src1 to 0 as the predicate operation will be
660 * doing an implicit src0 != src1.
662 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
663 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
664 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
666 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
667 mip
.LoadOperation
= LOAD_LOADINV
;
668 mip
.CombineOperation
= COMBINE_SET
;
669 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
672 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
676 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
677 const struct anv_image
*image
,
678 VkImageAspectFlagBits aspect
,
679 uint32_t level
, uint32_t array_layer
,
680 enum isl_aux_op resolve_op
,
681 enum anv_fast_clear_type fast_clear_supported
)
683 struct anv_address fast_clear_type_addr
=
684 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
686 /* This only works for partial resolves and only when the clear color is
687 * all or nothing. On the upside, this emits less command streamer code
688 * and works on Ivybridge and Bay Trail.
690 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
691 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
693 /* We don't support fast clears on anything other than the first slice. */
694 if (level
> 0 || array_layer
> 0)
697 /* On gen8, we don't have a concept of default clear colors because we
698 * can't sample from CCS surfaces. It's enough to just load the fast clear
699 * state into the predicate register.
701 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
702 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
703 lrm
.MemoryAddress
= fast_clear_type_addr
;
705 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
706 sdi
.Address
= fast_clear_type_addr
;
707 sdi
.ImmediateData
= 0;
710 /* We use the first half of src0 for the actual predicate. Set the second
711 * half of src0 and all of src1 to 0 as the predicate operation will be
712 * doing an implicit src0 != src1.
714 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
715 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
716 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
718 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
719 mip
.LoadOperation
= LOAD_LOADINV
;
720 mip
.CombineOperation
= COMBINE_SET
;
721 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
724 #endif /* GEN_GEN <= 8 */
727 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
728 const struct anv_image
*image
,
729 VkImageAspectFlagBits aspect
,
730 uint32_t level
, uint32_t array_layer
,
731 enum isl_aux_op resolve_op
,
732 enum anv_fast_clear_type fast_clear_supported
)
734 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
737 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
738 aspect
, level
, array_layer
,
739 resolve_op
, fast_clear_supported
);
740 #else /* GEN_GEN <= 8 */
741 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
742 aspect
, level
, array_layer
,
743 resolve_op
, fast_clear_supported
);
746 /* CCS_D only supports full resolves and BLORP will assert on us if we try
747 * to do a partial resolve on a CCS_D surface.
749 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
750 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
751 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
753 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
754 array_layer
, 1, resolve_op
, NULL
, true);
758 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
759 const struct anv_image
*image
,
760 VkImageAspectFlagBits aspect
,
761 uint32_t array_layer
,
762 enum isl_aux_op resolve_op
,
763 enum anv_fast_clear_type fast_clear_supported
)
765 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
766 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
768 #if GEN_GEN >= 8 || GEN_IS_HASWELL
769 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
770 aspect
, 0, array_layer
,
771 resolve_op
, fast_clear_supported
);
773 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
774 array_layer
, 1, resolve_op
, NULL
, true);
776 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
781 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
782 const struct anv_image
*image
,
783 VkImageAspectFlagBits aspect
,
784 enum isl_aux_usage aux_usage
,
787 uint32_t layer_count
)
789 /* The aspect must be exactly one of the image aspects. */
790 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
792 /* The only compression types with more than just fast-clears are MCS,
793 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
794 * track the current fast-clear and compression state. This leaves us
795 * with just MCS and CCS_E.
797 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
798 aux_usage
!= ISL_AUX_USAGE_MCS
)
801 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
802 level
, base_layer
, layer_count
, true);
806 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
807 const struct anv_image
*image
,
808 VkImageAspectFlagBits aspect
)
810 assert(cmd_buffer
&& image
);
811 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
813 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
814 ANV_FAST_CLEAR_NONE
);
816 /* The fast clear value dword(s) will be copied into a surface state object.
817 * Ensure that the restrictions of the fields in the dword(s) are followed.
819 * CCS buffers on SKL+ can have any value set for the clear colors.
821 if (image
->samples
== 1 && GEN_GEN
>= 9)
824 /* Other combinations of auxiliary buffers and platforms require specific
825 * values in the clear value dword(s).
827 struct anv_address addr
=
828 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
831 for (unsigned i
= 0; i
< 4; i
++) {
832 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
834 sdi
.Address
.offset
+= i
* 4;
835 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
836 assert(image
->samples
> 1);
837 sdi
.ImmediateData
= 0;
841 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
843 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
844 /* Pre-SKL, the dword containing the clear values also contains
845 * other fields, so we need to initialize those fields to match the
846 * values that would be in a color attachment.
848 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
849 ISL_CHANNEL_SELECT_GREEN
<< 22 |
850 ISL_CHANNEL_SELECT_BLUE
<< 19 |
851 ISL_CHANNEL_SELECT_ALPHA
<< 16;
852 } else if (GEN_GEN
== 7) {
853 /* On IVB, the dword containing the clear values also contains
854 * other fields that must be zero or can be zero.
856 sdi
.ImmediateData
= 0;
862 /* Copy the fast-clear value dword(s) between a surface state object and an
863 * image's fast clear state buffer.
866 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
867 struct anv_state surface_state
,
868 const struct anv_image
*image
,
869 VkImageAspectFlagBits aspect
,
870 bool copy_from_surface_state
)
872 assert(cmd_buffer
&& image
);
873 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
875 struct anv_bo
*ss_bo
=
876 &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
;
877 uint32_t ss_clear_offset
= surface_state
.offset
+
878 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
;
879 const struct anv_address entry_addr
=
880 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
881 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
883 if (copy_from_surface_state
) {
884 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
.bo
, entry_addr
.offset
,
885 ss_bo
, ss_clear_offset
, copy_size
);
887 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_bo
, ss_clear_offset
,
888 entry_addr
.bo
, entry_addr
.offset
, copy_size
);
890 /* Updating a surface state object may require that the state cache be
891 * invalidated. From the SKL PRM, Shared Functions -> State -> State
894 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
895 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
896 * modified [...], the L1 state cache must be invalidated to ensure
897 * the new surface or sampler state is fetched from system memory.
899 * In testing, SKL doesn't actually seem to need this, but HSW does.
901 cmd_buffer
->state
.pending_pipe_bits
|=
902 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
907 * @brief Transitions a color buffer from one layout to another.
909 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
912 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
913 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
914 * this represents the maximum layers to transition at each
915 * specified miplevel.
918 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
919 const struct anv_image
*image
,
920 VkImageAspectFlagBits aspect
,
921 const uint32_t base_level
, uint32_t level_count
,
922 uint32_t base_layer
, uint32_t layer_count
,
923 VkImageLayout initial_layout
,
924 VkImageLayout final_layout
)
926 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
927 /* Validate the inputs. */
929 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
930 /* These values aren't supported for simplicity's sake. */
931 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
932 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
933 /* Ensure the subresource range is valid. */
934 uint64_t last_level_num
= base_level
+ level_count
;
935 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
936 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
937 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
938 assert(last_level_num
<= image
->levels
);
939 /* The spec disallows these final layouts. */
940 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
941 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
943 /* No work is necessary if the layout stays the same or if this subresource
944 * range lacks auxiliary data.
946 if (initial_layout
== final_layout
)
949 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
951 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
952 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
953 /* This surface is a linear compressed image with a tiled shadow surface
954 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
955 * we need to ensure the shadow copy is up-to-date.
957 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
958 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
959 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
960 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
962 anv_image_copy_to_shadow(cmd_buffer
, image
,
963 base_level
, level_count
,
964 base_layer
, layer_count
);
967 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
970 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
972 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
973 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
974 /* A subresource in the undefined layout may have been aliased and
975 * populated with any arrangement of bits. Therefore, we must initialize
976 * the related aux buffer and clear buffer entry with desirable values.
977 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
978 * images with VK_IMAGE_TILING_OPTIMAL.
980 * Initialize the relevant clear buffer entries.
982 if (base_level
== 0 && base_layer
== 0)
983 init_fast_clear_color(cmd_buffer
, image
, aspect
);
985 /* Initialize the aux buffers to enable correct rendering. In order to
986 * ensure that things such as storage images work correctly, aux buffers
987 * need to be initialized to valid data.
989 * Having an aux buffer with invalid data is a problem for two reasons:
991 * 1) Having an invalid value in the buffer can confuse the hardware.
992 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
993 * invalid and leads to the hardware doing strange things. It
994 * doesn't hang as far as we can tell but rendering corruption can
997 * 2) If this transition is into the GENERAL layout and we then use the
998 * image as a storage image, then we must have the aux buffer in the
999 * pass-through state so that, if we then go to texture from the
1000 * image, we get the results of our storage image writes and not the
1001 * fast clear color or other random data.
1003 * For CCS both of the problems above are real demonstrable issues. In
1004 * that case, the only thing we can do is to perform an ambiguate to
1005 * transition the aux surface into the pass-through state.
1007 * For MCS, (2) is never an issue because we don't support multisampled
1008 * storage images. In theory, issue (1) is a problem with MCS but we've
1009 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1010 * theory, be interpreted as something but we don't know that all bit
1011 * patterns are actually valid. For 2x and 8x, you could easily end up
1012 * with the MCS referring to an invalid plane because not all bits of
1013 * the MCS value are actually used. Even though we've never seen issues
1014 * in the wild, it's best to play it safe and initialize the MCS. We
1015 * can use a fast-clear for MCS because we only ever touch from render
1016 * and texture (no image load store).
1018 if (image
->samples
== 1) {
1019 for (uint32_t l
= 0; l
< level_count
; l
++) {
1020 const uint32_t level
= base_level
+ l
;
1022 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1023 if (base_layer
>= aux_layers
)
1024 break; /* We will only get fewer layers as level increases */
1025 uint32_t level_layer_count
=
1026 MIN2(layer_count
, aux_layers
- base_layer
);
1028 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
1029 base_layer
, level_layer_count
,
1030 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1032 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1033 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1034 level
, base_layer
, level_layer_count
,
1039 if (image
->samples
== 4 || image
->samples
== 16) {
1040 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1041 "Doing a potentially unnecessary fast-clear to "
1042 "define an MCS buffer.");
1045 assert(base_level
== 0 && level_count
== 1);
1046 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
1047 base_layer
, layer_count
,
1048 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1053 const enum isl_aux_usage initial_aux_usage
=
1054 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1055 const enum isl_aux_usage final_aux_usage
=
1056 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1058 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1059 * We can handle transitions between CCS_D/E to and from NONE. What we
1060 * don't yet handle is switching between CCS_E and CCS_D within a given
1061 * image. Doing so in a performant way requires more detailed aux state
1062 * tracking such as what is done in i965. For now, just assume that we
1063 * only have one type of compression.
1065 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1066 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1067 initial_aux_usage
== final_aux_usage
);
1069 /* If initial aux usage is NONE, there is nothing to resolve */
1070 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1073 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1075 /* If the initial layout supports more fast clear than the final layout
1076 * then we need at least a partial resolve.
1078 const enum anv_fast_clear_type initial_fast_clear
=
1079 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1080 const enum anv_fast_clear_type final_fast_clear
=
1081 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1082 if (final_fast_clear
< initial_fast_clear
)
1083 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1085 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1086 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1087 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1089 if (resolve_op
== ISL_AUX_OP_NONE
)
1092 /* Perform a resolve to synchronize data between the main and aux buffer.
1093 * Before we begin, we must satisfy the cache flushing requirement specified
1094 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1096 * Any transition from any value in {Clear, Render, Resolve} to a
1097 * different value in {Clear, Render, Resolve} requires end of pipe
1100 * We perform a flush of the write cache before and after the clear and
1101 * resolve operations to meet this requirement.
1103 * Unlike other drawing, fast clear operations are not properly
1104 * synchronized. The first PIPE_CONTROL here likely ensures that the
1105 * contents of the previous render or clear hit the render target before we
1106 * resolve and the second likely ensures that the resolve is complete before
1107 * we do any more rendering or clearing.
1109 cmd_buffer
->state
.pending_pipe_bits
|=
1110 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1112 for (uint32_t l
= 0; l
< level_count
; l
++) {
1113 uint32_t level
= base_level
+ l
;
1115 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1116 if (base_layer
>= aux_layers
)
1117 break; /* We will only get fewer layers as level increases */
1118 uint32_t level_layer_count
=
1119 MIN2(layer_count
, aux_layers
- base_layer
);
1121 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1122 uint32_t array_layer
= base_layer
+ a
;
1123 if (image
->samples
== 1) {
1124 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
, aspect
,
1125 level
, array_layer
, resolve_op
,
1128 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
, aspect
,
1129 array_layer
, resolve_op
,
1135 cmd_buffer
->state
.pending_pipe_bits
|=
1136 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1140 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1143 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1144 struct anv_render_pass
*pass
,
1145 const VkRenderPassBeginInfo
*begin
)
1147 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1148 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1150 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1152 if (pass
->attachment_count
> 0) {
1153 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1154 pass
->attachment_count
*
1155 sizeof(state
->attachments
[0]),
1156 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1157 if (state
->attachments
== NULL
) {
1158 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1159 return anv_batch_set_error(&cmd_buffer
->batch
,
1160 VK_ERROR_OUT_OF_HOST_MEMORY
);
1163 state
->attachments
= NULL
;
1166 /* Reserve one for the NULL state. */
1167 unsigned num_states
= 1;
1168 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1169 if (vk_format_is_color(pass
->attachments
[i
].format
))
1172 if (need_input_attachment_state(&pass
->attachments
[i
]))
1176 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1177 state
->render_pass_states
=
1178 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1179 num_states
* ss_stride
, isl_dev
->ss
.align
);
1181 struct anv_state next_state
= state
->render_pass_states
;
1182 next_state
.alloc_size
= isl_dev
->ss
.size
;
1184 state
->null_surface_state
= next_state
;
1185 next_state
.offset
+= ss_stride
;
1186 next_state
.map
+= ss_stride
;
1188 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1189 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1190 state
->attachments
[i
].color
.state
= next_state
;
1191 next_state
.offset
+= ss_stride
;
1192 next_state
.map
+= ss_stride
;
1195 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1196 state
->attachments
[i
].input
.state
= next_state
;
1197 next_state
.offset
+= ss_stride
;
1198 next_state
.map
+= ss_stride
;
1201 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1202 state
->render_pass_states
.alloc_size
);
1205 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1206 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1208 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1209 isl_extent3d(framebuffer
->width
,
1210 framebuffer
->height
,
1211 framebuffer
->layers
));
1213 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1214 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1215 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1216 VkImageAspectFlags clear_aspects
= 0;
1217 VkImageAspectFlags load_aspects
= 0;
1219 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1220 /* color attachment */
1221 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1222 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1223 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1224 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1227 /* depthstencil attachment */
1228 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1229 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1230 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1231 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1232 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1235 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1236 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1237 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1238 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1239 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1244 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1245 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1246 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1248 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1250 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1251 anv_assert(iview
->vk_format
== att
->format
);
1253 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1254 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1256 union isl_color_value clear_color
= { .u32
= { 0, } };
1257 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1258 anv_assert(iview
->n_planes
== 1);
1259 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1260 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1261 state
, i
, begin
->renderArea
,
1264 anv_image_fill_surface_state(cmd_buffer
->device
,
1266 VK_IMAGE_ASPECT_COLOR_BIT
,
1267 &iview
->planes
[0].isl
,
1268 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1269 state
->attachments
[i
].aux_usage
,
1272 &state
->attachments
[i
].color
,
1275 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1277 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1282 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1283 anv_image_fill_surface_state(cmd_buffer
->device
,
1285 VK_IMAGE_ASPECT_COLOR_BIT
,
1286 &iview
->planes
[0].isl
,
1287 ISL_SURF_USAGE_TEXTURE_BIT
,
1288 state
->attachments
[i
].input_aux_usage
,
1291 &state
->attachments
[i
].input
,
1294 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1303 genX(BeginCommandBuffer
)(
1304 VkCommandBuffer commandBuffer
,
1305 const VkCommandBufferBeginInfo
* pBeginInfo
)
1307 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1309 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1310 * command buffer's state. Otherwise, we must *reset* its state. In both
1311 * cases we reset it.
1313 * From the Vulkan 1.0 spec:
1315 * If a command buffer is in the executable state and the command buffer
1316 * was allocated from a command pool with the
1317 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1318 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1319 * as if vkResetCommandBuffer had been called with
1320 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1321 * the command buffer in the recording state.
1323 anv_cmd_buffer_reset(cmd_buffer
);
1325 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1327 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1328 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1330 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1332 /* We sometimes store vertex data in the dynamic state buffer for blorp
1333 * operations and our dynamic state stream may re-use data from previous
1334 * command buffers. In order to prevent stale cache data, we flush the VF
1335 * cache. We could do this on every blorp call but that's not really
1336 * needed as all of the data will get written by the CPU prior to the GPU
1337 * executing anything. The chances are fairly high that they will use
1338 * blorp at least once per primary command buffer so it shouldn't be
1341 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1342 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1344 /* We send an "Indirect State Pointers Disable" packet at
1345 * EndCommandBuffer, so all push contant packets are ignored during a
1346 * context restore. Documentation says after that command, we need to
1347 * emit push constants again before any rendering operation. So we
1348 * flag them dirty here to make sure they get emitted.
1350 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1352 VkResult result
= VK_SUCCESS
;
1353 if (cmd_buffer
->usage_flags
&
1354 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1355 assert(pBeginInfo
->pInheritanceInfo
);
1356 cmd_buffer
->state
.pass
=
1357 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1358 cmd_buffer
->state
.subpass
=
1359 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1361 /* This is optional in the inheritance info. */
1362 cmd_buffer
->state
.framebuffer
=
1363 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1365 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1366 cmd_buffer
->state
.pass
, NULL
);
1368 /* Record that HiZ is enabled if we can. */
1369 if (cmd_buffer
->state
.framebuffer
) {
1370 const struct anv_image_view
* const iview
=
1371 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1374 VkImageLayout layout
=
1375 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1377 enum isl_aux_usage aux_usage
=
1378 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1379 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1381 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1385 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1391 /* From the PRM, Volume 2a:
1393 * "Indirect State Pointers Disable
1395 * At the completion of the post-sync operation associated with this pipe
1396 * control packet, the indirect state pointers in the hardware are
1397 * considered invalid; the indirect pointers are not saved in the context.
1398 * If any new indirect state commands are executed in the command stream
1399 * while the pipe control is pending, the new indirect state commands are
1402 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1403 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1404 * commands are only considered as Indirect State Pointers. Once ISP is
1405 * issued in a context, SW must initialize by programming push constant
1406 * commands for all the shaders (at least to zero length) before attempting
1407 * any rendering operation for the same context."
1409 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1410 * even though they point to a BO that has been already unreferenced at
1411 * the end of the previous batch buffer. This has been fine so far since
1412 * we are protected by these scratch page (every address not covered by
1413 * a BO should be pointing to the scratch page). But on CNL, it is
1414 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1417 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1418 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1419 * context restore, so the mentioned hang doesn't happen. However,
1420 * software must program push constant commands for all stages prior to
1421 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1423 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1424 * constants have been loaded into the EUs prior to disable the push constants
1425 * so that it doesn't hang a previous 3DPRIMITIVE.
1428 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1430 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1431 pc
.StallAtPixelScoreboard
= true;
1432 pc
.CommandStreamerStallEnable
= true;
1434 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1435 pc
.IndirectStatePointersDisable
= true;
1436 pc
.CommandStreamerStallEnable
= true;
1441 genX(EndCommandBuffer
)(
1442 VkCommandBuffer commandBuffer
)
1444 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1446 if (anv_batch_has_error(&cmd_buffer
->batch
))
1447 return cmd_buffer
->batch
.status
;
1449 /* We want every command buffer to start with the PMA fix in a known state,
1450 * so we disable it at the end of the command buffer.
1452 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1454 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1456 emit_isp_disable(cmd_buffer
);
1458 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1464 genX(CmdExecuteCommands
)(
1465 VkCommandBuffer commandBuffer
,
1466 uint32_t commandBufferCount
,
1467 const VkCommandBuffer
* pCmdBuffers
)
1469 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1471 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1473 if (anv_batch_has_error(&primary
->batch
))
1476 /* The secondary command buffers will assume that the PMA fix is disabled
1477 * when they begin executing. Make sure this is true.
1479 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1481 /* The secondary command buffer doesn't know which textures etc. have been
1482 * flushed prior to their execution. Apply those flushes now.
1484 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1486 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1487 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1489 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1490 assert(!anv_batch_has_error(&secondary
->batch
));
1492 if (secondary
->usage_flags
&
1493 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1494 /* If we're continuing a render pass from the primary, we need to
1495 * copy the surface states for the current subpass into the storage
1496 * we allocated for them in BeginCommandBuffer.
1498 struct anv_bo
*ss_bo
=
1499 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1500 struct anv_state src_state
= primary
->state
.render_pass_states
;
1501 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1502 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1504 genX(cmd_buffer_so_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
1505 ss_bo
, src_state
.offset
,
1506 src_state
.alloc_size
);
1509 anv_cmd_buffer_add_secondary(primary
, secondary
);
1512 /* The secondary may have selected a different pipeline (3D or compute) and
1513 * may have changed the current L3$ configuration. Reset our tracking
1514 * variables to invalid values to ensure that we re-emit these in the case
1515 * where we do any draws or compute dispatches from the primary after the
1516 * secondary has returned.
1518 primary
->state
.current_pipeline
= UINT32_MAX
;
1519 primary
->state
.current_l3_config
= NULL
;
1521 /* Each of the secondary command buffers will use its own state base
1522 * address. We need to re-emit state base address for the primary after
1523 * all of the secondaries are done.
1525 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1528 genX(cmd_buffer_emit_state_base_address
)(primary
);
1531 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1532 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1533 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1536 * Program the hardware to use the specified L3 configuration.
1539 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1540 const struct gen_l3_config
*cfg
)
1543 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1546 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1547 intel_logd("L3 config transition: ");
1548 gen_dump_l3_config(cfg
, stderr
);
1551 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1553 /* According to the hardware docs, the L3 partitioning can only be changed
1554 * while the pipeline is completely drained and the caches are flushed,
1555 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1557 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1558 pc
.DCFlushEnable
= true;
1559 pc
.PostSyncOperation
= NoWrite
;
1560 pc
.CommandStreamerStallEnable
= true;
1563 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1564 * invalidation of the relevant caches. Note that because RO invalidation
1565 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1566 * command is processed by the CS) we cannot combine it with the previous
1567 * stalling flush as the hardware documentation suggests, because that
1568 * would cause the CS to stall on previous rendering *after* RO
1569 * invalidation and wouldn't prevent the RO caches from being polluted by
1570 * concurrent rendering before the stall completes. This intentionally
1571 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1572 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1573 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1574 * already guarantee that there is no concurrent GPGPU kernel execution
1575 * (see SKL HSD 2132585).
1577 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1578 pc
.TextureCacheInvalidationEnable
= true;
1579 pc
.ConstantCacheInvalidationEnable
= true;
1580 pc
.InstructionCacheInvalidateEnable
= true;
1581 pc
.StateCacheInvalidationEnable
= true;
1582 pc
.PostSyncOperation
= NoWrite
;
1585 /* Now send a third stalling flush to make sure that invalidation is
1586 * complete when the L3 configuration registers are modified.
1588 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1589 pc
.DCFlushEnable
= true;
1590 pc
.PostSyncOperation
= NoWrite
;
1591 pc
.CommandStreamerStallEnable
= true;
1596 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1599 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1600 .SLMEnable
= has_slm
,
1601 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1602 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1603 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1604 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1606 /* Set up the L3 partitioning. */
1607 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1611 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1612 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1613 cfg
->n
[GEN_L3P_ALL
];
1614 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1615 cfg
->n
[GEN_L3P_ALL
];
1616 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1617 cfg
->n
[GEN_L3P_ALL
];
1619 assert(!cfg
->n
[GEN_L3P_ALL
]);
1621 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1622 * the matching space on the remaining banks has to be allocated to a
1623 * client (URB for all validated configurations) set to the
1624 * lower-bandwidth 2-bank address hashing mode.
1626 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1627 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1628 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1630 /* Minimum number of ways that can be allocated to the URB. */
1631 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1632 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1634 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1635 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1636 .ConvertDC_UC
= !has_dc
,
1637 .ConvertIS_UC
= !has_is
,
1638 .ConvertC_UC
= !has_c
,
1639 .ConvertT_UC
= !has_t
);
1641 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1642 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1643 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1645 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1646 .SLMEnable
= has_slm
,
1647 .URBLowBandwidth
= urb_low_bw
,
1648 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1650 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1652 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1653 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1655 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1656 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1657 .ISLowBandwidth
= 0,
1658 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1660 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1661 .TLowBandwidth
= 0);
1663 /* Set up the L3 partitioning. */
1664 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1665 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1666 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1669 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1670 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1671 * them disabled to avoid crashing the system hard.
1673 uint32_t scratch1
, chicken3
;
1674 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1675 .L3AtomicDisable
= !has_dc
);
1676 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1677 .L3AtomicDisableMask
= true,
1678 .L3AtomicDisable
= !has_dc
);
1679 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1680 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1686 cmd_buffer
->state
.current_l3_config
= cfg
;
1690 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1692 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1694 /* Flushes are pipelined while invalidations are handled immediately.
1695 * Therefore, if we're flushing anything then we need to schedule a stall
1696 * before any invalidations can happen.
1698 if (bits
& ANV_PIPE_FLUSH_BITS
)
1699 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1701 /* If we're going to do an invalidate and we have a pending CS stall that
1702 * has yet to be resolved, we do the CS stall now.
1704 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1705 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1706 bits
|= ANV_PIPE_CS_STALL_BIT
;
1707 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1710 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1711 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1712 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1713 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1714 pipe
.RenderTargetCacheFlushEnable
=
1715 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1717 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1718 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1719 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1722 * According to the Broadwell documentation, any PIPE_CONTROL with the
1723 * "Command Streamer Stall" bit set must also have another bit set,
1724 * with five different options:
1726 * - Render Target Cache Flush
1727 * - Depth Cache Flush
1728 * - Stall at Pixel Scoreboard
1729 * - Post-Sync Operation
1733 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1734 * mesa and it seems to work fine. The choice is fairly arbitrary.
1736 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1737 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1738 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1739 pipe
.StallAtPixelScoreboard
= true;
1742 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1745 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1746 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1747 pipe
.StateCacheInvalidationEnable
=
1748 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1749 pipe
.ConstantCacheInvalidationEnable
=
1750 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1751 pipe
.VFCacheInvalidationEnable
=
1752 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1753 pipe
.TextureCacheInvalidationEnable
=
1754 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1755 pipe
.InstructionCacheInvalidateEnable
=
1756 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1759 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1762 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1765 void genX(CmdPipelineBarrier
)(
1766 VkCommandBuffer commandBuffer
,
1767 VkPipelineStageFlags srcStageMask
,
1768 VkPipelineStageFlags destStageMask
,
1770 uint32_t memoryBarrierCount
,
1771 const VkMemoryBarrier
* pMemoryBarriers
,
1772 uint32_t bufferMemoryBarrierCount
,
1773 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1774 uint32_t imageMemoryBarrierCount
,
1775 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1777 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1779 /* XXX: Right now, we're really dumb and just flush whatever categories
1780 * the app asks for. One of these days we may make this a bit better
1781 * but right now that's all the hardware allows for in most areas.
1783 VkAccessFlags src_flags
= 0;
1784 VkAccessFlags dst_flags
= 0;
1786 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1787 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1788 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1791 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1792 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1793 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1796 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1797 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1798 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1799 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1800 const VkImageSubresourceRange
*range
=
1801 &pImageMemoryBarriers
[i
].subresourceRange
;
1803 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1804 transition_depth_buffer(cmd_buffer
, image
,
1805 pImageMemoryBarriers
[i
].oldLayout
,
1806 pImageMemoryBarriers
[i
].newLayout
);
1807 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1808 VkImageAspectFlags color_aspects
=
1809 anv_image_expand_aspects(image
, range
->aspectMask
);
1810 uint32_t aspect_bit
;
1812 uint32_t base_layer
, layer_count
;
1813 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1815 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1817 base_layer
= range
->baseArrayLayer
;
1818 layer_count
= anv_get_layerCount(image
, range
);
1821 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1822 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1823 range
->baseMipLevel
,
1824 anv_get_levelCount(image
, range
),
1825 base_layer
, layer_count
,
1826 pImageMemoryBarriers
[i
].oldLayout
,
1827 pImageMemoryBarriers
[i
].newLayout
);
1832 cmd_buffer
->state
.pending_pipe_bits
|=
1833 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1834 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1838 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1840 VkShaderStageFlags stages
=
1841 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1843 /* In order to avoid thrash, we assume that vertex and fragment stages
1844 * always exist. In the rare case where one is missing *and* the other
1845 * uses push concstants, this may be suboptimal. However, avoiding stalls
1846 * seems more important.
1848 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1850 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1854 const unsigned push_constant_kb
= 32;
1855 #elif GEN_IS_HASWELL
1856 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1858 const unsigned push_constant_kb
= 16;
1861 const unsigned num_stages
=
1862 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1863 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1865 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1866 * units of 2KB. Incidentally, these are the same platforms that have
1867 * 32KB worth of push constant space.
1869 if (push_constant_kb
== 32)
1870 size_per_stage
&= ~1u;
1872 uint32_t kb_used
= 0;
1873 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1874 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1875 anv_batch_emit(&cmd_buffer
->batch
,
1876 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1877 alloc
._3DCommandSubOpcode
= 18 + i
;
1878 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1879 alloc
.ConstantBufferSize
= push_size
;
1881 kb_used
+= push_size
;
1884 anv_batch_emit(&cmd_buffer
->batch
,
1885 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1886 alloc
.ConstantBufferOffset
= kb_used
;
1887 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1890 cmd_buffer
->state
.push_constant_stages
= stages
;
1892 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1894 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1895 * the next 3DPRIMITIVE command after programming the
1896 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1898 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1899 * pipeline setup, we need to dirty push constants.
1901 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1904 static const struct anv_descriptor
*
1905 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1906 const struct anv_pipeline_binding
*binding
)
1908 assert(binding
->set
< MAX_SETS
);
1909 const struct anv_descriptor_set
*set
=
1910 pipe_state
->descriptors
[binding
->set
];
1911 const uint32_t offset
=
1912 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1913 return &set
->descriptors
[offset
+ binding
->index
];
1917 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1918 const struct anv_pipeline_binding
*binding
)
1920 assert(binding
->set
< MAX_SETS
);
1921 const struct anv_descriptor_set
*set
=
1922 pipe_state
->descriptors
[binding
->set
];
1924 uint32_t dynamic_offset_idx
=
1925 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1926 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1929 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1933 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1934 gl_shader_stage stage
,
1935 struct anv_state
*bt_state
)
1937 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1938 struct anv_cmd_pipeline_state
*pipe_state
;
1939 struct anv_pipeline
*pipeline
;
1940 uint32_t bias
, state_offset
;
1943 case MESA_SHADER_COMPUTE
:
1944 pipe_state
= &cmd_buffer
->state
.compute
.base
;
1948 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
1952 pipeline
= pipe_state
->pipeline
;
1954 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1955 *bt_state
= (struct anv_state
) { 0, };
1959 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1960 if (bias
+ map
->surface_count
== 0) {
1961 *bt_state
= (struct anv_state
) { 0, };
1965 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1966 bias
+ map
->surface_count
,
1968 uint32_t *bt_map
= bt_state
->map
;
1970 if (bt_state
->map
== NULL
)
1971 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1973 if (stage
== MESA_SHADER_COMPUTE
&&
1974 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
1975 struct anv_state surface_state
;
1977 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1979 const enum isl_format format
=
1980 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1981 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1983 cmd_buffer
->state
.compute
.num_workgroups
,
1986 bt_map
[0] = surface_state
.offset
+ state_offset
;
1987 add_surface_reloc(cmd_buffer
, surface_state
,
1988 cmd_buffer
->state
.compute
.num_workgroups
);
1991 if (map
->surface_count
== 0)
1994 if (map
->image_count
> 0) {
1996 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1997 if (result
!= VK_SUCCESS
)
2000 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2004 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2005 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2007 struct anv_state surface_state
;
2009 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2010 /* Color attachment binding */
2011 assert(stage
== MESA_SHADER_FRAGMENT
);
2012 assert(binding
->binding
== 0);
2013 if (binding
->index
< subpass
->color_count
) {
2014 const unsigned att
=
2015 subpass
->color_attachments
[binding
->index
].attachment
;
2017 /* From the Vulkan 1.0.46 spec:
2019 * "If any color or depth/stencil attachments are
2020 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2023 if (att
== VK_ATTACHMENT_UNUSED
) {
2024 surface_state
= cmd_buffer
->state
.null_surface_state
;
2026 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2029 surface_state
= cmd_buffer
->state
.null_surface_state
;
2032 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2034 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2035 struct anv_state surface_state
=
2036 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2038 struct anv_address constant_data
= {
2039 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2040 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2042 unsigned constant_data_size
=
2043 pipeline
->shaders
[stage
]->constant_data_size
;
2045 const enum isl_format format
=
2046 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2047 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2048 surface_state
, format
,
2049 constant_data
, constant_data_size
, 1);
2051 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2052 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2056 const struct anv_descriptor
*desc
=
2057 anv_descriptor_for_binding(pipe_state
, binding
);
2059 switch (desc
->type
) {
2060 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2061 /* Nothing for us to do here */
2064 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2065 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2066 struct anv_surface_state sstate
=
2067 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2068 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2069 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2070 surface_state
= sstate
.state
;
2071 assert(surface_state
.alloc_size
);
2072 add_surface_state_relocs(cmd_buffer
, sstate
);
2075 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2076 assert(stage
== MESA_SHADER_FRAGMENT
);
2077 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2078 /* For depth and stencil input attachments, we treat it like any
2079 * old texture that a user may have bound.
2081 struct anv_surface_state sstate
=
2082 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2083 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2084 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2085 surface_state
= sstate
.state
;
2086 assert(surface_state
.alloc_size
);
2087 add_surface_state_relocs(cmd_buffer
, sstate
);
2089 /* For color input attachments, we create the surface state at
2090 * vkBeginRenderPass time so that we can include aux and clear
2091 * color information.
2093 assert(binding
->input_attachment_index
< subpass
->input_count
);
2094 const unsigned subpass_att
= binding
->input_attachment_index
;
2095 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2096 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2100 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2101 struct anv_surface_state sstate
= (binding
->write_only
)
2102 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2103 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2104 surface_state
= sstate
.state
;
2105 assert(surface_state
.alloc_size
);
2106 add_surface_state_relocs(cmd_buffer
, sstate
);
2108 struct brw_image_param
*image_param
=
2109 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2111 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2112 image_param
->surface_idx
= bias
+ s
;
2116 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2117 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2118 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2119 surface_state
= desc
->buffer_view
->surface_state
;
2120 assert(surface_state
.alloc_size
);
2121 add_surface_reloc(cmd_buffer
, surface_state
,
2122 desc
->buffer_view
->address
);
2125 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2126 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2127 /* Compute the offset within the buffer */
2128 uint32_t dynamic_offset
=
2129 dynamic_offset_for_binding(pipe_state
, binding
);
2130 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2131 /* Clamp to the buffer size */
2132 offset
= MIN2(offset
, desc
->buffer
->size
);
2133 /* Clamp the range to the buffer size */
2134 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2136 struct anv_address address
=
2137 anv_address_add(desc
->buffer
->address
, offset
);
2140 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2141 enum isl_format format
=
2142 anv_isl_format_for_descriptor_type(desc
->type
);
2144 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2145 format
, address
, range
, 1);
2146 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2150 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2151 surface_state
= (binding
->write_only
)
2152 ? desc
->buffer_view
->writeonly_storage_surface_state
2153 : desc
->buffer_view
->storage_surface_state
;
2154 assert(surface_state
.alloc_size
);
2155 add_surface_reloc(cmd_buffer
, surface_state
,
2156 desc
->buffer_view
->address
);
2158 struct brw_image_param
*image_param
=
2159 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2161 *image_param
= desc
->buffer_view
->storage_image_param
;
2162 image_param
->surface_idx
= bias
+ s
;
2166 assert(!"Invalid descriptor type");
2170 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2172 assert(image
== map
->image_count
);
2175 anv_state_flush(cmd_buffer
->device
, *bt_state
);
2178 /* The PIPE_CONTROL command description says:
2180 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2181 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2182 * Target Cache Flush by enabling this bit. When render target flush
2183 * is set due to new association of BTI, PS Scoreboard Stall bit must
2184 * be set in this packet."
2186 * FINISHME: Currently we shuffle around the surface states in the binding
2187 * table based on if they are getting used or not. So, we've to do below
2188 * pipe control flush for every binding table upload. Make changes so
2189 * that we do it only when we modify render target surface states.
2191 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2192 pc
.RenderTargetCacheFlushEnable
= true;
2193 pc
.StallAtPixelScoreboard
= true;
2201 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2202 gl_shader_stage stage
,
2203 struct anv_state
*state
)
2205 struct anv_cmd_pipeline_state
*pipe_state
=
2206 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2207 &cmd_buffer
->state
.gfx
.base
;
2208 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2210 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2211 *state
= (struct anv_state
) { 0, };
2215 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2216 if (map
->sampler_count
== 0) {
2217 *state
= (struct anv_state
) { 0, };
2221 uint32_t size
= map
->sampler_count
* 16;
2222 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2224 if (state
->map
== NULL
)
2225 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2227 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2228 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2229 const struct anv_descriptor
*desc
=
2230 anv_descriptor_for_binding(pipe_state
, binding
);
2232 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2233 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2236 struct anv_sampler
*sampler
= desc
->sampler
;
2238 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2239 * happens to be zero.
2241 if (sampler
== NULL
)
2244 memcpy(state
->map
+ (s
* 16),
2245 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2248 anv_state_flush(cmd_buffer
->device
, *state
);
2254 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2256 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2258 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2259 pipeline
->active_stages
;
2261 VkResult result
= VK_SUCCESS
;
2262 anv_foreach_stage(s
, dirty
) {
2263 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2264 if (result
!= VK_SUCCESS
)
2266 result
= emit_binding_table(cmd_buffer
, s
,
2267 &cmd_buffer
->state
.binding_tables
[s
]);
2268 if (result
!= VK_SUCCESS
)
2272 if (result
!= VK_SUCCESS
) {
2273 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2275 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2276 if (result
!= VK_SUCCESS
)
2279 /* Re-emit state base addresses so we get the new surface state base
2280 * address before we start emitting binding tables etc.
2282 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2284 /* Re-emit all active binding tables */
2285 dirty
|= pipeline
->active_stages
;
2286 anv_foreach_stage(s
, dirty
) {
2287 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2288 if (result
!= VK_SUCCESS
) {
2289 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2292 result
= emit_binding_table(cmd_buffer
, s
,
2293 &cmd_buffer
->state
.binding_tables
[s
]);
2294 if (result
!= VK_SUCCESS
) {
2295 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2301 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2307 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2310 static const uint32_t sampler_state_opcodes
[] = {
2311 [MESA_SHADER_VERTEX
] = 43,
2312 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2313 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2314 [MESA_SHADER_GEOMETRY
] = 46,
2315 [MESA_SHADER_FRAGMENT
] = 47,
2316 [MESA_SHADER_COMPUTE
] = 0,
2319 static const uint32_t binding_table_opcodes
[] = {
2320 [MESA_SHADER_VERTEX
] = 38,
2321 [MESA_SHADER_TESS_CTRL
] = 39,
2322 [MESA_SHADER_TESS_EVAL
] = 40,
2323 [MESA_SHADER_GEOMETRY
] = 41,
2324 [MESA_SHADER_FRAGMENT
] = 42,
2325 [MESA_SHADER_COMPUTE
] = 0,
2328 anv_foreach_stage(s
, stages
) {
2329 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2330 assert(binding_table_opcodes
[s
] > 0);
2332 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2333 anv_batch_emit(&cmd_buffer
->batch
,
2334 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2335 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2336 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2340 /* Always emit binding table pointers if we're asked to, since on SKL
2341 * this is what flushes push constants. */
2342 anv_batch_emit(&cmd_buffer
->batch
,
2343 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2344 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2345 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2351 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2352 VkShaderStageFlags dirty_stages
)
2354 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2355 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2357 static const uint32_t push_constant_opcodes
[] = {
2358 [MESA_SHADER_VERTEX
] = 21,
2359 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2360 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2361 [MESA_SHADER_GEOMETRY
] = 22,
2362 [MESA_SHADER_FRAGMENT
] = 23,
2363 [MESA_SHADER_COMPUTE
] = 0,
2366 VkShaderStageFlags flushed
= 0;
2368 anv_foreach_stage(stage
, dirty_stages
) {
2369 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2370 assert(push_constant_opcodes
[stage
] > 0);
2372 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2373 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2375 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2376 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2377 const struct brw_stage_prog_data
*prog_data
=
2378 pipeline
->shaders
[stage
]->prog_data
;
2379 const struct anv_pipeline_bind_map
*bind_map
=
2380 &pipeline
->shaders
[stage
]->bind_map
;
2382 /* The Skylake PRM contains the following restriction:
2384 * "The driver must ensure The following case does not occur
2385 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2386 * buffer 3 read length equal to zero committed followed by a
2387 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2390 * To avoid this, we program the buffers in the highest slots.
2391 * This way, slot 0 is only used if slot 3 is also used.
2395 for (int i
= 3; i
>= 0; i
--) {
2396 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2397 if (range
->length
== 0)
2400 const unsigned surface
=
2401 prog_data
->binding_table
.ubo_start
+ range
->block
;
2403 assert(surface
<= bind_map
->surface_count
);
2404 const struct anv_pipeline_binding
*binding
=
2405 &bind_map
->surface_to_descriptor
[surface
];
2407 struct anv_address read_addr
;
2409 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2410 struct anv_address constant_data
= {
2411 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2412 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2414 unsigned constant_data_size
=
2415 pipeline
->shaders
[stage
]->constant_data_size
;
2417 read_len
= MIN2(range
->length
,
2418 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2419 read_addr
= anv_address_add(constant_data
,
2422 const struct anv_descriptor
*desc
=
2423 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2425 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2426 read_len
= MIN2(range
->length
,
2427 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2428 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2431 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2433 uint32_t dynamic_offset
=
2434 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2435 uint32_t buf_offset
=
2436 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2437 uint32_t buf_range
=
2438 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2440 read_len
= MIN2(range
->length
,
2441 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2442 read_addr
= anv_address_add(desc
->buffer
->address
,
2443 buf_offset
+ range
->start
* 32);
2448 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2449 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2454 struct anv_state state
=
2455 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2457 if (state
.alloc_size
> 0) {
2458 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2459 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2460 .offset
= state
.offset
,
2462 c
.ConstantBody
.ReadLength
[n
] =
2463 DIV_ROUND_UP(state
.alloc_size
, 32);
2466 /* For Ivy Bridge, the push constants packets have a different
2467 * rule that would require us to iterate in the other direction
2468 * and possibly mess around with dynamic state base address.
2469 * Don't bother; just emit regular push constants at n = 0.
2471 struct anv_state state
=
2472 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2474 if (state
.alloc_size
> 0) {
2475 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2476 c
.ConstantBody
.ReadLength
[0] =
2477 DIV_ROUND_UP(state
.alloc_size
, 32);
2483 flushed
|= mesa_to_vk_shader_stage(stage
);
2486 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2490 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2492 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2495 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2497 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2499 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2501 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2504 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2505 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2507 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2508 GENX(3DSTATE_VERTEX_BUFFERS
));
2510 for_each_bit(vb
, vb_emit
) {
2511 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2512 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2514 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2515 .VertexBufferIndex
= vb
,
2518 .MemoryObjectControlState
= GENX(MOCS
),
2520 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
2521 /* Our implementation of VK_KHR_multiview uses instancing to draw
2522 * the different views. If the client asks for instancing, we
2523 * need to use the Instance Data Step Rate to ensure that we
2524 * repeat the client's per-instance data once for each view.
2526 .InstanceDataStepRate
= anv_subpass_view_count(pipeline
->subpass
),
2527 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2530 .AddressModifyEnable
= true,
2531 .BufferPitch
= pipeline
->binding_stride
[vb
],
2532 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2535 .BufferSize
= buffer
->size
- offset
2537 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2541 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2546 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2548 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2549 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2551 /* The exact descriptor layout is pulled from the pipeline, so we need
2552 * to re-emit binding tables on every pipeline change.
2554 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2556 /* If the pipeline changed, we may need to re-allocate push constant
2559 cmd_buffer_alloc_push_constants(cmd_buffer
);
2563 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2564 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2565 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2567 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2568 * stall needs to be sent just prior to any 3DSTATE_VS,
2569 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2570 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2571 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2572 * PIPE_CONTROL needs to be sent before any combination of VS
2573 * associated 3DSTATE."
2575 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2576 pc
.DepthStallEnable
= true;
2577 pc
.PostSyncOperation
= WriteImmediateData
;
2579 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2584 /* Render targets live in the same binding table as fragment descriptors */
2585 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2586 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2588 /* We emit the binding tables and sampler tables first, then emit push
2589 * constants and then finally emit binding table and sampler table
2590 * pointers. It has to happen in this order, since emitting the binding
2591 * tables may change the push constants (in case of storage images). After
2592 * emitting push constants, on SKL+ we have to emit the corresponding
2593 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2596 if (cmd_buffer
->state
.descriptors_dirty
)
2597 dirty
= flush_descriptor_sets(cmd_buffer
);
2599 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2600 /* Because we're pushing UBOs, we have to push whenever either
2601 * descriptors or push constants is dirty.
2603 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2604 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2605 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2609 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2611 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2612 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2614 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2615 ANV_CMD_DIRTY_PIPELINE
)) {
2616 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2617 pipeline
->depth_clamp_enable
);
2620 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
2621 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2623 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2625 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2629 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2630 struct anv_address addr
,
2631 uint32_t size
, uint32_t index
)
2633 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2634 GENX(3DSTATE_VERTEX_BUFFERS
));
2636 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2637 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2638 .VertexBufferIndex
= index
,
2639 .AddressModifyEnable
= true,
2642 .MemoryObjectControlState
= GENX(MOCS
),
2643 .BufferStartingAddress
= addr
,
2646 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2647 .BufferStartingAddress
= addr
,
2648 .EndAddress
= anv_address_add(addr
, size
),
2654 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2655 struct anv_address addr
)
2657 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2661 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2662 uint32_t base_vertex
, uint32_t base_instance
)
2664 struct anv_state id_state
=
2665 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2667 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2668 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2670 anv_state_flush(cmd_buffer
->device
, id_state
);
2672 struct anv_address addr
= {
2673 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2674 .offset
= id_state
.offset
,
2677 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2681 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2683 struct anv_state state
=
2684 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2686 ((uint32_t *)state
.map
)[0] = draw_index
;
2688 anv_state_flush(cmd_buffer
->device
, state
);
2690 struct anv_address addr
= {
2691 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2692 .offset
= state
.offset
,
2695 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2699 VkCommandBuffer commandBuffer
,
2700 uint32_t vertexCount
,
2701 uint32_t instanceCount
,
2702 uint32_t firstVertex
,
2703 uint32_t firstInstance
)
2705 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2706 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2707 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2709 if (anv_batch_has_error(&cmd_buffer
->batch
))
2712 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2714 if (vs_prog_data
->uses_firstvertex
||
2715 vs_prog_data
->uses_baseinstance
)
2716 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2717 if (vs_prog_data
->uses_drawid
)
2718 emit_draw_index(cmd_buffer
, 0);
2720 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2721 * different views. We need to multiply instanceCount by the view count.
2723 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2725 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2726 prim
.VertexAccessType
= SEQUENTIAL
;
2727 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2728 prim
.VertexCountPerInstance
= vertexCount
;
2729 prim
.StartVertexLocation
= firstVertex
;
2730 prim
.InstanceCount
= instanceCount
;
2731 prim
.StartInstanceLocation
= firstInstance
;
2732 prim
.BaseVertexLocation
= 0;
2736 void genX(CmdDrawIndexed
)(
2737 VkCommandBuffer commandBuffer
,
2738 uint32_t indexCount
,
2739 uint32_t instanceCount
,
2740 uint32_t firstIndex
,
2741 int32_t vertexOffset
,
2742 uint32_t firstInstance
)
2744 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2745 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2746 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2748 if (anv_batch_has_error(&cmd_buffer
->batch
))
2751 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2753 if (vs_prog_data
->uses_firstvertex
||
2754 vs_prog_data
->uses_baseinstance
)
2755 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2756 if (vs_prog_data
->uses_drawid
)
2757 emit_draw_index(cmd_buffer
, 0);
2759 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2760 * different views. We need to multiply instanceCount by the view count.
2762 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2764 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2765 prim
.VertexAccessType
= RANDOM
;
2766 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2767 prim
.VertexCountPerInstance
= indexCount
;
2768 prim
.StartVertexLocation
= firstIndex
;
2769 prim
.InstanceCount
= instanceCount
;
2770 prim
.StartInstanceLocation
= firstInstance
;
2771 prim
.BaseVertexLocation
= vertexOffset
;
2775 /* Auto-Draw / Indirect Registers */
2776 #define GEN7_3DPRIM_END_OFFSET 0x2420
2777 #define GEN7_3DPRIM_START_VERTEX 0x2430
2778 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2779 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2780 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2781 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2783 /* MI_MATH only exists on Haswell+ */
2784 #if GEN_IS_HASWELL || GEN_GEN >= 8
2786 /* Emit dwords to multiply GPR0 by N */
2788 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2790 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2792 #define append_alu(opcode, operand1, operand2) \
2793 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2796 unsigned top_bit
= 31 - __builtin_clz(N
);
2797 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2798 /* We get our initial data in GPR0 and we write the final data out to
2799 * GPR0 but we use GPR1 as our scratch register.
2801 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2802 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2804 /* Shift the current value left by 1 */
2805 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2806 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2807 append_alu(MI_ALU_ADD
, 0, 0);
2810 /* Store ACCU to R1 and add R0 to R1 */
2811 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2812 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2813 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2814 append_alu(MI_ALU_ADD
, 0, 0);
2817 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2824 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2826 uint32_t num_dwords
;
2827 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2829 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2830 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2833 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2836 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2837 struct anv_address addr
,
2840 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2842 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, addr
.bo
, addr
.offset
);
2844 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2845 if (view_count
> 1) {
2846 #if GEN_IS_HASWELL || GEN_GEN >= 8
2847 emit_lrm(batch
, CS_GPR(0), addr
.bo
, addr
.offset
+ 4);
2848 emit_mul_gpr0(batch
, view_count
);
2849 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2851 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2852 "MI_MATH is not supported on Ivy Bridge");
2853 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, addr
.bo
, addr
.offset
+ 4);
2856 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, addr
.bo
, addr
.offset
+ 4);
2859 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, addr
.bo
, addr
.offset
+ 8);
2862 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, addr
.bo
, addr
.offset
+ 12);
2863 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, addr
.bo
, addr
.offset
+ 16);
2865 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, addr
.bo
, addr
.offset
+ 12);
2866 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2870 void genX(CmdDrawIndirect
)(
2871 VkCommandBuffer commandBuffer
,
2873 VkDeviceSize offset
,
2877 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2878 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2879 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2880 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2882 if (anv_batch_has_error(&cmd_buffer
->batch
))
2885 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2887 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2888 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2890 if (vs_prog_data
->uses_firstvertex
||
2891 vs_prog_data
->uses_baseinstance
)
2892 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
2893 if (vs_prog_data
->uses_drawid
)
2894 emit_draw_index(cmd_buffer
, i
);
2896 load_indirect_parameters(cmd_buffer
, draw
, false);
2898 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2899 prim
.IndirectParameterEnable
= true;
2900 prim
.VertexAccessType
= SEQUENTIAL
;
2901 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2908 void genX(CmdDrawIndexedIndirect
)(
2909 VkCommandBuffer commandBuffer
,
2911 VkDeviceSize offset
,
2915 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2916 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2917 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2918 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2920 if (anv_batch_has_error(&cmd_buffer
->batch
))
2923 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2925 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2926 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2928 /* TODO: We need to stomp base vertex to 0 somehow */
2929 if (vs_prog_data
->uses_firstvertex
||
2930 vs_prog_data
->uses_baseinstance
)
2931 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
2932 if (vs_prog_data
->uses_drawid
)
2933 emit_draw_index(cmd_buffer
, i
);
2935 load_indirect_parameters(cmd_buffer
, draw
, true);
2937 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2938 prim
.IndirectParameterEnable
= true;
2939 prim
.VertexAccessType
= RANDOM
;
2940 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2948 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2950 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2951 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2954 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2955 if (result
!= VK_SUCCESS
) {
2956 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2958 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2959 if (result
!= VK_SUCCESS
)
2962 /* Re-emit state base addresses so we get the new surface state base
2963 * address before we start emitting binding tables etc.
2965 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2967 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2968 if (result
!= VK_SUCCESS
) {
2969 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2974 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
2975 if (result
!= VK_SUCCESS
) {
2976 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2980 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
2981 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2982 .BindingTablePointer
= surfaces
.offset
,
2983 .SamplerStatePointer
= samplers
.offset
,
2985 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
2987 struct anv_state state
=
2988 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
2989 pipeline
->interface_descriptor_data
,
2990 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
2993 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
2994 anv_batch_emit(&cmd_buffer
->batch
,
2995 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
2996 mid
.InterfaceDescriptorTotalLength
= size
;
2997 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3004 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3006 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3007 MAYBE_UNUSED VkResult result
;
3009 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3011 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3013 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3015 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3016 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3018 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3019 * the only bits that are changed are scoreboard related: Scoreboard
3020 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3021 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3024 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3025 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3027 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3030 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3031 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3032 /* FIXME: figure out descriptors for gen7 */
3033 result
= flush_compute_descriptor_set(cmd_buffer
);
3034 if (result
!= VK_SUCCESS
)
3037 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3040 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3041 struct anv_state push_state
=
3042 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3044 if (push_state
.alloc_size
) {
3045 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3046 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3047 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3051 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3054 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3056 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3062 verify_cmd_parser(const struct anv_device
*device
,
3063 int required_version
,
3064 const char *function
)
3066 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3067 return vk_errorf(device
->instance
, device
->instance
,
3068 VK_ERROR_FEATURE_NOT_PRESENT
,
3069 "cmd parser version %d is required for %s",
3070 required_version
, function
);
3079 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3080 uint32_t baseGroupX
,
3081 uint32_t baseGroupY
,
3082 uint32_t baseGroupZ
)
3084 if (anv_batch_has_error(&cmd_buffer
->batch
))
3088 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3089 base_work_group_id
);
3090 if (result
!= VK_SUCCESS
) {
3091 cmd_buffer
->batch
.status
= result
;
3095 struct anv_push_constants
*push
=
3096 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3097 if (push
->base_work_group_id
[0] != baseGroupX
||
3098 push
->base_work_group_id
[1] != baseGroupY
||
3099 push
->base_work_group_id
[2] != baseGroupZ
) {
3100 push
->base_work_group_id
[0] = baseGroupX
;
3101 push
->base_work_group_id
[1] = baseGroupY
;
3102 push
->base_work_group_id
[2] = baseGroupZ
;
3104 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3108 void genX(CmdDispatch
)(
3109 VkCommandBuffer commandBuffer
,
3114 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3117 void genX(CmdDispatchBase
)(
3118 VkCommandBuffer commandBuffer
,
3119 uint32_t baseGroupX
,
3120 uint32_t baseGroupY
,
3121 uint32_t baseGroupZ
,
3122 uint32_t groupCountX
,
3123 uint32_t groupCountY
,
3124 uint32_t groupCountZ
)
3126 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3127 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3128 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3130 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3131 baseGroupY
, baseGroupZ
);
3133 if (anv_batch_has_error(&cmd_buffer
->batch
))
3136 if (prog_data
->uses_num_work_groups
) {
3137 struct anv_state state
=
3138 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3139 uint32_t *sizes
= state
.map
;
3140 sizes
[0] = groupCountX
;
3141 sizes
[1] = groupCountY
;
3142 sizes
[2] = groupCountZ
;
3143 anv_state_flush(cmd_buffer
->device
, state
);
3144 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3145 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3146 .offset
= state
.offset
,
3150 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3152 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3153 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3154 ggw
.ThreadDepthCounterMaximum
= 0;
3155 ggw
.ThreadHeightCounterMaximum
= 0;
3156 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3157 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3158 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3159 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3160 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3161 ggw
.BottomExecutionMask
= 0xffffffff;
3164 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3167 #define GPGPU_DISPATCHDIMX 0x2500
3168 #define GPGPU_DISPATCHDIMY 0x2504
3169 #define GPGPU_DISPATCHDIMZ 0x2508
3171 void genX(CmdDispatchIndirect
)(
3172 VkCommandBuffer commandBuffer
,
3174 VkDeviceSize offset
)
3176 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3177 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3178 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3179 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3180 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3181 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3183 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3186 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3187 * indirect dispatch registers to be written.
3189 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3190 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3194 if (prog_data
->uses_num_work_groups
)
3195 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3197 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3199 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, addr
.bo
, addr
.offset
);
3200 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, addr
.bo
, addr
.offset
+ 4);
3201 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, addr
.bo
, addr
.offset
+ 8);
3204 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3205 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3206 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3207 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3209 /* Load compute_dispatch_indirect_x_size into SRC0 */
3210 emit_lrm(batch
, MI_PREDICATE_SRC0
, addr
.bo
, addr
.offset
+ 0);
3212 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3213 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3214 mip
.LoadOperation
= LOAD_LOAD
;
3215 mip
.CombineOperation
= COMBINE_SET
;
3216 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3219 /* Load compute_dispatch_indirect_y_size into SRC0 */
3220 emit_lrm(batch
, MI_PREDICATE_SRC0
, addr
.bo
, addr
.offset
+ 4);
3222 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3223 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3224 mip
.LoadOperation
= LOAD_LOAD
;
3225 mip
.CombineOperation
= COMBINE_OR
;
3226 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3229 /* Load compute_dispatch_indirect_z_size into SRC0 */
3230 emit_lrm(batch
, MI_PREDICATE_SRC0
, addr
.bo
, addr
.offset
+ 8);
3232 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3233 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3234 mip
.LoadOperation
= LOAD_LOAD
;
3235 mip
.CombineOperation
= COMBINE_OR
;
3236 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3239 /* predicate = !predicate; */
3240 #define COMPARE_FALSE 1
3241 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3242 mip
.LoadOperation
= LOAD_LOADINV
;
3243 mip
.CombineOperation
= COMBINE_OR
;
3244 mip
.CompareOperation
= COMPARE_FALSE
;
3248 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3249 ggw
.IndirectParameterEnable
= true;
3250 ggw
.PredicateEnable
= GEN_GEN
<= 7;
3251 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3252 ggw
.ThreadDepthCounterMaximum
= 0;
3253 ggw
.ThreadHeightCounterMaximum
= 0;
3254 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3255 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3256 ggw
.BottomExecutionMask
= 0xffffffff;
3259 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3263 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3266 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3268 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3271 #if GEN_GEN >= 8 && GEN_GEN < 10
3272 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3274 * Software must clear the COLOR_CALC_STATE Valid field in
3275 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3276 * with Pipeline Select set to GPGPU.
3278 * The internal hardware docs recommend the same workaround for Gen9
3281 if (pipeline
== GPGPU
)
3282 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3285 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3286 * PIPELINE_SELECT [DevBWR+]":
3290 * Software must ensure all the write caches are flushed through a
3291 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3292 * command to invalidate read only caches prior to programming
3293 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3295 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3296 pc
.RenderTargetCacheFlushEnable
= true;
3297 pc
.DepthCacheFlushEnable
= true;
3298 pc
.DCFlushEnable
= true;
3299 pc
.PostSyncOperation
= NoWrite
;
3300 pc
.CommandStreamerStallEnable
= true;
3303 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3304 pc
.TextureCacheInvalidationEnable
= true;
3305 pc
.ConstantCacheInvalidationEnable
= true;
3306 pc
.StateCacheInvalidationEnable
= true;
3307 pc
.InstructionCacheInvalidateEnable
= true;
3308 pc
.PostSyncOperation
= NoWrite
;
3311 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3315 ps
.PipelineSelection
= pipeline
;
3319 if (devinfo
->is_geminilake
) {
3322 * "This chicken bit works around a hardware issue with barrier logic
3323 * encountered when switching between GPGPU and 3D pipelines. To
3324 * workaround the issue, this mode bit should be set after a pipeline
3328 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3330 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3331 : GLK_BARRIER_MODE_3D_HULL
,
3332 .GLKBarrierModeMask
= 1);
3333 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3337 cmd_buffer
->state
.current_pipeline
= pipeline
;
3341 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3343 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3347 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3349 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3353 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3358 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3360 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3361 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3362 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3363 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3364 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3365 * Depth Flush Bit set, followed by another pipelined depth stall
3366 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3367 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3368 * via a preceding MI_FLUSH)."
3370 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3371 pipe
.DepthStallEnable
= true;
3373 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3374 pipe
.DepthCacheFlushEnable
= true;
3376 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3377 pipe
.DepthStallEnable
= true;
3382 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3384 struct anv_device
*device
= cmd_buffer
->device
;
3385 const struct anv_image_view
*iview
=
3386 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3387 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3389 /* FIXME: Width and Height are wrong */
3391 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3393 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3394 device
->isl_dev
.ds
.size
/ 4);
3398 struct isl_depth_stencil_hiz_emit_info info
= {
3399 .mocs
= device
->default_mocs
,
3403 info
.view
= &iview
->planes
[0].isl
;
3405 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3406 uint32_t depth_plane
=
3407 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3408 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3410 info
.depth_surf
= &surface
->isl
;
3412 info
.depth_address
=
3413 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3414 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3415 image
->planes
[depth_plane
].address
.bo
,
3416 image
->planes
[depth_plane
].address
.offset
+
3420 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3421 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3422 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3423 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3426 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3427 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3428 image
->planes
[depth_plane
].address
.bo
,
3429 image
->planes
[depth_plane
].address
.offset
+
3430 image
->planes
[depth_plane
].aux_surface
.offset
);
3432 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3436 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3437 uint32_t stencil_plane
=
3438 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3439 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3441 info
.stencil_surf
= &surface
->isl
;
3443 info
.stencil_address
=
3444 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3445 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3446 image
->planes
[stencil_plane
].address
.bo
,
3447 image
->planes
[stencil_plane
].address
.offset
+
3451 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3453 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3457 * This ANDs the view mask of the current subpass with the pending clear
3458 * views in the attachment to get the mask of views active in the subpass
3459 * that still need to be cleared.
3461 static inline uint32_t
3462 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3463 const struct anv_attachment_state
*att_state
)
3465 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3469 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3470 const struct anv_attachment_state
*att_state
)
3472 if (!cmd_state
->subpass
->view_mask
)
3475 uint32_t pending_clear_mask
=
3476 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3478 return pending_clear_mask
& 1;
3482 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3485 const uint32_t last_subpass_idx
=
3486 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3487 const struct anv_subpass
*last_subpass
=
3488 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3489 return last_subpass
== cmd_state
->subpass
;
3493 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3494 uint32_t subpass_id
)
3496 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3497 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3498 cmd_state
->subpass
= subpass
;
3500 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3502 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3503 * different views. If the client asks for instancing, we need to use the
3504 * Instance Data Step Rate to ensure that we repeat the client's
3505 * per-instance data once for each view. Since this bit is in
3506 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3510 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3512 /* It is possible to start a render pass with an old pipeline. Because the
3513 * render pass and subpass index are both baked into the pipeline, this is
3514 * highly unlikely. In order to do so, it requires that you have a render
3515 * pass with a single subpass and that you use that render pass twice
3516 * back-to-back and use the same pipeline at the start of the second render
3517 * pass as at the end of the first. In order to avoid unpredictable issues
3518 * with this edge case, we just dirty the pipeline at the start of every
3521 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3523 /* Accumulate any subpass flushes that need to happen before the subpass */
3524 cmd_buffer
->state
.pending_pipe_bits
|=
3525 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3527 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3528 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3530 bool is_multiview
= subpass
->view_mask
!= 0;
3532 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3533 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3534 if (a
== VK_ATTACHMENT_UNUSED
)
3537 assert(a
< cmd_state
->pass
->attachment_count
);
3538 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3540 struct anv_image_view
*iview
= fb
->attachments
[a
];
3541 const struct anv_image
*image
= iview
->image
;
3543 /* A resolve is necessary before use as an input attachment if the clear
3544 * color or auxiliary buffer usage isn't supported by the sampler.
3546 const bool input_needs_resolve
=
3547 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3548 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3550 VkImageLayout target_layout
;
3551 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3552 !input_needs_resolve
) {
3553 /* Layout transitions before the final only help to enable sampling
3554 * as an input attachment. If the input attachment supports sampling
3555 * using the auxiliary surface, we can skip such transitions by
3556 * making the target layout one that is CCS-aware.
3558 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3560 target_layout
= subpass
->attachments
[i
].layout
;
3563 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3564 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3566 uint32_t base_layer
, layer_count
;
3567 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3569 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3570 iview
->planes
[0].isl
.base_level
);
3572 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3573 layer_count
= fb
->layers
;
3576 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3577 iview
->planes
[0].isl
.base_level
, 1,
3578 base_layer
, layer_count
,
3579 att_state
->current_layout
, target_layout
);
3580 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3581 transition_depth_buffer(cmd_buffer
, image
,
3582 att_state
->current_layout
, target_layout
);
3583 att_state
->aux_usage
=
3584 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3585 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3587 att_state
->current_layout
= target_layout
;
3589 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3590 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3592 /* Multi-planar images are not supported as attachments */
3593 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3594 assert(image
->n_planes
== 1);
3596 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
3597 uint32_t clear_layer_count
= fb
->layers
;
3599 if (att_state
->fast_clear
&&
3600 do_first_layer_clear(cmd_state
, att_state
)) {
3601 /* We only support fast-clears on the first layer */
3602 assert(iview
->planes
[0].isl
.base_level
== 0);
3603 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3605 union isl_color_value clear_color
= {};
3606 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
3607 if (iview
->image
->samples
== 1) {
3608 anv_image_ccs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3609 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3613 anv_image_mcs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3614 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3619 clear_layer_count
--;
3621 att_state
->pending_clear_views
&= ~1;
3623 if (att_state
->clear_color_is_zero
) {
3624 /* This image has the auxiliary buffer enabled. We can mark the
3625 * subresource as not needing a resolve because the clear color
3626 * will match what's in every RENDER_SURFACE_STATE object when
3627 * it's being used for sampling.
3629 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3630 VK_IMAGE_ASPECT_COLOR_BIT
,
3631 ANV_FAST_CLEAR_DEFAULT_VALUE
);
3633 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3634 VK_IMAGE_ASPECT_COLOR_BIT
,
3635 ANV_FAST_CLEAR_ANY
);
3639 /* From the VkFramebufferCreateInfo spec:
3641 * "If the render pass uses multiview, then layers must be one and each
3642 * attachment requires a number of layers that is greater than the
3643 * maximum bit index set in the view mask in the subpasses in which it
3646 * So if multiview is active we ignore the number of layers in the
3647 * framebuffer and instead we honor the view mask from the subpass.
3650 assert(image
->n_planes
== 1);
3651 uint32_t pending_clear_mask
=
3652 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3655 for_each_bit(layer_idx
, pending_clear_mask
) {
3657 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3659 anv_image_clear_color(cmd_buffer
, image
,
3660 VK_IMAGE_ASPECT_COLOR_BIT
,
3661 att_state
->aux_usage
,
3662 iview
->planes
[0].isl
.format
,
3663 iview
->planes
[0].isl
.swizzle
,
3664 iview
->planes
[0].isl
.base_level
,
3667 vk_to_isl_color(att_state
->clear_value
.color
));
3670 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3671 } else if (clear_layer_count
> 0) {
3672 assert(image
->n_planes
== 1);
3673 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3674 att_state
->aux_usage
,
3675 iview
->planes
[0].isl
.format
,
3676 iview
->planes
[0].isl
.swizzle
,
3677 iview
->planes
[0].isl
.base_level
,
3678 base_clear_layer
, clear_layer_count
,
3680 vk_to_isl_color(att_state
->clear_value
.color
));
3682 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
3683 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3684 if (att_state
->fast_clear
&& !is_multiview
) {
3685 /* We currently only support HiZ for single-layer images */
3686 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3687 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
3688 assert(iview
->planes
[0].isl
.base_level
== 0);
3689 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3690 assert(fb
->layers
== 1);
3693 anv_image_hiz_clear(cmd_buffer
, image
,
3694 att_state
->pending_clear_aspects
,
3695 iview
->planes
[0].isl
.base_level
,
3696 iview
->planes
[0].isl
.base_array_layer
,
3697 fb
->layers
, render_area
,
3698 att_state
->clear_value
.depthStencil
.stencil
);
3699 } else if (is_multiview
) {
3700 uint32_t pending_clear_mask
=
3701 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3704 for_each_bit(layer_idx
, pending_clear_mask
) {
3706 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3708 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3709 att_state
->pending_clear_aspects
,
3710 att_state
->aux_usage
,
3711 iview
->planes
[0].isl
.base_level
,
3714 att_state
->clear_value
.depthStencil
.depth
,
3715 att_state
->clear_value
.depthStencil
.stencil
);
3718 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3720 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3721 att_state
->pending_clear_aspects
,
3722 att_state
->aux_usage
,
3723 iview
->planes
[0].isl
.base_level
,
3724 iview
->planes
[0].isl
.base_array_layer
,
3725 fb
->layers
, render_area
,
3726 att_state
->clear_value
.depthStencil
.depth
,
3727 att_state
->clear_value
.depthStencil
.stencil
);
3730 assert(att_state
->pending_clear_aspects
== 0);
3734 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
3735 image
->planes
[0].aux_surface
.isl
.size
> 0 &&
3736 iview
->planes
[0].isl
.base_level
== 0 &&
3737 iview
->planes
[0].isl
.base_array_layer
== 0) {
3738 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
3739 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3740 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3741 false /* copy to ss */);
3744 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
3745 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3746 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3747 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3748 false /* copy to ss */);
3752 if (subpass
->attachments
[i
].usage
==
3753 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
3754 /* We assume that if we're starting a subpass, we're going to do some
3755 * rendering so we may end up with compressed data.
3757 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
3758 VK_IMAGE_ASPECT_COLOR_BIT
,
3759 att_state
->aux_usage
,
3760 iview
->planes
[0].isl
.base_level
,
3761 iview
->planes
[0].isl
.base_array_layer
,
3763 } else if (subpass
->attachments
[i
].usage
==
3764 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
3765 /* We may be writing depth or stencil so we need to mark the surface.
3766 * Unfortunately, there's no way to know at this point whether the
3767 * depth or stencil tests used will actually write to the surface.
3769 * Even though stencil may be plane 1, it always shares a base_level
3772 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
3773 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3774 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3775 VK_IMAGE_ASPECT_DEPTH_BIT
,
3776 att_state
->aux_usage
,
3777 ds_view
->base_level
,
3778 ds_view
->base_array_layer
,
3781 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
3782 /* Even though stencil may be plane 1, it always shares a
3783 * base_level with depth.
3785 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3786 VK_IMAGE_ASPECT_STENCIL_BIT
,
3788 ds_view
->base_level
,
3789 ds_view
->base_array_layer
,
3794 /* If multiview is enabled, then we are only done clearing when we no
3795 * longer have pending layers to clear, or when we have processed the
3796 * last subpass that uses this attachment.
3798 if (!is_multiview
||
3799 att_state
->pending_clear_views
== 0 ||
3800 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
3801 att_state
->pending_clear_aspects
= 0;
3804 att_state
->pending_load_aspects
= 0;
3807 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3811 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
3813 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3814 struct anv_subpass
*subpass
= cmd_state
->subpass
;
3815 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3817 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3819 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3820 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3821 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3822 if (a
== VK_ATTACHMENT_UNUSED
)
3825 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3828 assert(a
< cmd_state
->pass
->attachment_count
);
3829 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3830 struct anv_image_view
*iview
= fb
->attachments
[a
];
3831 const struct anv_image
*image
= iview
->image
;
3833 /* Transition the image into the final layout for this render pass */
3834 VkImageLayout target_layout
=
3835 cmd_state
->pass
->attachments
[a
].final_layout
;
3837 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3838 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3840 uint32_t base_layer
, layer_count
;
3841 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3843 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3844 iview
->planes
[0].isl
.base_level
);
3846 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3847 layer_count
= fb
->layers
;
3850 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3851 iview
->planes
[0].isl
.base_level
, 1,
3852 base_layer
, layer_count
,
3853 att_state
->current_layout
, target_layout
);
3854 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3855 transition_depth_buffer(cmd_buffer
, image
,
3856 att_state
->current_layout
, target_layout
);
3860 /* Accumulate any subpass flushes that need to happen after the subpass.
3861 * Yes, they do get accumulated twice in the NextSubpass case but since
3862 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
3863 * ORing the bits in twice so it's harmless.
3865 cmd_buffer
->state
.pending_pipe_bits
|=
3866 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
3869 void genX(CmdBeginRenderPass
)(
3870 VkCommandBuffer commandBuffer
,
3871 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3872 VkSubpassContents contents
)
3874 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3875 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3876 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3878 cmd_buffer
->state
.framebuffer
= framebuffer
;
3879 cmd_buffer
->state
.pass
= pass
;
3880 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3882 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3884 /* If we failed to setup the attachments we should not try to go further */
3885 if (result
!= VK_SUCCESS
) {
3886 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3890 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3892 cmd_buffer_begin_subpass(cmd_buffer
, 0);
3895 void genX(CmdNextSubpass
)(
3896 VkCommandBuffer commandBuffer
,
3897 VkSubpassContents contents
)
3899 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3901 if (anv_batch_has_error(&cmd_buffer
->batch
))
3904 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3906 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
3907 cmd_buffer_end_subpass(cmd_buffer
);
3908 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3911 void genX(CmdEndRenderPass
)(
3912 VkCommandBuffer commandBuffer
)
3914 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3916 if (anv_batch_has_error(&cmd_buffer
->batch
))
3919 cmd_buffer_end_subpass(cmd_buffer
);
3921 cmd_buffer
->state
.hiz_enabled
= false;
3924 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
3927 /* Remove references to render pass specific state. This enables us to
3928 * detect whether or not we're in a renderpass.
3930 cmd_buffer
->state
.framebuffer
= NULL
;
3931 cmd_buffer
->state
.pass
= NULL
;
3932 cmd_buffer
->state
.subpass
= NULL
;