2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_l3_config.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
37 emit_lrm(struct anv_batch
*batch
, uint32_t reg
, struct anv_address addr
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= addr
;
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* If we are emitting a new state base address we probably need to re-emit
73 cmd_buffer
->state
.descriptors_dirty
|= ~0;
75 /* Emit a render target cache flush.
77 * This isn't documented anywhere in the PRM. However, it seems to be
78 * necessary prior to changing the surface state base adress. Without
79 * this, we get GPU hangs when using multi-level command buffers which
80 * clear depth, reset state base address, and then go render stuff.
82 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
83 pc
.DCFlushEnable
= true;
84 pc
.RenderTargetCacheFlushEnable
= true;
85 pc
.CommandStreamerStallEnable
= true;
88 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
89 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
90 sba
.GeneralStateMOCS
= GENX(MOCS
);
91 sba
.GeneralStateBaseAddressModifyEnable
= true;
93 sba
.SurfaceStateBaseAddress
=
94 anv_cmd_buffer_surface_base_address(cmd_buffer
);
95 sba
.SurfaceStateMOCS
= GENX(MOCS
);
96 sba
.SurfaceStateBaseAddressModifyEnable
= true;
98 sba
.DynamicStateBaseAddress
=
99 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
100 sba
.DynamicStateMOCS
= GENX(MOCS
);
101 sba
.DynamicStateBaseAddressModifyEnable
= true;
103 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
104 sba
.IndirectObjectMOCS
= GENX(MOCS
);
105 sba
.IndirectObjectBaseAddressModifyEnable
= true;
107 sba
.InstructionBaseAddress
=
108 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
109 sba
.InstructionMOCS
= GENX(MOCS
);
110 sba
.InstructionBaseAddressModifyEnable
= true;
113 /* Broadwell requires that we specify a buffer size for a bunch of
114 * these fields. However, since we will be growing the BO's live, we
115 * just set them all to the maximum.
117 sba
.GeneralStateBufferSize
= 0xfffff;
118 sba
.GeneralStateBufferSizeModifyEnable
= true;
119 sba
.DynamicStateBufferSize
= 0xfffff;
120 sba
.DynamicStateBufferSizeModifyEnable
= true;
121 sba
.IndirectObjectBufferSize
= 0xfffff;
122 sba
.IndirectObjectBufferSizeModifyEnable
= true;
123 sba
.InstructionBufferSize
= 0xfffff;
124 sba
.InstructionBuffersizeModifyEnable
= true;
127 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
128 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
129 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
130 sba
.BindlessSurfaceStateSize
= 0;
133 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
134 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
135 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
136 sba
.BindlessSamplerStateBufferSize
= 0;
140 /* After re-setting the surface state base address, we have to do some
141 * cache flusing so that the sampler engine will pick up the new
142 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
143 * Shared Function > 3D Sampler > State > State Caching (page 96):
145 * Coherency with system memory in the state cache, like the texture
146 * cache is handled partially by software. It is expected that the
147 * command stream or shader will issue Cache Flush operation or
148 * Cache_Flush sampler message to ensure that the L1 cache remains
149 * coherent with system memory.
153 * Whenever the value of the Dynamic_State_Base_Addr,
154 * Surface_State_Base_Addr are altered, the L1 state cache must be
155 * invalidated to ensure the new surface or sampler state is fetched
156 * from system memory.
158 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
159 * which, according the PIPE_CONTROL instruction documentation in the
162 * Setting this bit is independent of any other bit in this packet.
163 * This bit controls the invalidation of the L1 and L2 state caches
164 * at the top of the pipe i.e. at the parsing time.
166 * Unfortunately, experimentation seems to indicate that state cache
167 * invalidation through a PIPE_CONTROL does nothing whatsoever in
168 * regards to surface state and binding tables. In stead, it seems that
169 * invalidating the texture cache is what is actually needed.
171 * XXX: As far as we have been able to determine through
172 * experimentation, shows that flush the texture cache appears to be
173 * sufficient. The theory here is that all of the sampling/rendering
174 * units cache the binding table in the texture cache. However, we have
175 * yet to be able to actually confirm this.
177 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
178 pc
.TextureCacheInvalidationEnable
= true;
179 pc
.ConstantCacheInvalidationEnable
= true;
180 pc
.StateCacheInvalidationEnable
= true;
185 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
186 struct anv_state state
, struct anv_address addr
)
188 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
191 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
192 state
.offset
+ isl_dev
->ss
.addr_offset
,
193 addr
.bo
, addr
.offset
);
194 if (result
!= VK_SUCCESS
)
195 anv_batch_set_error(&cmd_buffer
->batch
, result
);
199 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
200 struct anv_surface_state state
)
202 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
204 assert(!anv_address_is_null(state
.address
));
205 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
207 if (!anv_address_is_null(state
.aux_address
)) {
209 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
210 &cmd_buffer
->pool
->alloc
,
211 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
212 state
.aux_address
.bo
, state
.aux_address
.offset
);
213 if (result
!= VK_SUCCESS
)
214 anv_batch_set_error(&cmd_buffer
->batch
, result
);
217 if (!anv_address_is_null(state
.clear_address
)) {
219 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
220 &cmd_buffer
->pool
->alloc
,
222 isl_dev
->ss
.clear_color_state_offset
,
223 state
.clear_address
.bo
, state
.clear_address
.offset
);
224 if (result
!= VK_SUCCESS
)
225 anv_batch_set_error(&cmd_buffer
->batch
, result
);
230 color_attachment_compute_aux_usage(struct anv_device
* device
,
231 struct anv_cmd_state
* cmd_state
,
232 uint32_t att
, VkRect2D render_area
,
233 union isl_color_value
*fast_clear_color
)
235 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
236 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
238 assert(iview
->n_planes
== 1);
240 if (iview
->planes
[0].isl
.base_array_layer
>=
241 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
242 iview
->planes
[0].isl
.base_level
)) {
243 /* There is no aux buffer which corresponds to the level and layer(s)
246 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
247 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
248 att_state
->fast_clear
= false;
252 att_state
->aux_usage
=
253 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
254 VK_IMAGE_ASPECT_COLOR_BIT
,
255 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
257 /* If we don't have aux, then we should have returned early in the layer
258 * check above. If we got here, we must have something.
260 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
262 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
263 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
264 att_state
->input_aux_usage
= att_state
->aux_usage
;
266 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
268 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
269 * setting is only allowed if Surface Format supported for Fast
270 * Clear. In addition, if the surface is bound to the sampling
271 * engine, Surface Format must be supported for Render Target
272 * Compression for surfaces bound to the sampling engine."
274 * In other words, we can only sample from a fast-cleared image if it
275 * also supports color compression.
277 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
278 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
280 /* While fast-clear resolves and partial resolves are fairly cheap in the
281 * case where you render to most of the pixels, full resolves are not
282 * because they potentially involve reading and writing the entire
283 * framebuffer. If we can't texture with CCS_E, we should leave it off and
284 * limit ourselves to fast clears.
286 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
287 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
288 anv_perf_warn(device
->instance
, iview
->image
,
289 "Not temporarily enabling CCS_E.");
292 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
296 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
297 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
299 union isl_color_value clear_color
= {};
300 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
302 att_state
->clear_color_is_zero_one
=
303 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
304 att_state
->clear_color_is_zero
=
305 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
307 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
308 /* Start by getting the fast clear type. We use the first subpass
309 * layout here because we don't want to fast-clear if the first subpass
310 * to use the attachment can't handle fast-clears.
312 enum anv_fast_clear_type fast_clear_type
=
313 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
314 VK_IMAGE_ASPECT_COLOR_BIT
,
315 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
316 switch (fast_clear_type
) {
317 case ANV_FAST_CLEAR_NONE
:
318 att_state
->fast_clear
= false;
320 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
321 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
323 case ANV_FAST_CLEAR_ANY
:
324 att_state
->fast_clear
= true;
328 /* Potentially, we could do partial fast-clears but doing so has crazy
329 * alignment restrictions. It's easier to just restrict to full size
330 * fast clears for now.
332 if (render_area
.offset
.x
!= 0 ||
333 render_area
.offset
.y
!= 0 ||
334 render_area
.extent
.width
!= iview
->extent
.width
||
335 render_area
.extent
.height
!= iview
->extent
.height
)
336 att_state
->fast_clear
= false;
338 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
339 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
340 att_state
->fast_clear
= false;
342 /* We only allow fast clears to the first slice of an image (level 0,
343 * layer 0) and only for the entire slice. This guarantees us that, at
344 * any given time, there is only one clear color on any given image at
345 * any given time. At the time of our testing (Jan 17, 2018), there
346 * were no known applications which would benefit from fast-clearing
347 * more than just the first slice.
349 if (att_state
->fast_clear
&&
350 (iview
->planes
[0].isl
.base_level
> 0 ||
351 iview
->planes
[0].isl
.base_array_layer
> 0)) {
352 anv_perf_warn(device
->instance
, iview
->image
,
353 "Rendering with multi-lod or multi-layer framebuffer "
354 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
355 "baseArrayLayer > 0. Not fast clearing.");
356 att_state
->fast_clear
= false;
357 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
358 anv_perf_warn(device
->instance
, iview
->image
,
359 "Rendering to a multi-layer framebuffer with "
360 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
363 if (att_state
->fast_clear
)
364 *fast_clear_color
= clear_color
;
366 att_state
->fast_clear
= false;
371 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
372 struct anv_cmd_state
*cmd_state
,
373 uint32_t att
, VkRect2D render_area
)
375 struct anv_render_pass_attachment
*pass_att
=
376 &cmd_state
->pass
->attachments
[att
];
377 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
378 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
380 /* These will be initialized after the first subpass transition. */
381 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
382 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
385 /* We don't do any HiZ or depth fast-clears on gen7 yet */
386 att_state
->fast_clear
= false;
390 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
391 /* If we're just clearing stencil, we can always HiZ clear */
392 att_state
->fast_clear
= true;
396 /* Default to false for now */
397 att_state
->fast_clear
= false;
399 /* We must have depth in order to have HiZ */
400 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
403 const enum isl_aux_usage first_subpass_aux_usage
=
404 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
405 VK_IMAGE_ASPECT_DEPTH_BIT
,
406 pass_att
->first_subpass_layout
);
407 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
410 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
411 iview
->planes
[0].isl
.format
,
412 iview
->image
->samples
,
413 render_area
.offset
.x
,
414 render_area
.offset
.y
,
415 render_area
.offset
.x
+
416 render_area
.extent
.width
,
417 render_area
.offset
.y
+
418 render_area
.extent
.height
))
421 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
424 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
425 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
426 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
427 * only supports returning 0.0f. Gens prior to gen8 do not support this
433 /* If we got here, then we can fast clear */
434 att_state
->fast_clear
= true;
438 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
440 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
443 /* We only allocate input attachment states for color surfaces. Compression
444 * is not yet enabled for depth textures and stencil doesn't allow
445 * compression so we can just use the texture surface state from the view.
447 return vk_format_is_color(att
->format
);
450 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
451 * the initial layout is undefined, the HiZ buffer and depth buffer will
452 * represent the same data at the end of this operation.
455 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
456 const struct anv_image
*image
,
457 VkImageLayout initial_layout
,
458 VkImageLayout final_layout
)
460 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
461 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
462 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
463 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
464 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
465 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
467 enum isl_aux_op hiz_op
;
468 if (hiz_enabled
&& !enable_hiz
) {
469 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
470 } else if (!hiz_enabled
&& enable_hiz
) {
471 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
473 assert(hiz_enabled
== enable_hiz
);
474 /* If the same buffer will be used, no resolves are necessary. */
475 hiz_op
= ISL_AUX_OP_NONE
;
478 if (hiz_op
!= ISL_AUX_OP_NONE
)
479 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
483 #define MI_PREDICATE_SRC0 0x2400
484 #define MI_PREDICATE_SRC1 0x2408
485 #define MI_PREDICATE_RESULT 0x2418
488 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
489 const struct anv_image
*image
,
490 VkImageAspectFlagBits aspect
,
492 uint32_t base_layer
, uint32_t layer_count
,
495 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
497 /* We only have compression tracking for CCS_E */
498 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
501 for (uint32_t a
= 0; a
< layer_count
; a
++) {
502 uint32_t layer
= base_layer
+ a
;
503 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
504 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
507 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
513 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
514 const struct anv_image
*image
,
515 VkImageAspectFlagBits aspect
,
516 enum anv_fast_clear_type fast_clear
)
518 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
519 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
521 sdi
.ImmediateData
= fast_clear
;
524 /* Whenever we have fast-clear, we consider that slice to be compressed.
525 * This makes building predicates much easier.
527 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
528 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
531 #if GEN_IS_HASWELL || GEN_GEN >= 8
532 static inline uint32_t
533 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
535 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
537 .Operand1
= operand1
,
538 .Operand2
= operand2
,
542 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
548 #define CS_GPR(n) (0x2600 + (n) * 8)
550 /* This is only really practical on haswell and above because it requires
551 * MI math in order to get it correct.
553 #if GEN_GEN >= 8 || GEN_IS_HASWELL
555 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
556 const struct anv_image
*image
,
557 VkImageAspectFlagBits aspect
,
558 uint32_t level
, uint32_t array_layer
,
559 enum isl_aux_op resolve_op
,
560 enum anv_fast_clear_type fast_clear_supported
)
562 struct anv_address fast_clear_type_addr
=
563 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
565 /* Name some registers */
566 const int image_fc_reg
= MI_ALU_REG0
;
567 const int fc_imm_reg
= MI_ALU_REG1
;
568 const int pred_reg
= MI_ALU_REG2
;
572 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
573 /* In this case, we're doing a full resolve which means we want the
574 * resolve to happen if any compression (including fast-clears) is
577 * In order to simplify the logic a bit, we make the assumption that,
578 * if the first slice has been fast-cleared, it is also marked as
579 * compressed. See also set_image_fast_clear_state.
581 struct anv_address compression_state_addr
=
582 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
583 aspect
, level
, array_layer
);
584 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
585 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
586 lrm
.MemoryAddress
= compression_state_addr
;
588 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
589 sdi
.Address
= compression_state_addr
;
590 sdi
.ImmediateData
= 0;
593 if (level
== 0 && array_layer
== 0) {
594 /* If the predicate is true, we want to write 0 to the fast clear type
595 * and, if it's false, leave it alone. We can do this by writing
597 * clear_type = clear_type & ~predicate;
599 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
600 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
601 lrm
.MemoryAddress
= fast_clear_type_addr
;
603 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
604 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
605 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
608 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
609 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
610 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
611 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
612 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
614 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
615 srm
.MemoryAddress
= fast_clear_type_addr
;
616 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
619 } else if (level
== 0 && array_layer
== 0) {
620 /* In this case, we are doing a partial resolve to get rid of fast-clear
621 * colors. We don't care about the compression state but we do care
622 * about how much fast clear is allowed by the final layout.
624 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
625 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
627 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
628 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
629 lrm
.MemoryAddress
= fast_clear_type_addr
;
631 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
633 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
634 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
636 /* We need to compute (fast_clear_supported < image->fast_clear).
637 * We do this by subtracting and storing the carry bit.
639 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
640 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
641 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
642 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
643 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
645 /* Store the predicate */
646 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
648 /* If the predicate is true, we want to write 0 to the fast clear type
649 * and, if it's false, leave it alone. We can do this by writing
651 * clear_type = clear_type & ~predicate;
653 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
654 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
655 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
656 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
657 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
659 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
660 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
661 srm
.MemoryAddress
= fast_clear_type_addr
;
664 /* In this case, we're trying to do a partial resolve on a slice that
665 * doesn't have clear color. There's nothing to do.
667 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
671 /* We use the first half of src0 for the actual predicate. Set the second
672 * half of src0 and all of src1 to 0 as the predicate operation will be
673 * doing an implicit src0 != src1.
675 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
676 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
677 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
679 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
680 mip
.LoadOperation
= LOAD_LOADINV
;
681 mip
.CombineOperation
= COMBINE_SET
;
682 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
685 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
689 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
690 const struct anv_image
*image
,
691 VkImageAspectFlagBits aspect
,
692 uint32_t level
, uint32_t array_layer
,
693 enum isl_aux_op resolve_op
,
694 enum anv_fast_clear_type fast_clear_supported
)
696 struct anv_address fast_clear_type_addr
=
697 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
699 /* This only works for partial resolves and only when the clear color is
700 * all or nothing. On the upside, this emits less command streamer code
701 * and works on Ivybridge and Bay Trail.
703 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
704 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
706 /* We don't support fast clears on anything other than the first slice. */
707 if (level
> 0 || array_layer
> 0)
710 /* On gen8, we don't have a concept of default clear colors because we
711 * can't sample from CCS surfaces. It's enough to just load the fast clear
712 * state into the predicate register.
714 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
715 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
716 lrm
.MemoryAddress
= fast_clear_type_addr
;
718 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
719 sdi
.Address
= fast_clear_type_addr
;
720 sdi
.ImmediateData
= 0;
723 /* We use the first half of src0 for the actual predicate. Set the second
724 * half of src0 and all of src1 to 0 as the predicate operation will be
725 * doing an implicit src0 != src1.
727 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
728 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
729 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
731 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
732 mip
.LoadOperation
= LOAD_LOADINV
;
733 mip
.CombineOperation
= COMBINE_SET
;
734 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
737 #endif /* GEN_GEN <= 8 */
740 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
741 const struct anv_image
*image
,
742 enum isl_format format
,
743 VkImageAspectFlagBits aspect
,
744 uint32_t level
, uint32_t array_layer
,
745 enum isl_aux_op resolve_op
,
746 enum anv_fast_clear_type fast_clear_supported
)
748 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
751 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
752 aspect
, level
, array_layer
,
753 resolve_op
, fast_clear_supported
);
754 #else /* GEN_GEN <= 8 */
755 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
756 aspect
, level
, array_layer
,
757 resolve_op
, fast_clear_supported
);
760 /* CCS_D only supports full resolves and BLORP will assert on us if we try
761 * to do a partial resolve on a CCS_D surface.
763 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
764 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
765 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
767 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
768 array_layer
, 1, resolve_op
, NULL
, true);
772 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
773 const struct anv_image
*image
,
774 enum isl_format format
,
775 VkImageAspectFlagBits aspect
,
776 uint32_t array_layer
,
777 enum isl_aux_op resolve_op
,
778 enum anv_fast_clear_type fast_clear_supported
)
780 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
781 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
783 #if GEN_GEN >= 8 || GEN_IS_HASWELL
784 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
785 aspect
, 0, array_layer
,
786 resolve_op
, fast_clear_supported
);
788 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
789 array_layer
, 1, resolve_op
, NULL
, true);
791 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
796 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
797 const struct anv_image
*image
,
798 VkImageAspectFlagBits aspect
,
799 enum isl_aux_usage aux_usage
,
802 uint32_t layer_count
)
804 /* The aspect must be exactly one of the image aspects. */
805 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
807 /* The only compression types with more than just fast-clears are MCS,
808 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
809 * track the current fast-clear and compression state. This leaves us
810 * with just MCS and CCS_E.
812 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
813 aux_usage
!= ISL_AUX_USAGE_MCS
)
816 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
817 level
, base_layer
, layer_count
, true);
821 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
822 const struct anv_image
*image
,
823 VkImageAspectFlagBits aspect
)
825 assert(cmd_buffer
&& image
);
826 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
828 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
829 ANV_FAST_CLEAR_NONE
);
831 /* The fast clear value dword(s) will be copied into a surface state object.
832 * Ensure that the restrictions of the fields in the dword(s) are followed.
834 * CCS buffers on SKL+ can have any value set for the clear colors.
836 if (image
->samples
== 1 && GEN_GEN
>= 9)
839 /* Other combinations of auxiliary buffers and platforms require specific
840 * values in the clear value dword(s).
842 struct anv_address addr
=
843 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
846 for (unsigned i
= 0; i
< 4; i
++) {
847 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
849 sdi
.Address
.offset
+= i
* 4;
850 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
851 assert(image
->samples
> 1);
852 sdi
.ImmediateData
= 0;
856 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
858 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
859 /* Pre-SKL, the dword containing the clear values also contains
860 * other fields, so we need to initialize those fields to match the
861 * values that would be in a color attachment.
863 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
864 ISL_CHANNEL_SELECT_GREEN
<< 22 |
865 ISL_CHANNEL_SELECT_BLUE
<< 19 |
866 ISL_CHANNEL_SELECT_ALPHA
<< 16;
867 } else if (GEN_GEN
== 7) {
868 /* On IVB, the dword containing the clear values also contains
869 * other fields that must be zero or can be zero.
871 sdi
.ImmediateData
= 0;
877 /* Copy the fast-clear value dword(s) between a surface state object and an
878 * image's fast clear state buffer.
881 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
882 struct anv_state surface_state
,
883 const struct anv_image
*image
,
884 VkImageAspectFlagBits aspect
,
885 bool copy_from_surface_state
)
887 assert(cmd_buffer
&& image
);
888 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
890 struct anv_address ss_clear_addr
= {
891 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
892 .offset
= surface_state
.offset
+
893 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
895 const struct anv_address entry_addr
=
896 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
897 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
899 if (copy_from_surface_state
) {
900 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
,
901 ss_clear_addr
, copy_size
);
903 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_clear_addr
,
904 entry_addr
, copy_size
);
906 /* Updating a surface state object may require that the state cache be
907 * invalidated. From the SKL PRM, Shared Functions -> State -> State
910 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
911 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
912 * modified [...], the L1 state cache must be invalidated to ensure
913 * the new surface or sampler state is fetched from system memory.
915 * In testing, SKL doesn't actually seem to need this, but HSW does.
917 cmd_buffer
->state
.pending_pipe_bits
|=
918 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
923 * @brief Transitions a color buffer from one layout to another.
925 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
928 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
929 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
930 * this represents the maximum layers to transition at each
931 * specified miplevel.
934 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
935 const struct anv_image
*image
,
936 VkImageAspectFlagBits aspect
,
937 const uint32_t base_level
, uint32_t level_count
,
938 uint32_t base_layer
, uint32_t layer_count
,
939 VkImageLayout initial_layout
,
940 VkImageLayout final_layout
)
942 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
943 /* Validate the inputs. */
945 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
946 /* These values aren't supported for simplicity's sake. */
947 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
948 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
949 /* Ensure the subresource range is valid. */
950 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
951 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
952 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
953 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
954 assert(last_level_num
<= image
->levels
);
955 /* The spec disallows these final layouts. */
956 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
957 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
959 /* No work is necessary if the layout stays the same or if this subresource
960 * range lacks auxiliary data.
962 if (initial_layout
== final_layout
)
965 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
967 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
968 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
969 /* This surface is a linear compressed image with a tiled shadow surface
970 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
971 * we need to ensure the shadow copy is up-to-date.
973 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
974 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
975 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
976 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
978 anv_image_copy_to_shadow(cmd_buffer
, image
,
979 base_level
, level_count
,
980 base_layer
, layer_count
);
983 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
986 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
988 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
989 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
990 /* A subresource in the undefined layout may have been aliased and
991 * populated with any arrangement of bits. Therefore, we must initialize
992 * the related aux buffer and clear buffer entry with desirable values.
993 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
994 * images with VK_IMAGE_TILING_OPTIMAL.
996 * Initialize the relevant clear buffer entries.
998 if (base_level
== 0 && base_layer
== 0)
999 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1001 /* Initialize the aux buffers to enable correct rendering. In order to
1002 * ensure that things such as storage images work correctly, aux buffers
1003 * need to be initialized to valid data.
1005 * Having an aux buffer with invalid data is a problem for two reasons:
1007 * 1) Having an invalid value in the buffer can confuse the hardware.
1008 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1009 * invalid and leads to the hardware doing strange things. It
1010 * doesn't hang as far as we can tell but rendering corruption can
1013 * 2) If this transition is into the GENERAL layout and we then use the
1014 * image as a storage image, then we must have the aux buffer in the
1015 * pass-through state so that, if we then go to texture from the
1016 * image, we get the results of our storage image writes and not the
1017 * fast clear color or other random data.
1019 * For CCS both of the problems above are real demonstrable issues. In
1020 * that case, the only thing we can do is to perform an ambiguate to
1021 * transition the aux surface into the pass-through state.
1023 * For MCS, (2) is never an issue because we don't support multisampled
1024 * storage images. In theory, issue (1) is a problem with MCS but we've
1025 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1026 * theory, be interpreted as something but we don't know that all bit
1027 * patterns are actually valid. For 2x and 8x, you could easily end up
1028 * with the MCS referring to an invalid plane because not all bits of
1029 * the MCS value are actually used. Even though we've never seen issues
1030 * in the wild, it's best to play it safe and initialize the MCS. We
1031 * can use a fast-clear for MCS because we only ever touch from render
1032 * and texture (no image load store).
1034 if (image
->samples
== 1) {
1035 for (uint32_t l
= 0; l
< level_count
; l
++) {
1036 const uint32_t level
= base_level
+ l
;
1038 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1039 if (base_layer
>= aux_layers
)
1040 break; /* We will only get fewer layers as level increases */
1041 uint32_t level_layer_count
=
1042 MIN2(layer_count
, aux_layers
- base_layer
);
1044 anv_image_ccs_op(cmd_buffer
, image
,
1045 image
->planes
[plane
].surface
.isl
.format
,
1046 aspect
, level
, base_layer
, level_layer_count
,
1047 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1049 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1050 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1051 level
, base_layer
, level_layer_count
,
1056 if (image
->samples
== 4 || image
->samples
== 16) {
1057 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1058 "Doing a potentially unnecessary fast-clear to "
1059 "define an MCS buffer.");
1062 assert(base_level
== 0 && level_count
== 1);
1063 anv_image_mcs_op(cmd_buffer
, image
,
1064 image
->planes
[plane
].surface
.isl
.format
,
1065 aspect
, base_layer
, layer_count
,
1066 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1071 const enum isl_aux_usage initial_aux_usage
=
1072 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1073 const enum isl_aux_usage final_aux_usage
=
1074 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1076 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1077 * We can handle transitions between CCS_D/E to and from NONE. What we
1078 * don't yet handle is switching between CCS_E and CCS_D within a given
1079 * image. Doing so in a performant way requires more detailed aux state
1080 * tracking such as what is done in i965. For now, just assume that we
1081 * only have one type of compression.
1083 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1084 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1085 initial_aux_usage
== final_aux_usage
);
1087 /* If initial aux usage is NONE, there is nothing to resolve */
1088 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1091 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1093 /* If the initial layout supports more fast clear than the final layout
1094 * then we need at least a partial resolve.
1096 const enum anv_fast_clear_type initial_fast_clear
=
1097 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1098 const enum anv_fast_clear_type final_fast_clear
=
1099 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1100 if (final_fast_clear
< initial_fast_clear
)
1101 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1103 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1104 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1105 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1107 if (resolve_op
== ISL_AUX_OP_NONE
)
1110 /* Perform a resolve to synchronize data between the main and aux buffer.
1111 * Before we begin, we must satisfy the cache flushing requirement specified
1112 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1114 * Any transition from any value in {Clear, Render, Resolve} to a
1115 * different value in {Clear, Render, Resolve} requires end of pipe
1118 * We perform a flush of the write cache before and after the clear and
1119 * resolve operations to meet this requirement.
1121 * Unlike other drawing, fast clear operations are not properly
1122 * synchronized. The first PIPE_CONTROL here likely ensures that the
1123 * contents of the previous render or clear hit the render target before we
1124 * resolve and the second likely ensures that the resolve is complete before
1125 * we do any more rendering or clearing.
1127 cmd_buffer
->state
.pending_pipe_bits
|=
1128 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1130 for (uint32_t l
= 0; l
< level_count
; l
++) {
1131 uint32_t level
= base_level
+ l
;
1133 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1134 if (base_layer
>= aux_layers
)
1135 break; /* We will only get fewer layers as level increases */
1136 uint32_t level_layer_count
=
1137 MIN2(layer_count
, aux_layers
- base_layer
);
1139 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1140 uint32_t array_layer
= base_layer
+ a
;
1141 if (image
->samples
== 1) {
1142 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1143 image
->planes
[plane
].surface
.isl
.format
,
1144 aspect
, level
, array_layer
, resolve_op
,
1147 /* We only support fast-clear on the first layer so partial
1148 * resolves should not be used on other layers as they will use
1149 * the clear color stored in memory that is only valid for layer0.
1151 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1155 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1156 image
->planes
[plane
].surface
.isl
.format
,
1157 aspect
, array_layer
, resolve_op
,
1163 cmd_buffer
->state
.pending_pipe_bits
|=
1164 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1168 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1171 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1172 struct anv_render_pass
*pass
,
1173 const VkRenderPassBeginInfo
*begin
)
1175 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1176 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1178 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1180 if (pass
->attachment_count
> 0) {
1181 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1182 pass
->attachment_count
*
1183 sizeof(state
->attachments
[0]),
1184 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1185 if (state
->attachments
== NULL
) {
1186 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1187 return anv_batch_set_error(&cmd_buffer
->batch
,
1188 VK_ERROR_OUT_OF_HOST_MEMORY
);
1191 state
->attachments
= NULL
;
1194 /* Reserve one for the NULL state. */
1195 unsigned num_states
= 1;
1196 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1197 if (vk_format_is_color(pass
->attachments
[i
].format
))
1200 if (need_input_attachment_state(&pass
->attachments
[i
]))
1204 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1205 state
->render_pass_states
=
1206 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1207 num_states
* ss_stride
, isl_dev
->ss
.align
);
1209 struct anv_state next_state
= state
->render_pass_states
;
1210 next_state
.alloc_size
= isl_dev
->ss
.size
;
1212 state
->null_surface_state
= next_state
;
1213 next_state
.offset
+= ss_stride
;
1214 next_state
.map
+= ss_stride
;
1216 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1217 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1218 state
->attachments
[i
].color
.state
= next_state
;
1219 next_state
.offset
+= ss_stride
;
1220 next_state
.map
+= ss_stride
;
1223 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1224 state
->attachments
[i
].input
.state
= next_state
;
1225 next_state
.offset
+= ss_stride
;
1226 next_state
.map
+= ss_stride
;
1229 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1230 state
->render_pass_states
.alloc_size
);
1233 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1234 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1236 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1237 isl_extent3d(framebuffer
->width
,
1238 framebuffer
->height
,
1239 framebuffer
->layers
));
1241 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1242 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1243 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1244 VkImageAspectFlags clear_aspects
= 0;
1245 VkImageAspectFlags load_aspects
= 0;
1247 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1248 /* color attachment */
1249 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1250 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1251 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1252 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1255 /* depthstencil attachment */
1256 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1257 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1258 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1259 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1260 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1263 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1264 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1265 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1266 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1267 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1272 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1273 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1274 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1276 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1278 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1279 anv_assert(iview
->vk_format
== att
->format
);
1281 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1282 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1284 union isl_color_value clear_color
= { .u32
= { 0, } };
1285 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1286 anv_assert(iview
->n_planes
== 1);
1287 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1288 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1289 state
, i
, begin
->renderArea
,
1292 anv_image_fill_surface_state(cmd_buffer
->device
,
1294 VK_IMAGE_ASPECT_COLOR_BIT
,
1295 &iview
->planes
[0].isl
,
1296 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1297 state
->attachments
[i
].aux_usage
,
1300 &state
->attachments
[i
].color
,
1303 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1305 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1310 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1311 anv_image_fill_surface_state(cmd_buffer
->device
,
1313 VK_IMAGE_ASPECT_COLOR_BIT
,
1314 &iview
->planes
[0].isl
,
1315 ISL_SURF_USAGE_TEXTURE_BIT
,
1316 state
->attachments
[i
].input_aux_usage
,
1319 &state
->attachments
[i
].input
,
1322 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1331 genX(BeginCommandBuffer
)(
1332 VkCommandBuffer commandBuffer
,
1333 const VkCommandBufferBeginInfo
* pBeginInfo
)
1335 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1337 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1338 * command buffer's state. Otherwise, we must *reset* its state. In both
1339 * cases we reset it.
1341 * From the Vulkan 1.0 spec:
1343 * If a command buffer is in the executable state and the command buffer
1344 * was allocated from a command pool with the
1345 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1346 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1347 * as if vkResetCommandBuffer had been called with
1348 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1349 * the command buffer in the recording state.
1351 anv_cmd_buffer_reset(cmd_buffer
);
1353 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1355 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1356 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1358 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1360 /* We sometimes store vertex data in the dynamic state buffer for blorp
1361 * operations and our dynamic state stream may re-use data from previous
1362 * command buffers. In order to prevent stale cache data, we flush the VF
1363 * cache. We could do this on every blorp call but that's not really
1364 * needed as all of the data will get written by the CPU prior to the GPU
1365 * executing anything. The chances are fairly high that they will use
1366 * blorp at least once per primary command buffer so it shouldn't be
1369 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1370 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1372 /* We send an "Indirect State Pointers Disable" packet at
1373 * EndCommandBuffer, so all push contant packets are ignored during a
1374 * context restore. Documentation says after that command, we need to
1375 * emit push constants again before any rendering operation. So we
1376 * flag them dirty here to make sure they get emitted.
1378 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1380 VkResult result
= VK_SUCCESS
;
1381 if (cmd_buffer
->usage_flags
&
1382 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1383 assert(pBeginInfo
->pInheritanceInfo
);
1384 cmd_buffer
->state
.pass
=
1385 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1386 cmd_buffer
->state
.subpass
=
1387 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1389 /* This is optional in the inheritance info. */
1390 cmd_buffer
->state
.framebuffer
=
1391 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1393 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1394 cmd_buffer
->state
.pass
, NULL
);
1396 /* Record that HiZ is enabled if we can. */
1397 if (cmd_buffer
->state
.framebuffer
) {
1398 const struct anv_image_view
* const iview
=
1399 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1402 VkImageLayout layout
=
1403 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1405 enum isl_aux_usage aux_usage
=
1406 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1407 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1409 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1413 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1416 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1417 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1418 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1419 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1421 /* If secondary buffer supports conditional rendering
1422 * we should emit commands as if conditional rendering is enabled.
1424 cmd_buffer
->state
.conditional_render_enabled
=
1425 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1432 /* From the PRM, Volume 2a:
1434 * "Indirect State Pointers Disable
1436 * At the completion of the post-sync operation associated with this pipe
1437 * control packet, the indirect state pointers in the hardware are
1438 * considered invalid; the indirect pointers are not saved in the context.
1439 * If any new indirect state commands are executed in the command stream
1440 * while the pipe control is pending, the new indirect state commands are
1443 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1444 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1445 * commands are only considered as Indirect State Pointers. Once ISP is
1446 * issued in a context, SW must initialize by programming push constant
1447 * commands for all the shaders (at least to zero length) before attempting
1448 * any rendering operation for the same context."
1450 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1451 * even though they point to a BO that has been already unreferenced at
1452 * the end of the previous batch buffer. This has been fine so far since
1453 * we are protected by these scratch page (every address not covered by
1454 * a BO should be pointing to the scratch page). But on CNL, it is
1455 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1458 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1459 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1460 * context restore, so the mentioned hang doesn't happen. However,
1461 * software must program push constant commands for all stages prior to
1462 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1464 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1465 * constants have been loaded into the EUs prior to disable the push constants
1466 * so that it doesn't hang a previous 3DPRIMITIVE.
1469 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1471 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1472 pc
.StallAtPixelScoreboard
= true;
1473 pc
.CommandStreamerStallEnable
= true;
1475 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1476 pc
.IndirectStatePointersDisable
= true;
1477 pc
.CommandStreamerStallEnable
= true;
1482 genX(EndCommandBuffer
)(
1483 VkCommandBuffer commandBuffer
)
1485 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1487 if (anv_batch_has_error(&cmd_buffer
->batch
))
1488 return cmd_buffer
->batch
.status
;
1490 /* We want every command buffer to start with the PMA fix in a known state,
1491 * so we disable it at the end of the command buffer.
1493 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1495 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1497 emit_isp_disable(cmd_buffer
);
1499 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1505 genX(CmdExecuteCommands
)(
1506 VkCommandBuffer commandBuffer
,
1507 uint32_t commandBufferCount
,
1508 const VkCommandBuffer
* pCmdBuffers
)
1510 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1512 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1514 if (anv_batch_has_error(&primary
->batch
))
1517 /* The secondary command buffers will assume that the PMA fix is disabled
1518 * when they begin executing. Make sure this is true.
1520 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1522 /* The secondary command buffer doesn't know which textures etc. have been
1523 * flushed prior to their execution. Apply those flushes now.
1525 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1527 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1528 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1530 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1531 assert(!anv_batch_has_error(&secondary
->batch
));
1533 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1534 if (secondary
->state
.conditional_render_enabled
) {
1535 if (!primary
->state
.conditional_render_enabled
) {
1536 /* Secondary buffer is constructed as if it will be executed
1537 * with conditional rendering, we should satisfy this dependency
1538 * regardless of conditional rendering being enabled in primary.
1540 emit_lri(&primary
->batch
, CS_GPR(ANV_PREDICATE_RESULT_REG
), UINT32_MAX
);
1541 emit_lri(&primary
->batch
, CS_GPR(ANV_PREDICATE_RESULT_REG
) + 4, UINT32_MAX
);
1546 if (secondary
->usage_flags
&
1547 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1548 /* If we're continuing a render pass from the primary, we need to
1549 * copy the surface states for the current subpass into the storage
1550 * we allocated for them in BeginCommandBuffer.
1552 struct anv_bo
*ss_bo
=
1553 primary
->device
->surface_state_pool
.block_pool
.bo
;
1554 struct anv_state src_state
= primary
->state
.render_pass_states
;
1555 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1556 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1558 genX(cmd_buffer_so_memcpy
)(primary
,
1559 (struct anv_address
) {
1561 .offset
= dst_state
.offset
,
1563 (struct anv_address
) {
1565 .offset
= src_state
.offset
,
1567 src_state
.alloc_size
);
1570 anv_cmd_buffer_add_secondary(primary
, secondary
);
1573 /* The secondary may have selected a different pipeline (3D or compute) and
1574 * may have changed the current L3$ configuration. Reset our tracking
1575 * variables to invalid values to ensure that we re-emit these in the case
1576 * where we do any draws or compute dispatches from the primary after the
1577 * secondary has returned.
1579 primary
->state
.current_pipeline
= UINT32_MAX
;
1580 primary
->state
.current_l3_config
= NULL
;
1582 /* Each of the secondary command buffers will use its own state base
1583 * address. We need to re-emit state base address for the primary after
1584 * all of the secondaries are done.
1586 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1589 genX(cmd_buffer_emit_state_base_address
)(primary
);
1592 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1593 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1594 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1597 * Program the hardware to use the specified L3 configuration.
1600 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1601 const struct gen_l3_config
*cfg
)
1604 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1607 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1608 intel_logd("L3 config transition: ");
1609 gen_dump_l3_config(cfg
, stderr
);
1612 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1614 /* According to the hardware docs, the L3 partitioning can only be changed
1615 * while the pipeline is completely drained and the caches are flushed,
1616 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1618 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1619 pc
.DCFlushEnable
= true;
1620 pc
.PostSyncOperation
= NoWrite
;
1621 pc
.CommandStreamerStallEnable
= true;
1624 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1625 * invalidation of the relevant caches. Note that because RO invalidation
1626 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1627 * command is processed by the CS) we cannot combine it with the previous
1628 * stalling flush as the hardware documentation suggests, because that
1629 * would cause the CS to stall on previous rendering *after* RO
1630 * invalidation and wouldn't prevent the RO caches from being polluted by
1631 * concurrent rendering before the stall completes. This intentionally
1632 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1633 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1634 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1635 * already guarantee that there is no concurrent GPGPU kernel execution
1636 * (see SKL HSD 2132585).
1638 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1639 pc
.TextureCacheInvalidationEnable
= true;
1640 pc
.ConstantCacheInvalidationEnable
= true;
1641 pc
.InstructionCacheInvalidateEnable
= true;
1642 pc
.StateCacheInvalidationEnable
= true;
1643 pc
.PostSyncOperation
= NoWrite
;
1646 /* Now send a third stalling flush to make sure that invalidation is
1647 * complete when the L3 configuration registers are modified.
1649 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1650 pc
.DCFlushEnable
= true;
1651 pc
.PostSyncOperation
= NoWrite
;
1652 pc
.CommandStreamerStallEnable
= true;
1657 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1660 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1661 .SLMEnable
= has_slm
,
1663 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1664 * in L3CNTLREG register. The default setting of the bit is not the
1665 * desirable behavior.
1667 .ErrorDetectionBehaviorControl
= true,
1668 .UseFullWays
= true,
1670 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1671 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1672 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1673 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1675 /* Set up the L3 partitioning. */
1676 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1680 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1681 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1682 cfg
->n
[GEN_L3P_ALL
];
1683 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1684 cfg
->n
[GEN_L3P_ALL
];
1685 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1686 cfg
->n
[GEN_L3P_ALL
];
1688 assert(!cfg
->n
[GEN_L3P_ALL
]);
1690 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1691 * the matching space on the remaining banks has to be allocated to a
1692 * client (URB for all validated configurations) set to the
1693 * lower-bandwidth 2-bank address hashing mode.
1695 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1696 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1697 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1699 /* Minimum number of ways that can be allocated to the URB. */
1700 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1701 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1703 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1704 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1705 .ConvertDC_UC
= !has_dc
,
1706 .ConvertIS_UC
= !has_is
,
1707 .ConvertC_UC
= !has_c
,
1708 .ConvertT_UC
= !has_t
);
1710 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1711 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1712 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1714 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1715 .SLMEnable
= has_slm
,
1716 .URBLowBandwidth
= urb_low_bw
,
1717 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1719 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1721 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1722 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1724 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1725 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1726 .ISLowBandwidth
= 0,
1727 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1729 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1730 .TLowBandwidth
= 0);
1732 /* Set up the L3 partitioning. */
1733 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1734 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1735 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1738 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1739 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1740 * them disabled to avoid crashing the system hard.
1742 uint32_t scratch1
, chicken3
;
1743 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1744 .L3AtomicDisable
= !has_dc
);
1745 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1746 .L3AtomicDisableMask
= true,
1747 .L3AtomicDisable
= !has_dc
);
1748 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1749 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1755 cmd_buffer
->state
.current_l3_config
= cfg
;
1759 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1761 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1763 /* Flushes are pipelined while invalidations are handled immediately.
1764 * Therefore, if we're flushing anything then we need to schedule a stall
1765 * before any invalidations can happen.
1767 if (bits
& ANV_PIPE_FLUSH_BITS
)
1768 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1770 /* If we're going to do an invalidate and we have a pending CS stall that
1771 * has yet to be resolved, we do the CS stall now.
1773 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1774 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1775 bits
|= ANV_PIPE_CS_STALL_BIT
;
1776 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1779 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1780 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1781 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1782 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1783 pipe
.RenderTargetCacheFlushEnable
=
1784 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1786 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1787 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1788 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1791 * According to the Broadwell documentation, any PIPE_CONTROL with the
1792 * "Command Streamer Stall" bit set must also have another bit set,
1793 * with five different options:
1795 * - Render Target Cache Flush
1796 * - Depth Cache Flush
1797 * - Stall at Pixel Scoreboard
1798 * - Post-Sync Operation
1802 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1803 * mesa and it seems to work fine. The choice is fairly arbitrary.
1805 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1806 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1807 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1808 pipe
.StallAtPixelScoreboard
= true;
1811 /* If a render target flush was emitted, then we can toggle off the bit
1812 * saying that render target writes are ongoing.
1814 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1815 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1817 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1820 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1821 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1823 * "If the VF Cache Invalidation Enable is set to a 1 in a
1824 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1825 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1826 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1829 * This appears to hang Broadwell, so we restrict it to just gen9.
1831 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1832 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1834 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1835 pipe
.StateCacheInvalidationEnable
=
1836 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1837 pipe
.ConstantCacheInvalidationEnable
=
1838 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1839 pipe
.VFCacheInvalidationEnable
=
1840 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1841 pipe
.TextureCacheInvalidationEnable
=
1842 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1843 pipe
.InstructionCacheInvalidateEnable
=
1844 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1846 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1848 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1849 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1850 * “Write Timestamp”.
1852 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1853 pipe
.PostSyncOperation
= WriteImmediateData
;
1855 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1859 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1862 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1865 void genX(CmdPipelineBarrier
)(
1866 VkCommandBuffer commandBuffer
,
1867 VkPipelineStageFlags srcStageMask
,
1868 VkPipelineStageFlags destStageMask
,
1870 uint32_t memoryBarrierCount
,
1871 const VkMemoryBarrier
* pMemoryBarriers
,
1872 uint32_t bufferMemoryBarrierCount
,
1873 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1874 uint32_t imageMemoryBarrierCount
,
1875 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1877 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1879 /* XXX: Right now, we're really dumb and just flush whatever categories
1880 * the app asks for. One of these days we may make this a bit better
1881 * but right now that's all the hardware allows for in most areas.
1883 VkAccessFlags src_flags
= 0;
1884 VkAccessFlags dst_flags
= 0;
1886 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1887 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1888 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1891 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1892 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1893 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1896 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1897 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1898 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1899 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1900 const VkImageSubresourceRange
*range
=
1901 &pImageMemoryBarriers
[i
].subresourceRange
;
1903 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1904 transition_depth_buffer(cmd_buffer
, image
,
1905 pImageMemoryBarriers
[i
].oldLayout
,
1906 pImageMemoryBarriers
[i
].newLayout
);
1907 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1908 VkImageAspectFlags color_aspects
=
1909 anv_image_expand_aspects(image
, range
->aspectMask
);
1910 uint32_t aspect_bit
;
1912 uint32_t base_layer
, layer_count
;
1913 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1915 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1917 base_layer
= range
->baseArrayLayer
;
1918 layer_count
= anv_get_layerCount(image
, range
);
1921 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1922 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1923 range
->baseMipLevel
,
1924 anv_get_levelCount(image
, range
),
1925 base_layer
, layer_count
,
1926 pImageMemoryBarriers
[i
].oldLayout
,
1927 pImageMemoryBarriers
[i
].newLayout
);
1932 cmd_buffer
->state
.pending_pipe_bits
|=
1933 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1934 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1938 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1940 VkShaderStageFlags stages
=
1941 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1943 /* In order to avoid thrash, we assume that vertex and fragment stages
1944 * always exist. In the rare case where one is missing *and* the other
1945 * uses push concstants, this may be suboptimal. However, avoiding stalls
1946 * seems more important.
1948 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1950 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1954 const unsigned push_constant_kb
= 32;
1955 #elif GEN_IS_HASWELL
1956 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1958 const unsigned push_constant_kb
= 16;
1961 const unsigned num_stages
=
1962 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1963 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1965 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1966 * units of 2KB. Incidentally, these are the same platforms that have
1967 * 32KB worth of push constant space.
1969 if (push_constant_kb
== 32)
1970 size_per_stage
&= ~1u;
1972 uint32_t kb_used
= 0;
1973 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1974 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1975 anv_batch_emit(&cmd_buffer
->batch
,
1976 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1977 alloc
._3DCommandSubOpcode
= 18 + i
;
1978 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1979 alloc
.ConstantBufferSize
= push_size
;
1981 kb_used
+= push_size
;
1984 anv_batch_emit(&cmd_buffer
->batch
,
1985 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1986 alloc
.ConstantBufferOffset
= kb_used
;
1987 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1990 cmd_buffer
->state
.push_constant_stages
= stages
;
1992 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1994 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1995 * the next 3DPRIMITIVE command after programming the
1996 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1998 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1999 * pipeline setup, we need to dirty push constants.
2001 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2004 static const struct anv_descriptor
*
2005 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2006 const struct anv_pipeline_binding
*binding
)
2008 assert(binding
->set
< MAX_SETS
);
2009 const struct anv_descriptor_set
*set
=
2010 pipe_state
->descriptors
[binding
->set
];
2011 const uint32_t offset
=
2012 set
->layout
->binding
[binding
->binding
].descriptor_index
;
2013 return &set
->descriptors
[offset
+ binding
->index
];
2017 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2018 const struct anv_pipeline_binding
*binding
)
2020 assert(binding
->set
< MAX_SETS
);
2021 const struct anv_descriptor_set
*set
=
2022 pipe_state
->descriptors
[binding
->set
];
2024 uint32_t dynamic_offset_idx
=
2025 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
2026 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
2029 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
2033 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2034 gl_shader_stage stage
,
2035 struct anv_state
*bt_state
)
2037 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
2038 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2039 struct anv_cmd_pipeline_state
*pipe_state
;
2040 struct anv_pipeline
*pipeline
;
2041 uint32_t bias
, state_offset
;
2044 case MESA_SHADER_COMPUTE
:
2045 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2049 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2053 pipeline
= pipe_state
->pipeline
;
2055 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2056 *bt_state
= (struct anv_state
) { 0, };
2060 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2061 if (bias
+ map
->surface_count
== 0) {
2062 *bt_state
= (struct anv_state
) { 0, };
2066 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2067 bias
+ map
->surface_count
,
2069 uint32_t *bt_map
= bt_state
->map
;
2071 if (bt_state
->map
== NULL
)
2072 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2074 if (stage
== MESA_SHADER_COMPUTE
&&
2075 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
2076 struct anv_state surface_state
;
2078 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2080 const enum isl_format format
=
2081 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2082 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2084 cmd_buffer
->state
.compute
.num_workgroups
,
2087 bt_map
[0] = surface_state
.offset
+ state_offset
;
2088 add_surface_reloc(cmd_buffer
, surface_state
,
2089 cmd_buffer
->state
.compute
.num_workgroups
);
2092 if (map
->surface_count
== 0)
2095 /* We only use push constant space for images before gen9 */
2096 if (map
->image_count
> 0 && devinfo
->gen
< 9) {
2098 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
2099 if (result
!= VK_SUCCESS
)
2102 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2106 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2107 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2109 struct anv_state surface_state
;
2111 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2112 /* Color attachment binding */
2113 assert(stage
== MESA_SHADER_FRAGMENT
);
2114 assert(binding
->binding
== 0);
2115 if (binding
->index
< subpass
->color_count
) {
2116 const unsigned att
=
2117 subpass
->color_attachments
[binding
->index
].attachment
;
2119 /* From the Vulkan 1.0.46 spec:
2121 * "If any color or depth/stencil attachments are
2122 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2125 if (att
== VK_ATTACHMENT_UNUSED
) {
2126 surface_state
= cmd_buffer
->state
.null_surface_state
;
2128 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2131 surface_state
= cmd_buffer
->state
.null_surface_state
;
2134 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2136 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2137 struct anv_state surface_state
=
2138 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2140 struct anv_address constant_data
= {
2141 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2142 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2144 unsigned constant_data_size
=
2145 pipeline
->shaders
[stage
]->constant_data_size
;
2147 const enum isl_format format
=
2148 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2149 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2150 surface_state
, format
,
2151 constant_data
, constant_data_size
, 1);
2153 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2154 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2158 const struct anv_descriptor
*desc
=
2159 anv_descriptor_for_binding(pipe_state
, binding
);
2161 switch (desc
->type
) {
2162 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2163 /* Nothing for us to do here */
2166 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2167 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2168 struct anv_surface_state sstate
=
2169 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2170 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2171 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2172 surface_state
= sstate
.state
;
2173 assert(surface_state
.alloc_size
);
2174 add_surface_state_relocs(cmd_buffer
, sstate
);
2177 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2178 assert(stage
== MESA_SHADER_FRAGMENT
);
2179 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2180 /* For depth and stencil input attachments, we treat it like any
2181 * old texture that a user may have bound.
2183 struct anv_surface_state sstate
=
2184 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2185 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2186 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2187 surface_state
= sstate
.state
;
2188 assert(surface_state
.alloc_size
);
2189 add_surface_state_relocs(cmd_buffer
, sstate
);
2191 /* For color input attachments, we create the surface state at
2192 * vkBeginRenderPass time so that we can include aux and clear
2193 * color information.
2195 assert(binding
->input_attachment_index
< subpass
->input_count
);
2196 const unsigned subpass_att
= binding
->input_attachment_index
;
2197 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2198 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2202 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2203 struct anv_surface_state sstate
= (binding
->write_only
)
2204 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2205 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2206 surface_state
= sstate
.state
;
2207 assert(surface_state
.alloc_size
);
2208 add_surface_state_relocs(cmd_buffer
, sstate
);
2209 if (devinfo
->gen
< 9) {
2210 assert(image
< MAX_GEN8_IMAGES
);
2211 struct brw_image_param
*image_param
=
2212 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
];
2215 desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2221 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2222 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2223 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2224 surface_state
= desc
->buffer_view
->surface_state
;
2225 assert(surface_state
.alloc_size
);
2226 add_surface_reloc(cmd_buffer
, surface_state
,
2227 desc
->buffer_view
->address
);
2230 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2231 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2232 /* Compute the offset within the buffer */
2233 uint32_t dynamic_offset
=
2234 dynamic_offset_for_binding(pipe_state
, binding
);
2235 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2236 /* Clamp to the buffer size */
2237 offset
= MIN2(offset
, desc
->buffer
->size
);
2238 /* Clamp the range to the buffer size */
2239 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2241 struct anv_address address
=
2242 anv_address_add(desc
->buffer
->address
, offset
);
2245 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2246 enum isl_format format
=
2247 anv_isl_format_for_descriptor_type(desc
->type
);
2249 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2250 format
, address
, range
, 1);
2251 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2255 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2256 surface_state
= (binding
->write_only
)
2257 ? desc
->buffer_view
->writeonly_storage_surface_state
2258 : desc
->buffer_view
->storage_surface_state
;
2259 assert(surface_state
.alloc_size
);
2260 add_surface_reloc(cmd_buffer
, surface_state
,
2261 desc
->buffer_view
->address
);
2262 if (devinfo
->gen
< 9) {
2263 assert(image
< MAX_GEN8_IMAGES
);
2264 struct brw_image_param
*image_param
=
2265 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
];
2267 *image_param
= desc
->buffer_view
->storage_image_param
;
2273 assert(!"Invalid descriptor type");
2277 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2279 assert(image
== map
->image_count
);
2283 /* The PIPE_CONTROL command description says:
2285 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2286 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2287 * Target Cache Flush by enabling this bit. When render target flush
2288 * is set due to new association of BTI, PS Scoreboard Stall bit must
2289 * be set in this packet."
2291 * FINISHME: Currently we shuffle around the surface states in the binding
2292 * table based on if they are getting used or not. So, we've to do below
2293 * pipe control flush for every binding table upload. Make changes so
2294 * that we do it only when we modify render target surface states.
2296 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2297 pc
.RenderTargetCacheFlushEnable
= true;
2298 pc
.StallAtPixelScoreboard
= true;
2306 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2307 gl_shader_stage stage
,
2308 struct anv_state
*state
)
2310 struct anv_cmd_pipeline_state
*pipe_state
=
2311 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2312 &cmd_buffer
->state
.gfx
.base
;
2313 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2315 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2316 *state
= (struct anv_state
) { 0, };
2320 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2321 if (map
->sampler_count
== 0) {
2322 *state
= (struct anv_state
) { 0, };
2326 uint32_t size
= map
->sampler_count
* 16;
2327 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2329 if (state
->map
== NULL
)
2330 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2332 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2333 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2334 const struct anv_descriptor
*desc
=
2335 anv_descriptor_for_binding(pipe_state
, binding
);
2337 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2338 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2341 struct anv_sampler
*sampler
= desc
->sampler
;
2343 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2344 * happens to be zero.
2346 if (sampler
== NULL
)
2349 memcpy(state
->map
+ (s
* 16),
2350 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2357 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2359 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2361 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2362 pipeline
->active_stages
;
2364 VkResult result
= VK_SUCCESS
;
2365 anv_foreach_stage(s
, dirty
) {
2366 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2367 if (result
!= VK_SUCCESS
)
2369 result
= emit_binding_table(cmd_buffer
, s
,
2370 &cmd_buffer
->state
.binding_tables
[s
]);
2371 if (result
!= VK_SUCCESS
)
2375 if (result
!= VK_SUCCESS
) {
2376 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2378 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2379 if (result
!= VK_SUCCESS
)
2382 /* Re-emit state base addresses so we get the new surface state base
2383 * address before we start emitting binding tables etc.
2385 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2387 /* Re-emit all active binding tables */
2388 dirty
|= pipeline
->active_stages
;
2389 anv_foreach_stage(s
, dirty
) {
2390 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2391 if (result
!= VK_SUCCESS
) {
2392 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2395 result
= emit_binding_table(cmd_buffer
, s
,
2396 &cmd_buffer
->state
.binding_tables
[s
]);
2397 if (result
!= VK_SUCCESS
) {
2398 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2404 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2410 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2413 static const uint32_t sampler_state_opcodes
[] = {
2414 [MESA_SHADER_VERTEX
] = 43,
2415 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2416 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2417 [MESA_SHADER_GEOMETRY
] = 46,
2418 [MESA_SHADER_FRAGMENT
] = 47,
2419 [MESA_SHADER_COMPUTE
] = 0,
2422 static const uint32_t binding_table_opcodes
[] = {
2423 [MESA_SHADER_VERTEX
] = 38,
2424 [MESA_SHADER_TESS_CTRL
] = 39,
2425 [MESA_SHADER_TESS_EVAL
] = 40,
2426 [MESA_SHADER_GEOMETRY
] = 41,
2427 [MESA_SHADER_FRAGMENT
] = 42,
2428 [MESA_SHADER_COMPUTE
] = 0,
2431 anv_foreach_stage(s
, stages
) {
2432 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2433 assert(binding_table_opcodes
[s
] > 0);
2435 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2436 anv_batch_emit(&cmd_buffer
->batch
,
2437 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2438 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2439 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2443 /* Always emit binding table pointers if we're asked to, since on SKL
2444 * this is what flushes push constants. */
2445 anv_batch_emit(&cmd_buffer
->batch
,
2446 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2447 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2448 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2454 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2455 VkShaderStageFlags dirty_stages
)
2457 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2458 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2460 static const uint32_t push_constant_opcodes
[] = {
2461 [MESA_SHADER_VERTEX
] = 21,
2462 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2463 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2464 [MESA_SHADER_GEOMETRY
] = 22,
2465 [MESA_SHADER_FRAGMENT
] = 23,
2466 [MESA_SHADER_COMPUTE
] = 0,
2469 VkShaderStageFlags flushed
= 0;
2471 anv_foreach_stage(stage
, dirty_stages
) {
2472 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2473 assert(push_constant_opcodes
[stage
] > 0);
2475 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2476 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2478 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2479 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2480 const struct brw_stage_prog_data
*prog_data
=
2481 pipeline
->shaders
[stage
]->prog_data
;
2482 const struct anv_pipeline_bind_map
*bind_map
=
2483 &pipeline
->shaders
[stage
]->bind_map
;
2485 /* The Skylake PRM contains the following restriction:
2487 * "The driver must ensure The following case does not occur
2488 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2489 * buffer 3 read length equal to zero committed followed by a
2490 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2493 * To avoid this, we program the buffers in the highest slots.
2494 * This way, slot 0 is only used if slot 3 is also used.
2498 for (int i
= 3; i
>= 0; i
--) {
2499 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2500 if (range
->length
== 0)
2503 const unsigned surface
=
2504 prog_data
->binding_table
.ubo_start
+ range
->block
;
2506 assert(surface
<= bind_map
->surface_count
);
2507 const struct anv_pipeline_binding
*binding
=
2508 &bind_map
->surface_to_descriptor
[surface
];
2510 struct anv_address read_addr
;
2512 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2513 struct anv_address constant_data
= {
2514 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2515 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2517 unsigned constant_data_size
=
2518 pipeline
->shaders
[stage
]->constant_data_size
;
2520 read_len
= MIN2(range
->length
,
2521 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2522 read_addr
= anv_address_add(constant_data
,
2525 const struct anv_descriptor
*desc
=
2526 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2528 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2529 read_len
= MIN2(range
->length
,
2530 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2531 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2534 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2536 uint32_t dynamic_offset
=
2537 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2538 uint32_t buf_offset
=
2539 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2540 uint32_t buf_range
=
2541 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2543 read_len
= MIN2(range
->length
,
2544 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2545 read_addr
= anv_address_add(desc
->buffer
->address
,
2546 buf_offset
+ range
->start
* 32);
2551 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2552 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2557 struct anv_state state
=
2558 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2560 if (state
.alloc_size
> 0) {
2561 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2562 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2563 .offset
= state
.offset
,
2565 c
.ConstantBody
.ReadLength
[n
] =
2566 DIV_ROUND_UP(state
.alloc_size
, 32);
2569 /* For Ivy Bridge, the push constants packets have a different
2570 * rule that would require us to iterate in the other direction
2571 * and possibly mess around with dynamic state base address.
2572 * Don't bother; just emit regular push constants at n = 0.
2574 struct anv_state state
=
2575 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2577 if (state
.alloc_size
> 0) {
2578 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2579 c
.ConstantBody
.ReadLength
[0] =
2580 DIV_ROUND_UP(state
.alloc_size
, 32);
2586 flushed
|= mesa_to_vk_shader_stage(stage
);
2589 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2593 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2595 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2598 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2599 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2600 vb_emit
|= pipeline
->vb_used
;
2602 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2604 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2606 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2609 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2610 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2612 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2613 GENX(3DSTATE_VERTEX_BUFFERS
));
2615 for_each_bit(vb
, vb_emit
) {
2616 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2617 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2619 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2620 .VertexBufferIndex
= vb
,
2622 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2624 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2625 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2628 .AddressModifyEnable
= true,
2629 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2630 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2633 .BufferSize
= buffer
->size
- offset
2635 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2639 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2644 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2647 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2648 /* We don't need any per-buffer dirty tracking because you're not
2649 * allowed to bind different XFB buffers while XFB is enabled.
2651 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2652 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2653 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2654 sob
.SOBufferIndex
= idx
;
2656 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
) {
2657 sob
.SOBufferEnable
= true;
2658 sob
.MOCS
= cmd_buffer
->device
->default_mocs
,
2659 sob
.StreamOffsetWriteEnable
= false;
2660 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2662 /* Size is in DWords - 1 */
2663 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2668 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2670 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2674 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2675 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2677 /* The exact descriptor layout is pulled from the pipeline, so we need
2678 * to re-emit binding tables on every pipeline change.
2680 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2682 /* If the pipeline changed, we may need to re-allocate push constant
2685 cmd_buffer_alloc_push_constants(cmd_buffer
);
2689 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2690 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2691 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2693 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2694 * stall needs to be sent just prior to any 3DSTATE_VS,
2695 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2696 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2697 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2698 * PIPE_CONTROL needs to be sent before any combination of VS
2699 * associated 3DSTATE."
2701 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2702 pc
.DepthStallEnable
= true;
2703 pc
.PostSyncOperation
= WriteImmediateData
;
2705 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2710 /* Render targets live in the same binding table as fragment descriptors */
2711 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2712 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2714 /* We emit the binding tables and sampler tables first, then emit push
2715 * constants and then finally emit binding table and sampler table
2716 * pointers. It has to happen in this order, since emitting the binding
2717 * tables may change the push constants (in case of storage images). After
2718 * emitting push constants, on SKL+ we have to emit the corresponding
2719 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2722 if (cmd_buffer
->state
.descriptors_dirty
)
2723 dirty
= flush_descriptor_sets(cmd_buffer
);
2725 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2726 /* Because we're pushing UBOs, we have to push whenever either
2727 * descriptors or push constants is dirty.
2729 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2730 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2731 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2735 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2737 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2738 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2740 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2741 ANV_CMD_DIRTY_PIPELINE
)) {
2742 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2743 pipeline
->depth_clamp_enable
);
2746 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2747 ANV_CMD_DIRTY_RENDER_TARGETS
))
2748 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2750 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2752 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2756 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2757 struct anv_address addr
,
2758 uint32_t size
, uint32_t index
)
2760 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2761 GENX(3DSTATE_VERTEX_BUFFERS
));
2763 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2764 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2765 .VertexBufferIndex
= index
,
2766 .AddressModifyEnable
= true,
2768 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2770 .BufferStartingAddress
= addr
,
2773 .BufferStartingAddress
= addr
,
2774 .EndAddress
= anv_address_add(addr
, size
),
2780 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2781 struct anv_address addr
)
2783 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2787 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2788 uint32_t base_vertex
, uint32_t base_instance
)
2790 struct anv_state id_state
=
2791 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2793 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2794 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2796 struct anv_address addr
= {
2797 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2798 .offset
= id_state
.offset
,
2801 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2805 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2807 struct anv_state state
=
2808 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2810 ((uint32_t *)state
.map
)[0] = draw_index
;
2812 struct anv_address addr
= {
2813 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2814 .offset
= state
.offset
,
2817 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2821 VkCommandBuffer commandBuffer
,
2822 uint32_t vertexCount
,
2823 uint32_t instanceCount
,
2824 uint32_t firstVertex
,
2825 uint32_t firstInstance
)
2827 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2828 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2829 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2831 if (anv_batch_has_error(&cmd_buffer
->batch
))
2834 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2836 if (cmd_buffer
->state
.conditional_render_enabled
)
2837 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2839 if (vs_prog_data
->uses_firstvertex
||
2840 vs_prog_data
->uses_baseinstance
)
2841 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2842 if (vs_prog_data
->uses_drawid
)
2843 emit_draw_index(cmd_buffer
, 0);
2845 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2846 * different views. We need to multiply instanceCount by the view count.
2848 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2850 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2851 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2852 prim
.VertexAccessType
= SEQUENTIAL
;
2853 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2854 prim
.VertexCountPerInstance
= vertexCount
;
2855 prim
.StartVertexLocation
= firstVertex
;
2856 prim
.InstanceCount
= instanceCount
;
2857 prim
.StartInstanceLocation
= firstInstance
;
2858 prim
.BaseVertexLocation
= 0;
2862 void genX(CmdDrawIndexed
)(
2863 VkCommandBuffer commandBuffer
,
2864 uint32_t indexCount
,
2865 uint32_t instanceCount
,
2866 uint32_t firstIndex
,
2867 int32_t vertexOffset
,
2868 uint32_t firstInstance
)
2870 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2871 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2872 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2874 if (anv_batch_has_error(&cmd_buffer
->batch
))
2877 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2879 if (cmd_buffer
->state
.conditional_render_enabled
)
2880 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2882 if (vs_prog_data
->uses_firstvertex
||
2883 vs_prog_data
->uses_baseinstance
)
2884 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2885 if (vs_prog_data
->uses_drawid
)
2886 emit_draw_index(cmd_buffer
, 0);
2888 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2889 * different views. We need to multiply instanceCount by the view count.
2891 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2893 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2894 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2895 prim
.VertexAccessType
= RANDOM
;
2896 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2897 prim
.VertexCountPerInstance
= indexCount
;
2898 prim
.StartVertexLocation
= firstIndex
;
2899 prim
.InstanceCount
= instanceCount
;
2900 prim
.StartInstanceLocation
= firstInstance
;
2901 prim
.BaseVertexLocation
= vertexOffset
;
2905 /* Auto-Draw / Indirect Registers */
2906 #define GEN7_3DPRIM_END_OFFSET 0x2420
2907 #define GEN7_3DPRIM_START_VERTEX 0x2430
2908 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2909 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2910 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2911 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2913 /* MI_MATH only exists on Haswell+ */
2914 #if GEN_IS_HASWELL || GEN_GEN >= 8
2916 /* Emit dwords to multiply GPR0 by N */
2918 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2920 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2922 #define append_alu(opcode, operand1, operand2) \
2923 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2926 unsigned top_bit
= 31 - __builtin_clz(N
);
2927 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2928 /* We get our initial data in GPR0 and we write the final data out to
2929 * GPR0 but we use GPR1 as our scratch register.
2931 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2932 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2934 /* Shift the current value left by 1 */
2935 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2936 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2937 append_alu(MI_ALU_ADD
, 0, 0);
2940 /* Store ACCU to R1 and add R0 to R1 */
2941 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2942 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2943 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2944 append_alu(MI_ALU_ADD
, 0, 0);
2947 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2954 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2956 uint32_t num_dwords
;
2957 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2959 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2960 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2964 emit_alu_add(struct anv_batch
*batch
, unsigned dst_reg
,
2965 unsigned reg_a
, unsigned reg_b
)
2967 uint32_t *dw
= anv_batch_emitn(batch
, 1 + 4, GENX(MI_MATH
));
2968 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, reg_a
);
2969 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, reg_b
);
2970 dw
[3] = mi_alu(MI_ALU_ADD
, 0, 0);
2971 dw
[4] = mi_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2975 emit_add32_gpr0(struct anv_batch
*batch
, uint32_t N
)
2977 emit_lri(batch
, CS_GPR(1), N
);
2978 emit_alu_add(batch
, MI_ALU_REG0
, MI_ALU_REG0
, MI_ALU_REG1
);
2982 emit_alu_shl(struct anv_batch
*batch
, unsigned dst_reg
,
2983 unsigned src_reg
, unsigned shift
)
2987 uint32_t *dw
= anv_batch_emitn(batch
, 1 + 4 * shift
, GENX(MI_MATH
));
2988 for (unsigned i
= 0; i
< shift
; i
++) {
2989 unsigned add_src
= (i
== 0) ? src_reg
: dst_reg
;
2990 dw
[1 + (i
* 4) + 0] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, add_src
);
2991 dw
[1 + (i
* 4) + 1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, add_src
);
2992 dw
[1 + (i
* 4) + 2] = mi_alu(MI_ALU_ADD
, 0, 0);
2993 dw
[1 + (i
* 4) + 3] = mi_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2998 emit_div32_gpr0(struct anv_batch
*batch
, uint32_t D
)
3000 /* Zero out the top of GPR0 */
3001 emit_lri(batch
, CS_GPR(0) + 4, 0);
3004 /* This invalid, but we should do something so we set GPR0 to 0. */
3005 emit_lri(batch
, CS_GPR(0), 0);
3006 } else if (util_is_power_of_two_or_zero(D
)) {
3007 unsigned log2_D
= util_logbase2(D
);
3008 assert(log2_D
< 32);
3009 /* We right-shift by log2(D) by left-shifting by 32 - log2(D) and taking
3010 * the top 32 bits of the result.
3012 emit_alu_shl(batch
, MI_ALU_REG0
, MI_ALU_REG0
, 32 - log2_D
);
3013 emit_lrr(batch
, CS_GPR(0) + 0, CS_GPR(0) + 4);
3014 emit_lri(batch
, CS_GPR(0) + 4, 0);
3016 struct util_fast_udiv_info m
= util_compute_fast_udiv_info(D
, 32, 32);
3017 assert(m
.multiplier
<= UINT32_MAX
);
3020 /* We right-shift by L by left-shifting by 32 - l and taking the top
3021 * 32 bits of the result.
3023 if (m
.pre_shift
< 32)
3024 emit_alu_shl(batch
, MI_ALU_REG0
, MI_ALU_REG0
, 32 - m
.pre_shift
);
3025 emit_lrr(batch
, CS_GPR(0) + 0, CS_GPR(0) + 4);
3026 emit_lri(batch
, CS_GPR(0) + 4, 0);
3029 /* Do the 32x32 multiply into gpr0 */
3030 emit_mul_gpr0(batch
, m
.multiplier
);
3033 /* If we need to increment, save off a copy of GPR0 */
3034 emit_lri(batch
, CS_GPR(1) + 0, m
.multiplier
);
3035 emit_lri(batch
, CS_GPR(1) + 4, 0);
3036 emit_alu_add(batch
, MI_ALU_REG0
, MI_ALU_REG0
, MI_ALU_REG1
);
3040 emit_lrr(batch
, CS_GPR(0) + 0, CS_GPR(0) + 4);
3041 emit_lri(batch
, CS_GPR(0) + 4, 0);
3044 /* We right-shift by L by left-shifting by 32 - l and taking the top
3045 * 32 bits of the result.
3047 if (m
.post_shift
< 32)
3048 emit_alu_shl(batch
, MI_ALU_REG0
, MI_ALU_REG0
, 32 - m
.post_shift
);
3049 emit_lrr(batch
, CS_GPR(0) + 0, CS_GPR(0) + 4);
3050 emit_lri(batch
, CS_GPR(0) + 4, 0);
3055 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3057 void genX(CmdDrawIndirectByteCountEXT
)(
3058 VkCommandBuffer commandBuffer
,
3059 uint32_t instanceCount
,
3060 uint32_t firstInstance
,
3061 VkBuffer counterBuffer
,
3062 VkDeviceSize counterBufferOffset
,
3063 uint32_t counterOffset
,
3064 uint32_t vertexStride
)
3066 #if GEN_IS_HASWELL || GEN_GEN >= 8
3067 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3068 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3069 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3070 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3072 /* firstVertex is always zero for this draw function */
3073 const uint32_t firstVertex
= 0;
3075 if (anv_batch_has_error(&cmd_buffer
->batch
))
3078 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3080 if (vs_prog_data
->uses_firstvertex
||
3081 vs_prog_data
->uses_baseinstance
)
3082 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3083 if (vs_prog_data
->uses_drawid
)
3084 emit_draw_index(cmd_buffer
, 0);
3086 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3087 * different views. We need to multiply instanceCount by the view count.
3089 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3091 emit_lrm(&cmd_buffer
->batch
, CS_GPR(0),
3092 anv_address_add(counter_buffer
->address
, counterBufferOffset
));
3094 emit_add32_gpr0(&cmd_buffer
->batch
, -counterOffset
);
3095 emit_div32_gpr0(&cmd_buffer
->batch
, vertexStride
);
3096 emit_lrr(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, CS_GPR(0));
3098 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, firstVertex
);
3099 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, instanceCount
);
3100 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, firstInstance
);
3101 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
3103 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3104 prim
.IndirectParameterEnable
= true;
3105 prim
.VertexAccessType
= SEQUENTIAL
;
3106 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3108 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3112 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3113 struct anv_address addr
,
3116 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3118 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, anv_address_add(addr
, 0));
3120 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3121 if (view_count
> 1) {
3122 #if GEN_IS_HASWELL || GEN_GEN >= 8
3123 emit_lrm(batch
, CS_GPR(0), anv_address_add(addr
, 4));
3124 emit_mul_gpr0(batch
, view_count
);
3125 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
3127 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3128 "MI_MATH is not supported on Ivy Bridge");
3129 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
3132 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
3135 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, anv_address_add(addr
, 8));
3138 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, anv_address_add(addr
, 12));
3139 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 16));
3141 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 12));
3142 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
3146 void genX(CmdDrawIndirect
)(
3147 VkCommandBuffer commandBuffer
,
3149 VkDeviceSize offset
,
3153 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3154 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3155 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3156 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3158 if (anv_batch_has_error(&cmd_buffer
->batch
))
3161 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3163 if (cmd_buffer
->state
.conditional_render_enabled
)
3164 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3166 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3167 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3169 if (vs_prog_data
->uses_firstvertex
||
3170 vs_prog_data
->uses_baseinstance
)
3171 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3172 if (vs_prog_data
->uses_drawid
)
3173 emit_draw_index(cmd_buffer
, i
);
3175 load_indirect_parameters(cmd_buffer
, draw
, false);
3177 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3178 prim
.IndirectParameterEnable
= true;
3179 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3180 prim
.VertexAccessType
= SEQUENTIAL
;
3181 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3188 void genX(CmdDrawIndexedIndirect
)(
3189 VkCommandBuffer commandBuffer
,
3191 VkDeviceSize offset
,
3195 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3196 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3197 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3198 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3200 if (anv_batch_has_error(&cmd_buffer
->batch
))
3203 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3205 if (cmd_buffer
->state
.conditional_render_enabled
)
3206 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3208 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3209 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3211 /* TODO: We need to stomp base vertex to 0 somehow */
3212 if (vs_prog_data
->uses_firstvertex
||
3213 vs_prog_data
->uses_baseinstance
)
3214 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3215 if (vs_prog_data
->uses_drawid
)
3216 emit_draw_index(cmd_buffer
, i
);
3218 load_indirect_parameters(cmd_buffer
, draw
, true);
3220 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3221 prim
.IndirectParameterEnable
= true;
3222 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3223 prim
.VertexAccessType
= RANDOM
;
3224 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3231 #define TMP_DRAW_COUNT_REG MI_ALU_REG14
3234 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3235 struct anv_address count_address
,
3236 const bool conditional_render_enabled
)
3238 if (conditional_render_enabled
) {
3239 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3240 emit_lrm(&cmd_buffer
->batch
, CS_GPR(TMP_DRAW_COUNT_REG
), count_address
);
3241 emit_lri(&cmd_buffer
->batch
, CS_GPR(TMP_DRAW_COUNT_REG
) + 4, 0);
3244 /* Upload the current draw count from the draw parameters buffer to
3245 * MI_PREDICATE_SRC0.
3247 emit_lrm(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, count_address
);
3248 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
3250 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
3255 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3256 uint32_t draw_index
)
3258 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3259 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, draw_index
);
3261 if (draw_index
== 0) {
3262 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3263 mip
.LoadOperation
= LOAD_LOADINV
;
3264 mip
.CombineOperation
= COMBINE_SET
;
3265 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3268 /* While draw_index < draw_count the predicate's result will be
3269 * (draw_index == draw_count) ^ TRUE = TRUE
3270 * When draw_index == draw_count the result is
3271 * (TRUE) ^ TRUE = FALSE
3272 * After this all results will be:
3273 * (FALSE) ^ FALSE = FALSE
3275 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3276 mip
.LoadOperation
= LOAD_LOAD
;
3277 mip
.CombineOperation
= COMBINE_XOR
;
3278 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3283 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3285 emit_draw_count_predicate_with_conditional_render(
3286 struct anv_cmd_buffer
*cmd_buffer
,
3287 uint32_t draw_index
)
3289 const int draw_index_reg
= MI_ALU_REG0
;
3290 const int tmp_result_reg
= MI_ALU_REG1
;
3292 emit_lri(&cmd_buffer
->batch
, CS_GPR(draw_index_reg
), draw_index
);
3293 emit_lri(&cmd_buffer
->batch
, CS_GPR(draw_index_reg
) + 4, 0);
3296 /* Compute (draw_index < draw_count).
3297 * We do this by subtracting and storing the carry bit.
3299 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 9, GENX(MI_MATH
));
3300 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, draw_index_reg
);
3301 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, TMP_DRAW_COUNT_REG
);
3302 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
3303 dw
[4] = mi_alu(MI_ALU_STORE
, tmp_result_reg
, MI_ALU_CF
);
3305 dw
[5] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, tmp_result_reg
);
3306 dw
[6] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, ANV_PREDICATE_RESULT_REG
);
3307 dw
[7] = mi_alu(MI_ALU_AND
, 0, 0);
3308 dw
[8] = mi_alu(MI_ALU_STORE
, tmp_result_reg
, MI_ALU_ACCU
);
3311 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_RESULT
, CS_GPR(tmp_result_reg
));
3313 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3314 * so we emit MI_PREDICATE to set it.
3317 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(tmp_result_reg
));
3318 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
3319 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
3320 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
3322 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3323 mip
.LoadOperation
= LOAD_LOADINV
;
3324 mip
.CombineOperation
= COMBINE_SET
;
3325 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3331 void genX(CmdDrawIndirectCountKHR
)(
3332 VkCommandBuffer commandBuffer
,
3334 VkDeviceSize offset
,
3335 VkBuffer _countBuffer
,
3336 VkDeviceSize countBufferOffset
,
3337 uint32_t maxDrawCount
,
3340 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3341 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3342 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3343 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3344 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3345 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3347 if (anv_batch_has_error(&cmd_buffer
->batch
))
3350 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3352 struct anv_address count_address
=
3353 anv_address_add(count_buffer
->address
, countBufferOffset
);
3355 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3356 cmd_state
->conditional_render_enabled
);
3358 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3359 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3361 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3362 if (cmd_state
->conditional_render_enabled
) {
3363 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3365 emit_draw_count_predicate(cmd_buffer
, i
);
3368 emit_draw_count_predicate(cmd_buffer
, i
);
3371 if (vs_prog_data
->uses_firstvertex
||
3372 vs_prog_data
->uses_baseinstance
)
3373 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3374 if (vs_prog_data
->uses_drawid
)
3375 emit_draw_index(cmd_buffer
, i
);
3377 load_indirect_parameters(cmd_buffer
, draw
, false);
3379 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3380 prim
.IndirectParameterEnable
= true;
3381 prim
.PredicateEnable
= true;
3382 prim
.VertexAccessType
= SEQUENTIAL
;
3383 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3390 void genX(CmdDrawIndexedIndirectCountKHR
)(
3391 VkCommandBuffer commandBuffer
,
3393 VkDeviceSize offset
,
3394 VkBuffer _countBuffer
,
3395 VkDeviceSize countBufferOffset
,
3396 uint32_t maxDrawCount
,
3399 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3400 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3401 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3402 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3403 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3404 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3406 if (anv_batch_has_error(&cmd_buffer
->batch
))
3409 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3411 struct anv_address count_address
=
3412 anv_address_add(count_buffer
->address
, countBufferOffset
);
3414 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3415 cmd_state
->conditional_render_enabled
);
3417 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3418 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3420 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3421 if (cmd_state
->conditional_render_enabled
) {
3422 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3424 emit_draw_count_predicate(cmd_buffer
, i
);
3427 emit_draw_count_predicate(cmd_buffer
, i
);
3430 /* TODO: We need to stomp base vertex to 0 somehow */
3431 if (vs_prog_data
->uses_firstvertex
||
3432 vs_prog_data
->uses_baseinstance
)
3433 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3434 if (vs_prog_data
->uses_drawid
)
3435 emit_draw_index(cmd_buffer
, i
);
3437 load_indirect_parameters(cmd_buffer
, draw
, true);
3439 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3440 prim
.IndirectParameterEnable
= true;
3441 prim
.PredicateEnable
= true;
3442 prim
.VertexAccessType
= RANDOM
;
3443 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3450 void genX(CmdBeginTransformFeedbackEXT
)(
3451 VkCommandBuffer commandBuffer
,
3452 uint32_t firstCounterBuffer
,
3453 uint32_t counterBufferCount
,
3454 const VkBuffer
* pCounterBuffers
,
3455 const VkDeviceSize
* pCounterBufferOffsets
)
3457 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3459 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3460 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3461 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3463 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3465 * "Ssoftware must ensure that no HW stream output operations can be in
3466 * process or otherwise pending at the point that the MI_LOAD/STORE
3467 * commands are processed. This will likely require a pipeline flush."
3469 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3470 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3472 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3473 /* If we have a counter buffer, this is a resume so we need to load the
3474 * value into the streamout offset register. Otherwise, this is a begin
3475 * and we need to reset it to zero.
3477 if (pCounterBuffers
&&
3478 idx
>= firstCounterBuffer
&&
3479 idx
- firstCounterBuffer
< counterBufferCount
&&
3480 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3481 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3482 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3483 uint64_t offset
= pCounterBufferOffsets
?
3484 pCounterBufferOffsets
[cb_idx
] : 0;
3486 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3487 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3488 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3492 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3493 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3499 cmd_buffer
->state
.xfb_enabled
= true;
3500 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3503 void genX(CmdEndTransformFeedbackEXT
)(
3504 VkCommandBuffer commandBuffer
,
3505 uint32_t firstCounterBuffer
,
3506 uint32_t counterBufferCount
,
3507 const VkBuffer
* pCounterBuffers
,
3508 const VkDeviceSize
* pCounterBufferOffsets
)
3510 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3512 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3513 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3514 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3516 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3518 * "Ssoftware must ensure that no HW stream output operations can be in
3519 * process or otherwise pending at the point that the MI_LOAD/STORE
3520 * commands are processed. This will likely require a pipeline flush."
3522 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3523 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3525 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3526 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3528 /* If we have a counter buffer, this is a resume so we need to load the
3529 * value into the streamout offset register. Otherwise, this is a begin
3530 * and we need to reset it to zero.
3532 if (pCounterBuffers
&&
3533 cb_idx
< counterBufferCount
&&
3534 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3535 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3536 uint64_t offset
= pCounterBufferOffsets
?
3537 pCounterBufferOffsets
[cb_idx
] : 0;
3539 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3540 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3542 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3547 cmd_buffer
->state
.xfb_enabled
= false;
3548 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3552 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3554 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3555 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3558 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3559 if (result
!= VK_SUCCESS
) {
3560 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3562 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3563 if (result
!= VK_SUCCESS
)
3566 /* Re-emit state base addresses so we get the new surface state base
3567 * address before we start emitting binding tables etc.
3569 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3571 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3572 if (result
!= VK_SUCCESS
) {
3573 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3578 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3579 if (result
!= VK_SUCCESS
) {
3580 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3584 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3585 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3586 .BindingTablePointer
= surfaces
.offset
,
3587 .SamplerStatePointer
= samplers
.offset
,
3589 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3591 struct anv_state state
=
3592 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3593 pipeline
->interface_descriptor_data
,
3594 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3597 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3598 anv_batch_emit(&cmd_buffer
->batch
,
3599 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3600 mid
.InterfaceDescriptorTotalLength
= size
;
3601 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3608 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3610 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3611 MAYBE_UNUSED VkResult result
;
3613 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3615 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3617 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3619 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3620 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3622 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3623 * the only bits that are changed are scoreboard related: Scoreboard
3624 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3625 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3628 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3629 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3631 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3634 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3635 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3636 /* FIXME: figure out descriptors for gen7 */
3637 result
= flush_compute_descriptor_set(cmd_buffer
);
3638 if (result
!= VK_SUCCESS
)
3641 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3644 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3645 struct anv_state push_state
=
3646 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3648 if (push_state
.alloc_size
) {
3649 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3650 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3651 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3655 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3658 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3660 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3666 verify_cmd_parser(const struct anv_device
*device
,
3667 int required_version
,
3668 const char *function
)
3670 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3671 return vk_errorf(device
->instance
, device
->instance
,
3672 VK_ERROR_FEATURE_NOT_PRESENT
,
3673 "cmd parser version %d is required for %s",
3674 required_version
, function
);
3683 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3684 uint32_t baseGroupX
,
3685 uint32_t baseGroupY
,
3686 uint32_t baseGroupZ
)
3688 if (anv_batch_has_error(&cmd_buffer
->batch
))
3692 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3693 base_work_group_id
);
3694 if (result
!= VK_SUCCESS
) {
3695 cmd_buffer
->batch
.status
= result
;
3699 struct anv_push_constants
*push
=
3700 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3701 if (push
->base_work_group_id
[0] != baseGroupX
||
3702 push
->base_work_group_id
[1] != baseGroupY
||
3703 push
->base_work_group_id
[2] != baseGroupZ
) {
3704 push
->base_work_group_id
[0] = baseGroupX
;
3705 push
->base_work_group_id
[1] = baseGroupY
;
3706 push
->base_work_group_id
[2] = baseGroupZ
;
3708 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3712 void genX(CmdDispatch
)(
3713 VkCommandBuffer commandBuffer
,
3718 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3721 void genX(CmdDispatchBase
)(
3722 VkCommandBuffer commandBuffer
,
3723 uint32_t baseGroupX
,
3724 uint32_t baseGroupY
,
3725 uint32_t baseGroupZ
,
3726 uint32_t groupCountX
,
3727 uint32_t groupCountY
,
3728 uint32_t groupCountZ
)
3730 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3731 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3732 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3734 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3735 baseGroupY
, baseGroupZ
);
3737 if (anv_batch_has_error(&cmd_buffer
->batch
))
3740 if (prog_data
->uses_num_work_groups
) {
3741 struct anv_state state
=
3742 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3743 uint32_t *sizes
= state
.map
;
3744 sizes
[0] = groupCountX
;
3745 sizes
[1] = groupCountY
;
3746 sizes
[2] = groupCountZ
;
3747 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3748 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3749 .offset
= state
.offset
,
3753 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3755 if (cmd_buffer
->state
.conditional_render_enabled
)
3756 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3758 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3759 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3760 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3761 ggw
.ThreadDepthCounterMaximum
= 0;
3762 ggw
.ThreadHeightCounterMaximum
= 0;
3763 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3764 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3765 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3766 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3767 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3768 ggw
.BottomExecutionMask
= 0xffffffff;
3771 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3774 #define GPGPU_DISPATCHDIMX 0x2500
3775 #define GPGPU_DISPATCHDIMY 0x2504
3776 #define GPGPU_DISPATCHDIMZ 0x2508
3778 void genX(CmdDispatchIndirect
)(
3779 VkCommandBuffer commandBuffer
,
3781 VkDeviceSize offset
)
3783 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3784 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3785 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3786 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3787 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3788 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3790 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3793 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3794 * indirect dispatch registers to be written.
3796 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3797 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3801 if (prog_data
->uses_num_work_groups
)
3802 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3804 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3806 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, anv_address_add(addr
, 0));
3807 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, anv_address_add(addr
, 4));
3808 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, anv_address_add(addr
, 8));
3811 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3812 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3813 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3814 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3816 /* Load compute_dispatch_indirect_x_size into SRC0 */
3817 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 0));
3819 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3820 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3821 mip
.LoadOperation
= LOAD_LOAD
;
3822 mip
.CombineOperation
= COMBINE_SET
;
3823 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3826 /* Load compute_dispatch_indirect_y_size into SRC0 */
3827 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 4));
3829 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3830 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3831 mip
.LoadOperation
= LOAD_LOAD
;
3832 mip
.CombineOperation
= COMBINE_OR
;
3833 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3836 /* Load compute_dispatch_indirect_z_size into SRC0 */
3837 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 8));
3839 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3840 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3841 mip
.LoadOperation
= LOAD_LOAD
;
3842 mip
.CombineOperation
= COMBINE_OR
;
3843 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3846 /* predicate = !predicate; */
3847 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3848 mip
.LoadOperation
= LOAD_LOADINV
;
3849 mip
.CombineOperation
= COMBINE_OR
;
3850 mip
.CompareOperation
= COMPARE_FALSE
;
3854 if (cmd_buffer
->state
.conditional_render_enabled
) {
3855 emit_lrr(batch
, MI_PREDICATE_SRC0
, CS_GPR(ANV_PREDICATE_RESULT_REG
));
3856 /* predicate &= !(conditional_rendering_predicate == 0); */
3857 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3858 mip
.LoadOperation
= LOAD_LOADINV
;
3859 mip
.CombineOperation
= COMBINE_AND
;
3860 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3865 #else /* GEN_GEN > 7 */
3866 if (cmd_buffer
->state
.conditional_render_enabled
)
3867 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3870 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3871 ggw
.IndirectParameterEnable
= true;
3872 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3873 cmd_buffer
->state
.conditional_render_enabled
;
3874 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3875 ggw
.ThreadDepthCounterMaximum
= 0;
3876 ggw
.ThreadHeightCounterMaximum
= 0;
3877 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3878 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3879 ggw
.BottomExecutionMask
= 0xffffffff;
3882 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3886 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3889 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3891 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3894 #if GEN_GEN >= 8 && GEN_GEN < 10
3895 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3897 * Software must clear the COLOR_CALC_STATE Valid field in
3898 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3899 * with Pipeline Select set to GPGPU.
3901 * The internal hardware docs recommend the same workaround for Gen9
3904 if (pipeline
== GPGPU
)
3905 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3908 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3909 * PIPELINE_SELECT [DevBWR+]":
3913 * Software must ensure all the write caches are flushed through a
3914 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3915 * command to invalidate read only caches prior to programming
3916 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3918 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3919 pc
.RenderTargetCacheFlushEnable
= true;
3920 pc
.DepthCacheFlushEnable
= true;
3921 pc
.DCFlushEnable
= true;
3922 pc
.PostSyncOperation
= NoWrite
;
3923 pc
.CommandStreamerStallEnable
= true;
3926 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3927 pc
.TextureCacheInvalidationEnable
= true;
3928 pc
.ConstantCacheInvalidationEnable
= true;
3929 pc
.StateCacheInvalidationEnable
= true;
3930 pc
.InstructionCacheInvalidateEnable
= true;
3931 pc
.PostSyncOperation
= NoWrite
;
3934 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3938 ps
.PipelineSelection
= pipeline
;
3942 if (devinfo
->is_geminilake
) {
3945 * "This chicken bit works around a hardware issue with barrier logic
3946 * encountered when switching between GPGPU and 3D pipelines. To
3947 * workaround the issue, this mode bit should be set after a pipeline
3951 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3953 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3954 : GLK_BARRIER_MODE_3D_HULL
,
3955 .GLKBarrierModeMask
= 1);
3956 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3960 cmd_buffer
->state
.current_pipeline
= pipeline
;
3964 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3966 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3970 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3972 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3976 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3981 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3983 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3984 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3985 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3986 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3987 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3988 * Depth Flush Bit set, followed by another pipelined depth stall
3989 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3990 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3991 * via a preceding MI_FLUSH)."
3993 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3994 pipe
.DepthStallEnable
= true;
3996 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3997 pipe
.DepthCacheFlushEnable
= true;
3999 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4000 pipe
.DepthStallEnable
= true;
4005 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4007 struct anv_device
*device
= cmd_buffer
->device
;
4008 const struct anv_image_view
*iview
=
4009 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4010 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4012 /* FIXME: Width and Height are wrong */
4014 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4016 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4017 device
->isl_dev
.ds
.size
/ 4);
4021 struct isl_depth_stencil_hiz_emit_info info
= { };
4024 info
.view
= &iview
->planes
[0].isl
;
4026 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4027 uint32_t depth_plane
=
4028 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4029 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4031 info
.depth_surf
= &surface
->isl
;
4033 info
.depth_address
=
4034 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4035 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4036 image
->planes
[depth_plane
].address
.bo
,
4037 image
->planes
[depth_plane
].address
.offset
+
4040 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4043 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4044 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4045 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
4046 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4049 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4050 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4051 image
->planes
[depth_plane
].address
.bo
,
4052 image
->planes
[depth_plane
].address
.offset
+
4053 image
->planes
[depth_plane
].aux_surface
.offset
);
4055 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4059 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4060 uint32_t stencil_plane
=
4061 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4062 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4064 info
.stencil_surf
= &surface
->isl
;
4066 info
.stencil_address
=
4067 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4068 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4069 image
->planes
[stencil_plane
].address
.bo
,
4070 image
->planes
[stencil_plane
].address
.offset
+
4073 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4076 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4078 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
4082 * This ANDs the view mask of the current subpass with the pending clear
4083 * views in the attachment to get the mask of views active in the subpass
4084 * that still need to be cleared.
4086 static inline uint32_t
4087 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4088 const struct anv_attachment_state
*att_state
)
4090 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4094 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4095 const struct anv_attachment_state
*att_state
)
4097 if (!cmd_state
->subpass
->view_mask
)
4100 uint32_t pending_clear_mask
=
4101 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4103 return pending_clear_mask
& 1;
4107 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4110 const uint32_t last_subpass_idx
=
4111 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4112 const struct anv_subpass
*last_subpass
=
4113 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4114 return last_subpass
== cmd_state
->subpass
;
4118 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4119 uint32_t subpass_id
)
4121 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4122 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4123 cmd_state
->subpass
= subpass
;
4125 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4127 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4128 * different views. If the client asks for instancing, we need to use the
4129 * Instance Data Step Rate to ensure that we repeat the client's
4130 * per-instance data once for each view. Since this bit is in
4131 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4135 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4137 /* It is possible to start a render pass with an old pipeline. Because the
4138 * render pass and subpass index are both baked into the pipeline, this is
4139 * highly unlikely. In order to do so, it requires that you have a render
4140 * pass with a single subpass and that you use that render pass twice
4141 * back-to-back and use the same pipeline at the start of the second render
4142 * pass as at the end of the first. In order to avoid unpredictable issues
4143 * with this edge case, we just dirty the pipeline at the start of every
4146 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4148 /* Accumulate any subpass flushes that need to happen before the subpass */
4149 cmd_buffer
->state
.pending_pipe_bits
|=
4150 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4152 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4153 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4155 bool is_multiview
= subpass
->view_mask
!= 0;
4157 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4158 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4159 if (a
== VK_ATTACHMENT_UNUSED
)
4162 assert(a
< cmd_state
->pass
->attachment_count
);
4163 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4165 struct anv_image_view
*iview
= fb
->attachments
[a
];
4166 const struct anv_image
*image
= iview
->image
;
4168 /* A resolve is necessary before use as an input attachment if the clear
4169 * color or auxiliary buffer usage isn't supported by the sampler.
4171 const bool input_needs_resolve
=
4172 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4173 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4175 VkImageLayout target_layout
;
4176 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4177 !input_needs_resolve
) {
4178 /* Layout transitions before the final only help to enable sampling
4179 * as an input attachment. If the input attachment supports sampling
4180 * using the auxiliary surface, we can skip such transitions by
4181 * making the target layout one that is CCS-aware.
4183 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4185 target_layout
= subpass
->attachments
[i
].layout
;
4188 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4189 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4191 uint32_t base_layer
, layer_count
;
4192 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4194 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4195 iview
->planes
[0].isl
.base_level
);
4197 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4198 layer_count
= fb
->layers
;
4201 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4202 iview
->planes
[0].isl
.base_level
, 1,
4203 base_layer
, layer_count
,
4204 att_state
->current_layout
, target_layout
);
4205 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4206 transition_depth_buffer(cmd_buffer
, image
,
4207 att_state
->current_layout
, target_layout
);
4208 att_state
->aux_usage
=
4209 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4210 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4212 att_state
->current_layout
= target_layout
;
4214 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4215 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4217 /* Multi-planar images are not supported as attachments */
4218 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4219 assert(image
->n_planes
== 1);
4221 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4222 uint32_t clear_layer_count
= fb
->layers
;
4224 if (att_state
->fast_clear
&&
4225 do_first_layer_clear(cmd_state
, att_state
)) {
4226 /* We only support fast-clears on the first layer */
4227 assert(iview
->planes
[0].isl
.base_level
== 0);
4228 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4230 union isl_color_value clear_color
= {};
4231 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4232 if (iview
->image
->samples
== 1) {
4233 anv_image_ccs_op(cmd_buffer
, image
,
4234 iview
->planes
[0].isl
.format
,
4235 VK_IMAGE_ASPECT_COLOR_BIT
,
4236 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4240 anv_image_mcs_op(cmd_buffer
, image
,
4241 iview
->planes
[0].isl
.format
,
4242 VK_IMAGE_ASPECT_COLOR_BIT
,
4243 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4248 clear_layer_count
--;
4250 att_state
->pending_clear_views
&= ~1;
4252 if (att_state
->clear_color_is_zero
) {
4253 /* This image has the auxiliary buffer enabled. We can mark the
4254 * subresource as not needing a resolve because the clear color
4255 * will match what's in every RENDER_SURFACE_STATE object when
4256 * it's being used for sampling.
4258 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4259 VK_IMAGE_ASPECT_COLOR_BIT
,
4260 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4262 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4263 VK_IMAGE_ASPECT_COLOR_BIT
,
4264 ANV_FAST_CLEAR_ANY
);
4268 /* From the VkFramebufferCreateInfo spec:
4270 * "If the render pass uses multiview, then layers must be one and each
4271 * attachment requires a number of layers that is greater than the
4272 * maximum bit index set in the view mask in the subpasses in which it
4275 * So if multiview is active we ignore the number of layers in the
4276 * framebuffer and instead we honor the view mask from the subpass.
4279 assert(image
->n_planes
== 1);
4280 uint32_t pending_clear_mask
=
4281 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4284 for_each_bit(layer_idx
, pending_clear_mask
) {
4286 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4288 anv_image_clear_color(cmd_buffer
, image
,
4289 VK_IMAGE_ASPECT_COLOR_BIT
,
4290 att_state
->aux_usage
,
4291 iview
->planes
[0].isl
.format
,
4292 iview
->planes
[0].isl
.swizzle
,
4293 iview
->planes
[0].isl
.base_level
,
4296 vk_to_isl_color(att_state
->clear_value
.color
));
4299 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4300 } else if (clear_layer_count
> 0) {
4301 assert(image
->n_planes
== 1);
4302 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4303 att_state
->aux_usage
,
4304 iview
->planes
[0].isl
.format
,
4305 iview
->planes
[0].isl
.swizzle
,
4306 iview
->planes
[0].isl
.base_level
,
4307 base_clear_layer
, clear_layer_count
,
4309 vk_to_isl_color(att_state
->clear_value
.color
));
4311 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4312 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4313 if (att_state
->fast_clear
&& !is_multiview
) {
4314 /* We currently only support HiZ for single-layer images */
4315 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4316 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4317 assert(iview
->planes
[0].isl
.base_level
== 0);
4318 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4319 assert(fb
->layers
== 1);
4322 anv_image_hiz_clear(cmd_buffer
, image
,
4323 att_state
->pending_clear_aspects
,
4324 iview
->planes
[0].isl
.base_level
,
4325 iview
->planes
[0].isl
.base_array_layer
,
4326 fb
->layers
, render_area
,
4327 att_state
->clear_value
.depthStencil
.stencil
);
4328 } else if (is_multiview
) {
4329 uint32_t pending_clear_mask
=
4330 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4333 for_each_bit(layer_idx
, pending_clear_mask
) {
4335 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4337 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4338 att_state
->pending_clear_aspects
,
4339 att_state
->aux_usage
,
4340 iview
->planes
[0].isl
.base_level
,
4343 att_state
->clear_value
.depthStencil
.depth
,
4344 att_state
->clear_value
.depthStencil
.stencil
);
4347 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4349 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4350 att_state
->pending_clear_aspects
,
4351 att_state
->aux_usage
,
4352 iview
->planes
[0].isl
.base_level
,
4353 iview
->planes
[0].isl
.base_array_layer
,
4354 fb
->layers
, render_area
,
4355 att_state
->clear_value
.depthStencil
.depth
,
4356 att_state
->clear_value
.depthStencil
.stencil
);
4359 assert(att_state
->pending_clear_aspects
== 0);
4363 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4364 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4365 iview
->planes
[0].isl
.base_level
== 0 &&
4366 iview
->planes
[0].isl
.base_array_layer
== 0) {
4367 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4368 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4369 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4370 false /* copy to ss */);
4373 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4374 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4375 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4376 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4377 false /* copy to ss */);
4381 if (subpass
->attachments
[i
].usage
==
4382 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4383 /* We assume that if we're starting a subpass, we're going to do some
4384 * rendering so we may end up with compressed data.
4386 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4387 VK_IMAGE_ASPECT_COLOR_BIT
,
4388 att_state
->aux_usage
,
4389 iview
->planes
[0].isl
.base_level
,
4390 iview
->planes
[0].isl
.base_array_layer
,
4392 } else if (subpass
->attachments
[i
].usage
==
4393 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4394 /* We may be writing depth or stencil so we need to mark the surface.
4395 * Unfortunately, there's no way to know at this point whether the
4396 * depth or stencil tests used will actually write to the surface.
4398 * Even though stencil may be plane 1, it always shares a base_level
4401 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4402 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4403 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4404 VK_IMAGE_ASPECT_DEPTH_BIT
,
4405 att_state
->aux_usage
,
4406 ds_view
->base_level
,
4407 ds_view
->base_array_layer
,
4410 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4411 /* Even though stencil may be plane 1, it always shares a
4412 * base_level with depth.
4414 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4415 VK_IMAGE_ASPECT_STENCIL_BIT
,
4417 ds_view
->base_level
,
4418 ds_view
->base_array_layer
,
4423 /* If multiview is enabled, then we are only done clearing when we no
4424 * longer have pending layers to clear, or when we have processed the
4425 * last subpass that uses this attachment.
4427 if (!is_multiview
||
4428 att_state
->pending_clear_views
== 0 ||
4429 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4430 att_state
->pending_clear_aspects
= 0;
4433 att_state
->pending_load_aspects
= 0;
4436 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4439 static enum blorp_filter
4440 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4443 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4444 return BLORP_FILTER_SAMPLE_0
;
4445 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4446 return BLORP_FILTER_AVERAGE
;
4447 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4448 return BLORP_FILTER_MIN_SAMPLE
;
4449 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4450 return BLORP_FILTER_MAX_SAMPLE
;
4452 return BLORP_FILTER_NONE
;
4457 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4459 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4460 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4461 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4462 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4464 if (subpass
->has_color_resolve
) {
4465 /* We are about to do some MSAA resolves. We need to flush so that the
4466 * result of writes to the MSAA color attachments show up in the sampler
4467 * when we blit to the single-sampled resolve target.
4469 cmd_buffer
->state
.pending_pipe_bits
|=
4470 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4471 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4473 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4474 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4475 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4477 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4480 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4481 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4483 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4484 /* From the Vulkan 1.0 spec:
4486 * If the first use of an attachment in a render pass is as a
4487 * resolve attachment, then the loadOp is effectively ignored
4488 * as the resolve is guaranteed to overwrite all pixels in the
4491 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4494 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4495 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4497 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4499 enum isl_aux_usage src_aux_usage
=
4500 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4501 enum isl_aux_usage dst_aux_usage
=
4502 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4504 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4505 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4507 anv_image_msaa_resolve(cmd_buffer
,
4508 src_iview
->image
, src_aux_usage
,
4509 src_iview
->planes
[0].isl
.base_level
,
4510 src_iview
->planes
[0].isl
.base_array_layer
,
4511 dst_iview
->image
, dst_aux_usage
,
4512 dst_iview
->planes
[0].isl
.base_level
,
4513 dst_iview
->planes
[0].isl
.base_array_layer
,
4514 VK_IMAGE_ASPECT_COLOR_BIT
,
4515 render_area
.offset
.x
, render_area
.offset
.y
,
4516 render_area
.offset
.x
, render_area
.offset
.y
,
4517 render_area
.extent
.width
,
4518 render_area
.extent
.height
,
4519 fb
->layers
, BLORP_FILTER_NONE
);
4523 if (subpass
->ds_resolve_attachment
) {
4524 /* We are about to do some MSAA resolves. We need to flush so that the
4525 * result of writes to the MSAA depth attachments show up in the sampler
4526 * when we blit to the single-sampled resolve target.
4528 cmd_buffer
->state
.pending_pipe_bits
|=
4529 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4530 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4532 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4533 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4535 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4536 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4538 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4539 /* From the Vulkan 1.0 spec:
4541 * If the first use of an attachment in a render pass is as a
4542 * resolve attachment, then the loadOp is effectively ignored
4543 * as the resolve is guaranteed to overwrite all pixels in the
4546 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4549 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4550 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4552 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4554 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4555 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4557 struct anv_attachment_state
*src_state
=
4558 &cmd_state
->attachments
[src_att
];
4559 struct anv_attachment_state
*dst_state
=
4560 &cmd_state
->attachments
[dst_att
];
4562 /* MSAA resolves sample from the source attachment. Transition the
4563 * depth attachment first to get rid of any HiZ that we may not be
4566 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4567 src_state
->current_layout
,
4568 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4569 src_state
->aux_usage
=
4570 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4571 VK_IMAGE_ASPECT_DEPTH_BIT
,
4572 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4573 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4575 /* MSAA resolves write to the resolve attachment as if it were any
4576 * other transfer op. Transition the resolve attachment accordingly.
4578 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4580 /* If our render area is the entire size of the image, we're going to
4581 * blow it all away so we can claim the initial layout is UNDEFINED
4582 * and we'll get a HiZ ambiguate instead of a resolve.
4584 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4585 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4586 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4587 render_area
.extent
.height
== dst_iview
->extent
.height
)
4588 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4590 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4592 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4593 dst_state
->aux_usage
=
4594 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4595 VK_IMAGE_ASPECT_DEPTH_BIT
,
4596 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4597 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4599 enum blorp_filter filter
=
4600 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4602 anv_image_msaa_resolve(cmd_buffer
,
4603 src_iview
->image
, src_state
->aux_usage
,
4604 src_iview
->planes
[0].isl
.base_level
,
4605 src_iview
->planes
[0].isl
.base_array_layer
,
4606 dst_iview
->image
, dst_state
->aux_usage
,
4607 dst_iview
->planes
[0].isl
.base_level
,
4608 dst_iview
->planes
[0].isl
.base_array_layer
,
4609 VK_IMAGE_ASPECT_DEPTH_BIT
,
4610 render_area
.offset
.x
, render_area
.offset
.y
,
4611 render_area
.offset
.x
, render_area
.offset
.y
,
4612 render_area
.extent
.width
,
4613 render_area
.extent
.height
,
4614 fb
->layers
, filter
);
4617 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4618 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4620 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4621 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4623 enum blorp_filter filter
=
4624 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4626 anv_image_msaa_resolve(cmd_buffer
,
4627 src_iview
->image
, src_aux_usage
,
4628 src_iview
->planes
[0].isl
.base_level
,
4629 src_iview
->planes
[0].isl
.base_array_layer
,
4630 dst_iview
->image
, dst_aux_usage
,
4631 dst_iview
->planes
[0].isl
.base_level
,
4632 dst_iview
->planes
[0].isl
.base_array_layer
,
4633 VK_IMAGE_ASPECT_STENCIL_BIT
,
4634 render_area
.offset
.x
, render_area
.offset
.y
,
4635 render_area
.offset
.x
, render_area
.offset
.y
,
4636 render_area
.extent
.width
,
4637 render_area
.extent
.height
,
4638 fb
->layers
, filter
);
4642 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4643 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4644 if (a
== VK_ATTACHMENT_UNUSED
)
4647 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4650 assert(a
< cmd_state
->pass
->attachment_count
);
4651 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4652 struct anv_image_view
*iview
= fb
->attachments
[a
];
4653 const struct anv_image
*image
= iview
->image
;
4655 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4656 image
->vk_format
!= iview
->vk_format
) {
4657 enum anv_fast_clear_type fast_clear_type
=
4658 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4659 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4660 att_state
->current_layout
);
4662 /* If any clear color was used, flush it down the aux surfaces. If we
4663 * don't do it now using the view's format we might use the clear
4664 * color incorrectly in the following resolves (for example with an
4665 * SRGB view & a UNORM image).
4667 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4668 anv_perf_warn(cmd_buffer
->device
->instance
, fb
,
4669 "Doing a partial resolve to get rid of clear color at the "
4670 "end of a renderpass due to an image/view format mismatch");
4672 uint32_t base_layer
, layer_count
;
4673 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4675 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4676 iview
->planes
[0].isl
.base_level
);
4678 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4679 layer_count
= fb
->layers
;
4682 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4683 uint32_t array_layer
= base_layer
+ a
;
4684 if (image
->samples
== 1) {
4685 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4686 iview
->planes
[0].isl
.format
,
4687 VK_IMAGE_ASPECT_COLOR_BIT
,
4688 iview
->planes
[0].isl
.base_level
,
4690 ISL_AUX_OP_PARTIAL_RESOLVE
,
4691 ANV_FAST_CLEAR_NONE
);
4693 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4694 iview
->planes
[0].isl
.format
,
4695 VK_IMAGE_ASPECT_COLOR_BIT
,
4697 ISL_AUX_OP_PARTIAL_RESOLVE
,
4698 ANV_FAST_CLEAR_NONE
);
4704 /* Transition the image into the final layout for this render pass */
4705 VkImageLayout target_layout
=
4706 cmd_state
->pass
->attachments
[a
].final_layout
;
4708 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4709 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4711 uint32_t base_layer
, layer_count
;
4712 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4714 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4715 iview
->planes
[0].isl
.base_level
);
4717 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4718 layer_count
= fb
->layers
;
4721 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4722 iview
->planes
[0].isl
.base_level
, 1,
4723 base_layer
, layer_count
,
4724 att_state
->current_layout
, target_layout
);
4725 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4726 transition_depth_buffer(cmd_buffer
, image
,
4727 att_state
->current_layout
, target_layout
);
4731 /* Accumulate any subpass flushes that need to happen after the subpass.
4732 * Yes, they do get accumulated twice in the NextSubpass case but since
4733 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4734 * ORing the bits in twice so it's harmless.
4736 cmd_buffer
->state
.pending_pipe_bits
|=
4737 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4740 void genX(CmdBeginRenderPass
)(
4741 VkCommandBuffer commandBuffer
,
4742 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4743 VkSubpassContents contents
)
4745 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4746 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4747 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4749 cmd_buffer
->state
.framebuffer
= framebuffer
;
4750 cmd_buffer
->state
.pass
= pass
;
4751 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4753 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4755 /* If we failed to setup the attachments we should not try to go further */
4756 if (result
!= VK_SUCCESS
) {
4757 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4761 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4763 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4766 void genX(CmdBeginRenderPass2KHR
)(
4767 VkCommandBuffer commandBuffer
,
4768 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4769 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4771 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4772 pSubpassBeginInfo
->contents
);
4775 void genX(CmdNextSubpass
)(
4776 VkCommandBuffer commandBuffer
,
4777 VkSubpassContents contents
)
4779 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4781 if (anv_batch_has_error(&cmd_buffer
->batch
))
4784 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4786 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4787 cmd_buffer_end_subpass(cmd_buffer
);
4788 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4791 void genX(CmdNextSubpass2KHR
)(
4792 VkCommandBuffer commandBuffer
,
4793 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4794 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4796 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4799 void genX(CmdEndRenderPass
)(
4800 VkCommandBuffer commandBuffer
)
4802 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4804 if (anv_batch_has_error(&cmd_buffer
->batch
))
4807 cmd_buffer_end_subpass(cmd_buffer
);
4809 cmd_buffer
->state
.hiz_enabled
= false;
4812 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
4815 /* Remove references to render pass specific state. This enables us to
4816 * detect whether or not we're in a renderpass.
4818 cmd_buffer
->state
.framebuffer
= NULL
;
4819 cmd_buffer
->state
.pass
= NULL
;
4820 cmd_buffer
->state
.subpass
= NULL
;
4823 void genX(CmdEndRenderPass2KHR
)(
4824 VkCommandBuffer commandBuffer
,
4825 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4827 genX(CmdEndRenderPass
)(commandBuffer
);
4831 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
4833 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4834 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(ANV_PREDICATE_RESULT_REG
));
4835 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
4836 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
4837 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
4839 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
4840 mip
.LoadOperation
= LOAD_LOADINV
;
4841 mip
.CombineOperation
= COMBINE_SET
;
4842 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4847 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4848 void genX(CmdBeginConditionalRenderingEXT
)(
4849 VkCommandBuffer commandBuffer
,
4850 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4852 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4853 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4854 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4855 struct anv_address value_address
=
4856 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
4858 const bool isInverted
= pConditionalRenderingBegin
->flags
&
4859 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
4861 cmd_state
->conditional_render_enabled
= true;
4863 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4865 /* Section 19.4 of the Vulkan 1.1.85 spec says:
4867 * If the value of the predicate in buffer memory changes
4868 * while conditional rendering is active, the rendering commands
4869 * may be discarded in an implementation-dependent way.
4870 * Some implementations may latch the value of the predicate
4871 * upon beginning conditional rendering while others
4872 * may read it before every rendering command.
4874 * So it's perfectly fine to read a value from the buffer once.
4876 emit_lrm(&cmd_buffer
->batch
, CS_GPR(MI_ALU_REG0
), value_address
);
4877 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
4878 emit_lri(&cmd_buffer
->batch
, CS_GPR(MI_ALU_REG0
) + 4, 0);
4880 /* Precompute predicate result, it is necessary to support secondary
4881 * command buffers since it is unknown if conditional rendering is
4882 * inverted when populating them.
4884 uint32_t *dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
4885 dw
[1] = mi_alu(MI_ALU_LOAD0
, MI_ALU_SRCA
, 0);
4886 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG0
);
4887 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
4888 dw
[4] = mi_alu(isInverted
? MI_ALU_STOREINV
: MI_ALU_STORE
,
4889 ANV_PREDICATE_RESULT_REG
, MI_ALU_CF
);
4892 void genX(CmdEndConditionalRenderingEXT
)(
4893 VkCommandBuffer commandBuffer
)
4895 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4896 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4898 cmd_state
->conditional_render_enabled
= false;