2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
,
37 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
83 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
84 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
85 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
86 sba
.GeneralStateBaseAddressModifyEnable
= true;
88 sba
.SurfaceStateBaseAddress
=
89 anv_cmd_buffer_surface_base_address(cmd_buffer
);
90 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
91 sba
.SurfaceStateBaseAddressModifyEnable
= true;
93 sba
.DynamicStateBaseAddress
=
94 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
95 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
96 sba
.DynamicStateBaseAddressModifyEnable
= true;
98 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
99 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
100 sba
.IndirectObjectBaseAddressModifyEnable
= true;
102 sba
.InstructionBaseAddress
=
103 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
104 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
105 sba
.InstructionBaseAddressModifyEnable
= true;
108 /* Broadwell requires that we specify a buffer size for a bunch of
109 * these fields. However, since we will be growing the BO's live, we
110 * just set them all to the maximum.
112 sba
.GeneralStateBufferSize
= 0xfffff;
113 sba
.GeneralStateBufferSizeModifyEnable
= true;
114 sba
.DynamicStateBufferSize
= 0xfffff;
115 sba
.DynamicStateBufferSizeModifyEnable
= true;
116 sba
.IndirectObjectBufferSize
= 0xfffff;
117 sba
.IndirectObjectBufferSizeModifyEnable
= true;
118 sba
.InstructionBufferSize
= 0xfffff;
119 sba
.InstructionBuffersizeModifyEnable
= true;
123 /* After re-setting the surface state base address, we have to do some
124 * cache flusing so that the sampler engine will pick up the new
125 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
126 * Shared Function > 3D Sampler > State > State Caching (page 96):
128 * Coherency with system memory in the state cache, like the texture
129 * cache is handled partially by software. It is expected that the
130 * command stream or shader will issue Cache Flush operation or
131 * Cache_Flush sampler message to ensure that the L1 cache remains
132 * coherent with system memory.
136 * Whenever the value of the Dynamic_State_Base_Addr,
137 * Surface_State_Base_Addr are altered, the L1 state cache must be
138 * invalidated to ensure the new surface or sampler state is fetched
139 * from system memory.
141 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
142 * which, according the PIPE_CONTROL instruction documentation in the
145 * Setting this bit is independent of any other bit in this packet.
146 * This bit controls the invalidation of the L1 and L2 state caches
147 * at the top of the pipe i.e. at the parsing time.
149 * Unfortunately, experimentation seems to indicate that state cache
150 * invalidation through a PIPE_CONTROL does nothing whatsoever in
151 * regards to surface state and binding tables. In stead, it seems that
152 * invalidating the texture cache is what is actually needed.
154 * XXX: As far as we have been able to determine through
155 * experimentation, shows that flush the texture cache appears to be
156 * sufficient. The theory here is that all of the sampling/rendering
157 * units cache the binding table in the texture cache. However, we have
158 * yet to be able to actually confirm this.
160 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
161 pc
.TextureCacheInvalidationEnable
= true;
162 pc
.ConstantCacheInvalidationEnable
= true;
163 pc
.StateCacheInvalidationEnable
= true;
168 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
169 struct anv_state state
,
170 struct anv_bo
*bo
, uint32_t offset
)
172 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
175 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
176 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
177 if (result
!= VK_SUCCESS
)
178 anv_batch_set_error(&cmd_buffer
->batch
, result
);
182 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
183 const struct anv_image_view
*image_view
,
184 const uint32_t plane
,
185 struct anv_surface_state state
)
187 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
188 const struct anv_image
*image
= image_view
->image
;
189 uint32_t image_plane
= image_view
->planes
[plane
].image_plane
;
191 add_surface_state_reloc(cmd_buffer
, state
.state
,
192 image
->planes
[image_plane
].bo
, state
.address
);
194 if (state
.aux_address
) {
196 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
197 &cmd_buffer
->pool
->alloc
,
198 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
199 image
->planes
[image_plane
].bo
, state
.aux_address
);
200 if (result
!= VK_SUCCESS
)
201 anv_batch_set_error(&cmd_buffer
->batch
, result
);
206 color_attachment_compute_aux_usage(struct anv_device
* device
,
207 struct anv_cmd_state
* cmd_state
,
208 uint32_t att
, VkRect2D render_area
,
209 union isl_color_value
*fast_clear_color
)
211 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
212 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
214 assert(iview
->n_planes
== 1);
216 if (iview
->planes
[0].isl
.base_array_layer
>=
217 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
218 iview
->planes
[0].isl
.base_level
)) {
219 /* There is no aux buffer which corresponds to the level and layer(s)
222 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
223 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
224 att_state
->fast_clear
= false;
228 att_state
->aux_usage
=
229 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
230 VK_IMAGE_ASPECT_COLOR_BIT
,
231 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
233 /* If we don't have aux, then we should have returned early in the layer
234 * check above. If we got here, we must have something.
236 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
238 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
239 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
240 att_state
->input_aux_usage
= att_state
->aux_usage
;
242 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
244 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
245 * setting is only allowed if Surface Format supported for Fast
246 * Clear. In addition, if the surface is bound to the sampling
247 * engine, Surface Format must be supported for Render Target
248 * Compression for surfaces bound to the sampling engine."
250 * In other words, we can only sample from a fast-cleared image if it
251 * also supports color compression.
253 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
254 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
256 /* While fast-clear resolves and partial resolves are fairly cheap in the
257 * case where you render to most of the pixels, full resolves are not
258 * because they potentially involve reading and writing the entire
259 * framebuffer. If we can't texture with CCS_E, we should leave it off and
260 * limit ourselves to fast clears.
262 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
263 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
264 anv_perf_warn(device
->instance
, iview
->image
,
265 "Not temporarily enabling CCS_E.");
268 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
272 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
273 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
275 const struct isl_format_layout
*view_fmtl
=
276 isl_format_get_layout(iview
->planes
[0].isl
.format
);
277 union isl_color_value clear_color
= {};
279 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
280 if (view_fmtl->channels.c.bits) \
281 clear_color.u32[i] = att_state->clear_value.color.uint32[i]
283 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
284 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
285 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
286 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
288 #undef COPY_CLEAR_COLOR_CHANNEL
290 att_state
->clear_color_is_zero_one
=
291 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
292 att_state
->clear_color_is_zero
=
293 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
295 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
296 /* Start by getting the fast clear type. We use the first subpass
297 * layout here because we don't want to fast-clear if the first subpass
298 * to use the attachment can't handle fast-clears.
300 enum anv_fast_clear_type fast_clear_type
=
301 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
302 VK_IMAGE_ASPECT_COLOR_BIT
,
303 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
304 switch (fast_clear_type
) {
305 case ANV_FAST_CLEAR_NONE
:
306 att_state
->fast_clear
= false;
308 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
309 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
311 case ANV_FAST_CLEAR_ANY
:
312 att_state
->fast_clear
= true;
316 /* Potentially, we could do partial fast-clears but doing so has crazy
317 * alignment restrictions. It's easier to just restrict to full size
318 * fast clears for now.
320 if (render_area
.offset
.x
!= 0 ||
321 render_area
.offset
.y
!= 0 ||
322 render_area
.extent
.width
!= iview
->extent
.width
||
323 render_area
.extent
.height
!= iview
->extent
.height
)
324 att_state
->fast_clear
= false;
326 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
327 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
328 att_state
->fast_clear
= false;
330 /* We only allow fast clears to the first slice of an image (level 0,
331 * layer 0) and only for the entire slice. This guarantees us that, at
332 * any given time, there is only one clear color on any given image at
333 * any given time. At the time of our testing (Jan 17, 2018), there
334 * were no known applications which would benefit from fast-clearing
335 * more than just the first slice.
337 if (att_state
->fast_clear
&&
338 (iview
->planes
[0].isl
.base_level
> 0 ||
339 iview
->planes
[0].isl
.base_array_layer
> 0)) {
340 anv_perf_warn(device
->instance
, iview
->image
,
341 "Rendering with multi-lod or multi-layer framebuffer "
342 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
343 "baseArrayLayer > 0. Not fast clearing.");
344 att_state
->fast_clear
= false;
345 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
346 anv_perf_warn(device
->instance
, iview
->image
,
347 "Rendering to a multi-layer framebuffer with "
348 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
351 if (att_state
->fast_clear
)
352 *fast_clear_color
= clear_color
;
354 att_state
->fast_clear
= false;
359 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
360 struct anv_cmd_state
*cmd_state
,
361 uint32_t att
, VkRect2D render_area
)
363 struct anv_render_pass_attachment
*pass_att
=
364 &cmd_state
->pass
->attachments
[att
];
365 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
366 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
368 /* These will be initialized after the first subpass transition. */
369 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
370 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
373 /* We don't do any HiZ or depth fast-clears on gen7 yet */
374 att_state
->fast_clear
= false;
378 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
379 /* If we're just clearing stencil, we can always HiZ clear */
380 att_state
->fast_clear
= true;
384 /* Default to false for now */
385 att_state
->fast_clear
= false;
387 /* We must have depth in order to have HiZ */
388 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
391 const enum isl_aux_usage first_subpass_aux_usage
=
392 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
393 VK_IMAGE_ASPECT_DEPTH_BIT
,
394 pass_att
->first_subpass_layout
);
395 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
398 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
399 iview
->planes
[0].isl
.format
,
400 iview
->image
->samples
,
401 render_area
.offset
.x
,
402 render_area
.offset
.y
,
403 render_area
.offset
.x
+
404 render_area
.extent
.width
,
405 render_area
.offset
.y
+
406 render_area
.extent
.height
))
409 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
412 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
413 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
414 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
415 * only supports returning 0.0f. Gens prior to gen8 do not support this
421 /* If we got here, then we can fast clear */
422 att_state
->fast_clear
= true;
426 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
428 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
431 /* We only allocate input attachment states for color surfaces. Compression
432 * is not yet enabled for depth textures and stencil doesn't allow
433 * compression so we can just use the texture surface state from the view.
435 return vk_format_is_color(att
->format
);
438 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
439 * the initial layout is undefined, the HiZ buffer and depth buffer will
440 * represent the same data at the end of this operation.
443 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
444 const struct anv_image
*image
,
445 VkImageLayout initial_layout
,
446 VkImageLayout final_layout
)
448 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
449 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
450 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
451 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
452 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
453 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
455 enum isl_aux_op hiz_op
;
456 if (hiz_enabled
&& !enable_hiz
) {
457 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
458 } else if (!hiz_enabled
&& enable_hiz
) {
459 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
461 assert(hiz_enabled
== enable_hiz
);
462 /* If the same buffer will be used, no resolves are necessary. */
463 hiz_op
= ISL_AUX_OP_NONE
;
466 if (hiz_op
!= ISL_AUX_OP_NONE
)
467 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
471 #define MI_PREDICATE_SRC0 0x2400
472 #define MI_PREDICATE_SRC1 0x2408
475 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
476 const struct anv_image
*image
,
477 VkImageAspectFlagBits aspect
,
479 uint32_t base_layer
, uint32_t layer_count
,
482 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
484 /* We only have compression tracking for CCS_E */
485 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
488 for (uint32_t a
= 0; a
< layer_count
; a
++) {
489 uint32_t layer
= base_layer
+ a
;
490 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
491 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
494 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
500 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
501 const struct anv_image
*image
,
502 VkImageAspectFlagBits aspect
,
503 enum anv_fast_clear_type fast_clear
)
505 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
506 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
508 sdi
.ImmediateData
= fast_clear
;
511 /* Whenever we have fast-clear, we consider that slice to be compressed.
512 * This makes building predicates much easier.
514 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
515 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
518 #if GEN_IS_HASWELL || GEN_GEN >= 8
519 static inline uint32_t
520 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
522 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
524 .Operand1
= operand1
,
525 .Operand2
= operand2
,
529 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
535 #define CS_GPR(n) (0x2600 + (n) * 8)
538 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
539 const struct anv_image
*image
,
540 VkImageAspectFlagBits aspect
,
541 uint32_t level
, uint32_t array_layer
,
542 enum isl_aux_op resolve_op
,
543 enum anv_fast_clear_type fast_clear_supported
)
545 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
546 struct anv_address fast_clear_type_addr
=
547 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
550 /* Name some registers */
551 const int image_fc_reg
= MI_ALU_REG0
;
552 const int fc_imm_reg
= MI_ALU_REG1
;
553 const int pred_reg
= MI_ALU_REG2
;
557 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
558 /* In this case, we're doing a full resolve which means we want the
559 * resolve to happen if any compression (including fast-clears) is
562 * In order to simplify the logic a bit, we make the assumption that,
563 * if the first slice has been fast-cleared, it is also marked as
564 * compressed. See also set_image_fast_clear_state.
566 struct anv_address compression_state_addr
=
567 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
568 aspect
, level
, array_layer
);
569 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
570 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
571 lrm
.MemoryAddress
= compression_state_addr
;
573 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
574 sdi
.Address
= compression_state_addr
;
575 sdi
.ImmediateData
= 0;
578 if (level
== 0 && array_layer
== 0) {
579 /* If the predicate is true, we want to write 0 to the fast clear type
580 * and, if it's false, leave it alone. We can do this by writing
582 * clear_type = clear_type & ~predicate;
584 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
585 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
586 lrm
.MemoryAddress
= fast_clear_type_addr
;
588 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
589 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
590 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
593 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
594 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
595 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
596 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
597 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
599 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
600 srm
.MemoryAddress
= fast_clear_type_addr
;
601 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
604 } else if (level
== 0 && array_layer
== 0) {
605 /* In this case, we are doing a partial resolve to get rid of fast-clear
606 * colors. We don't care about the compression state but we do care
607 * about how much fast clear is allowed by the final layout.
609 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
610 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
612 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
613 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
614 lrm
.MemoryAddress
= fast_clear_type_addr
;
616 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
618 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
619 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
621 /* We need to compute (fast_clear_supported < image->fast_clear).
622 * We do this by subtracting and storing the carry bit.
624 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
625 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
626 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
627 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
628 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
630 /* Store the predicate */
631 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
633 /* If the predicate is true, we want to write 0 to the fast clear type
634 * and, if it's false, leave it alone. We can do this by writing
636 * clear_type = clear_type & ~predicate;
638 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
639 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
640 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
641 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
642 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
644 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
645 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
646 srm
.MemoryAddress
= fast_clear_type_addr
;
649 /* In this case, we're trying to do a partial resolve on a slice that
650 * doesn't have clear color. There's nothing to do.
652 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
656 #else /* GEN_GEN <= 8 */
657 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
658 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
660 /* We don't support fast clears on anything other than the first slice. */
661 if (level
> 0 || array_layer
> 0)
664 /* On gen8, we don't have a concept of default clear colors because we
665 * can't sample from CCS surfaces. It's enough to just load the fast clear
666 * state into the predicate register.
668 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
669 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
670 lrm
.MemoryAddress
= fast_clear_type_addr
;
672 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
673 sdi
.Address
= fast_clear_type_addr
;
674 sdi
.ImmediateData
= 0;
678 /* We use the first half of src0 for the actual predicate. Set the second
679 * half of src0 and all of src1 to 0 as the predicate operation will be
680 * doing an implicit src0 != src1.
682 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
683 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
684 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
686 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
687 mip
.LoadOperation
= LOAD_LOADINV
;
688 mip
.CombineOperation
= COMBINE_SET
;
689 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
692 /* CCS_D only supports full resolves and BLORP will assert on us if we try
693 * to do a partial resolve on a CCS_D surface.
695 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
696 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
697 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
699 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
700 array_layer
, 1, resolve_op
, true);
704 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
705 const struct anv_image
*image
,
706 VkImageAspectFlagBits aspect
,
707 enum isl_aux_usage aux_usage
,
710 uint32_t layer_count
)
712 /* The aspect must be exactly one of the image aspects. */
713 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
715 /* The only compression types with more than just fast-clears are MCS,
716 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
717 * track the current fast-clear and compression state. This leaves us
718 * with just MCS and CCS_E.
720 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
721 aux_usage
!= ISL_AUX_USAGE_MCS
)
724 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
725 level
, base_layer
, layer_count
, true);
729 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
730 const struct anv_image
*image
,
731 VkImageAspectFlagBits aspect
)
733 assert(cmd_buffer
&& image
);
734 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
736 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
737 ANV_FAST_CLEAR_NONE
);
739 /* The fast clear value dword(s) will be copied into a surface state object.
740 * Ensure that the restrictions of the fields in the dword(s) are followed.
742 * CCS buffers on SKL+ can have any value set for the clear colors.
744 if (image
->samples
== 1 && GEN_GEN
>= 9)
747 /* Other combinations of auxiliary buffers and platforms require specific
748 * values in the clear value dword(s).
750 struct anv_address addr
=
751 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
753 for (; i
< cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
; i
+= 4) {
754 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
758 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
759 assert(image
->samples
> 1);
760 sdi
.ImmediateData
= 0;
761 } else if (GEN_VERSIONx10
>= 75) {
762 /* Pre-SKL, the dword containing the clear values also contains
763 * other fields, so we need to initialize those fields to match the
764 * values that would be in a color attachment.
767 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
768 ISL_CHANNEL_SELECT_GREEN
<< 22 |
769 ISL_CHANNEL_SELECT_BLUE
<< 19 |
770 ISL_CHANNEL_SELECT_ALPHA
<< 16;
771 } else if (GEN_VERSIONx10
== 70) {
772 /* On IVB, the dword containing the clear values also contains
773 * other fields that must be zero or can be zero.
776 sdi
.ImmediateData
= 0;
784 /* Copy the fast-clear value dword(s) between a surface state object and an
785 * image's fast clear state buffer.
788 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
789 struct anv_state surface_state
,
790 const struct anv_image
*image
,
791 VkImageAspectFlagBits aspect
,
792 bool copy_from_surface_state
)
794 assert(cmd_buffer
&& image
);
795 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
797 struct anv_bo
*ss_bo
=
798 &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
;
799 uint32_t ss_clear_offset
= surface_state
.offset
+
800 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
;
801 const struct anv_address entry_addr
=
802 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
803 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
805 if (copy_from_surface_state
) {
806 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
.bo
, entry_addr
.offset
,
807 ss_bo
, ss_clear_offset
, copy_size
);
809 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_bo
, ss_clear_offset
,
810 entry_addr
.bo
, entry_addr
.offset
, copy_size
);
812 /* Updating a surface state object may require that the state cache be
813 * invalidated. From the SKL PRM, Shared Functions -> State -> State
816 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
817 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
818 * modified [...], the L1 state cache must be invalidated to ensure
819 * the new surface or sampler state is fetched from system memory.
821 * In testing, SKL doesn't actually seem to need this, but HSW does.
823 cmd_buffer
->state
.pending_pipe_bits
|=
824 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
829 * @brief Transitions a color buffer from one layout to another.
831 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
834 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
835 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
836 * this represents the maximum layers to transition at each
837 * specified miplevel.
840 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
841 const struct anv_image
*image
,
842 VkImageAspectFlagBits aspect
,
843 const uint32_t base_level
, uint32_t level_count
,
844 uint32_t base_layer
, uint32_t layer_count
,
845 VkImageLayout initial_layout
,
846 VkImageLayout final_layout
)
848 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
849 /* Validate the inputs. */
851 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
852 /* These values aren't supported for simplicity's sake. */
853 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
854 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
855 /* Ensure the subresource range is valid. */
856 uint64_t last_level_num
= base_level
+ level_count
;
857 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
858 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
859 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
860 assert(last_level_num
<= image
->levels
);
861 /* The spec disallows these final layouts. */
862 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
863 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
865 /* No work is necessary if the layout stays the same or if this subresource
866 * range lacks auxiliary data.
868 if (initial_layout
== final_layout
)
871 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
873 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
874 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
875 /* This surface is a linear compressed image with a tiled shadow surface
876 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
877 * we need to ensure the shadow copy is up-to-date.
879 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
880 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
881 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
882 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
884 anv_image_copy_to_shadow(cmd_buffer
, image
,
885 base_level
, level_count
,
886 base_layer
, layer_count
);
889 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
892 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
894 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
895 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
896 /* A subresource in the undefined layout may have been aliased and
897 * populated with any arrangement of bits. Therefore, we must initialize
898 * the related aux buffer and clear buffer entry with desirable values.
899 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
900 * images with VK_IMAGE_TILING_OPTIMAL.
902 * Initialize the relevant clear buffer entries.
904 if (base_level
== 0 && base_layer
== 0)
905 init_fast_clear_color(cmd_buffer
, image
, aspect
);
907 /* Initialize the aux buffers to enable correct rendering. In order to
908 * ensure that things such as storage images work correctly, aux buffers
909 * need to be initialized to valid data.
911 * Having an aux buffer with invalid data is a problem for two reasons:
913 * 1) Having an invalid value in the buffer can confuse the hardware.
914 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
915 * invalid and leads to the hardware doing strange things. It
916 * doesn't hang as far as we can tell but rendering corruption can
919 * 2) If this transition is into the GENERAL layout and we then use the
920 * image as a storage image, then we must have the aux buffer in the
921 * pass-through state so that, if we then go to texture from the
922 * image, we get the results of our storage image writes and not the
923 * fast clear color or other random data.
925 * For CCS both of the problems above are real demonstrable issues. In
926 * that case, the only thing we can do is to perform an ambiguate to
927 * transition the aux surface into the pass-through state.
929 * For MCS, (2) is never an issue because we don't support multisampled
930 * storage images. In theory, issue (1) is a problem with MCS but we've
931 * never seen it in the wild. For 4x and 16x, all bit patters could, in
932 * theory, be interpreted as something but we don't know that all bit
933 * patterns are actually valid. For 2x and 8x, you could easily end up
934 * with the MCS referring to an invalid plane because not all bits of
935 * the MCS value are actually used. Even though we've never seen issues
936 * in the wild, it's best to play it safe and initialize the MCS. We
937 * can use a fast-clear for MCS because we only ever touch from render
938 * and texture (no image load store).
940 if (image
->samples
== 1) {
941 for (uint32_t l
= 0; l
< level_count
; l
++) {
942 const uint32_t level
= base_level
+ l
;
944 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
945 if (base_layer
>= aux_layers
)
946 break; /* We will only get fewer layers as level increases */
947 uint32_t level_layer_count
=
948 MIN2(layer_count
, aux_layers
- base_layer
);
950 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
951 base_layer
, level_layer_count
,
952 ISL_AUX_OP_AMBIGUATE
, false);
954 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
955 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
956 level
, base_layer
, level_layer_count
,
961 if (image
->samples
== 4 || image
->samples
== 16) {
962 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
963 "Doing a potentially unnecessary fast-clear to "
964 "define an MCS buffer.");
967 assert(base_level
== 0 && level_count
== 1);
968 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
969 base_layer
, layer_count
,
970 ISL_AUX_OP_FAST_CLEAR
, false);
975 const enum isl_aux_usage initial_aux_usage
=
976 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
977 const enum isl_aux_usage final_aux_usage
=
978 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
980 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
981 * We can handle transitions between CCS_D/E to and from NONE. What we
982 * don't yet handle is switching between CCS_E and CCS_D within a given
983 * image. Doing so in a performant way requires more detailed aux state
984 * tracking such as what is done in i965. For now, just assume that we
985 * only have one type of compression.
987 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
988 final_aux_usage
== ISL_AUX_USAGE_NONE
||
989 initial_aux_usage
== final_aux_usage
);
991 /* If initial aux usage is NONE, there is nothing to resolve */
992 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
995 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
997 /* If the initial layout supports more fast clear than the final layout
998 * then we need at least a partial resolve.
1000 const enum anv_fast_clear_type initial_fast_clear
=
1001 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1002 const enum anv_fast_clear_type final_fast_clear
=
1003 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1004 if (final_fast_clear
< initial_fast_clear
)
1005 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1007 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1008 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1009 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1011 if (resolve_op
== ISL_AUX_OP_NONE
)
1014 /* Perform a resolve to synchronize data between the main and aux buffer.
1015 * Before we begin, we must satisfy the cache flushing requirement specified
1016 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1018 * Any transition from any value in {Clear, Render, Resolve} to a
1019 * different value in {Clear, Render, Resolve} requires end of pipe
1022 * We perform a flush of the write cache before and after the clear and
1023 * resolve operations to meet this requirement.
1025 * Unlike other drawing, fast clear operations are not properly
1026 * synchronized. The first PIPE_CONTROL here likely ensures that the
1027 * contents of the previous render or clear hit the render target before we
1028 * resolve and the second likely ensures that the resolve is complete before
1029 * we do any more rendering or clearing.
1031 cmd_buffer
->state
.pending_pipe_bits
|=
1032 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1034 for (uint32_t l
= 0; l
< level_count
; l
++) {
1035 uint32_t level
= base_level
+ l
;
1037 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1038 if (base_layer
>= aux_layers
)
1039 break; /* We will only get fewer layers as level increases */
1040 uint32_t level_layer_count
=
1041 MIN2(layer_count
, aux_layers
- base_layer
);
1043 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1044 uint32_t array_layer
= base_layer
+ a
;
1045 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
, aspect
,
1046 level
, array_layer
, resolve_op
,
1051 cmd_buffer
->state
.pending_pipe_bits
|=
1052 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1056 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1059 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1060 struct anv_render_pass
*pass
,
1061 const VkRenderPassBeginInfo
*begin
)
1063 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1064 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1066 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1068 if (pass
->attachment_count
> 0) {
1069 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1070 pass
->attachment_count
*
1071 sizeof(state
->attachments
[0]),
1072 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1073 if (state
->attachments
== NULL
) {
1074 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1075 return anv_batch_set_error(&cmd_buffer
->batch
,
1076 VK_ERROR_OUT_OF_HOST_MEMORY
);
1079 state
->attachments
= NULL
;
1082 /* Reserve one for the NULL state. */
1083 unsigned num_states
= 1;
1084 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1085 if (vk_format_is_color(pass
->attachments
[i
].format
))
1088 if (need_input_attachment_state(&pass
->attachments
[i
]))
1092 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1093 state
->render_pass_states
=
1094 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1095 num_states
* ss_stride
, isl_dev
->ss
.align
);
1097 struct anv_state next_state
= state
->render_pass_states
;
1098 next_state
.alloc_size
= isl_dev
->ss
.size
;
1100 state
->null_surface_state
= next_state
;
1101 next_state
.offset
+= ss_stride
;
1102 next_state
.map
+= ss_stride
;
1104 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1105 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1106 state
->attachments
[i
].color
.state
= next_state
;
1107 next_state
.offset
+= ss_stride
;
1108 next_state
.map
+= ss_stride
;
1111 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1112 state
->attachments
[i
].input
.state
= next_state
;
1113 next_state
.offset
+= ss_stride
;
1114 next_state
.map
+= ss_stride
;
1117 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1118 state
->render_pass_states
.alloc_size
);
1121 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1122 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1124 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1125 isl_extent3d(framebuffer
->width
,
1126 framebuffer
->height
,
1127 framebuffer
->layers
));
1129 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1130 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1131 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1132 VkImageAspectFlags clear_aspects
= 0;
1133 VkImageAspectFlags load_aspects
= 0;
1135 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1136 /* color attachment */
1137 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1138 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1139 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1140 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1143 /* depthstencil attachment */
1144 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1145 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1146 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1147 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1148 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1151 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1152 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1153 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1154 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1155 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1160 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1161 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1162 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1164 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1166 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1167 anv_assert(iview
->vk_format
== att
->format
);
1168 anv_assert(iview
->n_planes
== 1);
1170 union isl_color_value clear_color
= { .u32
= { 0, } };
1171 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1172 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1173 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1174 state
, i
, begin
->renderArea
,
1177 anv_image_fill_surface_state(cmd_buffer
->device
,
1179 VK_IMAGE_ASPECT_COLOR_BIT
,
1180 &iview
->planes
[0].isl
,
1181 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1182 state
->attachments
[i
].aux_usage
,
1185 &state
->attachments
[i
].color
,
1188 add_image_view_relocs(cmd_buffer
, iview
, 0,
1189 state
->attachments
[i
].color
);
1191 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1196 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1197 anv_image_fill_surface_state(cmd_buffer
->device
,
1199 VK_IMAGE_ASPECT_COLOR_BIT
,
1200 &iview
->planes
[0].isl
,
1201 ISL_SURF_USAGE_TEXTURE_BIT
,
1202 state
->attachments
[i
].input_aux_usage
,
1205 &state
->attachments
[i
].input
,
1208 add_image_view_relocs(cmd_buffer
, iview
, 0,
1209 state
->attachments
[i
].input
);
1218 genX(BeginCommandBuffer
)(
1219 VkCommandBuffer commandBuffer
,
1220 const VkCommandBufferBeginInfo
* pBeginInfo
)
1222 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1224 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1225 * command buffer's state. Otherwise, we must *reset* its state. In both
1226 * cases we reset it.
1228 * From the Vulkan 1.0 spec:
1230 * If a command buffer is in the executable state and the command buffer
1231 * was allocated from a command pool with the
1232 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1233 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1234 * as if vkResetCommandBuffer had been called with
1235 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1236 * the command buffer in the recording state.
1238 anv_cmd_buffer_reset(cmd_buffer
);
1240 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1242 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1243 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1245 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1247 /* We sometimes store vertex data in the dynamic state buffer for blorp
1248 * operations and our dynamic state stream may re-use data from previous
1249 * command buffers. In order to prevent stale cache data, we flush the VF
1250 * cache. We could do this on every blorp call but that's not really
1251 * needed as all of the data will get written by the CPU prior to the GPU
1252 * executing anything. The chances are fairly high that they will use
1253 * blorp at least once per primary command buffer so it shouldn't be
1256 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1257 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1259 /* We send an "Indirect State Pointers Disable" packet at
1260 * EndCommandBuffer, so all push contant packets are ignored during a
1261 * context restore. Documentation says after that command, we need to
1262 * emit push constants again before any rendering operation. So we
1263 * flag them dirty here to make sure they get emitted.
1265 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1267 VkResult result
= VK_SUCCESS
;
1268 if (cmd_buffer
->usage_flags
&
1269 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1270 assert(pBeginInfo
->pInheritanceInfo
);
1271 cmd_buffer
->state
.pass
=
1272 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1273 cmd_buffer
->state
.subpass
=
1274 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1276 /* This is optional in the inheritance info. */
1277 cmd_buffer
->state
.framebuffer
=
1278 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1280 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1281 cmd_buffer
->state
.pass
, NULL
);
1283 /* Record that HiZ is enabled if we can. */
1284 if (cmd_buffer
->state
.framebuffer
) {
1285 const struct anv_image_view
* const iview
=
1286 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1289 VkImageLayout layout
=
1290 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.layout
;
1292 enum isl_aux_usage aux_usage
=
1293 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1294 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1296 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1300 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1306 /* From the PRM, Volume 2a:
1308 * "Indirect State Pointers Disable
1310 * At the completion of the post-sync operation associated with this pipe
1311 * control packet, the indirect state pointers in the hardware are
1312 * considered invalid; the indirect pointers are not saved in the context.
1313 * If any new indirect state commands are executed in the command stream
1314 * while the pipe control is pending, the new indirect state commands are
1317 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1318 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1319 * commands are only considered as Indirect State Pointers. Once ISP is
1320 * issued in a context, SW must initialize by programming push constant
1321 * commands for all the shaders (at least to zero length) before attempting
1322 * any rendering operation for the same context."
1324 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1325 * even though they point to a BO that has been already unreferenced at
1326 * the end of the previous batch buffer. This has been fine so far since
1327 * we are protected by these scratch page (every address not covered by
1328 * a BO should be pointing to the scratch page). But on CNL, it is
1329 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1332 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1333 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1334 * context restore, so the mentioned hang doesn't happen. However,
1335 * software must program push constant commands for all stages prior to
1336 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1339 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1341 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1342 pc
.IndirectStatePointersDisable
= true;
1343 pc
.CommandStreamerStallEnable
= true;
1348 genX(EndCommandBuffer
)(
1349 VkCommandBuffer commandBuffer
)
1351 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1353 if (anv_batch_has_error(&cmd_buffer
->batch
))
1354 return cmd_buffer
->batch
.status
;
1356 /* We want every command buffer to start with the PMA fix in a known state,
1357 * so we disable it at the end of the command buffer.
1359 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1361 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1363 emit_isp_disable(cmd_buffer
);
1365 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1371 genX(CmdExecuteCommands
)(
1372 VkCommandBuffer commandBuffer
,
1373 uint32_t commandBufferCount
,
1374 const VkCommandBuffer
* pCmdBuffers
)
1376 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1378 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1380 if (anv_batch_has_error(&primary
->batch
))
1383 /* The secondary command buffers will assume that the PMA fix is disabled
1384 * when they begin executing. Make sure this is true.
1386 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1388 /* The secondary command buffer doesn't know which textures etc. have been
1389 * flushed prior to their execution. Apply those flushes now.
1391 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1393 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1394 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1396 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1397 assert(!anv_batch_has_error(&secondary
->batch
));
1399 if (secondary
->usage_flags
&
1400 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1401 /* If we're continuing a render pass from the primary, we need to
1402 * copy the surface states for the current subpass into the storage
1403 * we allocated for them in BeginCommandBuffer.
1405 struct anv_bo
*ss_bo
=
1406 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1407 struct anv_state src_state
= primary
->state
.render_pass_states
;
1408 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1409 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1411 genX(cmd_buffer_so_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
1412 ss_bo
, src_state
.offset
,
1413 src_state
.alloc_size
);
1416 anv_cmd_buffer_add_secondary(primary
, secondary
);
1419 /* The secondary may have selected a different pipeline (3D or compute) and
1420 * may have changed the current L3$ configuration. Reset our tracking
1421 * variables to invalid values to ensure that we re-emit these in the case
1422 * where we do any draws or compute dispatches from the primary after the
1423 * secondary has returned.
1425 primary
->state
.current_pipeline
= UINT32_MAX
;
1426 primary
->state
.current_l3_config
= NULL
;
1428 /* Each of the secondary command buffers will use its own state base
1429 * address. We need to re-emit state base address for the primary after
1430 * all of the secondaries are done.
1432 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1435 genX(cmd_buffer_emit_state_base_address
)(primary
);
1438 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1439 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1440 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1443 * Program the hardware to use the specified L3 configuration.
1446 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1447 const struct gen_l3_config
*cfg
)
1450 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1453 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1454 intel_logd("L3 config transition: ");
1455 gen_dump_l3_config(cfg
, stderr
);
1458 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1460 /* According to the hardware docs, the L3 partitioning can only be changed
1461 * while the pipeline is completely drained and the caches are flushed,
1462 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1464 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1465 pc
.DCFlushEnable
= true;
1466 pc
.PostSyncOperation
= NoWrite
;
1467 pc
.CommandStreamerStallEnable
= true;
1470 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1471 * invalidation of the relevant caches. Note that because RO invalidation
1472 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1473 * command is processed by the CS) we cannot combine it with the previous
1474 * stalling flush as the hardware documentation suggests, because that
1475 * would cause the CS to stall on previous rendering *after* RO
1476 * invalidation and wouldn't prevent the RO caches from being polluted by
1477 * concurrent rendering before the stall completes. This intentionally
1478 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1479 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1480 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1481 * already guarantee that there is no concurrent GPGPU kernel execution
1482 * (see SKL HSD 2132585).
1484 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1485 pc
.TextureCacheInvalidationEnable
= true;
1486 pc
.ConstantCacheInvalidationEnable
= true;
1487 pc
.InstructionCacheInvalidateEnable
= true;
1488 pc
.StateCacheInvalidationEnable
= true;
1489 pc
.PostSyncOperation
= NoWrite
;
1492 /* Now send a third stalling flush to make sure that invalidation is
1493 * complete when the L3 configuration registers are modified.
1495 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1496 pc
.DCFlushEnable
= true;
1497 pc
.PostSyncOperation
= NoWrite
;
1498 pc
.CommandStreamerStallEnable
= true;
1503 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1506 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1507 .SLMEnable
= has_slm
,
1508 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1509 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1510 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1511 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1513 /* Set up the L3 partitioning. */
1514 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1518 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1519 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1520 cfg
->n
[GEN_L3P_ALL
];
1521 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1522 cfg
->n
[GEN_L3P_ALL
];
1523 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1524 cfg
->n
[GEN_L3P_ALL
];
1526 assert(!cfg
->n
[GEN_L3P_ALL
]);
1528 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1529 * the matching space on the remaining banks has to be allocated to a
1530 * client (URB for all validated configurations) set to the
1531 * lower-bandwidth 2-bank address hashing mode.
1533 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1534 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1535 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1537 /* Minimum number of ways that can be allocated to the URB. */
1538 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1539 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1541 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1542 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1543 .ConvertDC_UC
= !has_dc
,
1544 .ConvertIS_UC
= !has_is
,
1545 .ConvertC_UC
= !has_c
,
1546 .ConvertT_UC
= !has_t
);
1548 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1549 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1550 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1552 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1553 .SLMEnable
= has_slm
,
1554 .URBLowBandwidth
= urb_low_bw
,
1555 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1557 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1559 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1560 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1562 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1563 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1564 .ISLowBandwidth
= 0,
1565 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1567 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1568 .TLowBandwidth
= 0);
1570 /* Set up the L3 partitioning. */
1571 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1572 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1573 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1576 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1577 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1578 * them disabled to avoid crashing the system hard.
1580 uint32_t scratch1
, chicken3
;
1581 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1582 .L3AtomicDisable
= !has_dc
);
1583 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1584 .L3AtomicDisableMask
= true,
1585 .L3AtomicDisable
= !has_dc
);
1586 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1587 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1593 cmd_buffer
->state
.current_l3_config
= cfg
;
1597 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1599 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1601 /* Flushes are pipelined while invalidations are handled immediately.
1602 * Therefore, if we're flushing anything then we need to schedule a stall
1603 * before any invalidations can happen.
1605 if (bits
& ANV_PIPE_FLUSH_BITS
)
1606 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1608 /* If we're going to do an invalidate and we have a pending CS stall that
1609 * has yet to be resolved, we do the CS stall now.
1611 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1612 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1613 bits
|= ANV_PIPE_CS_STALL_BIT
;
1614 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1617 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1618 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1619 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1620 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1621 pipe
.RenderTargetCacheFlushEnable
=
1622 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1624 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1625 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1626 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1629 * According to the Broadwell documentation, any PIPE_CONTROL with the
1630 * "Command Streamer Stall" bit set must also have another bit set,
1631 * with five different options:
1633 * - Render Target Cache Flush
1634 * - Depth Cache Flush
1635 * - Stall at Pixel Scoreboard
1636 * - Post-Sync Operation
1640 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1641 * mesa and it seems to work fine. The choice is fairly arbitrary.
1643 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1644 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1645 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1646 pipe
.StallAtPixelScoreboard
= true;
1649 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1652 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1653 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1654 pipe
.StateCacheInvalidationEnable
=
1655 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1656 pipe
.ConstantCacheInvalidationEnable
=
1657 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1658 pipe
.VFCacheInvalidationEnable
=
1659 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1660 pipe
.TextureCacheInvalidationEnable
=
1661 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1662 pipe
.InstructionCacheInvalidateEnable
=
1663 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1666 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1669 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1672 void genX(CmdPipelineBarrier
)(
1673 VkCommandBuffer commandBuffer
,
1674 VkPipelineStageFlags srcStageMask
,
1675 VkPipelineStageFlags destStageMask
,
1677 uint32_t memoryBarrierCount
,
1678 const VkMemoryBarrier
* pMemoryBarriers
,
1679 uint32_t bufferMemoryBarrierCount
,
1680 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1681 uint32_t imageMemoryBarrierCount
,
1682 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1684 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1686 /* XXX: Right now, we're really dumb and just flush whatever categories
1687 * the app asks for. One of these days we may make this a bit better
1688 * but right now that's all the hardware allows for in most areas.
1690 VkAccessFlags src_flags
= 0;
1691 VkAccessFlags dst_flags
= 0;
1693 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1694 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1695 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1698 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1699 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1700 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1703 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1704 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1705 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1706 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1707 const VkImageSubresourceRange
*range
=
1708 &pImageMemoryBarriers
[i
].subresourceRange
;
1710 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1711 transition_depth_buffer(cmd_buffer
, image
,
1712 pImageMemoryBarriers
[i
].oldLayout
,
1713 pImageMemoryBarriers
[i
].newLayout
);
1714 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1715 VkImageAspectFlags color_aspects
=
1716 anv_image_expand_aspects(image
, range
->aspectMask
);
1717 uint32_t aspect_bit
;
1719 uint32_t base_layer
, layer_count
;
1720 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1722 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1724 base_layer
= range
->baseArrayLayer
;
1725 layer_count
= anv_get_layerCount(image
, range
);
1728 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1729 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1730 range
->baseMipLevel
,
1731 anv_get_levelCount(image
, range
),
1732 base_layer
, layer_count
,
1733 pImageMemoryBarriers
[i
].oldLayout
,
1734 pImageMemoryBarriers
[i
].newLayout
);
1739 cmd_buffer
->state
.pending_pipe_bits
|=
1740 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1741 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1745 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1747 VkShaderStageFlags stages
=
1748 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1750 /* In order to avoid thrash, we assume that vertex and fragment stages
1751 * always exist. In the rare case where one is missing *and* the other
1752 * uses push concstants, this may be suboptimal. However, avoiding stalls
1753 * seems more important.
1755 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1757 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1761 const unsigned push_constant_kb
= 32;
1762 #elif GEN_IS_HASWELL
1763 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1765 const unsigned push_constant_kb
= 16;
1768 const unsigned num_stages
=
1769 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1770 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1772 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1773 * units of 2KB. Incidentally, these are the same platforms that have
1774 * 32KB worth of push constant space.
1776 if (push_constant_kb
== 32)
1777 size_per_stage
&= ~1u;
1779 uint32_t kb_used
= 0;
1780 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1781 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1782 anv_batch_emit(&cmd_buffer
->batch
,
1783 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1784 alloc
._3DCommandSubOpcode
= 18 + i
;
1785 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1786 alloc
.ConstantBufferSize
= push_size
;
1788 kb_used
+= push_size
;
1791 anv_batch_emit(&cmd_buffer
->batch
,
1792 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1793 alloc
.ConstantBufferOffset
= kb_used
;
1794 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1797 cmd_buffer
->state
.push_constant_stages
= stages
;
1799 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1801 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1802 * the next 3DPRIMITIVE command after programming the
1803 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1805 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1806 * pipeline setup, we need to dirty push constants.
1808 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1811 static const struct anv_descriptor
*
1812 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1813 const struct anv_pipeline_binding
*binding
)
1815 assert(binding
->set
< MAX_SETS
);
1816 const struct anv_descriptor_set
*set
=
1817 pipe_state
->descriptors
[binding
->set
];
1818 const uint32_t offset
=
1819 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1820 return &set
->descriptors
[offset
+ binding
->index
];
1824 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1825 const struct anv_pipeline_binding
*binding
)
1827 assert(binding
->set
< MAX_SETS
);
1828 const struct anv_descriptor_set
*set
=
1829 pipe_state
->descriptors
[binding
->set
];
1831 uint32_t dynamic_offset_idx
=
1832 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1833 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1836 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1840 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1841 gl_shader_stage stage
,
1842 struct anv_state
*bt_state
)
1844 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1845 struct anv_cmd_pipeline_state
*pipe_state
;
1846 struct anv_pipeline
*pipeline
;
1847 uint32_t bias
, state_offset
;
1850 case MESA_SHADER_COMPUTE
:
1851 pipe_state
= &cmd_buffer
->state
.compute
.base
;
1855 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
1859 pipeline
= pipe_state
->pipeline
;
1861 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1862 *bt_state
= (struct anv_state
) { 0, };
1866 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1867 if (bias
+ map
->surface_count
== 0) {
1868 *bt_state
= (struct anv_state
) { 0, };
1872 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1873 bias
+ map
->surface_count
,
1875 uint32_t *bt_map
= bt_state
->map
;
1877 if (bt_state
->map
== NULL
)
1878 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1880 if (stage
== MESA_SHADER_COMPUTE
&&
1881 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
1882 struct anv_bo
*bo
= cmd_buffer
->state
.compute
.num_workgroups
.bo
;
1883 uint32_t bo_offset
= cmd_buffer
->state
.compute
.num_workgroups
.offset
;
1885 struct anv_state surface_state
;
1887 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1889 const enum isl_format format
=
1890 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1891 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1892 format
, bo_offset
, 12, 1);
1894 bt_map
[0] = surface_state
.offset
+ state_offset
;
1895 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1898 if (map
->surface_count
== 0)
1901 if (map
->image_count
> 0) {
1903 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1904 if (result
!= VK_SUCCESS
)
1907 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1911 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1912 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1914 struct anv_state surface_state
;
1916 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1917 /* Color attachment binding */
1918 assert(stage
== MESA_SHADER_FRAGMENT
);
1919 assert(binding
->binding
== 0);
1920 if (binding
->index
< subpass
->color_count
) {
1921 const unsigned att
=
1922 subpass
->color_attachments
[binding
->index
].attachment
;
1924 /* From the Vulkan 1.0.46 spec:
1926 * "If any color or depth/stencil attachments are
1927 * VK_ATTACHMENT_UNUSED, then no writes occur for those
1930 if (att
== VK_ATTACHMENT_UNUSED
) {
1931 surface_state
= cmd_buffer
->state
.null_surface_state
;
1933 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
1936 surface_state
= cmd_buffer
->state
.null_surface_state
;
1939 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1943 const struct anv_descriptor
*desc
=
1944 anv_descriptor_for_binding(pipe_state
, binding
);
1946 switch (desc
->type
) {
1947 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1948 /* Nothing for us to do here */
1951 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1952 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
1953 struct anv_surface_state sstate
=
1954 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
1955 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
1956 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
1957 surface_state
= sstate
.state
;
1958 assert(surface_state
.alloc_size
);
1959 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1960 binding
->plane
, sstate
);
1963 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1964 assert(stage
== MESA_SHADER_FRAGMENT
);
1965 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
1966 /* For depth and stencil input attachments, we treat it like any
1967 * old texture that a user may have bound.
1969 struct anv_surface_state sstate
=
1970 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
1971 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
1972 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
1973 surface_state
= sstate
.state
;
1974 assert(surface_state
.alloc_size
);
1975 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1976 binding
->plane
, sstate
);
1978 /* For color input attachments, we create the surface state at
1979 * vkBeginRenderPass time so that we can include aux and clear
1980 * color information.
1982 assert(binding
->input_attachment_index
< subpass
->input_count
);
1983 const unsigned subpass_att
= binding
->input_attachment_index
;
1984 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
1985 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
1989 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1990 struct anv_surface_state sstate
= (binding
->write_only
)
1991 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
1992 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
1993 surface_state
= sstate
.state
;
1994 assert(surface_state
.alloc_size
);
1995 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1996 binding
->plane
, sstate
);
1998 struct brw_image_param
*image_param
=
1999 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2001 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2002 image_param
->surface_idx
= bias
+ s
;
2006 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2007 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2008 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2009 surface_state
= desc
->buffer_view
->surface_state
;
2010 assert(surface_state
.alloc_size
);
2011 add_surface_state_reloc(cmd_buffer
, surface_state
,
2012 desc
->buffer_view
->bo
,
2013 desc
->buffer_view
->offset
);
2016 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2017 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2018 /* Compute the offset within the buffer */
2019 uint32_t dynamic_offset
=
2020 dynamic_offset_for_binding(pipe_state
, binding
);
2021 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2022 /* Clamp to the buffer size */
2023 offset
= MIN2(offset
, desc
->buffer
->size
);
2024 /* Clamp the range to the buffer size */
2025 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2028 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2029 enum isl_format format
=
2030 anv_isl_format_for_descriptor_type(desc
->type
);
2032 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2033 format
, offset
, range
, 1);
2034 add_surface_state_reloc(cmd_buffer
, surface_state
,
2036 desc
->buffer
->offset
+ offset
);
2040 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2041 surface_state
= (binding
->write_only
)
2042 ? desc
->buffer_view
->writeonly_storage_surface_state
2043 : desc
->buffer_view
->storage_surface_state
;
2044 assert(surface_state
.alloc_size
);
2045 add_surface_state_reloc(cmd_buffer
, surface_state
,
2046 desc
->buffer_view
->bo
,
2047 desc
->buffer_view
->offset
);
2049 struct brw_image_param
*image_param
=
2050 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2052 *image_param
= desc
->buffer_view
->storage_image_param
;
2053 image_param
->surface_idx
= bias
+ s
;
2057 assert(!"Invalid descriptor type");
2061 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2063 assert(image
== map
->image_count
);
2066 anv_state_flush(cmd_buffer
->device
, *bt_state
);
2069 /* The PIPE_CONTROL command description says:
2071 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2072 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2073 * Target Cache Flush by enabling this bit. When render target flush
2074 * is set due to new association of BTI, PS Scoreboard Stall bit must
2075 * be set in this packet."
2077 * FINISHME: Currently we shuffle around the surface states in the binding
2078 * table based on if they are getting used or not. So, we've to do below
2079 * pipe control flush for every binding table upload. Make changes so
2080 * that we do it only when we modify render target surface states.
2082 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2083 pc
.RenderTargetCacheFlushEnable
= true;
2084 pc
.StallAtPixelScoreboard
= true;
2092 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2093 gl_shader_stage stage
,
2094 struct anv_state
*state
)
2096 struct anv_cmd_pipeline_state
*pipe_state
=
2097 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2098 &cmd_buffer
->state
.gfx
.base
;
2099 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2101 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2102 *state
= (struct anv_state
) { 0, };
2106 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2107 if (map
->sampler_count
== 0) {
2108 *state
= (struct anv_state
) { 0, };
2112 uint32_t size
= map
->sampler_count
* 16;
2113 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2115 if (state
->map
== NULL
)
2116 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2118 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2119 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2120 const struct anv_descriptor
*desc
=
2121 anv_descriptor_for_binding(pipe_state
, binding
);
2123 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2124 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2127 struct anv_sampler
*sampler
= desc
->sampler
;
2129 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2130 * happens to be zero.
2132 if (sampler
== NULL
)
2135 memcpy(state
->map
+ (s
* 16),
2136 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2139 anv_state_flush(cmd_buffer
->device
, *state
);
2145 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2147 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2149 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2150 pipeline
->active_stages
;
2152 VkResult result
= VK_SUCCESS
;
2153 anv_foreach_stage(s
, dirty
) {
2154 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2155 if (result
!= VK_SUCCESS
)
2157 result
= emit_binding_table(cmd_buffer
, s
,
2158 &cmd_buffer
->state
.binding_tables
[s
]);
2159 if (result
!= VK_SUCCESS
)
2163 if (result
!= VK_SUCCESS
) {
2164 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2166 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2167 if (result
!= VK_SUCCESS
)
2170 /* Re-emit state base addresses so we get the new surface state base
2171 * address before we start emitting binding tables etc.
2173 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2175 /* Re-emit all active binding tables */
2176 dirty
|= pipeline
->active_stages
;
2177 anv_foreach_stage(s
, dirty
) {
2178 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2179 if (result
!= VK_SUCCESS
) {
2180 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2183 result
= emit_binding_table(cmd_buffer
, s
,
2184 &cmd_buffer
->state
.binding_tables
[s
]);
2185 if (result
!= VK_SUCCESS
) {
2186 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2192 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2198 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2201 static const uint32_t sampler_state_opcodes
[] = {
2202 [MESA_SHADER_VERTEX
] = 43,
2203 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2204 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2205 [MESA_SHADER_GEOMETRY
] = 46,
2206 [MESA_SHADER_FRAGMENT
] = 47,
2207 [MESA_SHADER_COMPUTE
] = 0,
2210 static const uint32_t binding_table_opcodes
[] = {
2211 [MESA_SHADER_VERTEX
] = 38,
2212 [MESA_SHADER_TESS_CTRL
] = 39,
2213 [MESA_SHADER_TESS_EVAL
] = 40,
2214 [MESA_SHADER_GEOMETRY
] = 41,
2215 [MESA_SHADER_FRAGMENT
] = 42,
2216 [MESA_SHADER_COMPUTE
] = 0,
2219 anv_foreach_stage(s
, stages
) {
2220 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2221 assert(binding_table_opcodes
[s
] > 0);
2223 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2224 anv_batch_emit(&cmd_buffer
->batch
,
2225 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2226 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2227 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2231 /* Always emit binding table pointers if we're asked to, since on SKL
2232 * this is what flushes push constants. */
2233 anv_batch_emit(&cmd_buffer
->batch
,
2234 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2235 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2236 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2242 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2243 VkShaderStageFlags dirty_stages
)
2245 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2246 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2248 static const uint32_t push_constant_opcodes
[] = {
2249 [MESA_SHADER_VERTEX
] = 21,
2250 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2251 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2252 [MESA_SHADER_GEOMETRY
] = 22,
2253 [MESA_SHADER_FRAGMENT
] = 23,
2254 [MESA_SHADER_COMPUTE
] = 0,
2257 VkShaderStageFlags flushed
= 0;
2259 anv_foreach_stage(stage
, dirty_stages
) {
2260 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2261 assert(push_constant_opcodes
[stage
] > 0);
2263 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2264 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2266 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2267 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2268 const struct brw_stage_prog_data
*prog_data
=
2269 pipeline
->shaders
[stage
]->prog_data
;
2270 const struct anv_pipeline_bind_map
*bind_map
=
2271 &pipeline
->shaders
[stage
]->bind_map
;
2273 /* The Skylake PRM contains the following restriction:
2275 * "The driver must ensure The following case does not occur
2276 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2277 * buffer 3 read length equal to zero committed followed by a
2278 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2281 * To avoid this, we program the buffers in the highest slots.
2282 * This way, slot 0 is only used if slot 3 is also used.
2286 for (int i
= 3; i
>= 0; i
--) {
2287 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2288 if (range
->length
== 0)
2291 const unsigned surface
=
2292 prog_data
->binding_table
.ubo_start
+ range
->block
;
2294 assert(surface
<= bind_map
->surface_count
);
2295 const struct anv_pipeline_binding
*binding
=
2296 &bind_map
->surface_to_descriptor
[surface
];
2298 const struct anv_descriptor
*desc
=
2299 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2301 struct anv_address read_addr
;
2303 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2304 read_len
= MIN2(range
->length
,
2305 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2306 read_addr
= (struct anv_address
) {
2307 .bo
= desc
->buffer_view
->bo
,
2308 .offset
= desc
->buffer_view
->offset
+
2312 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2314 uint32_t dynamic_offset
=
2315 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2316 uint32_t buf_offset
=
2317 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2318 uint32_t buf_range
=
2319 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2321 read_len
= MIN2(range
->length
,
2322 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2323 read_addr
= (struct anv_address
) {
2324 .bo
= desc
->buffer
->bo
,
2325 .offset
= desc
->buffer
->offset
+ buf_offset
+
2331 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2332 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2337 struct anv_state state
=
2338 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2340 if (state
.alloc_size
> 0) {
2341 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2342 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2343 .offset
= state
.offset
,
2345 c
.ConstantBody
.ReadLength
[n
] =
2346 DIV_ROUND_UP(state
.alloc_size
, 32);
2349 /* For Ivy Bridge, the push constants packets have a different
2350 * rule that would require us to iterate in the other direction
2351 * and possibly mess around with dynamic state base address.
2352 * Don't bother; just emit regular push constants at n = 0.
2354 struct anv_state state
=
2355 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2357 if (state
.alloc_size
> 0) {
2358 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2359 c
.ConstantBody
.ReadLength
[0] =
2360 DIV_ROUND_UP(state
.alloc_size
, 32);
2366 flushed
|= mesa_to_vk_shader_stage(stage
);
2369 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2373 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2375 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2378 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2380 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2382 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2384 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2387 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2388 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2390 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2391 GENX(3DSTATE_VERTEX_BUFFERS
));
2393 for_each_bit(vb
, vb_emit
) {
2394 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2395 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2397 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2398 .VertexBufferIndex
= vb
,
2401 .MemoryObjectControlState
= GENX(MOCS
),
2403 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
2404 /* Our implementation of VK_KHR_multiview uses instancing to draw
2405 * the different views. If the client asks for instancing, we
2406 * need to use the Instance Data Step Rate to ensure that we
2407 * repeat the client's per-instance data once for each view.
2409 .InstanceDataStepRate
= anv_subpass_view_count(pipeline
->subpass
),
2410 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2413 .AddressModifyEnable
= true,
2414 .BufferPitch
= pipeline
->binding_stride
[vb
],
2415 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
2418 .BufferSize
= buffer
->size
- offset
2420 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
2424 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2429 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2431 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2432 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2434 /* The exact descriptor layout is pulled from the pipeline, so we need
2435 * to re-emit binding tables on every pipeline change.
2437 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2439 /* If the pipeline changed, we may need to re-allocate push constant
2442 cmd_buffer_alloc_push_constants(cmd_buffer
);
2446 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2447 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2448 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2450 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2451 * stall needs to be sent just prior to any 3DSTATE_VS,
2452 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2453 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2454 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2455 * PIPE_CONTROL needs to be sent before any combination of VS
2456 * associated 3DSTATE."
2458 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2459 pc
.DepthStallEnable
= true;
2460 pc
.PostSyncOperation
= WriteImmediateData
;
2462 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2467 /* Render targets live in the same binding table as fragment descriptors */
2468 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2469 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2471 /* We emit the binding tables and sampler tables first, then emit push
2472 * constants and then finally emit binding table and sampler table
2473 * pointers. It has to happen in this order, since emitting the binding
2474 * tables may change the push constants (in case of storage images). After
2475 * emitting push constants, on SKL+ we have to emit the corresponding
2476 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2479 if (cmd_buffer
->state
.descriptors_dirty
)
2480 dirty
= flush_descriptor_sets(cmd_buffer
);
2482 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2483 /* Because we're pushing UBOs, we have to push whenever either
2484 * descriptors or push constants is dirty.
2486 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2487 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2488 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2492 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2494 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2495 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2497 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2498 ANV_CMD_DIRTY_PIPELINE
)) {
2499 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2500 pipeline
->depth_clamp_enable
);
2503 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
2504 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2506 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2508 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2512 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2513 struct anv_bo
*bo
, uint32_t offset
,
2514 uint32_t size
, uint32_t index
)
2516 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2517 GENX(3DSTATE_VERTEX_BUFFERS
));
2519 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2520 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2521 .VertexBufferIndex
= index
,
2522 .AddressModifyEnable
= true,
2525 .MemoryObjectControlState
= GENX(MOCS
),
2526 .BufferStartingAddress
= { bo
, offset
},
2529 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2530 .BufferStartingAddress
= { bo
, offset
},
2531 .EndAddress
= { bo
, offset
+ size
},
2537 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2538 struct anv_bo
*bo
, uint32_t offset
)
2540 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
2544 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2545 uint32_t base_vertex
, uint32_t base_instance
)
2547 struct anv_state id_state
=
2548 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2550 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2551 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2553 anv_state_flush(cmd_buffer
->device
, id_state
);
2555 emit_base_vertex_instance_bo(cmd_buffer
,
2556 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
, id_state
.offset
);
2560 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2562 struct anv_state state
=
2563 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2565 ((uint32_t *)state
.map
)[0] = draw_index
;
2567 anv_state_flush(cmd_buffer
->device
, state
);
2569 emit_vertex_bo(cmd_buffer
,
2570 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2571 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
2575 VkCommandBuffer commandBuffer
,
2576 uint32_t vertexCount
,
2577 uint32_t instanceCount
,
2578 uint32_t firstVertex
,
2579 uint32_t firstInstance
)
2581 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2582 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2583 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2585 if (anv_batch_has_error(&cmd_buffer
->batch
))
2588 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2590 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2591 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2592 if (vs_prog_data
->uses_drawid
)
2593 emit_draw_index(cmd_buffer
, 0);
2595 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2596 * different views. We need to multiply instanceCount by the view count.
2598 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2600 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2601 prim
.VertexAccessType
= SEQUENTIAL
;
2602 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2603 prim
.VertexCountPerInstance
= vertexCount
;
2604 prim
.StartVertexLocation
= firstVertex
;
2605 prim
.InstanceCount
= instanceCount
;
2606 prim
.StartInstanceLocation
= firstInstance
;
2607 prim
.BaseVertexLocation
= 0;
2611 void genX(CmdDrawIndexed
)(
2612 VkCommandBuffer commandBuffer
,
2613 uint32_t indexCount
,
2614 uint32_t instanceCount
,
2615 uint32_t firstIndex
,
2616 int32_t vertexOffset
,
2617 uint32_t firstInstance
)
2619 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2620 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2621 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2623 if (anv_batch_has_error(&cmd_buffer
->batch
))
2626 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2628 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2629 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2630 if (vs_prog_data
->uses_drawid
)
2631 emit_draw_index(cmd_buffer
, 0);
2633 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2634 * different views. We need to multiply instanceCount by the view count.
2636 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2638 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2639 prim
.VertexAccessType
= RANDOM
;
2640 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2641 prim
.VertexCountPerInstance
= indexCount
;
2642 prim
.StartVertexLocation
= firstIndex
;
2643 prim
.InstanceCount
= instanceCount
;
2644 prim
.StartInstanceLocation
= firstInstance
;
2645 prim
.BaseVertexLocation
= vertexOffset
;
2649 /* Auto-Draw / Indirect Registers */
2650 #define GEN7_3DPRIM_END_OFFSET 0x2420
2651 #define GEN7_3DPRIM_START_VERTEX 0x2430
2652 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2653 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2654 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2655 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2657 /* MI_MATH only exists on Haswell+ */
2658 #if GEN_IS_HASWELL || GEN_GEN >= 8
2660 /* Emit dwords to multiply GPR0 by N */
2662 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2664 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2666 #define append_alu(opcode, operand1, operand2) \
2667 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2670 unsigned top_bit
= 31 - __builtin_clz(N
);
2671 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2672 /* We get our initial data in GPR0 and we write the final data out to
2673 * GPR0 but we use GPR1 as our scratch register.
2675 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2676 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2678 /* Shift the current value left by 1 */
2679 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2680 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2681 append_alu(MI_ALU_ADD
, 0, 0);
2684 /* Store ACCU to R1 and add R0 to R1 */
2685 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2686 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2687 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2688 append_alu(MI_ALU_ADD
, 0, 0);
2691 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2698 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2700 uint32_t num_dwords
;
2701 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2703 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2704 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2707 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2710 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2711 struct anv_buffer
*buffer
, uint64_t offset
,
2714 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2715 struct anv_bo
*bo
= buffer
->bo
;
2716 uint32_t bo_offset
= buffer
->offset
+ offset
;
2718 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
2720 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2721 if (view_count
> 1) {
2722 #if GEN_IS_HASWELL || GEN_GEN >= 8
2723 emit_lrm(batch
, CS_GPR(0), bo
, bo_offset
+ 4);
2724 emit_mul_gpr0(batch
, view_count
);
2725 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2727 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2728 "MI_MATH is not supported on Ivy Bridge");
2729 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2732 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2735 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
2738 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
2739 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
2741 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
2742 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2746 void genX(CmdDrawIndirect
)(
2747 VkCommandBuffer commandBuffer
,
2749 VkDeviceSize offset
,
2753 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2754 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2755 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2756 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2758 if (anv_batch_has_error(&cmd_buffer
->batch
))
2761 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2763 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2764 struct anv_bo
*bo
= buffer
->bo
;
2765 uint32_t bo_offset
= buffer
->offset
+ offset
;
2767 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2768 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
2769 if (vs_prog_data
->uses_drawid
)
2770 emit_draw_index(cmd_buffer
, i
);
2772 load_indirect_parameters(cmd_buffer
, buffer
, offset
, false);
2774 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2775 prim
.IndirectParameterEnable
= true;
2776 prim
.VertexAccessType
= SEQUENTIAL
;
2777 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2784 void genX(CmdDrawIndexedIndirect
)(
2785 VkCommandBuffer commandBuffer
,
2787 VkDeviceSize offset
,
2791 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2792 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2793 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2794 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2796 if (anv_batch_has_error(&cmd_buffer
->batch
))
2799 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2801 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2802 struct anv_bo
*bo
= buffer
->bo
;
2803 uint32_t bo_offset
= buffer
->offset
+ offset
;
2805 /* TODO: We need to stomp base vertex to 0 somehow */
2806 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2807 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
2808 if (vs_prog_data
->uses_drawid
)
2809 emit_draw_index(cmd_buffer
, i
);
2811 load_indirect_parameters(cmd_buffer
, buffer
, offset
, true);
2813 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2814 prim
.IndirectParameterEnable
= true;
2815 prim
.VertexAccessType
= RANDOM
;
2816 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2824 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2826 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2827 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2830 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2831 if (result
!= VK_SUCCESS
) {
2832 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2834 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2835 if (result
!= VK_SUCCESS
)
2838 /* Re-emit state base addresses so we get the new surface state base
2839 * address before we start emitting binding tables etc.
2841 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2843 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2844 if (result
!= VK_SUCCESS
) {
2845 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2850 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
2851 if (result
!= VK_SUCCESS
) {
2852 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2856 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
2857 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2858 .BindingTablePointer
= surfaces
.offset
,
2859 .SamplerStatePointer
= samplers
.offset
,
2861 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
2863 struct anv_state state
=
2864 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
2865 pipeline
->interface_descriptor_data
,
2866 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
2869 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
2870 anv_batch_emit(&cmd_buffer
->batch
,
2871 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
2872 mid
.InterfaceDescriptorTotalLength
= size
;
2873 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
2880 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2882 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2883 MAYBE_UNUSED VkResult result
;
2885 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
2887 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2889 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
2891 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
2892 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
2894 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
2895 * the only bits that are changed are scoreboard related: Scoreboard
2896 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
2897 * these scoreboard related states, a MEDIA_STATE_FLUSH is
2900 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2901 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2903 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2906 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
2907 cmd_buffer
->state
.compute
.pipeline_dirty
) {
2908 /* FIXME: figure out descriptors for gen7 */
2909 result
= flush_compute_descriptor_set(cmd_buffer
);
2910 if (result
!= VK_SUCCESS
)
2913 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
2916 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
2917 struct anv_state push_state
=
2918 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
2920 if (push_state
.alloc_size
) {
2921 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
2922 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
2923 curbe
.CURBEDataStartAddress
= push_state
.offset
;
2928 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
2930 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2936 verify_cmd_parser(const struct anv_device
*device
,
2937 int required_version
,
2938 const char *function
)
2940 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
2941 return vk_errorf(device
->instance
, device
->instance
,
2942 VK_ERROR_FEATURE_NOT_PRESENT
,
2943 "cmd parser version %d is required for %s",
2944 required_version
, function
);
2952 void genX(CmdDispatch
)(
2953 VkCommandBuffer commandBuffer
,
2958 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2959 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2960 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
2962 if (anv_batch_has_error(&cmd_buffer
->batch
))
2965 if (prog_data
->uses_num_work_groups
) {
2966 struct anv_state state
=
2967 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
2968 uint32_t *sizes
= state
.map
;
2972 anv_state_flush(cmd_buffer
->device
, state
);
2973 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
2974 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2975 .offset
= state
.offset
,
2979 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2981 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
2982 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2983 ggw
.ThreadDepthCounterMaximum
= 0;
2984 ggw
.ThreadHeightCounterMaximum
= 0;
2985 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2986 ggw
.ThreadGroupIDXDimension
= x
;
2987 ggw
.ThreadGroupIDYDimension
= y
;
2988 ggw
.ThreadGroupIDZDimension
= z
;
2989 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2990 ggw
.BottomExecutionMask
= 0xffffffff;
2993 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2996 #define GPGPU_DISPATCHDIMX 0x2500
2997 #define GPGPU_DISPATCHDIMY 0x2504
2998 #define GPGPU_DISPATCHDIMZ 0x2508
3000 void genX(CmdDispatchIndirect
)(
3001 VkCommandBuffer commandBuffer
,
3003 VkDeviceSize offset
)
3005 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3006 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3007 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3008 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3009 struct anv_bo
*bo
= buffer
->bo
;
3010 uint32_t bo_offset
= buffer
->offset
+ offset
;
3011 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3014 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3015 * indirect dispatch registers to be written.
3017 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3018 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3022 if (prog_data
->uses_num_work_groups
) {
3023 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3025 .offset
= bo_offset
,
3029 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3031 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
3032 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
3033 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
3036 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3037 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3038 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3039 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3041 /* Load compute_dispatch_indirect_x_size into SRC0 */
3042 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
3044 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3045 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3046 mip
.LoadOperation
= LOAD_LOAD
;
3047 mip
.CombineOperation
= COMBINE_SET
;
3048 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3051 /* Load compute_dispatch_indirect_y_size into SRC0 */
3052 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
3054 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3055 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3056 mip
.LoadOperation
= LOAD_LOAD
;
3057 mip
.CombineOperation
= COMBINE_OR
;
3058 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3061 /* Load compute_dispatch_indirect_z_size into SRC0 */
3062 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
3064 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3065 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3066 mip
.LoadOperation
= LOAD_LOAD
;
3067 mip
.CombineOperation
= COMBINE_OR
;
3068 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3071 /* predicate = !predicate; */
3072 #define COMPARE_FALSE 1
3073 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3074 mip
.LoadOperation
= LOAD_LOADINV
;
3075 mip
.CombineOperation
= COMBINE_OR
;
3076 mip
.CompareOperation
= COMPARE_FALSE
;
3080 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3081 ggw
.IndirectParameterEnable
= true;
3082 ggw
.PredicateEnable
= GEN_GEN
<= 7;
3083 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3084 ggw
.ThreadDepthCounterMaximum
= 0;
3085 ggw
.ThreadHeightCounterMaximum
= 0;
3086 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3087 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3088 ggw
.BottomExecutionMask
= 0xffffffff;
3091 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3095 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3098 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3100 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3103 #if GEN_GEN >= 8 && GEN_GEN < 10
3104 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3106 * Software must clear the COLOR_CALC_STATE Valid field in
3107 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3108 * with Pipeline Select set to GPGPU.
3110 * The internal hardware docs recommend the same workaround for Gen9
3113 if (pipeline
== GPGPU
)
3114 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3117 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3118 * PIPELINE_SELECT [DevBWR+]":
3122 * Software must ensure all the write caches are flushed through a
3123 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3124 * command to invalidate read only caches prior to programming
3125 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3127 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3128 pc
.RenderTargetCacheFlushEnable
= true;
3129 pc
.DepthCacheFlushEnable
= true;
3130 pc
.DCFlushEnable
= true;
3131 pc
.PostSyncOperation
= NoWrite
;
3132 pc
.CommandStreamerStallEnable
= true;
3135 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3136 pc
.TextureCacheInvalidationEnable
= true;
3137 pc
.ConstantCacheInvalidationEnable
= true;
3138 pc
.StateCacheInvalidationEnable
= true;
3139 pc
.InstructionCacheInvalidateEnable
= true;
3140 pc
.PostSyncOperation
= NoWrite
;
3143 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3147 ps
.PipelineSelection
= pipeline
;
3151 if (devinfo
->is_geminilake
) {
3154 * "This chicken bit works around a hardware issue with barrier logic
3155 * encountered when switching between GPGPU and 3D pipelines. To
3156 * workaround the issue, this mode bit should be set after a pipeline
3160 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3162 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3163 : GLK_BARRIER_MODE_3D_HULL
,
3164 .GLKBarrierModeMask
= 1);
3165 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3169 cmd_buffer
->state
.current_pipeline
= pipeline
;
3173 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3175 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3179 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3181 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3185 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3190 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3192 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3193 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3194 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3195 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3196 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3197 * Depth Flush Bit set, followed by another pipelined depth stall
3198 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3199 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3200 * via a preceding MI_FLUSH)."
3202 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3203 pipe
.DepthStallEnable
= true;
3205 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3206 pipe
.DepthCacheFlushEnable
= true;
3208 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3209 pipe
.DepthStallEnable
= true;
3214 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3216 struct anv_device
*device
= cmd_buffer
->device
;
3217 const struct anv_image_view
*iview
=
3218 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3219 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3221 /* FIXME: Width and Height are wrong */
3223 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3225 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3226 device
->isl_dev
.ds
.size
/ 4);
3230 struct isl_depth_stencil_hiz_emit_info info
= {
3231 .mocs
= device
->default_mocs
,
3235 info
.view
= &iview
->planes
[0].isl
;
3237 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3238 uint32_t depth_plane
=
3239 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3240 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3242 info
.depth_surf
= &surface
->isl
;
3244 info
.depth_address
=
3245 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3246 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3247 image
->planes
[depth_plane
].bo
,
3248 image
->planes
[depth_plane
].bo_offset
+
3252 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.attachment
;
3253 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3254 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3255 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3258 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3259 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3260 image
->planes
[depth_plane
].bo
,
3261 image
->planes
[depth_plane
].bo_offset
+
3262 image
->planes
[depth_plane
].aux_surface
.offset
);
3264 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3268 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3269 uint32_t stencil_plane
=
3270 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3271 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3273 info
.stencil_surf
= &surface
->isl
;
3275 info
.stencil_address
=
3276 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3277 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3278 image
->planes
[stencil_plane
].bo
,
3279 image
->planes
[stencil_plane
].bo_offset
+ surface
->offset
);
3282 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3284 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3288 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3289 uint32_t subpass_id
)
3291 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3292 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3293 cmd_state
->subpass
= subpass
;
3295 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3297 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3298 * different views. If the client asks for instancing, we need to use the
3299 * Instance Data Step Rate to ensure that we repeat the client's
3300 * per-instance data once for each view. Since this bit is in
3301 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3305 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3307 /* It is possible to start a render pass with an old pipeline. Because the
3308 * render pass and subpass index are both baked into the pipeline, this is
3309 * highly unlikely. In order to do so, it requires that you have a render
3310 * pass with a single subpass and that you use that render pass twice
3311 * back-to-back and use the same pipeline at the start of the second render
3312 * pass as at the end of the first. In order to avoid unpredictable issues
3313 * with this edge case, we just dirty the pipeline at the start of every
3316 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3318 /* Accumulate any subpass flushes that need to happen before the subpass */
3319 cmd_buffer
->state
.pending_pipe_bits
|=
3320 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3322 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3323 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3325 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3326 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3327 if (a
== VK_ATTACHMENT_UNUSED
)
3330 assert(a
< cmd_state
->pass
->attachment_count
);
3331 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3333 struct anv_image_view
*iview
= fb
->attachments
[a
];
3334 const struct anv_image
*image
= iview
->image
;
3336 /* A resolve is necessary before use as an input attachment if the clear
3337 * color or auxiliary buffer usage isn't supported by the sampler.
3339 const bool input_needs_resolve
=
3340 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3341 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3343 VkImageLayout target_layout
;
3344 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3345 !input_needs_resolve
) {
3346 /* Layout transitions before the final only help to enable sampling
3347 * as an input attachment. If the input attachment supports sampling
3348 * using the auxiliary surface, we can skip such transitions by
3349 * making the target layout one that is CCS-aware.
3351 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3353 target_layout
= subpass
->attachments
[i
].layout
;
3356 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3357 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3359 uint32_t base_layer
, layer_count
;
3360 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3362 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3363 iview
->planes
[0].isl
.base_level
);
3365 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3366 layer_count
= fb
->layers
;
3369 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3370 iview
->planes
[0].isl
.base_level
, 1,
3371 base_layer
, layer_count
,
3372 att_state
->current_layout
, target_layout
);
3373 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3374 transition_depth_buffer(cmd_buffer
, image
,
3375 att_state
->current_layout
, target_layout
);
3376 att_state
->aux_usage
=
3377 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3378 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3380 att_state
->current_layout
= target_layout
;
3382 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3383 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3385 /* Multi-planar images are not supported as attachments */
3386 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3387 assert(image
->n_planes
== 1);
3389 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
3390 uint32_t clear_layer_count
= fb
->layers
;
3392 if (att_state
->fast_clear
) {
3393 /* We only support fast-clears on the first layer */
3394 assert(iview
->planes
[0].isl
.base_level
== 0);
3395 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3397 anv_image_ccs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3398 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
, false);
3400 clear_layer_count
--;
3402 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3403 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3404 true /* copy from ss */);
3406 if (att_state
->clear_color_is_zero
) {
3407 /* This image has the auxiliary buffer enabled. We can mark the
3408 * subresource as not needing a resolve because the clear color
3409 * will match what's in every RENDER_SURFACE_STATE object when
3410 * it's being used for sampling.
3412 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3413 VK_IMAGE_ASPECT_COLOR_BIT
,
3414 ANV_FAST_CLEAR_DEFAULT_VALUE
);
3416 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3417 VK_IMAGE_ASPECT_COLOR_BIT
,
3418 ANV_FAST_CLEAR_ANY
);
3422 if (clear_layer_count
> 0) {
3423 assert(image
->n_planes
== 1);
3424 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3425 att_state
->aux_usage
,
3426 iview
->planes
[0].isl
.format
,
3427 iview
->planes
[0].isl
.swizzle
,
3428 iview
->planes
[0].isl
.base_level
,
3429 base_clear_layer
, clear_layer_count
,
3431 vk_to_isl_color(att_state
->clear_value
.color
));
3433 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
3434 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3435 if (att_state
->fast_clear
) {
3436 /* We currently only support HiZ for single-layer images */
3437 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3438 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
3439 assert(iview
->planes
[0].isl
.base_level
== 0);
3440 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3441 assert(fb
->layers
== 1);
3444 anv_image_hiz_clear(cmd_buffer
, image
,
3445 att_state
->pending_clear_aspects
,
3446 iview
->planes
[0].isl
.base_level
,
3447 iview
->planes
[0].isl
.base_array_layer
,
3448 fb
->layers
, render_area
,
3449 att_state
->clear_value
.depthStencil
.stencil
);
3451 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3452 att_state
->pending_clear_aspects
,
3453 att_state
->aux_usage
,
3454 iview
->planes
[0].isl
.base_level
,
3455 iview
->planes
[0].isl
.base_array_layer
,
3456 fb
->layers
, render_area
,
3457 att_state
->clear_value
.depthStencil
.depth
,
3458 att_state
->clear_value
.depthStencil
.stencil
);
3461 assert(att_state
->pending_clear_aspects
== 0);
3464 if ((att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
3465 image
->planes
[0].aux_surface
.isl
.size
> 0 &&
3466 iview
->planes
[0].isl
.base_level
== 0 &&
3467 iview
->planes
[0].isl
.base_array_layer
== 0) {
3468 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
3469 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3470 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3471 false /* copy to ss */);
3474 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
3475 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3476 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3477 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3478 false /* copy to ss */);
3482 if (subpass
->attachments
[i
].usage
==
3483 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
3484 /* We assume that if we're starting a subpass, we're going to do some
3485 * rendering so we may end up with compressed data.
3487 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
3488 VK_IMAGE_ASPECT_COLOR_BIT
,
3489 att_state
->aux_usage
,
3490 iview
->planes
[0].isl
.base_level
,
3491 iview
->planes
[0].isl
.base_array_layer
,
3493 } else if (subpass
->attachments
[i
].usage
==
3494 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
3495 /* We may be writing depth or stencil so we need to mark the surface.
3496 * Unfortunately, there's no way to know at this point whether the
3497 * depth or stencil tests used will actually write to the surface.
3499 * Even though stencil may be plane 1, it always shares a base_level
3502 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
3503 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3504 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3505 VK_IMAGE_ASPECT_DEPTH_BIT
,
3506 att_state
->aux_usage
,
3507 ds_view
->base_level
,
3508 ds_view
->base_array_layer
,
3511 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
3512 /* Even though stencil may be plane 1, it always shares a
3513 * base_level with depth.
3515 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3516 VK_IMAGE_ASPECT_STENCIL_BIT
,
3518 ds_view
->base_level
,
3519 ds_view
->base_array_layer
,
3524 att_state
->pending_clear_aspects
= 0;
3525 att_state
->pending_load_aspects
= 0;
3528 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3532 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
3534 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3535 struct anv_subpass
*subpass
= cmd_state
->subpass
;
3536 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3538 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3540 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3541 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3542 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3543 if (a
== VK_ATTACHMENT_UNUSED
)
3546 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3549 assert(a
< cmd_state
->pass
->attachment_count
);
3550 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3551 struct anv_image_view
*iview
= fb
->attachments
[a
];
3552 const struct anv_image
*image
= iview
->image
;
3554 /* Transition the image into the final layout for this render pass */
3555 VkImageLayout target_layout
=
3556 cmd_state
->pass
->attachments
[a
].final_layout
;
3558 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3559 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3561 uint32_t base_layer
, layer_count
;
3562 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3564 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3565 iview
->planes
[0].isl
.base_level
);
3567 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3568 layer_count
= fb
->layers
;
3571 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3572 iview
->planes
[0].isl
.base_level
, 1,
3573 base_layer
, layer_count
,
3574 att_state
->current_layout
, target_layout
);
3575 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3576 transition_depth_buffer(cmd_buffer
, image
,
3577 att_state
->current_layout
, target_layout
);
3581 /* Accumulate any subpass flushes that need to happen after the subpass.
3582 * Yes, they do get accumulated twice in the NextSubpass case but since
3583 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
3584 * ORing the bits in twice so it's harmless.
3586 cmd_buffer
->state
.pending_pipe_bits
|=
3587 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
3590 void genX(CmdBeginRenderPass
)(
3591 VkCommandBuffer commandBuffer
,
3592 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3593 VkSubpassContents contents
)
3595 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3596 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3597 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3599 cmd_buffer
->state
.framebuffer
= framebuffer
;
3600 cmd_buffer
->state
.pass
= pass
;
3601 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3603 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3605 /* If we failed to setup the attachments we should not try to go further */
3606 if (result
!= VK_SUCCESS
) {
3607 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3611 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3613 cmd_buffer_begin_subpass(cmd_buffer
, 0);
3616 void genX(CmdNextSubpass
)(
3617 VkCommandBuffer commandBuffer
,
3618 VkSubpassContents contents
)
3620 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3622 if (anv_batch_has_error(&cmd_buffer
->batch
))
3625 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3627 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
3628 cmd_buffer_end_subpass(cmd_buffer
);
3629 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3632 void genX(CmdEndRenderPass
)(
3633 VkCommandBuffer commandBuffer
)
3635 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3637 if (anv_batch_has_error(&cmd_buffer
->batch
))
3640 cmd_buffer_end_subpass(cmd_buffer
);
3642 cmd_buffer
->state
.hiz_enabled
= false;
3645 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
3648 /* Remove references to render pass specific state. This enables us to
3649 * detect whether or not we're in a renderpass.
3651 cmd_buffer
->state
.framebuffer
= NULL
;
3652 cmd_buffer
->state
.pass
= NULL
;
3653 cmd_buffer
->state
.subpass
= NULL
;