2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
,
37 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
83 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
84 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
85 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
86 sba
.GeneralStateBaseAddressModifyEnable
= true;
88 sba
.SurfaceStateBaseAddress
=
89 anv_cmd_buffer_surface_base_address(cmd_buffer
);
90 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
91 sba
.SurfaceStateBaseAddressModifyEnable
= true;
93 sba
.DynamicStateBaseAddress
=
94 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
95 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
96 sba
.DynamicStateBaseAddressModifyEnable
= true;
98 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
99 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
100 sba
.IndirectObjectBaseAddressModifyEnable
= true;
102 sba
.InstructionBaseAddress
=
103 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
104 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
105 sba
.InstructionBaseAddressModifyEnable
= true;
108 /* Broadwell requires that we specify a buffer size for a bunch of
109 * these fields. However, since we will be growing the BO's live, we
110 * just set them all to the maximum.
112 sba
.GeneralStateBufferSize
= 0xfffff;
113 sba
.GeneralStateBufferSizeModifyEnable
= true;
114 sba
.DynamicStateBufferSize
= 0xfffff;
115 sba
.DynamicStateBufferSizeModifyEnable
= true;
116 sba
.IndirectObjectBufferSize
= 0xfffff;
117 sba
.IndirectObjectBufferSizeModifyEnable
= true;
118 sba
.InstructionBufferSize
= 0xfffff;
119 sba
.InstructionBuffersizeModifyEnable
= true;
123 /* After re-setting the surface state base address, we have to do some
124 * cache flusing so that the sampler engine will pick up the new
125 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
126 * Shared Function > 3D Sampler > State > State Caching (page 96):
128 * Coherency with system memory in the state cache, like the texture
129 * cache is handled partially by software. It is expected that the
130 * command stream or shader will issue Cache Flush operation or
131 * Cache_Flush sampler message to ensure that the L1 cache remains
132 * coherent with system memory.
136 * Whenever the value of the Dynamic_State_Base_Addr,
137 * Surface_State_Base_Addr are altered, the L1 state cache must be
138 * invalidated to ensure the new surface or sampler state is fetched
139 * from system memory.
141 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
142 * which, according the PIPE_CONTROL instruction documentation in the
145 * Setting this bit is independent of any other bit in this packet.
146 * This bit controls the invalidation of the L1 and L2 state caches
147 * at the top of the pipe i.e. at the parsing time.
149 * Unfortunately, experimentation seems to indicate that state cache
150 * invalidation through a PIPE_CONTROL does nothing whatsoever in
151 * regards to surface state and binding tables. In stead, it seems that
152 * invalidating the texture cache is what is actually needed.
154 * XXX: As far as we have been able to determine through
155 * experimentation, shows that flush the texture cache appears to be
156 * sufficient. The theory here is that all of the sampling/rendering
157 * units cache the binding table in the texture cache. However, we have
158 * yet to be able to actually confirm this.
160 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
161 pc
.TextureCacheInvalidationEnable
= true;
162 pc
.ConstantCacheInvalidationEnable
= true;
163 pc
.StateCacheInvalidationEnable
= true;
168 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
169 struct anv_state state
,
170 struct anv_bo
*bo
, uint32_t offset
)
172 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
175 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
176 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
177 if (result
!= VK_SUCCESS
)
178 anv_batch_set_error(&cmd_buffer
->batch
, result
);
182 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
183 const struct anv_image_view
*image_view
,
184 const uint32_t plane
,
185 struct anv_surface_state state
)
187 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
188 const struct anv_image
*image
= image_view
->image
;
189 uint32_t image_plane
= image_view
->planes
[plane
].image_plane
;
191 add_surface_state_reloc(cmd_buffer
, state
.state
,
192 image
->planes
[image_plane
].bo
, state
.address
);
194 if (state
.aux_address
) {
196 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
197 &cmd_buffer
->pool
->alloc
,
198 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
199 image
->planes
[image_plane
].bo
, state
.aux_address
);
200 if (result
!= VK_SUCCESS
)
201 anv_batch_set_error(&cmd_buffer
->batch
, result
);
204 if (state
.clear_address
) {
206 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
207 &cmd_buffer
->pool
->alloc
,
209 isl_dev
->ss
.clear_color_state_offset
,
210 image
->planes
[image_plane
].bo
, state
.clear_address
);
211 if (result
!= VK_SUCCESS
)
212 anv_batch_set_error(&cmd_buffer
->batch
, result
);
217 color_attachment_compute_aux_usage(struct anv_device
* device
,
218 struct anv_cmd_state
* cmd_state
,
219 uint32_t att
, VkRect2D render_area
,
220 union isl_color_value
*fast_clear_color
)
222 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
223 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
225 assert(iview
->n_planes
== 1);
227 if (iview
->planes
[0].isl
.base_array_layer
>=
228 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
229 iview
->planes
[0].isl
.base_level
)) {
230 /* There is no aux buffer which corresponds to the level and layer(s)
233 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
234 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
235 att_state
->fast_clear
= false;
239 att_state
->aux_usage
=
240 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
241 VK_IMAGE_ASPECT_COLOR_BIT
,
242 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
244 /* If we don't have aux, then we should have returned early in the layer
245 * check above. If we got here, we must have something.
247 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
249 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
250 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
251 att_state
->input_aux_usage
= att_state
->aux_usage
;
253 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
255 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
256 * setting is only allowed if Surface Format supported for Fast
257 * Clear. In addition, if the surface is bound to the sampling
258 * engine, Surface Format must be supported for Render Target
259 * Compression for surfaces bound to the sampling engine."
261 * In other words, we can only sample from a fast-cleared image if it
262 * also supports color compression.
264 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
265 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
267 /* While fast-clear resolves and partial resolves are fairly cheap in the
268 * case where you render to most of the pixels, full resolves are not
269 * because they potentially involve reading and writing the entire
270 * framebuffer. If we can't texture with CCS_E, we should leave it off and
271 * limit ourselves to fast clears.
273 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
274 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
275 anv_perf_warn(device
->instance
, iview
->image
,
276 "Not temporarily enabling CCS_E.");
279 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
283 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
284 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
286 union isl_color_value clear_color
= {};
287 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
289 att_state
->clear_color_is_zero_one
=
290 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
291 att_state
->clear_color_is_zero
=
292 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
294 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
295 /* Start by getting the fast clear type. We use the first subpass
296 * layout here because we don't want to fast-clear if the first subpass
297 * to use the attachment can't handle fast-clears.
299 enum anv_fast_clear_type fast_clear_type
=
300 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
301 VK_IMAGE_ASPECT_COLOR_BIT
,
302 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
303 switch (fast_clear_type
) {
304 case ANV_FAST_CLEAR_NONE
:
305 att_state
->fast_clear
= false;
307 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
308 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
310 case ANV_FAST_CLEAR_ANY
:
311 att_state
->fast_clear
= true;
315 /* Potentially, we could do partial fast-clears but doing so has crazy
316 * alignment restrictions. It's easier to just restrict to full size
317 * fast clears for now.
319 if (render_area
.offset
.x
!= 0 ||
320 render_area
.offset
.y
!= 0 ||
321 render_area
.extent
.width
!= iview
->extent
.width
||
322 render_area
.extent
.height
!= iview
->extent
.height
)
323 att_state
->fast_clear
= false;
325 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
326 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
327 att_state
->fast_clear
= false;
329 /* We only allow fast clears to the first slice of an image (level 0,
330 * layer 0) and only for the entire slice. This guarantees us that, at
331 * any given time, there is only one clear color on any given image at
332 * any given time. At the time of our testing (Jan 17, 2018), there
333 * were no known applications which would benefit from fast-clearing
334 * more than just the first slice.
336 if (att_state
->fast_clear
&&
337 (iview
->planes
[0].isl
.base_level
> 0 ||
338 iview
->planes
[0].isl
.base_array_layer
> 0)) {
339 anv_perf_warn(device
->instance
, iview
->image
,
340 "Rendering with multi-lod or multi-layer framebuffer "
341 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
342 "baseArrayLayer > 0. Not fast clearing.");
343 att_state
->fast_clear
= false;
344 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
345 anv_perf_warn(device
->instance
, iview
->image
,
346 "Rendering to a multi-layer framebuffer with "
347 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
350 if (att_state
->fast_clear
)
351 *fast_clear_color
= clear_color
;
353 att_state
->fast_clear
= false;
358 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
359 struct anv_cmd_state
*cmd_state
,
360 uint32_t att
, VkRect2D render_area
)
362 struct anv_render_pass_attachment
*pass_att
=
363 &cmd_state
->pass
->attachments
[att
];
364 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
365 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
367 /* These will be initialized after the first subpass transition. */
368 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
369 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
372 /* We don't do any HiZ or depth fast-clears on gen7 yet */
373 att_state
->fast_clear
= false;
377 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
378 /* If we're just clearing stencil, we can always HiZ clear */
379 att_state
->fast_clear
= true;
383 /* Default to false for now */
384 att_state
->fast_clear
= false;
386 /* We must have depth in order to have HiZ */
387 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
390 const enum isl_aux_usage first_subpass_aux_usage
=
391 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
392 VK_IMAGE_ASPECT_DEPTH_BIT
,
393 pass_att
->first_subpass_layout
);
394 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
397 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
398 iview
->planes
[0].isl
.format
,
399 iview
->image
->samples
,
400 render_area
.offset
.x
,
401 render_area
.offset
.y
,
402 render_area
.offset
.x
+
403 render_area
.extent
.width
,
404 render_area
.offset
.y
+
405 render_area
.extent
.height
))
408 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
411 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
412 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
413 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
414 * only supports returning 0.0f. Gens prior to gen8 do not support this
420 /* If we got here, then we can fast clear */
421 att_state
->fast_clear
= true;
425 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
427 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
430 /* We only allocate input attachment states for color surfaces. Compression
431 * is not yet enabled for depth textures and stencil doesn't allow
432 * compression so we can just use the texture surface state from the view.
434 return vk_format_is_color(att
->format
);
437 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
438 * the initial layout is undefined, the HiZ buffer and depth buffer will
439 * represent the same data at the end of this operation.
442 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
443 const struct anv_image
*image
,
444 VkImageLayout initial_layout
,
445 VkImageLayout final_layout
)
447 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
448 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
449 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
450 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
451 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
452 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
454 enum isl_aux_op hiz_op
;
455 if (hiz_enabled
&& !enable_hiz
) {
456 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
457 } else if (!hiz_enabled
&& enable_hiz
) {
458 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
460 assert(hiz_enabled
== enable_hiz
);
461 /* If the same buffer will be used, no resolves are necessary. */
462 hiz_op
= ISL_AUX_OP_NONE
;
465 if (hiz_op
!= ISL_AUX_OP_NONE
)
466 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
470 #define MI_PREDICATE_SRC0 0x2400
471 #define MI_PREDICATE_SRC1 0x2408
474 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
475 const struct anv_image
*image
,
476 VkImageAspectFlagBits aspect
,
478 uint32_t base_layer
, uint32_t layer_count
,
481 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
483 /* We only have compression tracking for CCS_E */
484 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
487 for (uint32_t a
= 0; a
< layer_count
; a
++) {
488 uint32_t layer
= base_layer
+ a
;
489 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
490 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
493 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
499 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
500 const struct anv_image
*image
,
501 VkImageAspectFlagBits aspect
,
502 enum anv_fast_clear_type fast_clear
)
504 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
505 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
507 sdi
.ImmediateData
= fast_clear
;
510 /* Whenever we have fast-clear, we consider that slice to be compressed.
511 * This makes building predicates much easier.
513 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
514 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
517 #if GEN_IS_HASWELL || GEN_GEN >= 8
518 static inline uint32_t
519 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
521 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
523 .Operand1
= operand1
,
524 .Operand2
= operand2
,
528 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
534 #define CS_GPR(n) (0x2600 + (n) * 8)
536 /* This is only really practical on haswell and above because it requires
537 * MI math in order to get it correct.
539 #if GEN_GEN >= 8 || GEN_IS_HASWELL
541 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
542 const struct anv_image
*image
,
543 VkImageAspectFlagBits aspect
,
544 uint32_t level
, uint32_t array_layer
,
545 enum isl_aux_op resolve_op
,
546 enum anv_fast_clear_type fast_clear_supported
)
548 struct anv_address fast_clear_type_addr
=
549 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
551 /* Name some registers */
552 const int image_fc_reg
= MI_ALU_REG0
;
553 const int fc_imm_reg
= MI_ALU_REG1
;
554 const int pred_reg
= MI_ALU_REG2
;
558 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
559 /* In this case, we're doing a full resolve which means we want the
560 * resolve to happen if any compression (including fast-clears) is
563 * In order to simplify the logic a bit, we make the assumption that,
564 * if the first slice has been fast-cleared, it is also marked as
565 * compressed. See also set_image_fast_clear_state.
567 struct anv_address compression_state_addr
=
568 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
569 aspect
, level
, array_layer
);
570 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
571 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
572 lrm
.MemoryAddress
= compression_state_addr
;
574 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
575 sdi
.Address
= compression_state_addr
;
576 sdi
.ImmediateData
= 0;
579 if (level
== 0 && array_layer
== 0) {
580 /* If the predicate is true, we want to write 0 to the fast clear type
581 * and, if it's false, leave it alone. We can do this by writing
583 * clear_type = clear_type & ~predicate;
585 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
586 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
587 lrm
.MemoryAddress
= fast_clear_type_addr
;
589 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
590 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
591 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
594 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
595 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
596 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
597 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
598 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
600 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
601 srm
.MemoryAddress
= fast_clear_type_addr
;
602 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
605 } else if (level
== 0 && array_layer
== 0) {
606 /* In this case, we are doing a partial resolve to get rid of fast-clear
607 * colors. We don't care about the compression state but we do care
608 * about how much fast clear is allowed by the final layout.
610 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
611 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
613 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
614 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
615 lrm
.MemoryAddress
= fast_clear_type_addr
;
617 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
619 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
620 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
622 /* We need to compute (fast_clear_supported < image->fast_clear).
623 * We do this by subtracting and storing the carry bit.
625 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
626 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
627 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
628 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
629 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
631 /* Store the predicate */
632 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
634 /* If the predicate is true, we want to write 0 to the fast clear type
635 * and, if it's false, leave it alone. We can do this by writing
637 * clear_type = clear_type & ~predicate;
639 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
640 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
641 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
642 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
643 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
645 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
646 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
647 srm
.MemoryAddress
= fast_clear_type_addr
;
650 /* In this case, we're trying to do a partial resolve on a slice that
651 * doesn't have clear color. There's nothing to do.
653 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
657 /* We use the first half of src0 for the actual predicate. Set the second
658 * half of src0 and all of src1 to 0 as the predicate operation will be
659 * doing an implicit src0 != src1.
661 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
662 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
663 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
665 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
666 mip
.LoadOperation
= LOAD_LOADINV
;
667 mip
.CombineOperation
= COMBINE_SET
;
668 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
671 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
675 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
676 const struct anv_image
*image
,
677 VkImageAspectFlagBits aspect
,
678 uint32_t level
, uint32_t array_layer
,
679 enum isl_aux_op resolve_op
,
680 enum anv_fast_clear_type fast_clear_supported
)
682 struct anv_address fast_clear_type_addr
=
683 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
685 /* This only works for partial resolves and only when the clear color is
686 * all or nothing. On the upside, this emits less command streamer code
687 * and works on Ivybridge and Bay Trail.
689 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
690 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
692 /* We don't support fast clears on anything other than the first slice. */
693 if (level
> 0 || array_layer
> 0)
696 /* On gen8, we don't have a concept of default clear colors because we
697 * can't sample from CCS surfaces. It's enough to just load the fast clear
698 * state into the predicate register.
700 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
701 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
702 lrm
.MemoryAddress
= fast_clear_type_addr
;
704 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
705 sdi
.Address
= fast_clear_type_addr
;
706 sdi
.ImmediateData
= 0;
709 /* We use the first half of src0 for the actual predicate. Set the second
710 * half of src0 and all of src1 to 0 as the predicate operation will be
711 * doing an implicit src0 != src1.
713 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
714 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
715 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
717 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
718 mip
.LoadOperation
= LOAD_LOADINV
;
719 mip
.CombineOperation
= COMBINE_SET
;
720 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
723 #endif /* GEN_GEN <= 8 */
726 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
727 const struct anv_image
*image
,
728 VkImageAspectFlagBits aspect
,
729 uint32_t level
, uint32_t array_layer
,
730 enum isl_aux_op resolve_op
,
731 enum anv_fast_clear_type fast_clear_supported
)
733 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
736 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
737 aspect
, level
, array_layer
,
738 resolve_op
, fast_clear_supported
);
739 #else /* GEN_GEN <= 8 */
740 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
741 aspect
, level
, array_layer
,
742 resolve_op
, fast_clear_supported
);
745 /* CCS_D only supports full resolves and BLORP will assert on us if we try
746 * to do a partial resolve on a CCS_D surface.
748 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
749 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
750 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
752 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
753 array_layer
, 1, resolve_op
, NULL
, true);
757 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
758 const struct anv_image
*image
,
759 VkImageAspectFlagBits aspect
,
760 uint32_t array_layer
,
761 enum isl_aux_op resolve_op
,
762 enum anv_fast_clear_type fast_clear_supported
)
764 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
765 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
767 #if GEN_GEN >= 8 || GEN_IS_HASWELL
768 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
769 aspect
, 0, array_layer
,
770 resolve_op
, fast_clear_supported
);
772 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
773 array_layer
, 1, resolve_op
, NULL
, true);
775 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
780 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
781 const struct anv_image
*image
,
782 VkImageAspectFlagBits aspect
,
783 enum isl_aux_usage aux_usage
,
786 uint32_t layer_count
)
788 /* The aspect must be exactly one of the image aspects. */
789 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
791 /* The only compression types with more than just fast-clears are MCS,
792 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
793 * track the current fast-clear and compression state. This leaves us
794 * with just MCS and CCS_E.
796 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
797 aux_usage
!= ISL_AUX_USAGE_MCS
)
800 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
801 level
, base_layer
, layer_count
, true);
805 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
806 const struct anv_image
*image
,
807 VkImageAspectFlagBits aspect
)
809 assert(cmd_buffer
&& image
);
810 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
812 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
813 ANV_FAST_CLEAR_NONE
);
815 /* The fast clear value dword(s) will be copied into a surface state object.
816 * Ensure that the restrictions of the fields in the dword(s) are followed.
818 * CCS buffers on SKL+ can have any value set for the clear colors.
820 if (image
->samples
== 1 && GEN_GEN
>= 9)
823 /* Other combinations of auxiliary buffers and platforms require specific
824 * values in the clear value dword(s).
826 struct anv_address addr
=
827 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
830 for (unsigned i
= 0; i
< 4; i
++) {
831 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
833 sdi
.Address
.offset
+= i
* 4;
834 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
835 assert(image
->samples
> 1);
836 sdi
.ImmediateData
= 0;
840 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
842 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
843 /* Pre-SKL, the dword containing the clear values also contains
844 * other fields, so we need to initialize those fields to match the
845 * values that would be in a color attachment.
847 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
848 ISL_CHANNEL_SELECT_GREEN
<< 22 |
849 ISL_CHANNEL_SELECT_BLUE
<< 19 |
850 ISL_CHANNEL_SELECT_ALPHA
<< 16;
851 } else if (GEN_GEN
== 7) {
852 /* On IVB, the dword containing the clear values also contains
853 * other fields that must be zero or can be zero.
855 sdi
.ImmediateData
= 0;
861 /* Copy the fast-clear value dword(s) between a surface state object and an
862 * image's fast clear state buffer.
865 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
866 struct anv_state surface_state
,
867 const struct anv_image
*image
,
868 VkImageAspectFlagBits aspect
,
869 bool copy_from_surface_state
)
871 assert(cmd_buffer
&& image
);
872 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
874 struct anv_bo
*ss_bo
=
875 &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
;
876 uint32_t ss_clear_offset
= surface_state
.offset
+
877 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
;
878 const struct anv_address entry_addr
=
879 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
880 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
882 if (copy_from_surface_state
) {
883 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
.bo
, entry_addr
.offset
,
884 ss_bo
, ss_clear_offset
, copy_size
);
886 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_bo
, ss_clear_offset
,
887 entry_addr
.bo
, entry_addr
.offset
, copy_size
);
889 /* Updating a surface state object may require that the state cache be
890 * invalidated. From the SKL PRM, Shared Functions -> State -> State
893 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
894 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
895 * modified [...], the L1 state cache must be invalidated to ensure
896 * the new surface or sampler state is fetched from system memory.
898 * In testing, SKL doesn't actually seem to need this, but HSW does.
900 cmd_buffer
->state
.pending_pipe_bits
|=
901 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
906 * @brief Transitions a color buffer from one layout to another.
908 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
911 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
912 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
913 * this represents the maximum layers to transition at each
914 * specified miplevel.
917 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
918 const struct anv_image
*image
,
919 VkImageAspectFlagBits aspect
,
920 const uint32_t base_level
, uint32_t level_count
,
921 uint32_t base_layer
, uint32_t layer_count
,
922 VkImageLayout initial_layout
,
923 VkImageLayout final_layout
)
925 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
926 /* Validate the inputs. */
928 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
929 /* These values aren't supported for simplicity's sake. */
930 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
931 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
932 /* Ensure the subresource range is valid. */
933 uint64_t last_level_num
= base_level
+ level_count
;
934 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
935 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
936 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
937 assert(last_level_num
<= image
->levels
);
938 /* The spec disallows these final layouts. */
939 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
940 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
942 /* No work is necessary if the layout stays the same or if this subresource
943 * range lacks auxiliary data.
945 if (initial_layout
== final_layout
)
948 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
950 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
951 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
952 /* This surface is a linear compressed image with a tiled shadow surface
953 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
954 * we need to ensure the shadow copy is up-to-date.
956 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
957 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
958 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
959 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
961 anv_image_copy_to_shadow(cmd_buffer
, image
,
962 base_level
, level_count
,
963 base_layer
, layer_count
);
966 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
969 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
971 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
972 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
973 /* A subresource in the undefined layout may have been aliased and
974 * populated with any arrangement of bits. Therefore, we must initialize
975 * the related aux buffer and clear buffer entry with desirable values.
976 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
977 * images with VK_IMAGE_TILING_OPTIMAL.
979 * Initialize the relevant clear buffer entries.
981 if (base_level
== 0 && base_layer
== 0)
982 init_fast_clear_color(cmd_buffer
, image
, aspect
);
984 /* Initialize the aux buffers to enable correct rendering. In order to
985 * ensure that things such as storage images work correctly, aux buffers
986 * need to be initialized to valid data.
988 * Having an aux buffer with invalid data is a problem for two reasons:
990 * 1) Having an invalid value in the buffer can confuse the hardware.
991 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
992 * invalid and leads to the hardware doing strange things. It
993 * doesn't hang as far as we can tell but rendering corruption can
996 * 2) If this transition is into the GENERAL layout and we then use the
997 * image as a storage image, then we must have the aux buffer in the
998 * pass-through state so that, if we then go to texture from the
999 * image, we get the results of our storage image writes and not the
1000 * fast clear color or other random data.
1002 * For CCS both of the problems above are real demonstrable issues. In
1003 * that case, the only thing we can do is to perform an ambiguate to
1004 * transition the aux surface into the pass-through state.
1006 * For MCS, (2) is never an issue because we don't support multisampled
1007 * storage images. In theory, issue (1) is a problem with MCS but we've
1008 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1009 * theory, be interpreted as something but we don't know that all bit
1010 * patterns are actually valid. For 2x and 8x, you could easily end up
1011 * with the MCS referring to an invalid plane because not all bits of
1012 * the MCS value are actually used. Even though we've never seen issues
1013 * in the wild, it's best to play it safe and initialize the MCS. We
1014 * can use a fast-clear for MCS because we only ever touch from render
1015 * and texture (no image load store).
1017 if (image
->samples
== 1) {
1018 for (uint32_t l
= 0; l
< level_count
; l
++) {
1019 const uint32_t level
= base_level
+ l
;
1021 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1022 if (base_layer
>= aux_layers
)
1023 break; /* We will only get fewer layers as level increases */
1024 uint32_t level_layer_count
=
1025 MIN2(layer_count
, aux_layers
- base_layer
);
1027 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
1028 base_layer
, level_layer_count
,
1029 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1031 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1032 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1033 level
, base_layer
, level_layer_count
,
1038 if (image
->samples
== 4 || image
->samples
== 16) {
1039 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1040 "Doing a potentially unnecessary fast-clear to "
1041 "define an MCS buffer.");
1044 assert(base_level
== 0 && level_count
== 1);
1045 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
1046 base_layer
, layer_count
,
1047 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1052 const enum isl_aux_usage initial_aux_usage
=
1053 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1054 const enum isl_aux_usage final_aux_usage
=
1055 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1057 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1058 * We can handle transitions between CCS_D/E to and from NONE. What we
1059 * don't yet handle is switching between CCS_E and CCS_D within a given
1060 * image. Doing so in a performant way requires more detailed aux state
1061 * tracking such as what is done in i965. For now, just assume that we
1062 * only have one type of compression.
1064 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1065 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1066 initial_aux_usage
== final_aux_usage
);
1068 /* If initial aux usage is NONE, there is nothing to resolve */
1069 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1072 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1074 /* If the initial layout supports more fast clear than the final layout
1075 * then we need at least a partial resolve.
1077 const enum anv_fast_clear_type initial_fast_clear
=
1078 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1079 const enum anv_fast_clear_type final_fast_clear
=
1080 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1081 if (final_fast_clear
< initial_fast_clear
)
1082 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1084 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1085 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1086 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1088 if (resolve_op
== ISL_AUX_OP_NONE
)
1091 /* Perform a resolve to synchronize data between the main and aux buffer.
1092 * Before we begin, we must satisfy the cache flushing requirement specified
1093 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1095 * Any transition from any value in {Clear, Render, Resolve} to a
1096 * different value in {Clear, Render, Resolve} requires end of pipe
1099 * We perform a flush of the write cache before and after the clear and
1100 * resolve operations to meet this requirement.
1102 * Unlike other drawing, fast clear operations are not properly
1103 * synchronized. The first PIPE_CONTROL here likely ensures that the
1104 * contents of the previous render or clear hit the render target before we
1105 * resolve and the second likely ensures that the resolve is complete before
1106 * we do any more rendering or clearing.
1108 cmd_buffer
->state
.pending_pipe_bits
|=
1109 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1111 for (uint32_t l
= 0; l
< level_count
; l
++) {
1112 uint32_t level
= base_level
+ l
;
1114 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1115 if (base_layer
>= aux_layers
)
1116 break; /* We will only get fewer layers as level increases */
1117 uint32_t level_layer_count
=
1118 MIN2(layer_count
, aux_layers
- base_layer
);
1120 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1121 uint32_t array_layer
= base_layer
+ a
;
1122 if (image
->samples
== 1) {
1123 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
, aspect
,
1124 level
, array_layer
, resolve_op
,
1127 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
, aspect
,
1128 array_layer
, resolve_op
,
1134 cmd_buffer
->state
.pending_pipe_bits
|=
1135 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1139 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1142 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1143 struct anv_render_pass
*pass
,
1144 const VkRenderPassBeginInfo
*begin
)
1146 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1147 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1149 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1151 if (pass
->attachment_count
> 0) {
1152 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1153 pass
->attachment_count
*
1154 sizeof(state
->attachments
[0]),
1155 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1156 if (state
->attachments
== NULL
) {
1157 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1158 return anv_batch_set_error(&cmd_buffer
->batch
,
1159 VK_ERROR_OUT_OF_HOST_MEMORY
);
1162 state
->attachments
= NULL
;
1165 /* Reserve one for the NULL state. */
1166 unsigned num_states
= 1;
1167 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1168 if (vk_format_is_color(pass
->attachments
[i
].format
))
1171 if (need_input_attachment_state(&pass
->attachments
[i
]))
1175 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1176 state
->render_pass_states
=
1177 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1178 num_states
* ss_stride
, isl_dev
->ss
.align
);
1180 struct anv_state next_state
= state
->render_pass_states
;
1181 next_state
.alloc_size
= isl_dev
->ss
.size
;
1183 state
->null_surface_state
= next_state
;
1184 next_state
.offset
+= ss_stride
;
1185 next_state
.map
+= ss_stride
;
1187 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1188 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1189 state
->attachments
[i
].color
.state
= next_state
;
1190 next_state
.offset
+= ss_stride
;
1191 next_state
.map
+= ss_stride
;
1194 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1195 state
->attachments
[i
].input
.state
= next_state
;
1196 next_state
.offset
+= ss_stride
;
1197 next_state
.map
+= ss_stride
;
1200 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1201 state
->render_pass_states
.alloc_size
);
1204 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1205 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1207 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1208 isl_extent3d(framebuffer
->width
,
1209 framebuffer
->height
,
1210 framebuffer
->layers
));
1212 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1213 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1214 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1215 VkImageAspectFlags clear_aspects
= 0;
1216 VkImageAspectFlags load_aspects
= 0;
1218 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1219 /* color attachment */
1220 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1221 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1222 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1223 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1226 /* depthstencil attachment */
1227 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1228 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1229 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1230 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1231 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1234 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1235 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1236 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1237 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1238 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1243 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1244 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1245 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1247 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1249 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1250 anv_assert(iview
->vk_format
== att
->format
);
1252 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1253 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1255 union isl_color_value clear_color
= { .u32
= { 0, } };
1256 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1257 anv_assert(iview
->n_planes
== 1);
1258 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1259 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1260 state
, i
, begin
->renderArea
,
1263 anv_image_fill_surface_state(cmd_buffer
->device
,
1265 VK_IMAGE_ASPECT_COLOR_BIT
,
1266 &iview
->planes
[0].isl
,
1267 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1268 state
->attachments
[i
].aux_usage
,
1271 &state
->attachments
[i
].color
,
1274 add_image_view_relocs(cmd_buffer
, iview
, 0,
1275 state
->attachments
[i
].color
);
1277 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1282 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1283 anv_image_fill_surface_state(cmd_buffer
->device
,
1285 VK_IMAGE_ASPECT_COLOR_BIT
,
1286 &iview
->planes
[0].isl
,
1287 ISL_SURF_USAGE_TEXTURE_BIT
,
1288 state
->attachments
[i
].input_aux_usage
,
1291 &state
->attachments
[i
].input
,
1294 add_image_view_relocs(cmd_buffer
, iview
, 0,
1295 state
->attachments
[i
].input
);
1304 genX(BeginCommandBuffer
)(
1305 VkCommandBuffer commandBuffer
,
1306 const VkCommandBufferBeginInfo
* pBeginInfo
)
1308 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1310 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1311 * command buffer's state. Otherwise, we must *reset* its state. In both
1312 * cases we reset it.
1314 * From the Vulkan 1.0 spec:
1316 * If a command buffer is in the executable state and the command buffer
1317 * was allocated from a command pool with the
1318 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1319 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1320 * as if vkResetCommandBuffer had been called with
1321 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1322 * the command buffer in the recording state.
1324 anv_cmd_buffer_reset(cmd_buffer
);
1326 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1328 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1329 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1331 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1333 /* We sometimes store vertex data in the dynamic state buffer for blorp
1334 * operations and our dynamic state stream may re-use data from previous
1335 * command buffers. In order to prevent stale cache data, we flush the VF
1336 * cache. We could do this on every blorp call but that's not really
1337 * needed as all of the data will get written by the CPU prior to the GPU
1338 * executing anything. The chances are fairly high that they will use
1339 * blorp at least once per primary command buffer so it shouldn't be
1342 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1343 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1345 /* We send an "Indirect State Pointers Disable" packet at
1346 * EndCommandBuffer, so all push contant packets are ignored during a
1347 * context restore. Documentation says after that command, we need to
1348 * emit push constants again before any rendering operation. So we
1349 * flag them dirty here to make sure they get emitted.
1351 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1353 VkResult result
= VK_SUCCESS
;
1354 if (cmd_buffer
->usage_flags
&
1355 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1356 assert(pBeginInfo
->pInheritanceInfo
);
1357 cmd_buffer
->state
.pass
=
1358 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1359 cmd_buffer
->state
.subpass
=
1360 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1362 /* This is optional in the inheritance info. */
1363 cmd_buffer
->state
.framebuffer
=
1364 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1366 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1367 cmd_buffer
->state
.pass
, NULL
);
1369 /* Record that HiZ is enabled if we can. */
1370 if (cmd_buffer
->state
.framebuffer
) {
1371 const struct anv_image_view
* const iview
=
1372 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1375 VkImageLayout layout
=
1376 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.layout
;
1378 enum isl_aux_usage aux_usage
=
1379 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1380 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1382 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1386 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1392 /* From the PRM, Volume 2a:
1394 * "Indirect State Pointers Disable
1396 * At the completion of the post-sync operation associated with this pipe
1397 * control packet, the indirect state pointers in the hardware are
1398 * considered invalid; the indirect pointers are not saved in the context.
1399 * If any new indirect state commands are executed in the command stream
1400 * while the pipe control is pending, the new indirect state commands are
1403 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1404 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1405 * commands are only considered as Indirect State Pointers. Once ISP is
1406 * issued in a context, SW must initialize by programming push constant
1407 * commands for all the shaders (at least to zero length) before attempting
1408 * any rendering operation for the same context."
1410 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1411 * even though they point to a BO that has been already unreferenced at
1412 * the end of the previous batch buffer. This has been fine so far since
1413 * we are protected by these scratch page (every address not covered by
1414 * a BO should be pointing to the scratch page). But on CNL, it is
1415 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1418 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1419 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1420 * context restore, so the mentioned hang doesn't happen. However,
1421 * software must program push constant commands for all stages prior to
1422 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1424 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1425 * constants have been loaded into the EUs prior to disable the push constants
1426 * so that it doesn't hang a previous 3DPRIMITIVE.
1429 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1431 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1432 pc
.StallAtPixelScoreboard
= true;
1433 pc
.CommandStreamerStallEnable
= true;
1435 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1436 pc
.IndirectStatePointersDisable
= true;
1437 pc
.CommandStreamerStallEnable
= true;
1442 genX(EndCommandBuffer
)(
1443 VkCommandBuffer commandBuffer
)
1445 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1447 if (anv_batch_has_error(&cmd_buffer
->batch
))
1448 return cmd_buffer
->batch
.status
;
1450 /* We want every command buffer to start with the PMA fix in a known state,
1451 * so we disable it at the end of the command buffer.
1453 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1455 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1457 emit_isp_disable(cmd_buffer
);
1459 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1465 genX(CmdExecuteCommands
)(
1466 VkCommandBuffer commandBuffer
,
1467 uint32_t commandBufferCount
,
1468 const VkCommandBuffer
* pCmdBuffers
)
1470 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1472 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1474 if (anv_batch_has_error(&primary
->batch
))
1477 /* The secondary command buffers will assume that the PMA fix is disabled
1478 * when they begin executing. Make sure this is true.
1480 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1482 /* The secondary command buffer doesn't know which textures etc. have been
1483 * flushed prior to their execution. Apply those flushes now.
1485 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1487 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1488 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1490 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1491 assert(!anv_batch_has_error(&secondary
->batch
));
1493 if (secondary
->usage_flags
&
1494 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1495 /* If we're continuing a render pass from the primary, we need to
1496 * copy the surface states for the current subpass into the storage
1497 * we allocated for them in BeginCommandBuffer.
1499 struct anv_bo
*ss_bo
=
1500 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1501 struct anv_state src_state
= primary
->state
.render_pass_states
;
1502 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1503 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1505 genX(cmd_buffer_so_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
1506 ss_bo
, src_state
.offset
,
1507 src_state
.alloc_size
);
1510 anv_cmd_buffer_add_secondary(primary
, secondary
);
1513 /* The secondary may have selected a different pipeline (3D or compute) and
1514 * may have changed the current L3$ configuration. Reset our tracking
1515 * variables to invalid values to ensure that we re-emit these in the case
1516 * where we do any draws or compute dispatches from the primary after the
1517 * secondary has returned.
1519 primary
->state
.current_pipeline
= UINT32_MAX
;
1520 primary
->state
.current_l3_config
= NULL
;
1522 /* Each of the secondary command buffers will use its own state base
1523 * address. We need to re-emit state base address for the primary after
1524 * all of the secondaries are done.
1526 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1529 genX(cmd_buffer_emit_state_base_address
)(primary
);
1532 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1533 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1534 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1537 * Program the hardware to use the specified L3 configuration.
1540 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1541 const struct gen_l3_config
*cfg
)
1544 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1547 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1548 intel_logd("L3 config transition: ");
1549 gen_dump_l3_config(cfg
, stderr
);
1552 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1554 /* According to the hardware docs, the L3 partitioning can only be changed
1555 * while the pipeline is completely drained and the caches are flushed,
1556 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1558 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1559 pc
.DCFlushEnable
= true;
1560 pc
.PostSyncOperation
= NoWrite
;
1561 pc
.CommandStreamerStallEnable
= true;
1564 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1565 * invalidation of the relevant caches. Note that because RO invalidation
1566 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1567 * command is processed by the CS) we cannot combine it with the previous
1568 * stalling flush as the hardware documentation suggests, because that
1569 * would cause the CS to stall on previous rendering *after* RO
1570 * invalidation and wouldn't prevent the RO caches from being polluted by
1571 * concurrent rendering before the stall completes. This intentionally
1572 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1573 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1574 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1575 * already guarantee that there is no concurrent GPGPU kernel execution
1576 * (see SKL HSD 2132585).
1578 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1579 pc
.TextureCacheInvalidationEnable
= true;
1580 pc
.ConstantCacheInvalidationEnable
= true;
1581 pc
.InstructionCacheInvalidateEnable
= true;
1582 pc
.StateCacheInvalidationEnable
= true;
1583 pc
.PostSyncOperation
= NoWrite
;
1586 /* Now send a third stalling flush to make sure that invalidation is
1587 * complete when the L3 configuration registers are modified.
1589 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1590 pc
.DCFlushEnable
= true;
1591 pc
.PostSyncOperation
= NoWrite
;
1592 pc
.CommandStreamerStallEnable
= true;
1597 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1600 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1601 .SLMEnable
= has_slm
,
1602 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1603 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1604 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1605 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1607 /* Set up the L3 partitioning. */
1608 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1612 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1613 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1614 cfg
->n
[GEN_L3P_ALL
];
1615 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1616 cfg
->n
[GEN_L3P_ALL
];
1617 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1618 cfg
->n
[GEN_L3P_ALL
];
1620 assert(!cfg
->n
[GEN_L3P_ALL
]);
1622 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1623 * the matching space on the remaining banks has to be allocated to a
1624 * client (URB for all validated configurations) set to the
1625 * lower-bandwidth 2-bank address hashing mode.
1627 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1628 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1629 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1631 /* Minimum number of ways that can be allocated to the URB. */
1632 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1633 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1635 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1636 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1637 .ConvertDC_UC
= !has_dc
,
1638 .ConvertIS_UC
= !has_is
,
1639 .ConvertC_UC
= !has_c
,
1640 .ConvertT_UC
= !has_t
);
1642 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1643 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1644 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1646 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1647 .SLMEnable
= has_slm
,
1648 .URBLowBandwidth
= urb_low_bw
,
1649 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1651 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1653 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1654 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1656 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1657 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1658 .ISLowBandwidth
= 0,
1659 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1661 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1662 .TLowBandwidth
= 0);
1664 /* Set up the L3 partitioning. */
1665 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1666 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1667 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1670 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1671 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1672 * them disabled to avoid crashing the system hard.
1674 uint32_t scratch1
, chicken3
;
1675 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1676 .L3AtomicDisable
= !has_dc
);
1677 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1678 .L3AtomicDisableMask
= true,
1679 .L3AtomicDisable
= !has_dc
);
1680 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1681 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1687 cmd_buffer
->state
.current_l3_config
= cfg
;
1691 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1693 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1695 /* Flushes are pipelined while invalidations are handled immediately.
1696 * Therefore, if we're flushing anything then we need to schedule a stall
1697 * before any invalidations can happen.
1699 if (bits
& ANV_PIPE_FLUSH_BITS
)
1700 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1702 /* If we're going to do an invalidate and we have a pending CS stall that
1703 * has yet to be resolved, we do the CS stall now.
1705 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1706 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1707 bits
|= ANV_PIPE_CS_STALL_BIT
;
1708 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1711 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1712 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1713 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1714 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1715 pipe
.RenderTargetCacheFlushEnable
=
1716 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1718 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1719 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1720 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1723 * According to the Broadwell documentation, any PIPE_CONTROL with the
1724 * "Command Streamer Stall" bit set must also have another bit set,
1725 * with five different options:
1727 * - Render Target Cache Flush
1728 * - Depth Cache Flush
1729 * - Stall at Pixel Scoreboard
1730 * - Post-Sync Operation
1734 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1735 * mesa and it seems to work fine. The choice is fairly arbitrary.
1737 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1738 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1739 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1740 pipe
.StallAtPixelScoreboard
= true;
1743 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1746 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1747 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1748 pipe
.StateCacheInvalidationEnable
=
1749 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1750 pipe
.ConstantCacheInvalidationEnable
=
1751 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1752 pipe
.VFCacheInvalidationEnable
=
1753 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1754 pipe
.TextureCacheInvalidationEnable
=
1755 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1756 pipe
.InstructionCacheInvalidateEnable
=
1757 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1760 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1763 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1766 void genX(CmdPipelineBarrier
)(
1767 VkCommandBuffer commandBuffer
,
1768 VkPipelineStageFlags srcStageMask
,
1769 VkPipelineStageFlags destStageMask
,
1771 uint32_t memoryBarrierCount
,
1772 const VkMemoryBarrier
* pMemoryBarriers
,
1773 uint32_t bufferMemoryBarrierCount
,
1774 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1775 uint32_t imageMemoryBarrierCount
,
1776 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1778 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1780 /* XXX: Right now, we're really dumb and just flush whatever categories
1781 * the app asks for. One of these days we may make this a bit better
1782 * but right now that's all the hardware allows for in most areas.
1784 VkAccessFlags src_flags
= 0;
1785 VkAccessFlags dst_flags
= 0;
1787 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1788 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1789 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1792 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1793 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1794 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1797 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1798 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1799 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1800 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1801 const VkImageSubresourceRange
*range
=
1802 &pImageMemoryBarriers
[i
].subresourceRange
;
1804 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1805 transition_depth_buffer(cmd_buffer
, image
,
1806 pImageMemoryBarriers
[i
].oldLayout
,
1807 pImageMemoryBarriers
[i
].newLayout
);
1808 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1809 VkImageAspectFlags color_aspects
=
1810 anv_image_expand_aspects(image
, range
->aspectMask
);
1811 uint32_t aspect_bit
;
1813 uint32_t base_layer
, layer_count
;
1814 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1816 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1818 base_layer
= range
->baseArrayLayer
;
1819 layer_count
= anv_get_layerCount(image
, range
);
1822 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1823 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1824 range
->baseMipLevel
,
1825 anv_get_levelCount(image
, range
),
1826 base_layer
, layer_count
,
1827 pImageMemoryBarriers
[i
].oldLayout
,
1828 pImageMemoryBarriers
[i
].newLayout
);
1833 cmd_buffer
->state
.pending_pipe_bits
|=
1834 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1835 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1839 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1841 VkShaderStageFlags stages
=
1842 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1844 /* In order to avoid thrash, we assume that vertex and fragment stages
1845 * always exist. In the rare case where one is missing *and* the other
1846 * uses push concstants, this may be suboptimal. However, avoiding stalls
1847 * seems more important.
1849 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1851 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1855 const unsigned push_constant_kb
= 32;
1856 #elif GEN_IS_HASWELL
1857 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1859 const unsigned push_constant_kb
= 16;
1862 const unsigned num_stages
=
1863 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1864 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1866 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1867 * units of 2KB. Incidentally, these are the same platforms that have
1868 * 32KB worth of push constant space.
1870 if (push_constant_kb
== 32)
1871 size_per_stage
&= ~1u;
1873 uint32_t kb_used
= 0;
1874 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1875 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1876 anv_batch_emit(&cmd_buffer
->batch
,
1877 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1878 alloc
._3DCommandSubOpcode
= 18 + i
;
1879 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1880 alloc
.ConstantBufferSize
= push_size
;
1882 kb_used
+= push_size
;
1885 anv_batch_emit(&cmd_buffer
->batch
,
1886 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1887 alloc
.ConstantBufferOffset
= kb_used
;
1888 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1891 cmd_buffer
->state
.push_constant_stages
= stages
;
1893 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1895 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1896 * the next 3DPRIMITIVE command after programming the
1897 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1899 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1900 * pipeline setup, we need to dirty push constants.
1902 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1905 static const struct anv_descriptor
*
1906 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1907 const struct anv_pipeline_binding
*binding
)
1909 assert(binding
->set
< MAX_SETS
);
1910 const struct anv_descriptor_set
*set
=
1911 pipe_state
->descriptors
[binding
->set
];
1912 const uint32_t offset
=
1913 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1914 return &set
->descriptors
[offset
+ binding
->index
];
1918 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1919 const struct anv_pipeline_binding
*binding
)
1921 assert(binding
->set
< MAX_SETS
);
1922 const struct anv_descriptor_set
*set
=
1923 pipe_state
->descriptors
[binding
->set
];
1925 uint32_t dynamic_offset_idx
=
1926 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1927 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1930 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1934 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1935 gl_shader_stage stage
,
1936 struct anv_state
*bt_state
)
1938 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1939 struct anv_cmd_pipeline_state
*pipe_state
;
1940 struct anv_pipeline
*pipeline
;
1941 uint32_t bias
, state_offset
;
1944 case MESA_SHADER_COMPUTE
:
1945 pipe_state
= &cmd_buffer
->state
.compute
.base
;
1949 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
1953 pipeline
= pipe_state
->pipeline
;
1955 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1956 *bt_state
= (struct anv_state
) { 0, };
1960 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1961 if (bias
+ map
->surface_count
== 0) {
1962 *bt_state
= (struct anv_state
) { 0, };
1966 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1967 bias
+ map
->surface_count
,
1969 uint32_t *bt_map
= bt_state
->map
;
1971 if (bt_state
->map
== NULL
)
1972 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1974 if (stage
== MESA_SHADER_COMPUTE
&&
1975 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
1976 struct anv_bo
*bo
= cmd_buffer
->state
.compute
.num_workgroups
.bo
;
1977 uint32_t bo_offset
= cmd_buffer
->state
.compute
.num_workgroups
.offset
;
1979 struct anv_state surface_state
;
1981 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1983 const enum isl_format format
=
1984 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1985 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1986 format
, bo_offset
, 12, 1);
1988 bt_map
[0] = surface_state
.offset
+ state_offset
;
1989 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1992 if (map
->surface_count
== 0)
1995 if (map
->image_count
> 0) {
1997 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1998 if (result
!= VK_SUCCESS
)
2001 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2005 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2006 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2008 struct anv_state surface_state
;
2010 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2011 /* Color attachment binding */
2012 assert(stage
== MESA_SHADER_FRAGMENT
);
2013 assert(binding
->binding
== 0);
2014 if (binding
->index
< subpass
->color_count
) {
2015 const unsigned att
=
2016 subpass
->color_attachments
[binding
->index
].attachment
;
2018 /* From the Vulkan 1.0.46 spec:
2020 * "If any color or depth/stencil attachments are
2021 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2024 if (att
== VK_ATTACHMENT_UNUSED
) {
2025 surface_state
= cmd_buffer
->state
.null_surface_state
;
2027 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2030 surface_state
= cmd_buffer
->state
.null_surface_state
;
2033 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2037 const struct anv_descriptor
*desc
=
2038 anv_descriptor_for_binding(pipe_state
, binding
);
2040 switch (desc
->type
) {
2041 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2042 /* Nothing for us to do here */
2045 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2046 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2047 struct anv_surface_state sstate
=
2048 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2049 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2050 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2051 surface_state
= sstate
.state
;
2052 assert(surface_state
.alloc_size
);
2053 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
2054 binding
->plane
, sstate
);
2057 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2058 assert(stage
== MESA_SHADER_FRAGMENT
);
2059 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2060 /* For depth and stencil input attachments, we treat it like any
2061 * old texture that a user may have bound.
2063 struct anv_surface_state sstate
=
2064 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2065 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2066 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2067 surface_state
= sstate
.state
;
2068 assert(surface_state
.alloc_size
);
2069 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
2070 binding
->plane
, sstate
);
2072 /* For color input attachments, we create the surface state at
2073 * vkBeginRenderPass time so that we can include aux and clear
2074 * color information.
2076 assert(binding
->input_attachment_index
< subpass
->input_count
);
2077 const unsigned subpass_att
= binding
->input_attachment_index
;
2078 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2079 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2083 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2084 struct anv_surface_state sstate
= (binding
->write_only
)
2085 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2086 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2087 surface_state
= sstate
.state
;
2088 assert(surface_state
.alloc_size
);
2089 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
2090 binding
->plane
, sstate
);
2092 struct brw_image_param
*image_param
=
2093 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2095 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2096 image_param
->surface_idx
= bias
+ s
;
2100 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2101 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2102 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2103 surface_state
= desc
->buffer_view
->surface_state
;
2104 assert(surface_state
.alloc_size
);
2105 add_surface_state_reloc(cmd_buffer
, surface_state
,
2106 desc
->buffer_view
->bo
,
2107 desc
->buffer_view
->offset
);
2110 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2111 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2112 /* Compute the offset within the buffer */
2113 uint32_t dynamic_offset
=
2114 dynamic_offset_for_binding(pipe_state
, binding
);
2115 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2116 /* Clamp to the buffer size */
2117 offset
= MIN2(offset
, desc
->buffer
->size
);
2118 /* Clamp the range to the buffer size */
2119 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2122 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2123 enum isl_format format
=
2124 anv_isl_format_for_descriptor_type(desc
->type
);
2126 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2127 format
, offset
, range
, 1);
2128 add_surface_state_reloc(cmd_buffer
, surface_state
,
2130 desc
->buffer
->offset
+ offset
);
2134 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2135 surface_state
= (binding
->write_only
)
2136 ? desc
->buffer_view
->writeonly_storage_surface_state
2137 : desc
->buffer_view
->storage_surface_state
;
2138 assert(surface_state
.alloc_size
);
2139 add_surface_state_reloc(cmd_buffer
, surface_state
,
2140 desc
->buffer_view
->bo
,
2141 desc
->buffer_view
->offset
);
2143 struct brw_image_param
*image_param
=
2144 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2146 *image_param
= desc
->buffer_view
->storage_image_param
;
2147 image_param
->surface_idx
= bias
+ s
;
2151 assert(!"Invalid descriptor type");
2155 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2157 assert(image
== map
->image_count
);
2160 anv_state_flush(cmd_buffer
->device
, *bt_state
);
2163 /* The PIPE_CONTROL command description says:
2165 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2166 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2167 * Target Cache Flush by enabling this bit. When render target flush
2168 * is set due to new association of BTI, PS Scoreboard Stall bit must
2169 * be set in this packet."
2171 * FINISHME: Currently we shuffle around the surface states in the binding
2172 * table based on if they are getting used or not. So, we've to do below
2173 * pipe control flush for every binding table upload. Make changes so
2174 * that we do it only when we modify render target surface states.
2176 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2177 pc
.RenderTargetCacheFlushEnable
= true;
2178 pc
.StallAtPixelScoreboard
= true;
2186 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2187 gl_shader_stage stage
,
2188 struct anv_state
*state
)
2190 struct anv_cmd_pipeline_state
*pipe_state
=
2191 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2192 &cmd_buffer
->state
.gfx
.base
;
2193 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2195 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2196 *state
= (struct anv_state
) { 0, };
2200 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2201 if (map
->sampler_count
== 0) {
2202 *state
= (struct anv_state
) { 0, };
2206 uint32_t size
= map
->sampler_count
* 16;
2207 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2209 if (state
->map
== NULL
)
2210 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2212 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2213 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2214 const struct anv_descriptor
*desc
=
2215 anv_descriptor_for_binding(pipe_state
, binding
);
2217 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2218 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2221 struct anv_sampler
*sampler
= desc
->sampler
;
2223 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2224 * happens to be zero.
2226 if (sampler
== NULL
)
2229 memcpy(state
->map
+ (s
* 16),
2230 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2233 anv_state_flush(cmd_buffer
->device
, *state
);
2239 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2241 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2243 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2244 pipeline
->active_stages
;
2246 VkResult result
= VK_SUCCESS
;
2247 anv_foreach_stage(s
, dirty
) {
2248 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2249 if (result
!= VK_SUCCESS
)
2251 result
= emit_binding_table(cmd_buffer
, s
,
2252 &cmd_buffer
->state
.binding_tables
[s
]);
2253 if (result
!= VK_SUCCESS
)
2257 if (result
!= VK_SUCCESS
) {
2258 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2260 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2261 if (result
!= VK_SUCCESS
)
2264 /* Re-emit state base addresses so we get the new surface state base
2265 * address before we start emitting binding tables etc.
2267 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2269 /* Re-emit all active binding tables */
2270 dirty
|= pipeline
->active_stages
;
2271 anv_foreach_stage(s
, dirty
) {
2272 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2273 if (result
!= VK_SUCCESS
) {
2274 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2277 result
= emit_binding_table(cmd_buffer
, s
,
2278 &cmd_buffer
->state
.binding_tables
[s
]);
2279 if (result
!= VK_SUCCESS
) {
2280 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2286 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2292 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2295 static const uint32_t sampler_state_opcodes
[] = {
2296 [MESA_SHADER_VERTEX
] = 43,
2297 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2298 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2299 [MESA_SHADER_GEOMETRY
] = 46,
2300 [MESA_SHADER_FRAGMENT
] = 47,
2301 [MESA_SHADER_COMPUTE
] = 0,
2304 static const uint32_t binding_table_opcodes
[] = {
2305 [MESA_SHADER_VERTEX
] = 38,
2306 [MESA_SHADER_TESS_CTRL
] = 39,
2307 [MESA_SHADER_TESS_EVAL
] = 40,
2308 [MESA_SHADER_GEOMETRY
] = 41,
2309 [MESA_SHADER_FRAGMENT
] = 42,
2310 [MESA_SHADER_COMPUTE
] = 0,
2313 anv_foreach_stage(s
, stages
) {
2314 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2315 assert(binding_table_opcodes
[s
] > 0);
2317 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2318 anv_batch_emit(&cmd_buffer
->batch
,
2319 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2320 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2321 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2325 /* Always emit binding table pointers if we're asked to, since on SKL
2326 * this is what flushes push constants. */
2327 anv_batch_emit(&cmd_buffer
->batch
,
2328 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2329 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2330 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2336 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2337 VkShaderStageFlags dirty_stages
)
2339 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2340 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2342 static const uint32_t push_constant_opcodes
[] = {
2343 [MESA_SHADER_VERTEX
] = 21,
2344 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2345 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2346 [MESA_SHADER_GEOMETRY
] = 22,
2347 [MESA_SHADER_FRAGMENT
] = 23,
2348 [MESA_SHADER_COMPUTE
] = 0,
2351 VkShaderStageFlags flushed
= 0;
2353 anv_foreach_stage(stage
, dirty_stages
) {
2354 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2355 assert(push_constant_opcodes
[stage
] > 0);
2357 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2358 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2360 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2361 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2362 const struct brw_stage_prog_data
*prog_data
=
2363 pipeline
->shaders
[stage
]->prog_data
;
2364 const struct anv_pipeline_bind_map
*bind_map
=
2365 &pipeline
->shaders
[stage
]->bind_map
;
2367 /* The Skylake PRM contains the following restriction:
2369 * "The driver must ensure The following case does not occur
2370 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2371 * buffer 3 read length equal to zero committed followed by a
2372 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2375 * To avoid this, we program the buffers in the highest slots.
2376 * This way, slot 0 is only used if slot 3 is also used.
2380 for (int i
= 3; i
>= 0; i
--) {
2381 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2382 if (range
->length
== 0)
2385 const unsigned surface
=
2386 prog_data
->binding_table
.ubo_start
+ range
->block
;
2388 assert(surface
<= bind_map
->surface_count
);
2389 const struct anv_pipeline_binding
*binding
=
2390 &bind_map
->surface_to_descriptor
[surface
];
2392 const struct anv_descriptor
*desc
=
2393 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2395 struct anv_address read_addr
;
2397 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2398 read_len
= MIN2(range
->length
,
2399 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2400 read_addr
= (struct anv_address
) {
2401 .bo
= desc
->buffer_view
->bo
,
2402 .offset
= desc
->buffer_view
->offset
+
2406 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2408 uint32_t dynamic_offset
=
2409 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2410 uint32_t buf_offset
=
2411 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2412 uint32_t buf_range
=
2413 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2415 read_len
= MIN2(range
->length
,
2416 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2417 read_addr
= (struct anv_address
) {
2418 .bo
= desc
->buffer
->bo
,
2419 .offset
= desc
->buffer
->offset
+ buf_offset
+
2425 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2426 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2431 struct anv_state state
=
2432 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2434 if (state
.alloc_size
> 0) {
2435 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2436 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2437 .offset
= state
.offset
,
2439 c
.ConstantBody
.ReadLength
[n
] =
2440 DIV_ROUND_UP(state
.alloc_size
, 32);
2443 /* For Ivy Bridge, the push constants packets have a different
2444 * rule that would require us to iterate in the other direction
2445 * and possibly mess around with dynamic state base address.
2446 * Don't bother; just emit regular push constants at n = 0.
2448 struct anv_state state
=
2449 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2451 if (state
.alloc_size
> 0) {
2452 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2453 c
.ConstantBody
.ReadLength
[0] =
2454 DIV_ROUND_UP(state
.alloc_size
, 32);
2460 flushed
|= mesa_to_vk_shader_stage(stage
);
2463 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2467 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2469 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2472 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2474 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2476 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2478 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2481 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2482 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2484 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2485 GENX(3DSTATE_VERTEX_BUFFERS
));
2487 for_each_bit(vb
, vb_emit
) {
2488 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2489 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2491 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2492 .VertexBufferIndex
= vb
,
2495 .MemoryObjectControlState
= GENX(MOCS
),
2497 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
2498 /* Our implementation of VK_KHR_multiview uses instancing to draw
2499 * the different views. If the client asks for instancing, we
2500 * need to use the Instance Data Step Rate to ensure that we
2501 * repeat the client's per-instance data once for each view.
2503 .InstanceDataStepRate
= anv_subpass_view_count(pipeline
->subpass
),
2504 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2507 .AddressModifyEnable
= true,
2508 .BufferPitch
= pipeline
->binding_stride
[vb
],
2509 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
2512 .BufferSize
= buffer
->size
- offset
2514 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
2518 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2523 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2525 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2526 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2528 /* The exact descriptor layout is pulled from the pipeline, so we need
2529 * to re-emit binding tables on every pipeline change.
2531 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2533 /* If the pipeline changed, we may need to re-allocate push constant
2536 cmd_buffer_alloc_push_constants(cmd_buffer
);
2540 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2541 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2542 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2544 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2545 * stall needs to be sent just prior to any 3DSTATE_VS,
2546 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2547 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2548 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2549 * PIPE_CONTROL needs to be sent before any combination of VS
2550 * associated 3DSTATE."
2552 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2553 pc
.DepthStallEnable
= true;
2554 pc
.PostSyncOperation
= WriteImmediateData
;
2556 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2561 /* Render targets live in the same binding table as fragment descriptors */
2562 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2563 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2565 /* We emit the binding tables and sampler tables first, then emit push
2566 * constants and then finally emit binding table and sampler table
2567 * pointers. It has to happen in this order, since emitting the binding
2568 * tables may change the push constants (in case of storage images). After
2569 * emitting push constants, on SKL+ we have to emit the corresponding
2570 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2573 if (cmd_buffer
->state
.descriptors_dirty
)
2574 dirty
= flush_descriptor_sets(cmd_buffer
);
2576 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2577 /* Because we're pushing UBOs, we have to push whenever either
2578 * descriptors or push constants is dirty.
2580 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2581 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2582 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2586 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2588 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2589 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2591 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2592 ANV_CMD_DIRTY_PIPELINE
)) {
2593 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2594 pipeline
->depth_clamp_enable
);
2597 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
2598 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2600 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2602 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2606 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2607 struct anv_bo
*bo
, uint32_t offset
,
2608 uint32_t size
, uint32_t index
)
2610 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2611 GENX(3DSTATE_VERTEX_BUFFERS
));
2613 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2614 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2615 .VertexBufferIndex
= index
,
2616 .AddressModifyEnable
= true,
2619 .MemoryObjectControlState
= GENX(MOCS
),
2620 .BufferStartingAddress
= { bo
, offset
},
2623 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2624 .BufferStartingAddress
= { bo
, offset
},
2625 .EndAddress
= { bo
, offset
+ size
},
2631 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2632 struct anv_bo
*bo
, uint32_t offset
)
2634 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
2638 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2639 uint32_t base_vertex
, uint32_t base_instance
)
2641 struct anv_state id_state
=
2642 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2644 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2645 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2647 anv_state_flush(cmd_buffer
->device
, id_state
);
2649 emit_base_vertex_instance_bo(cmd_buffer
,
2650 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
, id_state
.offset
);
2654 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2656 struct anv_state state
=
2657 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2659 ((uint32_t *)state
.map
)[0] = draw_index
;
2661 anv_state_flush(cmd_buffer
->device
, state
);
2663 emit_vertex_bo(cmd_buffer
,
2664 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2665 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
2669 VkCommandBuffer commandBuffer
,
2670 uint32_t vertexCount
,
2671 uint32_t instanceCount
,
2672 uint32_t firstVertex
,
2673 uint32_t firstInstance
)
2675 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2676 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2677 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2679 if (anv_batch_has_error(&cmd_buffer
->batch
))
2682 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2684 if (vs_prog_data
->uses_firstvertex
||
2685 vs_prog_data
->uses_baseinstance
)
2686 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2687 if (vs_prog_data
->uses_drawid
)
2688 emit_draw_index(cmd_buffer
, 0);
2690 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2691 * different views. We need to multiply instanceCount by the view count.
2693 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2695 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2696 prim
.VertexAccessType
= SEQUENTIAL
;
2697 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2698 prim
.VertexCountPerInstance
= vertexCount
;
2699 prim
.StartVertexLocation
= firstVertex
;
2700 prim
.InstanceCount
= instanceCount
;
2701 prim
.StartInstanceLocation
= firstInstance
;
2702 prim
.BaseVertexLocation
= 0;
2706 void genX(CmdDrawIndexed
)(
2707 VkCommandBuffer commandBuffer
,
2708 uint32_t indexCount
,
2709 uint32_t instanceCount
,
2710 uint32_t firstIndex
,
2711 int32_t vertexOffset
,
2712 uint32_t firstInstance
)
2714 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2715 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2716 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2718 if (anv_batch_has_error(&cmd_buffer
->batch
))
2721 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2723 if (vs_prog_data
->uses_firstvertex
||
2724 vs_prog_data
->uses_baseinstance
)
2725 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2726 if (vs_prog_data
->uses_drawid
)
2727 emit_draw_index(cmd_buffer
, 0);
2729 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2730 * different views. We need to multiply instanceCount by the view count.
2732 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2734 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2735 prim
.VertexAccessType
= RANDOM
;
2736 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2737 prim
.VertexCountPerInstance
= indexCount
;
2738 prim
.StartVertexLocation
= firstIndex
;
2739 prim
.InstanceCount
= instanceCount
;
2740 prim
.StartInstanceLocation
= firstInstance
;
2741 prim
.BaseVertexLocation
= vertexOffset
;
2745 /* Auto-Draw / Indirect Registers */
2746 #define GEN7_3DPRIM_END_OFFSET 0x2420
2747 #define GEN7_3DPRIM_START_VERTEX 0x2430
2748 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2749 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2750 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2751 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2753 /* MI_MATH only exists on Haswell+ */
2754 #if GEN_IS_HASWELL || GEN_GEN >= 8
2756 /* Emit dwords to multiply GPR0 by N */
2758 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2760 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2762 #define append_alu(opcode, operand1, operand2) \
2763 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2766 unsigned top_bit
= 31 - __builtin_clz(N
);
2767 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2768 /* We get our initial data in GPR0 and we write the final data out to
2769 * GPR0 but we use GPR1 as our scratch register.
2771 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2772 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2774 /* Shift the current value left by 1 */
2775 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2776 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2777 append_alu(MI_ALU_ADD
, 0, 0);
2780 /* Store ACCU to R1 and add R0 to R1 */
2781 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2782 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2783 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2784 append_alu(MI_ALU_ADD
, 0, 0);
2787 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2794 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2796 uint32_t num_dwords
;
2797 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2799 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2800 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2803 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2806 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2807 struct anv_buffer
*buffer
, uint64_t offset
,
2810 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2811 struct anv_bo
*bo
= buffer
->bo
;
2812 uint32_t bo_offset
= buffer
->offset
+ offset
;
2814 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
2816 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2817 if (view_count
> 1) {
2818 #if GEN_IS_HASWELL || GEN_GEN >= 8
2819 emit_lrm(batch
, CS_GPR(0), bo
, bo_offset
+ 4);
2820 emit_mul_gpr0(batch
, view_count
);
2821 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2823 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2824 "MI_MATH is not supported on Ivy Bridge");
2825 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2828 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2831 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
2834 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
2835 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
2837 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
2838 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2842 void genX(CmdDrawIndirect
)(
2843 VkCommandBuffer commandBuffer
,
2845 VkDeviceSize offset
,
2849 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2850 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2851 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2852 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2854 if (anv_batch_has_error(&cmd_buffer
->batch
))
2857 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2859 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2860 struct anv_bo
*bo
= buffer
->bo
;
2861 uint32_t bo_offset
= buffer
->offset
+ offset
;
2863 if (vs_prog_data
->uses_firstvertex
||
2864 vs_prog_data
->uses_baseinstance
)
2865 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
2866 if (vs_prog_data
->uses_drawid
)
2867 emit_draw_index(cmd_buffer
, i
);
2869 load_indirect_parameters(cmd_buffer
, buffer
, offset
, false);
2871 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2872 prim
.IndirectParameterEnable
= true;
2873 prim
.VertexAccessType
= SEQUENTIAL
;
2874 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2881 void genX(CmdDrawIndexedIndirect
)(
2882 VkCommandBuffer commandBuffer
,
2884 VkDeviceSize offset
,
2888 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2889 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2890 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2891 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2893 if (anv_batch_has_error(&cmd_buffer
->batch
))
2896 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2898 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2899 struct anv_bo
*bo
= buffer
->bo
;
2900 uint32_t bo_offset
= buffer
->offset
+ offset
;
2902 /* TODO: We need to stomp base vertex to 0 somehow */
2903 if (vs_prog_data
->uses_firstvertex
||
2904 vs_prog_data
->uses_baseinstance
)
2905 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
2906 if (vs_prog_data
->uses_drawid
)
2907 emit_draw_index(cmd_buffer
, i
);
2909 load_indirect_parameters(cmd_buffer
, buffer
, offset
, true);
2911 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2912 prim
.IndirectParameterEnable
= true;
2913 prim
.VertexAccessType
= RANDOM
;
2914 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2922 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2924 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2925 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2928 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2929 if (result
!= VK_SUCCESS
) {
2930 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2932 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2933 if (result
!= VK_SUCCESS
)
2936 /* Re-emit state base addresses so we get the new surface state base
2937 * address before we start emitting binding tables etc.
2939 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2941 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2942 if (result
!= VK_SUCCESS
) {
2943 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2948 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
2949 if (result
!= VK_SUCCESS
) {
2950 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2954 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
2955 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2956 .BindingTablePointer
= surfaces
.offset
,
2957 .SamplerStatePointer
= samplers
.offset
,
2959 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
2961 struct anv_state state
=
2962 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
2963 pipeline
->interface_descriptor_data
,
2964 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
2967 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
2968 anv_batch_emit(&cmd_buffer
->batch
,
2969 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
2970 mid
.InterfaceDescriptorTotalLength
= size
;
2971 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
2978 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2980 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2981 MAYBE_UNUSED VkResult result
;
2983 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
2985 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2987 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
2989 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
2990 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
2992 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
2993 * the only bits that are changed are scoreboard related: Scoreboard
2994 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
2995 * these scoreboard related states, a MEDIA_STATE_FLUSH is
2998 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2999 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3001 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3004 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3005 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3006 /* FIXME: figure out descriptors for gen7 */
3007 result
= flush_compute_descriptor_set(cmd_buffer
);
3008 if (result
!= VK_SUCCESS
)
3011 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3014 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3015 struct anv_state push_state
=
3016 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3018 if (push_state
.alloc_size
) {
3019 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3020 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3021 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3026 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3028 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3034 verify_cmd_parser(const struct anv_device
*device
,
3035 int required_version
,
3036 const char *function
)
3038 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3039 return vk_errorf(device
->instance
, device
->instance
,
3040 VK_ERROR_FEATURE_NOT_PRESENT
,
3041 "cmd parser version %d is required for %s",
3042 required_version
, function
);
3051 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3052 uint32_t baseGroupX
,
3053 uint32_t baseGroupY
,
3054 uint32_t baseGroupZ
)
3056 if (anv_batch_has_error(&cmd_buffer
->batch
))
3060 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3061 base_work_group_id
);
3062 if (result
!= VK_SUCCESS
) {
3063 cmd_buffer
->batch
.status
= result
;
3067 struct anv_push_constants
*push
=
3068 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3069 if (push
->base_work_group_id
[0] != baseGroupX
||
3070 push
->base_work_group_id
[1] != baseGroupY
||
3071 push
->base_work_group_id
[2] != baseGroupZ
) {
3072 push
->base_work_group_id
[0] = baseGroupX
;
3073 push
->base_work_group_id
[1] = baseGroupY
;
3074 push
->base_work_group_id
[2] = baseGroupZ
;
3076 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3080 void genX(CmdDispatch
)(
3081 VkCommandBuffer commandBuffer
,
3086 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3089 void genX(CmdDispatchBase
)(
3090 VkCommandBuffer commandBuffer
,
3091 uint32_t baseGroupX
,
3092 uint32_t baseGroupY
,
3093 uint32_t baseGroupZ
,
3094 uint32_t groupCountX
,
3095 uint32_t groupCountY
,
3096 uint32_t groupCountZ
)
3098 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3099 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3100 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3102 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3103 baseGroupY
, baseGroupZ
);
3105 if (anv_batch_has_error(&cmd_buffer
->batch
))
3108 if (prog_data
->uses_num_work_groups
) {
3109 struct anv_state state
=
3110 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3111 uint32_t *sizes
= state
.map
;
3112 sizes
[0] = groupCountX
;
3113 sizes
[1] = groupCountY
;
3114 sizes
[2] = groupCountZ
;
3115 anv_state_flush(cmd_buffer
->device
, state
);
3116 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3117 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3118 .offset
= state
.offset
,
3122 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3124 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3125 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3126 ggw
.ThreadDepthCounterMaximum
= 0;
3127 ggw
.ThreadHeightCounterMaximum
= 0;
3128 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3129 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3130 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3131 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3132 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3133 ggw
.BottomExecutionMask
= 0xffffffff;
3136 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3139 #define GPGPU_DISPATCHDIMX 0x2500
3140 #define GPGPU_DISPATCHDIMY 0x2504
3141 #define GPGPU_DISPATCHDIMZ 0x2508
3143 void genX(CmdDispatchIndirect
)(
3144 VkCommandBuffer commandBuffer
,
3146 VkDeviceSize offset
)
3148 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3149 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3150 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3151 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3152 struct anv_bo
*bo
= buffer
->bo
;
3153 uint32_t bo_offset
= buffer
->offset
+ offset
;
3154 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3156 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3159 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3160 * indirect dispatch registers to be written.
3162 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3163 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3167 if (prog_data
->uses_num_work_groups
) {
3168 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3170 .offset
= bo_offset
,
3174 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3176 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
3177 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
3178 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
3181 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3182 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3183 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3184 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3186 /* Load compute_dispatch_indirect_x_size into SRC0 */
3187 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
3189 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3190 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3191 mip
.LoadOperation
= LOAD_LOAD
;
3192 mip
.CombineOperation
= COMBINE_SET
;
3193 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3196 /* Load compute_dispatch_indirect_y_size into SRC0 */
3197 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
3199 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3200 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3201 mip
.LoadOperation
= LOAD_LOAD
;
3202 mip
.CombineOperation
= COMBINE_OR
;
3203 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3206 /* Load compute_dispatch_indirect_z_size into SRC0 */
3207 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
3209 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3210 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3211 mip
.LoadOperation
= LOAD_LOAD
;
3212 mip
.CombineOperation
= COMBINE_OR
;
3213 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3216 /* predicate = !predicate; */
3217 #define COMPARE_FALSE 1
3218 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3219 mip
.LoadOperation
= LOAD_LOADINV
;
3220 mip
.CombineOperation
= COMBINE_OR
;
3221 mip
.CompareOperation
= COMPARE_FALSE
;
3225 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3226 ggw
.IndirectParameterEnable
= true;
3227 ggw
.PredicateEnable
= GEN_GEN
<= 7;
3228 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3229 ggw
.ThreadDepthCounterMaximum
= 0;
3230 ggw
.ThreadHeightCounterMaximum
= 0;
3231 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3232 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3233 ggw
.BottomExecutionMask
= 0xffffffff;
3236 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3240 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3243 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3245 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3248 #if GEN_GEN >= 8 && GEN_GEN < 10
3249 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3251 * Software must clear the COLOR_CALC_STATE Valid field in
3252 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3253 * with Pipeline Select set to GPGPU.
3255 * The internal hardware docs recommend the same workaround for Gen9
3258 if (pipeline
== GPGPU
)
3259 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3262 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3263 * PIPELINE_SELECT [DevBWR+]":
3267 * Software must ensure all the write caches are flushed through a
3268 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3269 * command to invalidate read only caches prior to programming
3270 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3272 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3273 pc
.RenderTargetCacheFlushEnable
= true;
3274 pc
.DepthCacheFlushEnable
= true;
3275 pc
.DCFlushEnable
= true;
3276 pc
.PostSyncOperation
= NoWrite
;
3277 pc
.CommandStreamerStallEnable
= true;
3280 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3281 pc
.TextureCacheInvalidationEnable
= true;
3282 pc
.ConstantCacheInvalidationEnable
= true;
3283 pc
.StateCacheInvalidationEnable
= true;
3284 pc
.InstructionCacheInvalidateEnable
= true;
3285 pc
.PostSyncOperation
= NoWrite
;
3288 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3292 ps
.PipelineSelection
= pipeline
;
3296 if (devinfo
->is_geminilake
) {
3299 * "This chicken bit works around a hardware issue with barrier logic
3300 * encountered when switching between GPGPU and 3D pipelines. To
3301 * workaround the issue, this mode bit should be set after a pipeline
3305 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3307 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3308 : GLK_BARRIER_MODE_3D_HULL
,
3309 .GLKBarrierModeMask
= 1);
3310 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3314 cmd_buffer
->state
.current_pipeline
= pipeline
;
3318 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3320 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3324 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3326 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3330 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3335 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3337 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3338 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3339 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3340 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3341 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3342 * Depth Flush Bit set, followed by another pipelined depth stall
3343 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3344 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3345 * via a preceding MI_FLUSH)."
3347 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3348 pipe
.DepthStallEnable
= true;
3350 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3351 pipe
.DepthCacheFlushEnable
= true;
3353 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3354 pipe
.DepthStallEnable
= true;
3359 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3361 struct anv_device
*device
= cmd_buffer
->device
;
3362 const struct anv_image_view
*iview
=
3363 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3364 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3366 /* FIXME: Width and Height are wrong */
3368 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3370 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3371 device
->isl_dev
.ds
.size
/ 4);
3375 struct isl_depth_stencil_hiz_emit_info info
= {
3376 .mocs
= device
->default_mocs
,
3380 info
.view
= &iview
->planes
[0].isl
;
3382 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3383 uint32_t depth_plane
=
3384 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3385 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3387 info
.depth_surf
= &surface
->isl
;
3389 info
.depth_address
=
3390 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3391 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3392 image
->planes
[depth_plane
].bo
,
3393 image
->planes
[depth_plane
].bo_offset
+
3397 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.attachment
;
3398 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3399 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3400 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3403 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3404 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3405 image
->planes
[depth_plane
].bo
,
3406 image
->planes
[depth_plane
].bo_offset
+
3407 image
->planes
[depth_plane
].aux_surface
.offset
);
3409 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3413 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3414 uint32_t stencil_plane
=
3415 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3416 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3418 info
.stencil_surf
= &surface
->isl
;
3420 info
.stencil_address
=
3421 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3422 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3423 image
->planes
[stencil_plane
].bo
,
3424 image
->planes
[stencil_plane
].bo_offset
+ surface
->offset
);
3427 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3429 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3433 * This ANDs the view mask of the current subpass with the pending clear
3434 * views in the attachment to get the mask of views active in the subpass
3435 * that still need to be cleared.
3437 static inline uint32_t
3438 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3439 const struct anv_attachment_state
*att_state
)
3441 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3445 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3446 const struct anv_attachment_state
*att_state
)
3448 if (!cmd_state
->subpass
->view_mask
)
3451 uint32_t pending_clear_mask
=
3452 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3454 return pending_clear_mask
& 1;
3458 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3461 const uint32_t last_subpass_idx
=
3462 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3463 const struct anv_subpass
*last_subpass
=
3464 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3465 return last_subpass
== cmd_state
->subpass
;
3469 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3470 uint32_t subpass_id
)
3472 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3473 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3474 cmd_state
->subpass
= subpass
;
3476 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3478 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3479 * different views. If the client asks for instancing, we need to use the
3480 * Instance Data Step Rate to ensure that we repeat the client's
3481 * per-instance data once for each view. Since this bit is in
3482 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3486 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3488 /* It is possible to start a render pass with an old pipeline. Because the
3489 * render pass and subpass index are both baked into the pipeline, this is
3490 * highly unlikely. In order to do so, it requires that you have a render
3491 * pass with a single subpass and that you use that render pass twice
3492 * back-to-back and use the same pipeline at the start of the second render
3493 * pass as at the end of the first. In order to avoid unpredictable issues
3494 * with this edge case, we just dirty the pipeline at the start of every
3497 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3499 /* Accumulate any subpass flushes that need to happen before the subpass */
3500 cmd_buffer
->state
.pending_pipe_bits
|=
3501 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3503 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3504 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3506 bool is_multiview
= subpass
->view_mask
!= 0;
3508 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3509 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3510 if (a
== VK_ATTACHMENT_UNUSED
)
3513 assert(a
< cmd_state
->pass
->attachment_count
);
3514 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3516 struct anv_image_view
*iview
= fb
->attachments
[a
];
3517 const struct anv_image
*image
= iview
->image
;
3519 /* A resolve is necessary before use as an input attachment if the clear
3520 * color or auxiliary buffer usage isn't supported by the sampler.
3522 const bool input_needs_resolve
=
3523 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3524 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3526 VkImageLayout target_layout
;
3527 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3528 !input_needs_resolve
) {
3529 /* Layout transitions before the final only help to enable sampling
3530 * as an input attachment. If the input attachment supports sampling
3531 * using the auxiliary surface, we can skip such transitions by
3532 * making the target layout one that is CCS-aware.
3534 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3536 target_layout
= subpass
->attachments
[i
].layout
;
3539 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3540 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3542 uint32_t base_layer
, layer_count
;
3543 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3545 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3546 iview
->planes
[0].isl
.base_level
);
3548 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3549 layer_count
= fb
->layers
;
3552 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3553 iview
->planes
[0].isl
.base_level
, 1,
3554 base_layer
, layer_count
,
3555 att_state
->current_layout
, target_layout
);
3556 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3557 transition_depth_buffer(cmd_buffer
, image
,
3558 att_state
->current_layout
, target_layout
);
3559 att_state
->aux_usage
=
3560 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3561 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3563 att_state
->current_layout
= target_layout
;
3565 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3566 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3568 /* Multi-planar images are not supported as attachments */
3569 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3570 assert(image
->n_planes
== 1);
3572 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
3573 uint32_t clear_layer_count
= fb
->layers
;
3575 if (att_state
->fast_clear
&&
3576 do_first_layer_clear(cmd_state
, att_state
)) {
3577 /* We only support fast-clears on the first layer */
3578 assert(iview
->planes
[0].isl
.base_level
== 0);
3579 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3581 union isl_color_value clear_color
= {};
3582 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
3583 if (iview
->image
->samples
== 1) {
3584 anv_image_ccs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3585 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3589 anv_image_mcs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3590 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3595 clear_layer_count
--;
3597 att_state
->pending_clear_views
&= ~1;
3599 if (att_state
->clear_color_is_zero
) {
3600 /* This image has the auxiliary buffer enabled. We can mark the
3601 * subresource as not needing a resolve because the clear color
3602 * will match what's in every RENDER_SURFACE_STATE object when
3603 * it's being used for sampling.
3605 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3606 VK_IMAGE_ASPECT_COLOR_BIT
,
3607 ANV_FAST_CLEAR_DEFAULT_VALUE
);
3609 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3610 VK_IMAGE_ASPECT_COLOR_BIT
,
3611 ANV_FAST_CLEAR_ANY
);
3615 /* From the VkFramebufferCreateInfo spec:
3617 * "If the render pass uses multiview, then layers must be one and each
3618 * attachment requires a number of layers that is greater than the
3619 * maximum bit index set in the view mask in the subpasses in which it
3622 * So if multiview is active we ignore the number of layers in the
3623 * framebuffer and instead we honor the view mask from the subpass.
3626 assert(image
->n_planes
== 1);
3627 uint32_t pending_clear_mask
=
3628 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3631 for_each_bit(layer_idx
, pending_clear_mask
) {
3633 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3635 anv_image_clear_color(cmd_buffer
, image
,
3636 VK_IMAGE_ASPECT_COLOR_BIT
,
3637 att_state
->aux_usage
,
3638 iview
->planes
[0].isl
.format
,
3639 iview
->planes
[0].isl
.swizzle
,
3640 iview
->planes
[0].isl
.base_level
,
3643 vk_to_isl_color(att_state
->clear_value
.color
));
3646 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3647 } else if (clear_layer_count
> 0) {
3648 assert(image
->n_planes
== 1);
3649 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3650 att_state
->aux_usage
,
3651 iview
->planes
[0].isl
.format
,
3652 iview
->planes
[0].isl
.swizzle
,
3653 iview
->planes
[0].isl
.base_level
,
3654 base_clear_layer
, clear_layer_count
,
3656 vk_to_isl_color(att_state
->clear_value
.color
));
3658 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
3659 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3660 if (att_state
->fast_clear
&& !is_multiview
) {
3661 /* We currently only support HiZ for single-layer images */
3662 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3663 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
3664 assert(iview
->planes
[0].isl
.base_level
== 0);
3665 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3666 assert(fb
->layers
== 1);
3669 anv_image_hiz_clear(cmd_buffer
, image
,
3670 att_state
->pending_clear_aspects
,
3671 iview
->planes
[0].isl
.base_level
,
3672 iview
->planes
[0].isl
.base_array_layer
,
3673 fb
->layers
, render_area
,
3674 att_state
->clear_value
.depthStencil
.stencil
);
3675 } else if (is_multiview
) {
3676 uint32_t pending_clear_mask
=
3677 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3680 for_each_bit(layer_idx
, pending_clear_mask
) {
3682 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3684 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3685 att_state
->pending_clear_aspects
,
3686 att_state
->aux_usage
,
3687 iview
->planes
[0].isl
.base_level
,
3690 att_state
->clear_value
.depthStencil
.depth
,
3691 att_state
->clear_value
.depthStencil
.stencil
);
3694 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3696 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3697 att_state
->pending_clear_aspects
,
3698 att_state
->aux_usage
,
3699 iview
->planes
[0].isl
.base_level
,
3700 iview
->planes
[0].isl
.base_array_layer
,
3701 fb
->layers
, render_area
,
3702 att_state
->clear_value
.depthStencil
.depth
,
3703 att_state
->clear_value
.depthStencil
.stencil
);
3706 assert(att_state
->pending_clear_aspects
== 0);
3710 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
3711 image
->planes
[0].aux_surface
.isl
.size
> 0 &&
3712 iview
->planes
[0].isl
.base_level
== 0 &&
3713 iview
->planes
[0].isl
.base_array_layer
== 0) {
3714 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
3715 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3716 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3717 false /* copy to ss */);
3720 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
3721 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3722 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3723 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3724 false /* copy to ss */);
3728 if (subpass
->attachments
[i
].usage
==
3729 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
3730 /* We assume that if we're starting a subpass, we're going to do some
3731 * rendering so we may end up with compressed data.
3733 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
3734 VK_IMAGE_ASPECT_COLOR_BIT
,
3735 att_state
->aux_usage
,
3736 iview
->planes
[0].isl
.base_level
,
3737 iview
->planes
[0].isl
.base_array_layer
,
3739 } else if (subpass
->attachments
[i
].usage
==
3740 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
3741 /* We may be writing depth or stencil so we need to mark the surface.
3742 * Unfortunately, there's no way to know at this point whether the
3743 * depth or stencil tests used will actually write to the surface.
3745 * Even though stencil may be plane 1, it always shares a base_level
3748 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
3749 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3750 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3751 VK_IMAGE_ASPECT_DEPTH_BIT
,
3752 att_state
->aux_usage
,
3753 ds_view
->base_level
,
3754 ds_view
->base_array_layer
,
3757 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
3758 /* Even though stencil may be plane 1, it always shares a
3759 * base_level with depth.
3761 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3762 VK_IMAGE_ASPECT_STENCIL_BIT
,
3764 ds_view
->base_level
,
3765 ds_view
->base_array_layer
,
3770 /* If multiview is enabled, then we are only done clearing when we no
3771 * longer have pending layers to clear, or when we have processed the
3772 * last subpass that uses this attachment.
3774 if (!is_multiview
||
3775 att_state
->pending_clear_views
== 0 ||
3776 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
3777 att_state
->pending_clear_aspects
= 0;
3780 att_state
->pending_load_aspects
= 0;
3783 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3787 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
3789 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3790 struct anv_subpass
*subpass
= cmd_state
->subpass
;
3791 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3793 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3795 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3796 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3797 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3798 if (a
== VK_ATTACHMENT_UNUSED
)
3801 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3804 assert(a
< cmd_state
->pass
->attachment_count
);
3805 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3806 struct anv_image_view
*iview
= fb
->attachments
[a
];
3807 const struct anv_image
*image
= iview
->image
;
3809 /* Transition the image into the final layout for this render pass */
3810 VkImageLayout target_layout
=
3811 cmd_state
->pass
->attachments
[a
].final_layout
;
3813 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3814 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3816 uint32_t base_layer
, layer_count
;
3817 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3819 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3820 iview
->planes
[0].isl
.base_level
);
3822 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3823 layer_count
= fb
->layers
;
3826 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3827 iview
->planes
[0].isl
.base_level
, 1,
3828 base_layer
, layer_count
,
3829 att_state
->current_layout
, target_layout
);
3830 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3831 transition_depth_buffer(cmd_buffer
, image
,
3832 att_state
->current_layout
, target_layout
);
3836 /* Accumulate any subpass flushes that need to happen after the subpass.
3837 * Yes, they do get accumulated twice in the NextSubpass case but since
3838 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
3839 * ORing the bits in twice so it's harmless.
3841 cmd_buffer
->state
.pending_pipe_bits
|=
3842 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
3845 void genX(CmdBeginRenderPass
)(
3846 VkCommandBuffer commandBuffer
,
3847 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3848 VkSubpassContents contents
)
3850 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3851 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3852 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3854 cmd_buffer
->state
.framebuffer
= framebuffer
;
3855 cmd_buffer
->state
.pass
= pass
;
3856 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3858 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3860 /* If we failed to setup the attachments we should not try to go further */
3861 if (result
!= VK_SUCCESS
) {
3862 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3866 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3868 cmd_buffer_begin_subpass(cmd_buffer
, 0);
3871 void genX(CmdNextSubpass
)(
3872 VkCommandBuffer commandBuffer
,
3873 VkSubpassContents contents
)
3875 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3877 if (anv_batch_has_error(&cmd_buffer
->batch
))
3880 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3882 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
3883 cmd_buffer_end_subpass(cmd_buffer
);
3884 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3887 void genX(CmdEndRenderPass
)(
3888 VkCommandBuffer commandBuffer
)
3890 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3892 if (anv_batch_has_error(&cmd_buffer
->batch
))
3895 cmd_buffer_end_subpass(cmd_buffer
);
3897 cmd_buffer
->state
.hiz_enabled
= false;
3900 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
3903 /* Remove references to render pass specific state. This enables us to
3904 * detect whether or not we're in a renderpass.
3906 cmd_buffer
->state
.framebuffer
= NULL
;
3907 cmd_buffer
->state
.pass
= NULL
;
3908 cmd_buffer
->state
.subpass
= NULL
;