2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
,
37 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
83 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
84 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
85 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
86 sba
.GeneralStateBaseAddressModifyEnable
= true;
88 sba
.SurfaceStateBaseAddress
=
89 anv_cmd_buffer_surface_base_address(cmd_buffer
);
90 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
91 sba
.SurfaceStateBaseAddressModifyEnable
= true;
93 sba
.DynamicStateBaseAddress
=
94 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
95 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
96 sba
.DynamicStateBaseAddressModifyEnable
= true;
98 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
99 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
100 sba
.IndirectObjectBaseAddressModifyEnable
= true;
102 sba
.InstructionBaseAddress
=
103 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
104 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
105 sba
.InstructionBaseAddressModifyEnable
= true;
108 /* Broadwell requires that we specify a buffer size for a bunch of
109 * these fields. However, since we will be growing the BO's live, we
110 * just set them all to the maximum.
112 sba
.GeneralStateBufferSize
= 0xfffff;
113 sba
.GeneralStateBufferSizeModifyEnable
= true;
114 sba
.DynamicStateBufferSize
= 0xfffff;
115 sba
.DynamicStateBufferSizeModifyEnable
= true;
116 sba
.IndirectObjectBufferSize
= 0xfffff;
117 sba
.IndirectObjectBufferSizeModifyEnable
= true;
118 sba
.InstructionBufferSize
= 0xfffff;
119 sba
.InstructionBuffersizeModifyEnable
= true;
123 /* After re-setting the surface state base address, we have to do some
124 * cache flusing so that the sampler engine will pick up the new
125 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
126 * Shared Function > 3D Sampler > State > State Caching (page 96):
128 * Coherency with system memory in the state cache, like the texture
129 * cache is handled partially by software. It is expected that the
130 * command stream or shader will issue Cache Flush operation or
131 * Cache_Flush sampler message to ensure that the L1 cache remains
132 * coherent with system memory.
136 * Whenever the value of the Dynamic_State_Base_Addr,
137 * Surface_State_Base_Addr are altered, the L1 state cache must be
138 * invalidated to ensure the new surface or sampler state is fetched
139 * from system memory.
141 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
142 * which, according the PIPE_CONTROL instruction documentation in the
145 * Setting this bit is independent of any other bit in this packet.
146 * This bit controls the invalidation of the L1 and L2 state caches
147 * at the top of the pipe i.e. at the parsing time.
149 * Unfortunately, experimentation seems to indicate that state cache
150 * invalidation through a PIPE_CONTROL does nothing whatsoever in
151 * regards to surface state and binding tables. In stead, it seems that
152 * invalidating the texture cache is what is actually needed.
154 * XXX: As far as we have been able to determine through
155 * experimentation, shows that flush the texture cache appears to be
156 * sufficient. The theory here is that all of the sampling/rendering
157 * units cache the binding table in the texture cache. However, we have
158 * yet to be able to actually confirm this.
160 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
161 pc
.TextureCacheInvalidationEnable
= true;
162 pc
.ConstantCacheInvalidationEnable
= true;
163 pc
.StateCacheInvalidationEnable
= true;
168 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
169 struct anv_state state
,
170 struct anv_bo
*bo
, uint32_t offset
)
172 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
175 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
176 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
177 if (result
!= VK_SUCCESS
)
178 anv_batch_set_error(&cmd_buffer
->batch
, result
);
182 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
183 const struct anv_image_view
*image_view
,
184 const uint32_t plane
,
185 struct anv_surface_state state
)
187 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
188 const struct anv_image
*image
= image_view
->image
;
189 uint32_t image_plane
= image_view
->planes
[plane
].image_plane
;
191 add_surface_state_reloc(cmd_buffer
, state
.state
,
192 image
->planes
[image_plane
].bo
, state
.address
);
194 if (state
.aux_address
) {
196 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
197 &cmd_buffer
->pool
->alloc
,
198 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
199 image
->planes
[image_plane
].bo
, state
.aux_address
);
200 if (result
!= VK_SUCCESS
)
201 anv_batch_set_error(&cmd_buffer
->batch
, result
);
206 color_attachment_compute_aux_usage(struct anv_device
* device
,
207 struct anv_cmd_state
* cmd_state
,
208 uint32_t att
, VkRect2D render_area
,
209 union isl_color_value
*fast_clear_color
)
211 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
212 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
214 assert(iview
->n_planes
== 1);
216 if (iview
->planes
[0].isl
.base_array_layer
>=
217 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
218 iview
->planes
[0].isl
.base_level
)) {
219 /* There is no aux buffer which corresponds to the level and layer(s)
222 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
223 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
224 att_state
->fast_clear
= false;
228 att_state
->aux_usage
=
229 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
230 VK_IMAGE_ASPECT_COLOR_BIT
,
231 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
233 /* If we don't have aux, then we should have returned early in the layer
234 * check above. If we got here, we must have something.
236 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
238 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
239 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
240 att_state
->input_aux_usage
= att_state
->aux_usage
;
242 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
244 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
245 * setting is only allowed if Surface Format supported for Fast
246 * Clear. In addition, if the surface is bound to the sampling
247 * engine, Surface Format must be supported for Render Target
248 * Compression for surfaces bound to the sampling engine."
250 * In other words, we can only sample from a fast-cleared image if it
251 * also supports color compression.
253 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
254 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
256 /* While fast-clear resolves and partial resolves are fairly cheap in the
257 * case where you render to most of the pixels, full resolves are not
258 * because they potentially involve reading and writing the entire
259 * framebuffer. If we can't texture with CCS_E, we should leave it off and
260 * limit ourselves to fast clears.
262 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
263 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
264 anv_perf_warn(device
->instance
, iview
->image
,
265 "Not temporarily enabling CCS_E.");
268 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
272 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
273 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
275 const struct isl_format_layout
*view_fmtl
=
276 isl_format_get_layout(iview
->planes
[0].isl
.format
);
277 union isl_color_value clear_color
= {};
279 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
280 if (view_fmtl->channels.c.bits) \
281 clear_color.u32[i] = att_state->clear_value.color.uint32[i]
283 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
284 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
285 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
286 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
288 #undef COPY_CLEAR_COLOR_CHANNEL
290 att_state
->clear_color_is_zero_one
=
291 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
292 att_state
->clear_color_is_zero
=
293 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
295 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
296 /* Start by getting the fast clear type. We use the first subpass
297 * layout here because we don't want to fast-clear if the first subpass
298 * to use the attachment can't handle fast-clears.
300 enum anv_fast_clear_type fast_clear_type
=
301 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
302 VK_IMAGE_ASPECT_COLOR_BIT
,
303 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
304 switch (fast_clear_type
) {
305 case ANV_FAST_CLEAR_NONE
:
306 att_state
->fast_clear
= false;
308 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
309 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
311 case ANV_FAST_CLEAR_ANY
:
312 att_state
->fast_clear
= true;
316 /* Potentially, we could do partial fast-clears but doing so has crazy
317 * alignment restrictions. It's easier to just restrict to full size
318 * fast clears for now.
320 if (render_area
.offset
.x
!= 0 ||
321 render_area
.offset
.y
!= 0 ||
322 render_area
.extent
.width
!= iview
->extent
.width
||
323 render_area
.extent
.height
!= iview
->extent
.height
)
324 att_state
->fast_clear
= false;
326 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
327 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
328 att_state
->fast_clear
= false;
330 /* We only allow fast clears to the first slice of an image (level 0,
331 * layer 0) and only for the entire slice. This guarantees us that, at
332 * any given time, there is only one clear color on any given image at
333 * any given time. At the time of our testing (Jan 17, 2018), there
334 * were no known applications which would benefit from fast-clearing
335 * more than just the first slice.
337 if (att_state
->fast_clear
&&
338 (iview
->planes
[0].isl
.base_level
> 0 ||
339 iview
->planes
[0].isl
.base_array_layer
> 0)) {
340 anv_perf_warn(device
->instance
, iview
->image
,
341 "Rendering with multi-lod or multi-layer framebuffer "
342 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
343 "baseArrayLayer > 0. Not fast clearing.");
344 att_state
->fast_clear
= false;
345 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
346 anv_perf_warn(device
->instance
, iview
->image
,
347 "Rendering to a multi-layer framebuffer with "
348 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
351 if (att_state
->fast_clear
)
352 *fast_clear_color
= clear_color
;
354 att_state
->fast_clear
= false;
359 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
360 struct anv_cmd_state
*cmd_state
,
361 uint32_t att
, VkRect2D render_area
)
363 struct anv_render_pass_attachment
*pass_att
=
364 &cmd_state
->pass
->attachments
[att
];
365 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
366 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
368 /* These will be initialized after the first subpass transition. */
369 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
370 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
373 /* We don't do any HiZ or depth fast-clears on gen7 yet */
374 att_state
->fast_clear
= false;
378 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
379 /* If we're just clearing stencil, we can always HiZ clear */
380 att_state
->fast_clear
= true;
384 /* Default to false for now */
385 att_state
->fast_clear
= false;
387 /* We must have depth in order to have HiZ */
388 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
391 const enum isl_aux_usage first_subpass_aux_usage
=
392 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
393 VK_IMAGE_ASPECT_DEPTH_BIT
,
394 pass_att
->first_subpass_layout
);
395 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
398 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
399 iview
->planes
[0].isl
.format
,
400 iview
->image
->samples
,
401 render_area
.offset
.x
,
402 render_area
.offset
.y
,
403 render_area
.offset
.x
+
404 render_area
.extent
.width
,
405 render_area
.offset
.y
+
406 render_area
.extent
.height
))
409 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
412 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
413 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
414 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
415 * only supports returning 0.0f. Gens prior to gen8 do not support this
421 /* If we got here, then we can fast clear */
422 att_state
->fast_clear
= true;
426 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
428 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
431 /* We only allocate input attachment states for color surfaces. Compression
432 * is not yet enabled for depth textures and stencil doesn't allow
433 * compression so we can just use the texture surface state from the view.
435 return vk_format_is_color(att
->format
);
438 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
439 * the initial layout is undefined, the HiZ buffer and depth buffer will
440 * represent the same data at the end of this operation.
443 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
444 const struct anv_image
*image
,
445 VkImageLayout initial_layout
,
446 VkImageLayout final_layout
)
448 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
449 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
450 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
451 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
452 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
453 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
455 enum isl_aux_op hiz_op
;
456 if (hiz_enabled
&& !enable_hiz
) {
457 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
458 } else if (!hiz_enabled
&& enable_hiz
) {
459 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
461 assert(hiz_enabled
== enable_hiz
);
462 /* If the same buffer will be used, no resolves are necessary. */
463 hiz_op
= ISL_AUX_OP_NONE
;
466 if (hiz_op
!= ISL_AUX_OP_NONE
)
467 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
471 #define MI_PREDICATE_SRC0 0x2400
472 #define MI_PREDICATE_SRC1 0x2408
475 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
476 const struct anv_image
*image
,
477 VkImageAspectFlagBits aspect
,
479 uint32_t base_layer
, uint32_t layer_count
,
482 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
484 /* We only have compression tracking for CCS_E */
485 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
488 for (uint32_t a
= 0; a
< layer_count
; a
++) {
489 uint32_t layer
= base_layer
+ a
;
490 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
491 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
494 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
500 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
501 const struct anv_image
*image
,
502 VkImageAspectFlagBits aspect
,
503 enum anv_fast_clear_type fast_clear
)
505 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
506 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
508 sdi
.ImmediateData
= fast_clear
;
511 /* Whenever we have fast-clear, we consider that slice to be compressed.
512 * This makes building predicates much easier.
514 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
515 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
518 #if GEN_IS_HASWELL || GEN_GEN >= 8
519 static inline uint32_t
520 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
522 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
524 .Operand1
= operand1
,
525 .Operand2
= operand2
,
529 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
535 #define CS_GPR(n) (0x2600 + (n) * 8)
537 /* This is only really practical on haswell and above because it requires
538 * MI math in order to get it correct.
540 #if GEN_GEN >= 8 || GEN_IS_HASWELL
542 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
543 const struct anv_image
*image
,
544 VkImageAspectFlagBits aspect
,
545 uint32_t level
, uint32_t array_layer
,
546 enum isl_aux_op resolve_op
,
547 enum anv_fast_clear_type fast_clear_supported
)
549 struct anv_address fast_clear_type_addr
=
550 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
552 /* Name some registers */
553 const int image_fc_reg
= MI_ALU_REG0
;
554 const int fc_imm_reg
= MI_ALU_REG1
;
555 const int pred_reg
= MI_ALU_REG2
;
559 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
560 /* In this case, we're doing a full resolve which means we want the
561 * resolve to happen if any compression (including fast-clears) is
564 * In order to simplify the logic a bit, we make the assumption that,
565 * if the first slice has been fast-cleared, it is also marked as
566 * compressed. See also set_image_fast_clear_state.
568 struct anv_address compression_state_addr
=
569 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
570 aspect
, level
, array_layer
);
571 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
572 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
573 lrm
.MemoryAddress
= compression_state_addr
;
575 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
576 sdi
.Address
= compression_state_addr
;
577 sdi
.ImmediateData
= 0;
580 if (level
== 0 && array_layer
== 0) {
581 /* If the predicate is true, we want to write 0 to the fast clear type
582 * and, if it's false, leave it alone. We can do this by writing
584 * clear_type = clear_type & ~predicate;
586 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
587 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
588 lrm
.MemoryAddress
= fast_clear_type_addr
;
590 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
591 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
592 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
595 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
596 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
597 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
598 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
599 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
601 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
602 srm
.MemoryAddress
= fast_clear_type_addr
;
603 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
606 } else if (level
== 0 && array_layer
== 0) {
607 /* In this case, we are doing a partial resolve to get rid of fast-clear
608 * colors. We don't care about the compression state but we do care
609 * about how much fast clear is allowed by the final layout.
611 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
612 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
614 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
615 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
616 lrm
.MemoryAddress
= fast_clear_type_addr
;
618 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
620 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
621 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
623 /* We need to compute (fast_clear_supported < image->fast_clear).
624 * We do this by subtracting and storing the carry bit.
626 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
627 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
628 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
629 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
630 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
632 /* Store the predicate */
633 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
635 /* If the predicate is true, we want to write 0 to the fast clear type
636 * and, if it's false, leave it alone. We can do this by writing
638 * clear_type = clear_type & ~predicate;
640 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
641 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
642 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
643 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
644 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
646 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
647 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
648 srm
.MemoryAddress
= fast_clear_type_addr
;
651 /* In this case, we're trying to do a partial resolve on a slice that
652 * doesn't have clear color. There's nothing to do.
654 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
658 /* We use the first half of src0 for the actual predicate. Set the second
659 * half of src0 and all of src1 to 0 as the predicate operation will be
660 * doing an implicit src0 != src1.
662 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
663 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
664 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
666 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
667 mip
.LoadOperation
= LOAD_LOADINV
;
668 mip
.CombineOperation
= COMBINE_SET
;
669 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
672 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
676 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
677 const struct anv_image
*image
,
678 VkImageAspectFlagBits aspect
,
679 uint32_t level
, uint32_t array_layer
,
680 enum isl_aux_op resolve_op
,
681 enum anv_fast_clear_type fast_clear_supported
)
683 struct anv_address fast_clear_type_addr
=
684 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
686 /* This only works for partial resolves and only when the clear color is
687 * all or nothing. On the upside, this emits less command streamer code
688 * and works on Ivybridge and Bay Trail.
690 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
691 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
693 /* We don't support fast clears on anything other than the first slice. */
694 if (level
> 0 || array_layer
> 0)
697 /* On gen8, we don't have a concept of default clear colors because we
698 * can't sample from CCS surfaces. It's enough to just load the fast clear
699 * state into the predicate register.
701 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
702 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
703 lrm
.MemoryAddress
= fast_clear_type_addr
;
705 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
706 sdi
.Address
= fast_clear_type_addr
;
707 sdi
.ImmediateData
= 0;
710 /* We use the first half of src0 for the actual predicate. Set the second
711 * half of src0 and all of src1 to 0 as the predicate operation will be
712 * doing an implicit src0 != src1.
714 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
715 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
716 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
718 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
719 mip
.LoadOperation
= LOAD_LOADINV
;
720 mip
.CombineOperation
= COMBINE_SET
;
721 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
724 #endif /* GEN_GEN <= 8 */
727 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
728 const struct anv_image
*image
,
729 VkImageAspectFlagBits aspect
,
730 uint32_t level
, uint32_t array_layer
,
731 enum isl_aux_op resolve_op
,
732 enum anv_fast_clear_type fast_clear_supported
)
734 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
737 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
738 aspect
, level
, array_layer
,
739 resolve_op
, fast_clear_supported
);
740 #else /* GEN_GEN <= 8 */
741 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
742 aspect
, level
, array_layer
,
743 resolve_op
, fast_clear_supported
);
746 /* CCS_D only supports full resolves and BLORP will assert on us if we try
747 * to do a partial resolve on a CCS_D surface.
749 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
750 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
751 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
753 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
754 array_layer
, 1, resolve_op
, true);
758 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
759 const struct anv_image
*image
,
760 VkImageAspectFlagBits aspect
,
761 uint32_t array_layer
,
762 enum isl_aux_op resolve_op
,
763 enum anv_fast_clear_type fast_clear_supported
)
765 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
766 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
768 #if GEN_GEN >= 8 || GEN_IS_HASWELL
769 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
770 aspect
, 0, array_layer
,
771 resolve_op
, fast_clear_supported
);
773 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
774 array_layer
, 1, resolve_op
, true);
776 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
781 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
782 const struct anv_image
*image
,
783 VkImageAspectFlagBits aspect
,
784 enum isl_aux_usage aux_usage
,
787 uint32_t layer_count
)
789 /* The aspect must be exactly one of the image aspects. */
790 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
792 /* The only compression types with more than just fast-clears are MCS,
793 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
794 * track the current fast-clear and compression state. This leaves us
795 * with just MCS and CCS_E.
797 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
798 aux_usage
!= ISL_AUX_USAGE_MCS
)
801 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
802 level
, base_layer
, layer_count
, true);
806 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
807 const struct anv_image
*image
,
808 VkImageAspectFlagBits aspect
)
810 assert(cmd_buffer
&& image
);
811 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
813 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
814 ANV_FAST_CLEAR_NONE
);
816 /* The fast clear value dword(s) will be copied into a surface state object.
817 * Ensure that the restrictions of the fields in the dword(s) are followed.
819 * CCS buffers on SKL+ can have any value set for the clear colors.
821 if (image
->samples
== 1 && GEN_GEN
>= 9)
824 /* Other combinations of auxiliary buffers and platforms require specific
825 * values in the clear value dword(s).
827 struct anv_address addr
=
828 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
830 for (; i
< cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
; i
+= 4) {
831 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
835 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
836 assert(image
->samples
> 1);
837 sdi
.ImmediateData
= 0;
838 } else if (GEN_VERSIONx10
>= 75) {
839 /* Pre-SKL, the dword containing the clear values also contains
840 * other fields, so we need to initialize those fields to match the
841 * values that would be in a color attachment.
844 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
845 ISL_CHANNEL_SELECT_GREEN
<< 22 |
846 ISL_CHANNEL_SELECT_BLUE
<< 19 |
847 ISL_CHANNEL_SELECT_ALPHA
<< 16;
848 } else if (GEN_VERSIONx10
== 70) {
849 /* On IVB, the dword containing the clear values also contains
850 * other fields that must be zero or can be zero.
853 sdi
.ImmediateData
= 0;
861 /* Copy the fast-clear value dword(s) between a surface state object and an
862 * image's fast clear state buffer.
865 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
866 struct anv_state surface_state
,
867 const struct anv_image
*image
,
868 VkImageAspectFlagBits aspect
,
869 bool copy_from_surface_state
)
871 assert(cmd_buffer
&& image
);
872 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
874 struct anv_bo
*ss_bo
=
875 &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
;
876 uint32_t ss_clear_offset
= surface_state
.offset
+
877 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
;
878 const struct anv_address entry_addr
=
879 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
880 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
882 if (copy_from_surface_state
) {
883 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
.bo
, entry_addr
.offset
,
884 ss_bo
, ss_clear_offset
, copy_size
);
886 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_bo
, ss_clear_offset
,
887 entry_addr
.bo
, entry_addr
.offset
, copy_size
);
889 /* Updating a surface state object may require that the state cache be
890 * invalidated. From the SKL PRM, Shared Functions -> State -> State
893 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
894 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
895 * modified [...], the L1 state cache must be invalidated to ensure
896 * the new surface or sampler state is fetched from system memory.
898 * In testing, SKL doesn't actually seem to need this, but HSW does.
900 cmd_buffer
->state
.pending_pipe_bits
|=
901 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
906 * @brief Transitions a color buffer from one layout to another.
908 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
911 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
912 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
913 * this represents the maximum layers to transition at each
914 * specified miplevel.
917 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
918 const struct anv_image
*image
,
919 VkImageAspectFlagBits aspect
,
920 const uint32_t base_level
, uint32_t level_count
,
921 uint32_t base_layer
, uint32_t layer_count
,
922 VkImageLayout initial_layout
,
923 VkImageLayout final_layout
)
925 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
926 /* Validate the inputs. */
928 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
929 /* These values aren't supported for simplicity's sake. */
930 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
931 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
932 /* Ensure the subresource range is valid. */
933 uint64_t last_level_num
= base_level
+ level_count
;
934 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
935 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
936 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
937 assert(last_level_num
<= image
->levels
);
938 /* The spec disallows these final layouts. */
939 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
940 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
942 /* No work is necessary if the layout stays the same or if this subresource
943 * range lacks auxiliary data.
945 if (initial_layout
== final_layout
)
948 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
950 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
951 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
952 /* This surface is a linear compressed image with a tiled shadow surface
953 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
954 * we need to ensure the shadow copy is up-to-date.
956 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
957 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
958 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
959 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
961 anv_image_copy_to_shadow(cmd_buffer
, image
,
962 base_level
, level_count
,
963 base_layer
, layer_count
);
966 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
969 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
971 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
972 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
973 /* A subresource in the undefined layout may have been aliased and
974 * populated with any arrangement of bits. Therefore, we must initialize
975 * the related aux buffer and clear buffer entry with desirable values.
976 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
977 * images with VK_IMAGE_TILING_OPTIMAL.
979 * Initialize the relevant clear buffer entries.
981 if (base_level
== 0 && base_layer
== 0)
982 init_fast_clear_color(cmd_buffer
, image
, aspect
);
984 /* Initialize the aux buffers to enable correct rendering. In order to
985 * ensure that things such as storage images work correctly, aux buffers
986 * need to be initialized to valid data.
988 * Having an aux buffer with invalid data is a problem for two reasons:
990 * 1) Having an invalid value in the buffer can confuse the hardware.
991 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
992 * invalid and leads to the hardware doing strange things. It
993 * doesn't hang as far as we can tell but rendering corruption can
996 * 2) If this transition is into the GENERAL layout and we then use the
997 * image as a storage image, then we must have the aux buffer in the
998 * pass-through state so that, if we then go to texture from the
999 * image, we get the results of our storage image writes and not the
1000 * fast clear color or other random data.
1002 * For CCS both of the problems above are real demonstrable issues. In
1003 * that case, the only thing we can do is to perform an ambiguate to
1004 * transition the aux surface into the pass-through state.
1006 * For MCS, (2) is never an issue because we don't support multisampled
1007 * storage images. In theory, issue (1) is a problem with MCS but we've
1008 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1009 * theory, be interpreted as something but we don't know that all bit
1010 * patterns are actually valid. For 2x and 8x, you could easily end up
1011 * with the MCS referring to an invalid plane because not all bits of
1012 * the MCS value are actually used. Even though we've never seen issues
1013 * in the wild, it's best to play it safe and initialize the MCS. We
1014 * can use a fast-clear for MCS because we only ever touch from render
1015 * and texture (no image load store).
1017 if (image
->samples
== 1) {
1018 for (uint32_t l
= 0; l
< level_count
; l
++) {
1019 const uint32_t level
= base_level
+ l
;
1021 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1022 if (base_layer
>= aux_layers
)
1023 break; /* We will only get fewer layers as level increases */
1024 uint32_t level_layer_count
=
1025 MIN2(layer_count
, aux_layers
- base_layer
);
1027 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
1028 base_layer
, level_layer_count
,
1029 ISL_AUX_OP_AMBIGUATE
, false);
1031 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1032 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1033 level
, base_layer
, level_layer_count
,
1038 if (image
->samples
== 4 || image
->samples
== 16) {
1039 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1040 "Doing a potentially unnecessary fast-clear to "
1041 "define an MCS buffer.");
1044 assert(base_level
== 0 && level_count
== 1);
1045 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
1046 base_layer
, layer_count
,
1047 ISL_AUX_OP_FAST_CLEAR
, false);
1052 const enum isl_aux_usage initial_aux_usage
=
1053 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1054 const enum isl_aux_usage final_aux_usage
=
1055 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1057 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1058 * We can handle transitions between CCS_D/E to and from NONE. What we
1059 * don't yet handle is switching between CCS_E and CCS_D within a given
1060 * image. Doing so in a performant way requires more detailed aux state
1061 * tracking such as what is done in i965. For now, just assume that we
1062 * only have one type of compression.
1064 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1065 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1066 initial_aux_usage
== final_aux_usage
);
1068 /* If initial aux usage is NONE, there is nothing to resolve */
1069 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1072 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1074 /* If the initial layout supports more fast clear than the final layout
1075 * then we need at least a partial resolve.
1077 const enum anv_fast_clear_type initial_fast_clear
=
1078 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1079 const enum anv_fast_clear_type final_fast_clear
=
1080 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1081 if (final_fast_clear
< initial_fast_clear
)
1082 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1084 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1085 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1086 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1088 if (resolve_op
== ISL_AUX_OP_NONE
)
1091 /* Perform a resolve to synchronize data between the main and aux buffer.
1092 * Before we begin, we must satisfy the cache flushing requirement specified
1093 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1095 * Any transition from any value in {Clear, Render, Resolve} to a
1096 * different value in {Clear, Render, Resolve} requires end of pipe
1099 * We perform a flush of the write cache before and after the clear and
1100 * resolve operations to meet this requirement.
1102 * Unlike other drawing, fast clear operations are not properly
1103 * synchronized. The first PIPE_CONTROL here likely ensures that the
1104 * contents of the previous render or clear hit the render target before we
1105 * resolve and the second likely ensures that the resolve is complete before
1106 * we do any more rendering or clearing.
1108 cmd_buffer
->state
.pending_pipe_bits
|=
1109 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1111 for (uint32_t l
= 0; l
< level_count
; l
++) {
1112 uint32_t level
= base_level
+ l
;
1114 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1115 if (base_layer
>= aux_layers
)
1116 break; /* We will only get fewer layers as level increases */
1117 uint32_t level_layer_count
=
1118 MIN2(layer_count
, aux_layers
- base_layer
);
1120 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1121 uint32_t array_layer
= base_layer
+ a
;
1122 if (image
->samples
== 1) {
1123 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
, aspect
,
1124 level
, array_layer
, resolve_op
,
1127 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
, aspect
,
1128 array_layer
, resolve_op
,
1134 cmd_buffer
->state
.pending_pipe_bits
|=
1135 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1139 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1142 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1143 struct anv_render_pass
*pass
,
1144 const VkRenderPassBeginInfo
*begin
)
1146 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1147 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1149 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1151 if (pass
->attachment_count
> 0) {
1152 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1153 pass
->attachment_count
*
1154 sizeof(state
->attachments
[0]),
1155 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1156 if (state
->attachments
== NULL
) {
1157 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1158 return anv_batch_set_error(&cmd_buffer
->batch
,
1159 VK_ERROR_OUT_OF_HOST_MEMORY
);
1162 state
->attachments
= NULL
;
1165 /* Reserve one for the NULL state. */
1166 unsigned num_states
= 1;
1167 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1168 if (vk_format_is_color(pass
->attachments
[i
].format
))
1171 if (need_input_attachment_state(&pass
->attachments
[i
]))
1175 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1176 state
->render_pass_states
=
1177 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1178 num_states
* ss_stride
, isl_dev
->ss
.align
);
1180 struct anv_state next_state
= state
->render_pass_states
;
1181 next_state
.alloc_size
= isl_dev
->ss
.size
;
1183 state
->null_surface_state
= next_state
;
1184 next_state
.offset
+= ss_stride
;
1185 next_state
.map
+= ss_stride
;
1187 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1188 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1189 state
->attachments
[i
].color
.state
= next_state
;
1190 next_state
.offset
+= ss_stride
;
1191 next_state
.map
+= ss_stride
;
1194 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1195 state
->attachments
[i
].input
.state
= next_state
;
1196 next_state
.offset
+= ss_stride
;
1197 next_state
.map
+= ss_stride
;
1200 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1201 state
->render_pass_states
.alloc_size
);
1204 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1205 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1207 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1208 isl_extent3d(framebuffer
->width
,
1209 framebuffer
->height
,
1210 framebuffer
->layers
));
1212 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1213 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1214 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1215 VkImageAspectFlags clear_aspects
= 0;
1216 VkImageAspectFlags load_aspects
= 0;
1218 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1219 /* color attachment */
1220 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1221 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1222 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1223 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1226 /* depthstencil attachment */
1227 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1228 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1229 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1230 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1231 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1234 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1235 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1236 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1237 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1238 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1243 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1244 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1245 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1247 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1249 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1250 anv_assert(iview
->vk_format
== att
->format
);
1251 anv_assert(iview
->n_planes
== 1);
1253 union isl_color_value clear_color
= { .u32
= { 0, } };
1254 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1255 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1256 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1257 state
, i
, begin
->renderArea
,
1260 anv_image_fill_surface_state(cmd_buffer
->device
,
1262 VK_IMAGE_ASPECT_COLOR_BIT
,
1263 &iview
->planes
[0].isl
,
1264 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1265 state
->attachments
[i
].aux_usage
,
1268 &state
->attachments
[i
].color
,
1271 add_image_view_relocs(cmd_buffer
, iview
, 0,
1272 state
->attachments
[i
].color
);
1274 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1279 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1280 anv_image_fill_surface_state(cmd_buffer
->device
,
1282 VK_IMAGE_ASPECT_COLOR_BIT
,
1283 &iview
->planes
[0].isl
,
1284 ISL_SURF_USAGE_TEXTURE_BIT
,
1285 state
->attachments
[i
].input_aux_usage
,
1288 &state
->attachments
[i
].input
,
1291 add_image_view_relocs(cmd_buffer
, iview
, 0,
1292 state
->attachments
[i
].input
);
1301 genX(BeginCommandBuffer
)(
1302 VkCommandBuffer commandBuffer
,
1303 const VkCommandBufferBeginInfo
* pBeginInfo
)
1305 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1307 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1308 * command buffer's state. Otherwise, we must *reset* its state. In both
1309 * cases we reset it.
1311 * From the Vulkan 1.0 spec:
1313 * If a command buffer is in the executable state and the command buffer
1314 * was allocated from a command pool with the
1315 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1316 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1317 * as if vkResetCommandBuffer had been called with
1318 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1319 * the command buffer in the recording state.
1321 anv_cmd_buffer_reset(cmd_buffer
);
1323 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1325 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1326 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1328 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1330 /* We sometimes store vertex data in the dynamic state buffer for blorp
1331 * operations and our dynamic state stream may re-use data from previous
1332 * command buffers. In order to prevent stale cache data, we flush the VF
1333 * cache. We could do this on every blorp call but that's not really
1334 * needed as all of the data will get written by the CPU prior to the GPU
1335 * executing anything. The chances are fairly high that they will use
1336 * blorp at least once per primary command buffer so it shouldn't be
1339 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1340 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1342 /* We send an "Indirect State Pointers Disable" packet at
1343 * EndCommandBuffer, so all push contant packets are ignored during a
1344 * context restore. Documentation says after that command, we need to
1345 * emit push constants again before any rendering operation. So we
1346 * flag them dirty here to make sure they get emitted.
1348 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1350 VkResult result
= VK_SUCCESS
;
1351 if (cmd_buffer
->usage_flags
&
1352 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1353 assert(pBeginInfo
->pInheritanceInfo
);
1354 cmd_buffer
->state
.pass
=
1355 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1356 cmd_buffer
->state
.subpass
=
1357 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1359 /* This is optional in the inheritance info. */
1360 cmd_buffer
->state
.framebuffer
=
1361 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1363 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1364 cmd_buffer
->state
.pass
, NULL
);
1366 /* Record that HiZ is enabled if we can. */
1367 if (cmd_buffer
->state
.framebuffer
) {
1368 const struct anv_image_view
* const iview
=
1369 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1372 VkImageLayout layout
=
1373 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.layout
;
1375 enum isl_aux_usage aux_usage
=
1376 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1377 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1379 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1383 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1389 /* From the PRM, Volume 2a:
1391 * "Indirect State Pointers Disable
1393 * At the completion of the post-sync operation associated with this pipe
1394 * control packet, the indirect state pointers in the hardware are
1395 * considered invalid; the indirect pointers are not saved in the context.
1396 * If any new indirect state commands are executed in the command stream
1397 * while the pipe control is pending, the new indirect state commands are
1400 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1401 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1402 * commands are only considered as Indirect State Pointers. Once ISP is
1403 * issued in a context, SW must initialize by programming push constant
1404 * commands for all the shaders (at least to zero length) before attempting
1405 * any rendering operation for the same context."
1407 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1408 * even though they point to a BO that has been already unreferenced at
1409 * the end of the previous batch buffer. This has been fine so far since
1410 * we are protected by these scratch page (every address not covered by
1411 * a BO should be pointing to the scratch page). But on CNL, it is
1412 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1415 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1416 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1417 * context restore, so the mentioned hang doesn't happen. However,
1418 * software must program push constant commands for all stages prior to
1419 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1422 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1424 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1425 pc
.IndirectStatePointersDisable
= true;
1426 pc
.CommandStreamerStallEnable
= true;
1431 genX(EndCommandBuffer
)(
1432 VkCommandBuffer commandBuffer
)
1434 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1436 if (anv_batch_has_error(&cmd_buffer
->batch
))
1437 return cmd_buffer
->batch
.status
;
1439 /* We want every command buffer to start with the PMA fix in a known state,
1440 * so we disable it at the end of the command buffer.
1442 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1444 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1446 emit_isp_disable(cmd_buffer
);
1448 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1454 genX(CmdExecuteCommands
)(
1455 VkCommandBuffer commandBuffer
,
1456 uint32_t commandBufferCount
,
1457 const VkCommandBuffer
* pCmdBuffers
)
1459 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1461 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1463 if (anv_batch_has_error(&primary
->batch
))
1466 /* The secondary command buffers will assume that the PMA fix is disabled
1467 * when they begin executing. Make sure this is true.
1469 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1471 /* The secondary command buffer doesn't know which textures etc. have been
1472 * flushed prior to their execution. Apply those flushes now.
1474 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1476 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1477 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1479 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1480 assert(!anv_batch_has_error(&secondary
->batch
));
1482 if (secondary
->usage_flags
&
1483 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1484 /* If we're continuing a render pass from the primary, we need to
1485 * copy the surface states for the current subpass into the storage
1486 * we allocated for them in BeginCommandBuffer.
1488 struct anv_bo
*ss_bo
=
1489 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1490 struct anv_state src_state
= primary
->state
.render_pass_states
;
1491 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1492 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1494 genX(cmd_buffer_so_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
1495 ss_bo
, src_state
.offset
,
1496 src_state
.alloc_size
);
1499 anv_cmd_buffer_add_secondary(primary
, secondary
);
1502 /* The secondary may have selected a different pipeline (3D or compute) and
1503 * may have changed the current L3$ configuration. Reset our tracking
1504 * variables to invalid values to ensure that we re-emit these in the case
1505 * where we do any draws or compute dispatches from the primary after the
1506 * secondary has returned.
1508 primary
->state
.current_pipeline
= UINT32_MAX
;
1509 primary
->state
.current_l3_config
= NULL
;
1511 /* Each of the secondary command buffers will use its own state base
1512 * address. We need to re-emit state base address for the primary after
1513 * all of the secondaries are done.
1515 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1518 genX(cmd_buffer_emit_state_base_address
)(primary
);
1521 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1522 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1523 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1526 * Program the hardware to use the specified L3 configuration.
1529 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1530 const struct gen_l3_config
*cfg
)
1533 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1536 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1537 intel_logd("L3 config transition: ");
1538 gen_dump_l3_config(cfg
, stderr
);
1541 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1543 /* According to the hardware docs, the L3 partitioning can only be changed
1544 * while the pipeline is completely drained and the caches are flushed,
1545 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1547 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1548 pc
.DCFlushEnable
= true;
1549 pc
.PostSyncOperation
= NoWrite
;
1550 pc
.CommandStreamerStallEnable
= true;
1553 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1554 * invalidation of the relevant caches. Note that because RO invalidation
1555 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1556 * command is processed by the CS) we cannot combine it with the previous
1557 * stalling flush as the hardware documentation suggests, because that
1558 * would cause the CS to stall on previous rendering *after* RO
1559 * invalidation and wouldn't prevent the RO caches from being polluted by
1560 * concurrent rendering before the stall completes. This intentionally
1561 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1562 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1563 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1564 * already guarantee that there is no concurrent GPGPU kernel execution
1565 * (see SKL HSD 2132585).
1567 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1568 pc
.TextureCacheInvalidationEnable
= true;
1569 pc
.ConstantCacheInvalidationEnable
= true;
1570 pc
.InstructionCacheInvalidateEnable
= true;
1571 pc
.StateCacheInvalidationEnable
= true;
1572 pc
.PostSyncOperation
= NoWrite
;
1575 /* Now send a third stalling flush to make sure that invalidation is
1576 * complete when the L3 configuration registers are modified.
1578 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1579 pc
.DCFlushEnable
= true;
1580 pc
.PostSyncOperation
= NoWrite
;
1581 pc
.CommandStreamerStallEnable
= true;
1586 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1589 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1590 .SLMEnable
= has_slm
,
1591 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1592 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1593 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1594 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1596 /* Set up the L3 partitioning. */
1597 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1601 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1602 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1603 cfg
->n
[GEN_L3P_ALL
];
1604 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1605 cfg
->n
[GEN_L3P_ALL
];
1606 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1607 cfg
->n
[GEN_L3P_ALL
];
1609 assert(!cfg
->n
[GEN_L3P_ALL
]);
1611 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1612 * the matching space on the remaining banks has to be allocated to a
1613 * client (URB for all validated configurations) set to the
1614 * lower-bandwidth 2-bank address hashing mode.
1616 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1617 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1618 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1620 /* Minimum number of ways that can be allocated to the URB. */
1621 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1622 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1624 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1625 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1626 .ConvertDC_UC
= !has_dc
,
1627 .ConvertIS_UC
= !has_is
,
1628 .ConvertC_UC
= !has_c
,
1629 .ConvertT_UC
= !has_t
);
1631 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1632 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1633 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1635 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1636 .SLMEnable
= has_slm
,
1637 .URBLowBandwidth
= urb_low_bw
,
1638 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1640 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1642 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1643 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1645 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1646 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1647 .ISLowBandwidth
= 0,
1648 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1650 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1651 .TLowBandwidth
= 0);
1653 /* Set up the L3 partitioning. */
1654 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1655 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1656 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1659 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1660 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1661 * them disabled to avoid crashing the system hard.
1663 uint32_t scratch1
, chicken3
;
1664 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1665 .L3AtomicDisable
= !has_dc
);
1666 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1667 .L3AtomicDisableMask
= true,
1668 .L3AtomicDisable
= !has_dc
);
1669 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1670 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1676 cmd_buffer
->state
.current_l3_config
= cfg
;
1680 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1682 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1684 /* Flushes are pipelined while invalidations are handled immediately.
1685 * Therefore, if we're flushing anything then we need to schedule a stall
1686 * before any invalidations can happen.
1688 if (bits
& ANV_PIPE_FLUSH_BITS
)
1689 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1691 /* If we're going to do an invalidate and we have a pending CS stall that
1692 * has yet to be resolved, we do the CS stall now.
1694 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1695 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1696 bits
|= ANV_PIPE_CS_STALL_BIT
;
1697 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1700 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1701 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1702 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1703 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1704 pipe
.RenderTargetCacheFlushEnable
=
1705 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1707 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1708 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1709 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1712 * According to the Broadwell documentation, any PIPE_CONTROL with the
1713 * "Command Streamer Stall" bit set must also have another bit set,
1714 * with five different options:
1716 * - Render Target Cache Flush
1717 * - Depth Cache Flush
1718 * - Stall at Pixel Scoreboard
1719 * - Post-Sync Operation
1723 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1724 * mesa and it seems to work fine. The choice is fairly arbitrary.
1726 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1727 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1728 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1729 pipe
.StallAtPixelScoreboard
= true;
1732 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1735 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1736 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1737 pipe
.StateCacheInvalidationEnable
=
1738 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1739 pipe
.ConstantCacheInvalidationEnable
=
1740 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1741 pipe
.VFCacheInvalidationEnable
=
1742 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1743 pipe
.TextureCacheInvalidationEnable
=
1744 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1745 pipe
.InstructionCacheInvalidateEnable
=
1746 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1749 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1752 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1755 void genX(CmdPipelineBarrier
)(
1756 VkCommandBuffer commandBuffer
,
1757 VkPipelineStageFlags srcStageMask
,
1758 VkPipelineStageFlags destStageMask
,
1760 uint32_t memoryBarrierCount
,
1761 const VkMemoryBarrier
* pMemoryBarriers
,
1762 uint32_t bufferMemoryBarrierCount
,
1763 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1764 uint32_t imageMemoryBarrierCount
,
1765 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1767 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1769 /* XXX: Right now, we're really dumb and just flush whatever categories
1770 * the app asks for. One of these days we may make this a bit better
1771 * but right now that's all the hardware allows for in most areas.
1773 VkAccessFlags src_flags
= 0;
1774 VkAccessFlags dst_flags
= 0;
1776 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1777 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1778 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1781 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1782 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1783 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1786 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1787 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1788 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1789 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1790 const VkImageSubresourceRange
*range
=
1791 &pImageMemoryBarriers
[i
].subresourceRange
;
1793 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1794 transition_depth_buffer(cmd_buffer
, image
,
1795 pImageMemoryBarriers
[i
].oldLayout
,
1796 pImageMemoryBarriers
[i
].newLayout
);
1797 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1798 VkImageAspectFlags color_aspects
=
1799 anv_image_expand_aspects(image
, range
->aspectMask
);
1800 uint32_t aspect_bit
;
1802 uint32_t base_layer
, layer_count
;
1803 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1805 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1807 base_layer
= range
->baseArrayLayer
;
1808 layer_count
= anv_get_layerCount(image
, range
);
1811 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1812 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1813 range
->baseMipLevel
,
1814 anv_get_levelCount(image
, range
),
1815 base_layer
, layer_count
,
1816 pImageMemoryBarriers
[i
].oldLayout
,
1817 pImageMemoryBarriers
[i
].newLayout
);
1822 cmd_buffer
->state
.pending_pipe_bits
|=
1823 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1824 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1828 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1830 VkShaderStageFlags stages
=
1831 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1833 /* In order to avoid thrash, we assume that vertex and fragment stages
1834 * always exist. In the rare case where one is missing *and* the other
1835 * uses push concstants, this may be suboptimal. However, avoiding stalls
1836 * seems more important.
1838 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1840 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1844 const unsigned push_constant_kb
= 32;
1845 #elif GEN_IS_HASWELL
1846 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1848 const unsigned push_constant_kb
= 16;
1851 const unsigned num_stages
=
1852 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1853 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1855 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1856 * units of 2KB. Incidentally, these are the same platforms that have
1857 * 32KB worth of push constant space.
1859 if (push_constant_kb
== 32)
1860 size_per_stage
&= ~1u;
1862 uint32_t kb_used
= 0;
1863 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1864 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1865 anv_batch_emit(&cmd_buffer
->batch
,
1866 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1867 alloc
._3DCommandSubOpcode
= 18 + i
;
1868 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1869 alloc
.ConstantBufferSize
= push_size
;
1871 kb_used
+= push_size
;
1874 anv_batch_emit(&cmd_buffer
->batch
,
1875 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1876 alloc
.ConstantBufferOffset
= kb_used
;
1877 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1880 cmd_buffer
->state
.push_constant_stages
= stages
;
1882 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1884 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1885 * the next 3DPRIMITIVE command after programming the
1886 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1888 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1889 * pipeline setup, we need to dirty push constants.
1891 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1894 static const struct anv_descriptor
*
1895 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1896 const struct anv_pipeline_binding
*binding
)
1898 assert(binding
->set
< MAX_SETS
);
1899 const struct anv_descriptor_set
*set
=
1900 pipe_state
->descriptors
[binding
->set
];
1901 const uint32_t offset
=
1902 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1903 return &set
->descriptors
[offset
+ binding
->index
];
1907 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1908 const struct anv_pipeline_binding
*binding
)
1910 assert(binding
->set
< MAX_SETS
);
1911 const struct anv_descriptor_set
*set
=
1912 pipe_state
->descriptors
[binding
->set
];
1914 uint32_t dynamic_offset_idx
=
1915 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1916 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1919 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1923 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1924 gl_shader_stage stage
,
1925 struct anv_state
*bt_state
)
1927 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1928 struct anv_cmd_pipeline_state
*pipe_state
;
1929 struct anv_pipeline
*pipeline
;
1930 uint32_t bias
, state_offset
;
1933 case MESA_SHADER_COMPUTE
:
1934 pipe_state
= &cmd_buffer
->state
.compute
.base
;
1938 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
1942 pipeline
= pipe_state
->pipeline
;
1944 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1945 *bt_state
= (struct anv_state
) { 0, };
1949 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1950 if (bias
+ map
->surface_count
== 0) {
1951 *bt_state
= (struct anv_state
) { 0, };
1955 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1956 bias
+ map
->surface_count
,
1958 uint32_t *bt_map
= bt_state
->map
;
1960 if (bt_state
->map
== NULL
)
1961 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1963 if (stage
== MESA_SHADER_COMPUTE
&&
1964 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
1965 struct anv_bo
*bo
= cmd_buffer
->state
.compute
.num_workgroups
.bo
;
1966 uint32_t bo_offset
= cmd_buffer
->state
.compute
.num_workgroups
.offset
;
1968 struct anv_state surface_state
;
1970 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1972 const enum isl_format format
=
1973 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1974 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1975 format
, bo_offset
, 12, 1);
1977 bt_map
[0] = surface_state
.offset
+ state_offset
;
1978 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1981 if (map
->surface_count
== 0)
1984 if (map
->image_count
> 0) {
1986 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1987 if (result
!= VK_SUCCESS
)
1990 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1994 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1995 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1997 struct anv_state surface_state
;
1999 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2000 /* Color attachment binding */
2001 assert(stage
== MESA_SHADER_FRAGMENT
);
2002 assert(binding
->binding
== 0);
2003 if (binding
->index
< subpass
->color_count
) {
2004 const unsigned att
=
2005 subpass
->color_attachments
[binding
->index
].attachment
;
2007 /* From the Vulkan 1.0.46 spec:
2009 * "If any color or depth/stencil attachments are
2010 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2013 if (att
== VK_ATTACHMENT_UNUSED
) {
2014 surface_state
= cmd_buffer
->state
.null_surface_state
;
2016 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2019 surface_state
= cmd_buffer
->state
.null_surface_state
;
2022 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2026 const struct anv_descriptor
*desc
=
2027 anv_descriptor_for_binding(pipe_state
, binding
);
2029 switch (desc
->type
) {
2030 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2031 /* Nothing for us to do here */
2034 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2035 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2036 struct anv_surface_state sstate
=
2037 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2038 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2039 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2040 surface_state
= sstate
.state
;
2041 assert(surface_state
.alloc_size
);
2042 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
2043 binding
->plane
, sstate
);
2046 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2047 assert(stage
== MESA_SHADER_FRAGMENT
);
2048 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2049 /* For depth and stencil input attachments, we treat it like any
2050 * old texture that a user may have bound.
2052 struct anv_surface_state sstate
=
2053 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2054 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2055 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2056 surface_state
= sstate
.state
;
2057 assert(surface_state
.alloc_size
);
2058 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
2059 binding
->plane
, sstate
);
2061 /* For color input attachments, we create the surface state at
2062 * vkBeginRenderPass time so that we can include aux and clear
2063 * color information.
2065 assert(binding
->input_attachment_index
< subpass
->input_count
);
2066 const unsigned subpass_att
= binding
->input_attachment_index
;
2067 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2068 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2072 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2073 struct anv_surface_state sstate
= (binding
->write_only
)
2074 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2075 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2076 surface_state
= sstate
.state
;
2077 assert(surface_state
.alloc_size
);
2078 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
2079 binding
->plane
, sstate
);
2081 struct brw_image_param
*image_param
=
2082 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2084 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2085 image_param
->surface_idx
= bias
+ s
;
2089 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2090 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2091 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2092 surface_state
= desc
->buffer_view
->surface_state
;
2093 assert(surface_state
.alloc_size
);
2094 add_surface_state_reloc(cmd_buffer
, surface_state
,
2095 desc
->buffer_view
->bo
,
2096 desc
->buffer_view
->offset
);
2099 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2100 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2101 /* Compute the offset within the buffer */
2102 uint32_t dynamic_offset
=
2103 dynamic_offset_for_binding(pipe_state
, binding
);
2104 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2105 /* Clamp to the buffer size */
2106 offset
= MIN2(offset
, desc
->buffer
->size
);
2107 /* Clamp the range to the buffer size */
2108 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2111 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2112 enum isl_format format
=
2113 anv_isl_format_for_descriptor_type(desc
->type
);
2115 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2116 format
, offset
, range
, 1);
2117 add_surface_state_reloc(cmd_buffer
, surface_state
,
2119 desc
->buffer
->offset
+ offset
);
2123 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2124 surface_state
= (binding
->write_only
)
2125 ? desc
->buffer_view
->writeonly_storage_surface_state
2126 : desc
->buffer_view
->storage_surface_state
;
2127 assert(surface_state
.alloc_size
);
2128 add_surface_state_reloc(cmd_buffer
, surface_state
,
2129 desc
->buffer_view
->bo
,
2130 desc
->buffer_view
->offset
);
2132 struct brw_image_param
*image_param
=
2133 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2135 *image_param
= desc
->buffer_view
->storage_image_param
;
2136 image_param
->surface_idx
= bias
+ s
;
2140 assert(!"Invalid descriptor type");
2144 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2146 assert(image
== map
->image_count
);
2149 anv_state_flush(cmd_buffer
->device
, *bt_state
);
2152 /* The PIPE_CONTROL command description says:
2154 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2155 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2156 * Target Cache Flush by enabling this bit. When render target flush
2157 * is set due to new association of BTI, PS Scoreboard Stall bit must
2158 * be set in this packet."
2160 * FINISHME: Currently we shuffle around the surface states in the binding
2161 * table based on if they are getting used or not. So, we've to do below
2162 * pipe control flush for every binding table upload. Make changes so
2163 * that we do it only when we modify render target surface states.
2165 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2166 pc
.RenderTargetCacheFlushEnable
= true;
2167 pc
.StallAtPixelScoreboard
= true;
2175 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2176 gl_shader_stage stage
,
2177 struct anv_state
*state
)
2179 struct anv_cmd_pipeline_state
*pipe_state
=
2180 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2181 &cmd_buffer
->state
.gfx
.base
;
2182 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2184 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2185 *state
= (struct anv_state
) { 0, };
2189 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2190 if (map
->sampler_count
== 0) {
2191 *state
= (struct anv_state
) { 0, };
2195 uint32_t size
= map
->sampler_count
* 16;
2196 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2198 if (state
->map
== NULL
)
2199 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2201 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2202 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2203 const struct anv_descriptor
*desc
=
2204 anv_descriptor_for_binding(pipe_state
, binding
);
2206 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2207 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2210 struct anv_sampler
*sampler
= desc
->sampler
;
2212 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2213 * happens to be zero.
2215 if (sampler
== NULL
)
2218 memcpy(state
->map
+ (s
* 16),
2219 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2222 anv_state_flush(cmd_buffer
->device
, *state
);
2228 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2230 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2232 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2233 pipeline
->active_stages
;
2235 VkResult result
= VK_SUCCESS
;
2236 anv_foreach_stage(s
, dirty
) {
2237 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2238 if (result
!= VK_SUCCESS
)
2240 result
= emit_binding_table(cmd_buffer
, s
,
2241 &cmd_buffer
->state
.binding_tables
[s
]);
2242 if (result
!= VK_SUCCESS
)
2246 if (result
!= VK_SUCCESS
) {
2247 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2249 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2250 if (result
!= VK_SUCCESS
)
2253 /* Re-emit state base addresses so we get the new surface state base
2254 * address before we start emitting binding tables etc.
2256 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2258 /* Re-emit all active binding tables */
2259 dirty
|= pipeline
->active_stages
;
2260 anv_foreach_stage(s
, dirty
) {
2261 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2262 if (result
!= VK_SUCCESS
) {
2263 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2266 result
= emit_binding_table(cmd_buffer
, s
,
2267 &cmd_buffer
->state
.binding_tables
[s
]);
2268 if (result
!= VK_SUCCESS
) {
2269 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2275 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2281 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2284 static const uint32_t sampler_state_opcodes
[] = {
2285 [MESA_SHADER_VERTEX
] = 43,
2286 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2287 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2288 [MESA_SHADER_GEOMETRY
] = 46,
2289 [MESA_SHADER_FRAGMENT
] = 47,
2290 [MESA_SHADER_COMPUTE
] = 0,
2293 static const uint32_t binding_table_opcodes
[] = {
2294 [MESA_SHADER_VERTEX
] = 38,
2295 [MESA_SHADER_TESS_CTRL
] = 39,
2296 [MESA_SHADER_TESS_EVAL
] = 40,
2297 [MESA_SHADER_GEOMETRY
] = 41,
2298 [MESA_SHADER_FRAGMENT
] = 42,
2299 [MESA_SHADER_COMPUTE
] = 0,
2302 anv_foreach_stage(s
, stages
) {
2303 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2304 assert(binding_table_opcodes
[s
] > 0);
2306 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2307 anv_batch_emit(&cmd_buffer
->batch
,
2308 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2309 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2310 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2314 /* Always emit binding table pointers if we're asked to, since on SKL
2315 * this is what flushes push constants. */
2316 anv_batch_emit(&cmd_buffer
->batch
,
2317 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2318 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2319 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2325 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2326 VkShaderStageFlags dirty_stages
)
2328 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2329 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2331 static const uint32_t push_constant_opcodes
[] = {
2332 [MESA_SHADER_VERTEX
] = 21,
2333 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2334 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2335 [MESA_SHADER_GEOMETRY
] = 22,
2336 [MESA_SHADER_FRAGMENT
] = 23,
2337 [MESA_SHADER_COMPUTE
] = 0,
2340 VkShaderStageFlags flushed
= 0;
2342 anv_foreach_stage(stage
, dirty_stages
) {
2343 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2344 assert(push_constant_opcodes
[stage
] > 0);
2346 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2347 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2349 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2350 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2351 const struct brw_stage_prog_data
*prog_data
=
2352 pipeline
->shaders
[stage
]->prog_data
;
2353 const struct anv_pipeline_bind_map
*bind_map
=
2354 &pipeline
->shaders
[stage
]->bind_map
;
2356 /* The Skylake PRM contains the following restriction:
2358 * "The driver must ensure The following case does not occur
2359 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2360 * buffer 3 read length equal to zero committed followed by a
2361 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2364 * To avoid this, we program the buffers in the highest slots.
2365 * This way, slot 0 is only used if slot 3 is also used.
2369 for (int i
= 3; i
>= 0; i
--) {
2370 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2371 if (range
->length
== 0)
2374 const unsigned surface
=
2375 prog_data
->binding_table
.ubo_start
+ range
->block
;
2377 assert(surface
<= bind_map
->surface_count
);
2378 const struct anv_pipeline_binding
*binding
=
2379 &bind_map
->surface_to_descriptor
[surface
];
2381 const struct anv_descriptor
*desc
=
2382 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2384 struct anv_address read_addr
;
2386 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2387 read_len
= MIN2(range
->length
,
2388 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2389 read_addr
= (struct anv_address
) {
2390 .bo
= desc
->buffer_view
->bo
,
2391 .offset
= desc
->buffer_view
->offset
+
2395 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2397 uint32_t dynamic_offset
=
2398 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2399 uint32_t buf_offset
=
2400 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2401 uint32_t buf_range
=
2402 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2404 read_len
= MIN2(range
->length
,
2405 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2406 read_addr
= (struct anv_address
) {
2407 .bo
= desc
->buffer
->bo
,
2408 .offset
= desc
->buffer
->offset
+ buf_offset
+
2414 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2415 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2420 struct anv_state state
=
2421 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2423 if (state
.alloc_size
> 0) {
2424 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2425 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2426 .offset
= state
.offset
,
2428 c
.ConstantBody
.ReadLength
[n
] =
2429 DIV_ROUND_UP(state
.alloc_size
, 32);
2432 /* For Ivy Bridge, the push constants packets have a different
2433 * rule that would require us to iterate in the other direction
2434 * and possibly mess around with dynamic state base address.
2435 * Don't bother; just emit regular push constants at n = 0.
2437 struct anv_state state
=
2438 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2440 if (state
.alloc_size
> 0) {
2441 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2442 c
.ConstantBody
.ReadLength
[0] =
2443 DIV_ROUND_UP(state
.alloc_size
, 32);
2449 flushed
|= mesa_to_vk_shader_stage(stage
);
2452 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2456 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2458 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2461 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2463 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2465 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2467 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2470 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2471 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2473 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2474 GENX(3DSTATE_VERTEX_BUFFERS
));
2476 for_each_bit(vb
, vb_emit
) {
2477 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2478 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2480 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2481 .VertexBufferIndex
= vb
,
2484 .MemoryObjectControlState
= GENX(MOCS
),
2486 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
2487 /* Our implementation of VK_KHR_multiview uses instancing to draw
2488 * the different views. If the client asks for instancing, we
2489 * need to use the Instance Data Step Rate to ensure that we
2490 * repeat the client's per-instance data once for each view.
2492 .InstanceDataStepRate
= anv_subpass_view_count(pipeline
->subpass
),
2493 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2496 .AddressModifyEnable
= true,
2497 .BufferPitch
= pipeline
->binding_stride
[vb
],
2498 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
2501 .BufferSize
= buffer
->size
- offset
2503 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
2507 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2512 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2514 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2515 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2517 /* The exact descriptor layout is pulled from the pipeline, so we need
2518 * to re-emit binding tables on every pipeline change.
2520 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2522 /* If the pipeline changed, we may need to re-allocate push constant
2525 cmd_buffer_alloc_push_constants(cmd_buffer
);
2529 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2530 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2531 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2533 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2534 * stall needs to be sent just prior to any 3DSTATE_VS,
2535 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2536 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2537 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2538 * PIPE_CONTROL needs to be sent before any combination of VS
2539 * associated 3DSTATE."
2541 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2542 pc
.DepthStallEnable
= true;
2543 pc
.PostSyncOperation
= WriteImmediateData
;
2545 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2550 /* Render targets live in the same binding table as fragment descriptors */
2551 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2552 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2554 /* We emit the binding tables and sampler tables first, then emit push
2555 * constants and then finally emit binding table and sampler table
2556 * pointers. It has to happen in this order, since emitting the binding
2557 * tables may change the push constants (in case of storage images). After
2558 * emitting push constants, on SKL+ we have to emit the corresponding
2559 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2562 if (cmd_buffer
->state
.descriptors_dirty
)
2563 dirty
= flush_descriptor_sets(cmd_buffer
);
2565 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2566 /* Because we're pushing UBOs, we have to push whenever either
2567 * descriptors or push constants is dirty.
2569 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2570 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2571 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2575 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2577 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2578 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2580 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2581 ANV_CMD_DIRTY_PIPELINE
)) {
2582 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2583 pipeline
->depth_clamp_enable
);
2586 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
2587 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2589 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2591 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2595 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2596 struct anv_bo
*bo
, uint32_t offset
,
2597 uint32_t size
, uint32_t index
)
2599 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2600 GENX(3DSTATE_VERTEX_BUFFERS
));
2602 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2603 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2604 .VertexBufferIndex
= index
,
2605 .AddressModifyEnable
= true,
2608 .MemoryObjectControlState
= GENX(MOCS
),
2609 .BufferStartingAddress
= { bo
, offset
},
2612 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2613 .BufferStartingAddress
= { bo
, offset
},
2614 .EndAddress
= { bo
, offset
+ size
},
2620 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2621 struct anv_bo
*bo
, uint32_t offset
)
2623 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
2627 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2628 uint32_t base_vertex
, uint32_t base_instance
)
2630 struct anv_state id_state
=
2631 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2633 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2634 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2636 anv_state_flush(cmd_buffer
->device
, id_state
);
2638 emit_base_vertex_instance_bo(cmd_buffer
,
2639 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
, id_state
.offset
);
2643 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2645 struct anv_state state
=
2646 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2648 ((uint32_t *)state
.map
)[0] = draw_index
;
2650 anv_state_flush(cmd_buffer
->device
, state
);
2652 emit_vertex_bo(cmd_buffer
,
2653 &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2654 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
2658 VkCommandBuffer commandBuffer
,
2659 uint32_t vertexCount
,
2660 uint32_t instanceCount
,
2661 uint32_t firstVertex
,
2662 uint32_t firstInstance
)
2664 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2665 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2666 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2668 if (anv_batch_has_error(&cmd_buffer
->batch
))
2671 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2673 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2674 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2675 if (vs_prog_data
->uses_drawid
)
2676 emit_draw_index(cmd_buffer
, 0);
2678 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2679 * different views. We need to multiply instanceCount by the view count.
2681 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2683 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2684 prim
.VertexAccessType
= SEQUENTIAL
;
2685 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2686 prim
.VertexCountPerInstance
= vertexCount
;
2687 prim
.StartVertexLocation
= firstVertex
;
2688 prim
.InstanceCount
= instanceCount
;
2689 prim
.StartInstanceLocation
= firstInstance
;
2690 prim
.BaseVertexLocation
= 0;
2694 void genX(CmdDrawIndexed
)(
2695 VkCommandBuffer commandBuffer
,
2696 uint32_t indexCount
,
2697 uint32_t instanceCount
,
2698 uint32_t firstIndex
,
2699 int32_t vertexOffset
,
2700 uint32_t firstInstance
)
2702 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2703 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2704 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2706 if (anv_batch_has_error(&cmd_buffer
->batch
))
2709 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2711 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2712 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2713 if (vs_prog_data
->uses_drawid
)
2714 emit_draw_index(cmd_buffer
, 0);
2716 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2717 * different views. We need to multiply instanceCount by the view count.
2719 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2721 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2722 prim
.VertexAccessType
= RANDOM
;
2723 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2724 prim
.VertexCountPerInstance
= indexCount
;
2725 prim
.StartVertexLocation
= firstIndex
;
2726 prim
.InstanceCount
= instanceCount
;
2727 prim
.StartInstanceLocation
= firstInstance
;
2728 prim
.BaseVertexLocation
= vertexOffset
;
2732 /* Auto-Draw / Indirect Registers */
2733 #define GEN7_3DPRIM_END_OFFSET 0x2420
2734 #define GEN7_3DPRIM_START_VERTEX 0x2430
2735 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2736 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2737 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2738 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2740 /* MI_MATH only exists on Haswell+ */
2741 #if GEN_IS_HASWELL || GEN_GEN >= 8
2743 /* Emit dwords to multiply GPR0 by N */
2745 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2747 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2749 #define append_alu(opcode, operand1, operand2) \
2750 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2753 unsigned top_bit
= 31 - __builtin_clz(N
);
2754 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2755 /* We get our initial data in GPR0 and we write the final data out to
2756 * GPR0 but we use GPR1 as our scratch register.
2758 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2759 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2761 /* Shift the current value left by 1 */
2762 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2763 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2764 append_alu(MI_ALU_ADD
, 0, 0);
2767 /* Store ACCU to R1 and add R0 to R1 */
2768 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2769 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2770 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2771 append_alu(MI_ALU_ADD
, 0, 0);
2774 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2781 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2783 uint32_t num_dwords
;
2784 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2786 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2787 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2790 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2793 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2794 struct anv_buffer
*buffer
, uint64_t offset
,
2797 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2798 struct anv_bo
*bo
= buffer
->bo
;
2799 uint32_t bo_offset
= buffer
->offset
+ offset
;
2801 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
2803 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2804 if (view_count
> 1) {
2805 #if GEN_IS_HASWELL || GEN_GEN >= 8
2806 emit_lrm(batch
, CS_GPR(0), bo
, bo_offset
+ 4);
2807 emit_mul_gpr0(batch
, view_count
);
2808 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2810 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2811 "MI_MATH is not supported on Ivy Bridge");
2812 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2815 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
2818 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
2821 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
2822 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
2824 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
2825 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2829 void genX(CmdDrawIndirect
)(
2830 VkCommandBuffer commandBuffer
,
2832 VkDeviceSize offset
,
2836 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2837 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2838 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2839 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2841 if (anv_batch_has_error(&cmd_buffer
->batch
))
2844 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2846 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2847 struct anv_bo
*bo
= buffer
->bo
;
2848 uint32_t bo_offset
= buffer
->offset
+ offset
;
2850 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2851 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
2852 if (vs_prog_data
->uses_drawid
)
2853 emit_draw_index(cmd_buffer
, i
);
2855 load_indirect_parameters(cmd_buffer
, buffer
, offset
, false);
2857 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2858 prim
.IndirectParameterEnable
= true;
2859 prim
.VertexAccessType
= SEQUENTIAL
;
2860 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2867 void genX(CmdDrawIndexedIndirect
)(
2868 VkCommandBuffer commandBuffer
,
2870 VkDeviceSize offset
,
2874 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2875 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2876 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2877 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2879 if (anv_batch_has_error(&cmd_buffer
->batch
))
2882 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2884 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2885 struct anv_bo
*bo
= buffer
->bo
;
2886 uint32_t bo_offset
= buffer
->offset
+ offset
;
2888 /* TODO: We need to stomp base vertex to 0 somehow */
2889 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
2890 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
2891 if (vs_prog_data
->uses_drawid
)
2892 emit_draw_index(cmd_buffer
, i
);
2894 load_indirect_parameters(cmd_buffer
, buffer
, offset
, true);
2896 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2897 prim
.IndirectParameterEnable
= true;
2898 prim
.VertexAccessType
= RANDOM
;
2899 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2907 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2909 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2910 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2913 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2914 if (result
!= VK_SUCCESS
) {
2915 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2917 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2918 if (result
!= VK_SUCCESS
)
2921 /* Re-emit state base addresses so we get the new surface state base
2922 * address before we start emitting binding tables etc.
2924 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2926 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2927 if (result
!= VK_SUCCESS
) {
2928 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2933 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
2934 if (result
!= VK_SUCCESS
) {
2935 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2939 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
2940 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2941 .BindingTablePointer
= surfaces
.offset
,
2942 .SamplerStatePointer
= samplers
.offset
,
2944 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
2946 struct anv_state state
=
2947 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
2948 pipeline
->interface_descriptor_data
,
2949 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
2952 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
2953 anv_batch_emit(&cmd_buffer
->batch
,
2954 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
2955 mid
.InterfaceDescriptorTotalLength
= size
;
2956 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
2963 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2965 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2966 MAYBE_UNUSED VkResult result
;
2968 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
2970 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2972 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
2974 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
2975 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
2977 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
2978 * the only bits that are changed are scoreboard related: Scoreboard
2979 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
2980 * these scoreboard related states, a MEDIA_STATE_FLUSH is
2983 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2984 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2986 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2989 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
2990 cmd_buffer
->state
.compute
.pipeline_dirty
) {
2991 /* FIXME: figure out descriptors for gen7 */
2992 result
= flush_compute_descriptor_set(cmd_buffer
);
2993 if (result
!= VK_SUCCESS
)
2996 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
2999 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3000 struct anv_state push_state
=
3001 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3003 if (push_state
.alloc_size
) {
3004 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3005 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3006 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3011 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3013 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3019 verify_cmd_parser(const struct anv_device
*device
,
3020 int required_version
,
3021 const char *function
)
3023 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3024 return vk_errorf(device
->instance
, device
->instance
,
3025 VK_ERROR_FEATURE_NOT_PRESENT
,
3026 "cmd parser version %d is required for %s",
3027 required_version
, function
);
3036 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3037 uint32_t baseGroupX
,
3038 uint32_t baseGroupY
,
3039 uint32_t baseGroupZ
)
3041 if (anv_batch_has_error(&cmd_buffer
->batch
))
3045 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3046 base_work_group_id
);
3047 if (result
!= VK_SUCCESS
) {
3048 cmd_buffer
->batch
.status
= result
;
3052 struct anv_push_constants
*push
=
3053 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3054 if (push
->base_work_group_id
[0] != baseGroupX
||
3055 push
->base_work_group_id
[1] != baseGroupY
||
3056 push
->base_work_group_id
[2] != baseGroupZ
) {
3057 push
->base_work_group_id
[0] = baseGroupX
;
3058 push
->base_work_group_id
[1] = baseGroupY
;
3059 push
->base_work_group_id
[2] = baseGroupZ
;
3061 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3065 void genX(CmdDispatch
)(
3066 VkCommandBuffer commandBuffer
,
3071 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3074 void genX(CmdDispatchBase
)(
3075 VkCommandBuffer commandBuffer
,
3076 uint32_t baseGroupX
,
3077 uint32_t baseGroupY
,
3078 uint32_t baseGroupZ
,
3079 uint32_t groupCountX
,
3080 uint32_t groupCountY
,
3081 uint32_t groupCountZ
)
3083 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3084 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3085 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3087 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3088 baseGroupY
, baseGroupZ
);
3090 if (anv_batch_has_error(&cmd_buffer
->batch
))
3093 if (prog_data
->uses_num_work_groups
) {
3094 struct anv_state state
=
3095 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3096 uint32_t *sizes
= state
.map
;
3097 sizes
[0] = groupCountX
;
3098 sizes
[1] = groupCountY
;
3099 sizes
[2] = groupCountZ
;
3100 anv_state_flush(cmd_buffer
->device
, state
);
3101 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3102 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3103 .offset
= state
.offset
,
3107 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3109 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3110 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3111 ggw
.ThreadDepthCounterMaximum
= 0;
3112 ggw
.ThreadHeightCounterMaximum
= 0;
3113 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3114 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3115 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3116 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3117 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3118 ggw
.BottomExecutionMask
= 0xffffffff;
3121 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3124 #define GPGPU_DISPATCHDIMX 0x2500
3125 #define GPGPU_DISPATCHDIMY 0x2504
3126 #define GPGPU_DISPATCHDIMZ 0x2508
3128 void genX(CmdDispatchIndirect
)(
3129 VkCommandBuffer commandBuffer
,
3131 VkDeviceSize offset
)
3133 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3134 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3135 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3136 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3137 struct anv_bo
*bo
= buffer
->bo
;
3138 uint32_t bo_offset
= buffer
->offset
+ offset
;
3139 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3141 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3144 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3145 * indirect dispatch registers to be written.
3147 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3148 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3152 if (prog_data
->uses_num_work_groups
) {
3153 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3155 .offset
= bo_offset
,
3159 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3161 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
3162 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
3163 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
3166 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3167 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3168 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3169 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3171 /* Load compute_dispatch_indirect_x_size into SRC0 */
3172 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
3174 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3175 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3176 mip
.LoadOperation
= LOAD_LOAD
;
3177 mip
.CombineOperation
= COMBINE_SET
;
3178 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3181 /* Load compute_dispatch_indirect_y_size into SRC0 */
3182 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
3184 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3185 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3186 mip
.LoadOperation
= LOAD_LOAD
;
3187 mip
.CombineOperation
= COMBINE_OR
;
3188 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3191 /* Load compute_dispatch_indirect_z_size into SRC0 */
3192 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
3194 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3195 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3196 mip
.LoadOperation
= LOAD_LOAD
;
3197 mip
.CombineOperation
= COMBINE_OR
;
3198 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3201 /* predicate = !predicate; */
3202 #define COMPARE_FALSE 1
3203 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3204 mip
.LoadOperation
= LOAD_LOADINV
;
3205 mip
.CombineOperation
= COMBINE_OR
;
3206 mip
.CompareOperation
= COMPARE_FALSE
;
3210 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3211 ggw
.IndirectParameterEnable
= true;
3212 ggw
.PredicateEnable
= GEN_GEN
<= 7;
3213 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3214 ggw
.ThreadDepthCounterMaximum
= 0;
3215 ggw
.ThreadHeightCounterMaximum
= 0;
3216 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3217 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3218 ggw
.BottomExecutionMask
= 0xffffffff;
3221 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3225 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3228 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3230 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3233 #if GEN_GEN >= 8 && GEN_GEN < 10
3234 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3236 * Software must clear the COLOR_CALC_STATE Valid field in
3237 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3238 * with Pipeline Select set to GPGPU.
3240 * The internal hardware docs recommend the same workaround for Gen9
3243 if (pipeline
== GPGPU
)
3244 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3247 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3248 * PIPELINE_SELECT [DevBWR+]":
3252 * Software must ensure all the write caches are flushed through a
3253 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3254 * command to invalidate read only caches prior to programming
3255 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3257 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3258 pc
.RenderTargetCacheFlushEnable
= true;
3259 pc
.DepthCacheFlushEnable
= true;
3260 pc
.DCFlushEnable
= true;
3261 pc
.PostSyncOperation
= NoWrite
;
3262 pc
.CommandStreamerStallEnable
= true;
3265 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3266 pc
.TextureCacheInvalidationEnable
= true;
3267 pc
.ConstantCacheInvalidationEnable
= true;
3268 pc
.StateCacheInvalidationEnable
= true;
3269 pc
.InstructionCacheInvalidateEnable
= true;
3270 pc
.PostSyncOperation
= NoWrite
;
3273 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3277 ps
.PipelineSelection
= pipeline
;
3281 if (devinfo
->is_geminilake
) {
3284 * "This chicken bit works around a hardware issue with barrier logic
3285 * encountered when switching between GPGPU and 3D pipelines. To
3286 * workaround the issue, this mode bit should be set after a pipeline
3290 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3292 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3293 : GLK_BARRIER_MODE_3D_HULL
,
3294 .GLKBarrierModeMask
= 1);
3295 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3299 cmd_buffer
->state
.current_pipeline
= pipeline
;
3303 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3305 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3309 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3311 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3315 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3320 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3322 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3323 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3324 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3325 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3326 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3327 * Depth Flush Bit set, followed by another pipelined depth stall
3328 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3329 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3330 * via a preceding MI_FLUSH)."
3332 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3333 pipe
.DepthStallEnable
= true;
3335 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3336 pipe
.DepthCacheFlushEnable
= true;
3338 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3339 pipe
.DepthStallEnable
= true;
3344 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3346 struct anv_device
*device
= cmd_buffer
->device
;
3347 const struct anv_image_view
*iview
=
3348 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3349 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3351 /* FIXME: Width and Height are wrong */
3353 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3355 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3356 device
->isl_dev
.ds
.size
/ 4);
3360 struct isl_depth_stencil_hiz_emit_info info
= {
3361 .mocs
= device
->default_mocs
,
3365 info
.view
= &iview
->planes
[0].isl
;
3367 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3368 uint32_t depth_plane
=
3369 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3370 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3372 info
.depth_surf
= &surface
->isl
;
3374 info
.depth_address
=
3375 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3376 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3377 image
->planes
[depth_plane
].bo
,
3378 image
->planes
[depth_plane
].bo_offset
+
3382 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.attachment
;
3383 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3384 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3385 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3388 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3389 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3390 image
->planes
[depth_plane
].bo
,
3391 image
->planes
[depth_plane
].bo_offset
+
3392 image
->planes
[depth_plane
].aux_surface
.offset
);
3394 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3398 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3399 uint32_t stencil_plane
=
3400 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3401 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3403 info
.stencil_surf
= &surface
->isl
;
3405 info
.stencil_address
=
3406 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3407 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3408 image
->planes
[stencil_plane
].bo
,
3409 image
->planes
[stencil_plane
].bo_offset
+ surface
->offset
);
3412 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3414 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3418 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3419 uint32_t subpass_id
)
3421 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3422 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3423 cmd_state
->subpass
= subpass
;
3425 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3427 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3428 * different views. If the client asks for instancing, we need to use the
3429 * Instance Data Step Rate to ensure that we repeat the client's
3430 * per-instance data once for each view. Since this bit is in
3431 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3435 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3437 /* It is possible to start a render pass with an old pipeline. Because the
3438 * render pass and subpass index are both baked into the pipeline, this is
3439 * highly unlikely. In order to do so, it requires that you have a render
3440 * pass with a single subpass and that you use that render pass twice
3441 * back-to-back and use the same pipeline at the start of the second render
3442 * pass as at the end of the first. In order to avoid unpredictable issues
3443 * with this edge case, we just dirty the pipeline at the start of every
3446 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3448 /* Accumulate any subpass flushes that need to happen before the subpass */
3449 cmd_buffer
->state
.pending_pipe_bits
|=
3450 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3452 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3453 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3455 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3456 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3457 if (a
== VK_ATTACHMENT_UNUSED
)
3460 assert(a
< cmd_state
->pass
->attachment_count
);
3461 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3463 struct anv_image_view
*iview
= fb
->attachments
[a
];
3464 const struct anv_image
*image
= iview
->image
;
3466 /* A resolve is necessary before use as an input attachment if the clear
3467 * color or auxiliary buffer usage isn't supported by the sampler.
3469 const bool input_needs_resolve
=
3470 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3471 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3473 VkImageLayout target_layout
;
3474 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3475 !input_needs_resolve
) {
3476 /* Layout transitions before the final only help to enable sampling
3477 * as an input attachment. If the input attachment supports sampling
3478 * using the auxiliary surface, we can skip such transitions by
3479 * making the target layout one that is CCS-aware.
3481 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3483 target_layout
= subpass
->attachments
[i
].layout
;
3486 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3487 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3489 uint32_t base_layer
, layer_count
;
3490 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3492 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3493 iview
->planes
[0].isl
.base_level
);
3495 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3496 layer_count
= fb
->layers
;
3499 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3500 iview
->planes
[0].isl
.base_level
, 1,
3501 base_layer
, layer_count
,
3502 att_state
->current_layout
, target_layout
);
3503 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3504 transition_depth_buffer(cmd_buffer
, image
,
3505 att_state
->current_layout
, target_layout
);
3506 att_state
->aux_usage
=
3507 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3508 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3510 att_state
->current_layout
= target_layout
;
3512 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3513 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3515 /* Multi-planar images are not supported as attachments */
3516 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3517 assert(image
->n_planes
== 1);
3519 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
3520 uint32_t clear_layer_count
= fb
->layers
;
3522 if (att_state
->fast_clear
) {
3523 /* We only support fast-clears on the first layer */
3524 assert(iview
->planes
[0].isl
.base_level
== 0);
3525 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3527 if (iview
->image
->samples
== 1) {
3528 anv_image_ccs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3529 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
, false);
3531 anv_image_mcs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3532 0, 1, ISL_AUX_OP_FAST_CLEAR
, false);
3535 clear_layer_count
--;
3537 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3538 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3539 true /* copy from ss */);
3541 if (att_state
->clear_color_is_zero
) {
3542 /* This image has the auxiliary buffer enabled. We can mark the
3543 * subresource as not needing a resolve because the clear color
3544 * will match what's in every RENDER_SURFACE_STATE object when
3545 * it's being used for sampling.
3547 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3548 VK_IMAGE_ASPECT_COLOR_BIT
,
3549 ANV_FAST_CLEAR_DEFAULT_VALUE
);
3551 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3552 VK_IMAGE_ASPECT_COLOR_BIT
,
3553 ANV_FAST_CLEAR_ANY
);
3557 if (clear_layer_count
> 0) {
3558 assert(image
->n_planes
== 1);
3559 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3560 att_state
->aux_usage
,
3561 iview
->planes
[0].isl
.format
,
3562 iview
->planes
[0].isl
.swizzle
,
3563 iview
->planes
[0].isl
.base_level
,
3564 base_clear_layer
, clear_layer_count
,
3566 vk_to_isl_color(att_state
->clear_value
.color
));
3568 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
3569 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3570 if (att_state
->fast_clear
) {
3571 /* We currently only support HiZ for single-layer images */
3572 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3573 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
3574 assert(iview
->planes
[0].isl
.base_level
== 0);
3575 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3576 assert(fb
->layers
== 1);
3579 anv_image_hiz_clear(cmd_buffer
, image
,
3580 att_state
->pending_clear_aspects
,
3581 iview
->planes
[0].isl
.base_level
,
3582 iview
->planes
[0].isl
.base_array_layer
,
3583 fb
->layers
, render_area
,
3584 att_state
->clear_value
.depthStencil
.stencil
);
3586 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3587 att_state
->pending_clear_aspects
,
3588 att_state
->aux_usage
,
3589 iview
->planes
[0].isl
.base_level
,
3590 iview
->planes
[0].isl
.base_array_layer
,
3591 fb
->layers
, render_area
,
3592 att_state
->clear_value
.depthStencil
.depth
,
3593 att_state
->clear_value
.depthStencil
.stencil
);
3596 assert(att_state
->pending_clear_aspects
== 0);
3599 if ((att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
3600 image
->planes
[0].aux_surface
.isl
.size
> 0 &&
3601 iview
->planes
[0].isl
.base_level
== 0 &&
3602 iview
->planes
[0].isl
.base_array_layer
== 0) {
3603 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
3604 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3605 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3606 false /* copy to ss */);
3609 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
3610 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3611 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3612 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3613 false /* copy to ss */);
3617 if (subpass
->attachments
[i
].usage
==
3618 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
3619 /* We assume that if we're starting a subpass, we're going to do some
3620 * rendering so we may end up with compressed data.
3622 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
3623 VK_IMAGE_ASPECT_COLOR_BIT
,
3624 att_state
->aux_usage
,
3625 iview
->planes
[0].isl
.base_level
,
3626 iview
->planes
[0].isl
.base_array_layer
,
3628 } else if (subpass
->attachments
[i
].usage
==
3629 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
3630 /* We may be writing depth or stencil so we need to mark the surface.
3631 * Unfortunately, there's no way to know at this point whether the
3632 * depth or stencil tests used will actually write to the surface.
3634 * Even though stencil may be plane 1, it always shares a base_level
3637 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
3638 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3639 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3640 VK_IMAGE_ASPECT_DEPTH_BIT
,
3641 att_state
->aux_usage
,
3642 ds_view
->base_level
,
3643 ds_view
->base_array_layer
,
3646 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
3647 /* Even though stencil may be plane 1, it always shares a
3648 * base_level with depth.
3650 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3651 VK_IMAGE_ASPECT_STENCIL_BIT
,
3653 ds_view
->base_level
,
3654 ds_view
->base_array_layer
,
3659 att_state
->pending_clear_aspects
= 0;
3660 att_state
->pending_load_aspects
= 0;
3663 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3667 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
3669 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3670 struct anv_subpass
*subpass
= cmd_state
->subpass
;
3671 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3673 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3675 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3676 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3677 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3678 if (a
== VK_ATTACHMENT_UNUSED
)
3681 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3684 assert(a
< cmd_state
->pass
->attachment_count
);
3685 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3686 struct anv_image_view
*iview
= fb
->attachments
[a
];
3687 const struct anv_image
*image
= iview
->image
;
3689 /* Transition the image into the final layout for this render pass */
3690 VkImageLayout target_layout
=
3691 cmd_state
->pass
->attachments
[a
].final_layout
;
3693 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3694 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3696 uint32_t base_layer
, layer_count
;
3697 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3699 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3700 iview
->planes
[0].isl
.base_level
);
3702 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3703 layer_count
= fb
->layers
;
3706 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3707 iview
->planes
[0].isl
.base_level
, 1,
3708 base_layer
, layer_count
,
3709 att_state
->current_layout
, target_layout
);
3710 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3711 transition_depth_buffer(cmd_buffer
, image
,
3712 att_state
->current_layout
, target_layout
);
3716 /* Accumulate any subpass flushes that need to happen after the subpass.
3717 * Yes, they do get accumulated twice in the NextSubpass case but since
3718 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
3719 * ORing the bits in twice so it's harmless.
3721 cmd_buffer
->state
.pending_pipe_bits
|=
3722 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
3725 void genX(CmdBeginRenderPass
)(
3726 VkCommandBuffer commandBuffer
,
3727 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3728 VkSubpassContents contents
)
3730 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3731 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3732 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3734 cmd_buffer
->state
.framebuffer
= framebuffer
;
3735 cmd_buffer
->state
.pass
= pass
;
3736 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3738 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3740 /* If we failed to setup the attachments we should not try to go further */
3741 if (result
!= VK_SUCCESS
) {
3742 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3746 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3748 cmd_buffer_begin_subpass(cmd_buffer
, 0);
3751 void genX(CmdNextSubpass
)(
3752 VkCommandBuffer commandBuffer
,
3753 VkSubpassContents contents
)
3755 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3757 if (anv_batch_has_error(&cmd_buffer
->batch
))
3760 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3762 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
3763 cmd_buffer_end_subpass(cmd_buffer
);
3764 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3767 void genX(CmdEndRenderPass
)(
3768 VkCommandBuffer commandBuffer
)
3770 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3772 if (anv_batch_has_error(&cmd_buffer
->batch
))
3775 cmd_buffer_end_subpass(cmd_buffer
);
3777 cmd_buffer
->state
.hiz_enabled
= false;
3780 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
3783 /* Remove references to render pass specific state. This enables us to
3784 * detect whether or not we're in a renderpass.
3786 cmd_buffer
->state
.framebuffer
= NULL
;
3787 cmd_buffer
->state
.pass
= NULL
;
3788 cmd_buffer
->state
.subpass
= NULL
;