2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
, uint32_t reg
, struct anv_address addr
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= addr
;
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
53 #if GEN_IS_HASWELL || GEN_GEN >= 8
55 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
57 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
58 lrr
.SourceRegisterAddress
= src
;
59 lrr
.DestinationRegisterAddress
= dst
;
65 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
67 struct anv_device
*device
= cmd_buffer
->device
;
69 /* If we are emitting a new state base address we probably need to re-emit
72 cmd_buffer
->state
.descriptors_dirty
|= ~0;
74 /* Emit a render target cache flush.
76 * This isn't documented anywhere in the PRM. However, it seems to be
77 * necessary prior to changing the surface state base adress. Without
78 * this, we get GPU hangs when using multi-level command buffers which
79 * clear depth, reset state base address, and then go render stuff.
81 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
82 pc
.DCFlushEnable
= true;
83 pc
.RenderTargetCacheFlushEnable
= true;
84 pc
.CommandStreamerStallEnable
= true;
87 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
88 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
89 sba
.GeneralStateMOCS
= GENX(MOCS
);
90 sba
.GeneralStateBaseAddressModifyEnable
= true;
92 sba
.SurfaceStateBaseAddress
=
93 anv_cmd_buffer_surface_base_address(cmd_buffer
);
94 sba
.SurfaceStateMOCS
= GENX(MOCS
);
95 sba
.SurfaceStateBaseAddressModifyEnable
= true;
97 sba
.DynamicStateBaseAddress
=
98 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
99 sba
.DynamicStateMOCS
= GENX(MOCS
);
100 sba
.DynamicStateBaseAddressModifyEnable
= true;
102 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
103 sba
.IndirectObjectMOCS
= GENX(MOCS
);
104 sba
.IndirectObjectBaseAddressModifyEnable
= true;
106 sba
.InstructionBaseAddress
=
107 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
108 sba
.InstructionMOCS
= GENX(MOCS
);
109 sba
.InstructionBaseAddressModifyEnable
= true;
112 /* Broadwell requires that we specify a buffer size for a bunch of
113 * these fields. However, since we will be growing the BO's live, we
114 * just set them all to the maximum.
116 sba
.GeneralStateBufferSize
= 0xfffff;
117 sba
.GeneralStateBufferSizeModifyEnable
= true;
118 sba
.DynamicStateBufferSize
= 0xfffff;
119 sba
.DynamicStateBufferSizeModifyEnable
= true;
120 sba
.IndirectObjectBufferSize
= 0xfffff;
121 sba
.IndirectObjectBufferSizeModifyEnable
= true;
122 sba
.InstructionBufferSize
= 0xfffff;
123 sba
.InstructionBuffersizeModifyEnable
= true;
126 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
127 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
128 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
129 sba
.BindlessSurfaceStateSize
= 0;
132 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
133 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
134 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
135 sba
.BindlessSamplerStateBufferSize
= 0;
139 /* After re-setting the surface state base address, we have to do some
140 * cache flusing so that the sampler engine will pick up the new
141 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
142 * Shared Function > 3D Sampler > State > State Caching (page 96):
144 * Coherency with system memory in the state cache, like the texture
145 * cache is handled partially by software. It is expected that the
146 * command stream or shader will issue Cache Flush operation or
147 * Cache_Flush sampler message to ensure that the L1 cache remains
148 * coherent with system memory.
152 * Whenever the value of the Dynamic_State_Base_Addr,
153 * Surface_State_Base_Addr are altered, the L1 state cache must be
154 * invalidated to ensure the new surface or sampler state is fetched
155 * from system memory.
157 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
158 * which, according the PIPE_CONTROL instruction documentation in the
161 * Setting this bit is independent of any other bit in this packet.
162 * This bit controls the invalidation of the L1 and L2 state caches
163 * at the top of the pipe i.e. at the parsing time.
165 * Unfortunately, experimentation seems to indicate that state cache
166 * invalidation through a PIPE_CONTROL does nothing whatsoever in
167 * regards to surface state and binding tables. In stead, it seems that
168 * invalidating the texture cache is what is actually needed.
170 * XXX: As far as we have been able to determine through
171 * experimentation, shows that flush the texture cache appears to be
172 * sufficient. The theory here is that all of the sampling/rendering
173 * units cache the binding table in the texture cache. However, we have
174 * yet to be able to actually confirm this.
176 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
177 pc
.TextureCacheInvalidationEnable
= true;
178 pc
.ConstantCacheInvalidationEnable
= true;
179 pc
.StateCacheInvalidationEnable
= true;
184 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
185 struct anv_state state
, struct anv_address addr
)
187 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
190 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
191 state
.offset
+ isl_dev
->ss
.addr_offset
,
192 addr
.bo
, addr
.offset
);
193 if (result
!= VK_SUCCESS
)
194 anv_batch_set_error(&cmd_buffer
->batch
, result
);
198 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
199 struct anv_surface_state state
)
201 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
203 assert(!anv_address_is_null(state
.address
));
204 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
206 if (!anv_address_is_null(state
.aux_address
)) {
208 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
209 &cmd_buffer
->pool
->alloc
,
210 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
211 state
.aux_address
.bo
, state
.aux_address
.offset
);
212 if (result
!= VK_SUCCESS
)
213 anv_batch_set_error(&cmd_buffer
->batch
, result
);
216 if (!anv_address_is_null(state
.clear_address
)) {
218 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
219 &cmd_buffer
->pool
->alloc
,
221 isl_dev
->ss
.clear_color_state_offset
,
222 state
.clear_address
.bo
, state
.clear_address
.offset
);
223 if (result
!= VK_SUCCESS
)
224 anv_batch_set_error(&cmd_buffer
->batch
, result
);
229 color_attachment_compute_aux_usage(struct anv_device
* device
,
230 struct anv_cmd_state
* cmd_state
,
231 uint32_t att
, VkRect2D render_area
,
232 union isl_color_value
*fast_clear_color
)
234 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
235 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
237 assert(iview
->n_planes
== 1);
239 if (iview
->planes
[0].isl
.base_array_layer
>=
240 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
241 iview
->planes
[0].isl
.base_level
)) {
242 /* There is no aux buffer which corresponds to the level and layer(s)
245 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
246 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
247 att_state
->fast_clear
= false;
251 att_state
->aux_usage
=
252 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
253 VK_IMAGE_ASPECT_COLOR_BIT
,
254 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
256 /* If we don't have aux, then we should have returned early in the layer
257 * check above. If we got here, we must have something.
259 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
261 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
262 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
263 att_state
->input_aux_usage
= att_state
->aux_usage
;
265 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
267 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
268 * setting is only allowed if Surface Format supported for Fast
269 * Clear. In addition, if the surface is bound to the sampling
270 * engine, Surface Format must be supported for Render Target
271 * Compression for surfaces bound to the sampling engine."
273 * In other words, we can only sample from a fast-cleared image if it
274 * also supports color compression.
276 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
277 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
279 /* While fast-clear resolves and partial resolves are fairly cheap in the
280 * case where you render to most of the pixels, full resolves are not
281 * because they potentially involve reading and writing the entire
282 * framebuffer. If we can't texture with CCS_E, we should leave it off and
283 * limit ourselves to fast clears.
285 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
286 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
287 anv_perf_warn(device
->instance
, iview
->image
,
288 "Not temporarily enabling CCS_E.");
291 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
295 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
296 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
298 union isl_color_value clear_color
= {};
299 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
301 att_state
->clear_color_is_zero_one
=
302 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
303 att_state
->clear_color_is_zero
=
304 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
306 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
307 /* Start by getting the fast clear type. We use the first subpass
308 * layout here because we don't want to fast-clear if the first subpass
309 * to use the attachment can't handle fast-clears.
311 enum anv_fast_clear_type fast_clear_type
=
312 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
313 VK_IMAGE_ASPECT_COLOR_BIT
,
314 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
315 switch (fast_clear_type
) {
316 case ANV_FAST_CLEAR_NONE
:
317 att_state
->fast_clear
= false;
319 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
320 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
322 case ANV_FAST_CLEAR_ANY
:
323 att_state
->fast_clear
= true;
327 /* Potentially, we could do partial fast-clears but doing so has crazy
328 * alignment restrictions. It's easier to just restrict to full size
329 * fast clears for now.
331 if (render_area
.offset
.x
!= 0 ||
332 render_area
.offset
.y
!= 0 ||
333 render_area
.extent
.width
!= iview
->extent
.width
||
334 render_area
.extent
.height
!= iview
->extent
.height
)
335 att_state
->fast_clear
= false;
337 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
338 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
339 att_state
->fast_clear
= false;
341 /* We only allow fast clears to the first slice of an image (level 0,
342 * layer 0) and only for the entire slice. This guarantees us that, at
343 * any given time, there is only one clear color on any given image at
344 * any given time. At the time of our testing (Jan 17, 2018), there
345 * were no known applications which would benefit from fast-clearing
346 * more than just the first slice.
348 if (att_state
->fast_clear
&&
349 (iview
->planes
[0].isl
.base_level
> 0 ||
350 iview
->planes
[0].isl
.base_array_layer
> 0)) {
351 anv_perf_warn(device
->instance
, iview
->image
,
352 "Rendering with multi-lod or multi-layer framebuffer "
353 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
354 "baseArrayLayer > 0. Not fast clearing.");
355 att_state
->fast_clear
= false;
356 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
357 anv_perf_warn(device
->instance
, iview
->image
,
358 "Rendering to a multi-layer framebuffer with "
359 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
362 if (att_state
->fast_clear
)
363 *fast_clear_color
= clear_color
;
365 att_state
->fast_clear
= false;
370 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
371 struct anv_cmd_state
*cmd_state
,
372 uint32_t att
, VkRect2D render_area
)
374 struct anv_render_pass_attachment
*pass_att
=
375 &cmd_state
->pass
->attachments
[att
];
376 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
377 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
379 /* These will be initialized after the first subpass transition. */
380 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
381 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
384 /* We don't do any HiZ or depth fast-clears on gen7 yet */
385 att_state
->fast_clear
= false;
389 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
390 /* If we're just clearing stencil, we can always HiZ clear */
391 att_state
->fast_clear
= true;
395 /* Default to false for now */
396 att_state
->fast_clear
= false;
398 /* We must have depth in order to have HiZ */
399 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
402 const enum isl_aux_usage first_subpass_aux_usage
=
403 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
404 VK_IMAGE_ASPECT_DEPTH_BIT
,
405 pass_att
->first_subpass_layout
);
406 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
409 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
410 iview
->planes
[0].isl
.format
,
411 iview
->image
->samples
,
412 render_area
.offset
.x
,
413 render_area
.offset
.y
,
414 render_area
.offset
.x
+
415 render_area
.extent
.width
,
416 render_area
.offset
.y
+
417 render_area
.extent
.height
))
420 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
423 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
424 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
425 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
426 * only supports returning 0.0f. Gens prior to gen8 do not support this
432 /* If we got here, then we can fast clear */
433 att_state
->fast_clear
= true;
437 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
439 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
442 /* We only allocate input attachment states for color surfaces. Compression
443 * is not yet enabled for depth textures and stencil doesn't allow
444 * compression so we can just use the texture surface state from the view.
446 return vk_format_is_color(att
->format
);
449 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
450 * the initial layout is undefined, the HiZ buffer and depth buffer will
451 * represent the same data at the end of this operation.
454 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
455 const struct anv_image
*image
,
456 VkImageLayout initial_layout
,
457 VkImageLayout final_layout
)
459 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
460 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
461 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
462 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
463 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
464 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
466 enum isl_aux_op hiz_op
;
467 if (hiz_enabled
&& !enable_hiz
) {
468 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
469 } else if (!hiz_enabled
&& enable_hiz
) {
470 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
472 assert(hiz_enabled
== enable_hiz
);
473 /* If the same buffer will be used, no resolves are necessary. */
474 hiz_op
= ISL_AUX_OP_NONE
;
477 if (hiz_op
!= ISL_AUX_OP_NONE
)
478 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
482 #define MI_PREDICATE_SRC0 0x2400
483 #define MI_PREDICATE_SRC1 0x2408
486 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
487 const struct anv_image
*image
,
488 VkImageAspectFlagBits aspect
,
490 uint32_t base_layer
, uint32_t layer_count
,
493 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
495 /* We only have compression tracking for CCS_E */
496 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
499 for (uint32_t a
= 0; a
< layer_count
; a
++) {
500 uint32_t layer
= base_layer
+ a
;
501 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
502 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
505 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
511 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
512 const struct anv_image
*image
,
513 VkImageAspectFlagBits aspect
,
514 enum anv_fast_clear_type fast_clear
)
516 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
517 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
519 sdi
.ImmediateData
= fast_clear
;
522 /* Whenever we have fast-clear, we consider that slice to be compressed.
523 * This makes building predicates much easier.
525 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
526 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
529 #if GEN_IS_HASWELL || GEN_GEN >= 8
530 static inline uint32_t
531 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
533 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
535 .Operand1
= operand1
,
536 .Operand2
= operand2
,
540 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
546 #define CS_GPR(n) (0x2600 + (n) * 8)
548 /* This is only really practical on haswell and above because it requires
549 * MI math in order to get it correct.
551 #if GEN_GEN >= 8 || GEN_IS_HASWELL
553 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
554 const struct anv_image
*image
,
555 VkImageAspectFlagBits aspect
,
556 uint32_t level
, uint32_t array_layer
,
557 enum isl_aux_op resolve_op
,
558 enum anv_fast_clear_type fast_clear_supported
)
560 struct anv_address fast_clear_type_addr
=
561 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
563 /* Name some registers */
564 const int image_fc_reg
= MI_ALU_REG0
;
565 const int fc_imm_reg
= MI_ALU_REG1
;
566 const int pred_reg
= MI_ALU_REG2
;
570 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
571 /* In this case, we're doing a full resolve which means we want the
572 * resolve to happen if any compression (including fast-clears) is
575 * In order to simplify the logic a bit, we make the assumption that,
576 * if the first slice has been fast-cleared, it is also marked as
577 * compressed. See also set_image_fast_clear_state.
579 struct anv_address compression_state_addr
=
580 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
581 aspect
, level
, array_layer
);
582 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
583 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
584 lrm
.MemoryAddress
= compression_state_addr
;
586 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
587 sdi
.Address
= compression_state_addr
;
588 sdi
.ImmediateData
= 0;
591 if (level
== 0 && array_layer
== 0) {
592 /* If the predicate is true, we want to write 0 to the fast clear type
593 * and, if it's false, leave it alone. We can do this by writing
595 * clear_type = clear_type & ~predicate;
597 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
598 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
599 lrm
.MemoryAddress
= fast_clear_type_addr
;
601 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
602 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
603 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
606 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
607 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
608 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
609 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
610 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
612 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
613 srm
.MemoryAddress
= fast_clear_type_addr
;
614 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
617 } else if (level
== 0 && array_layer
== 0) {
618 /* In this case, we are doing a partial resolve to get rid of fast-clear
619 * colors. We don't care about the compression state but we do care
620 * about how much fast clear is allowed by the final layout.
622 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
623 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
625 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
626 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
627 lrm
.MemoryAddress
= fast_clear_type_addr
;
629 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
631 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
632 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
634 /* We need to compute (fast_clear_supported < image->fast_clear).
635 * We do this by subtracting and storing the carry bit.
637 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
638 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
639 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
640 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
641 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
643 /* Store the predicate */
644 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
646 /* If the predicate is true, we want to write 0 to the fast clear type
647 * and, if it's false, leave it alone. We can do this by writing
649 * clear_type = clear_type & ~predicate;
651 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
652 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
653 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
654 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
655 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
657 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
658 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
659 srm
.MemoryAddress
= fast_clear_type_addr
;
662 /* In this case, we're trying to do a partial resolve on a slice that
663 * doesn't have clear color. There's nothing to do.
665 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
669 /* We use the first half of src0 for the actual predicate. Set the second
670 * half of src0 and all of src1 to 0 as the predicate operation will be
671 * doing an implicit src0 != src1.
673 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
674 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
675 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
677 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
678 mip
.LoadOperation
= LOAD_LOADINV
;
679 mip
.CombineOperation
= COMBINE_SET
;
680 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
683 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
687 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
688 const struct anv_image
*image
,
689 VkImageAspectFlagBits aspect
,
690 uint32_t level
, uint32_t array_layer
,
691 enum isl_aux_op resolve_op
,
692 enum anv_fast_clear_type fast_clear_supported
)
694 struct anv_address fast_clear_type_addr
=
695 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
697 /* This only works for partial resolves and only when the clear color is
698 * all or nothing. On the upside, this emits less command streamer code
699 * and works on Ivybridge and Bay Trail.
701 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
702 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
704 /* We don't support fast clears on anything other than the first slice. */
705 if (level
> 0 || array_layer
> 0)
708 /* On gen8, we don't have a concept of default clear colors because we
709 * can't sample from CCS surfaces. It's enough to just load the fast clear
710 * state into the predicate register.
712 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
713 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
714 lrm
.MemoryAddress
= fast_clear_type_addr
;
716 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
717 sdi
.Address
= fast_clear_type_addr
;
718 sdi
.ImmediateData
= 0;
721 /* We use the first half of src0 for the actual predicate. Set the second
722 * half of src0 and all of src1 to 0 as the predicate operation will be
723 * doing an implicit src0 != src1.
725 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
726 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
727 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
729 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
730 mip
.LoadOperation
= LOAD_LOADINV
;
731 mip
.CombineOperation
= COMBINE_SET
;
732 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
735 #endif /* GEN_GEN <= 8 */
738 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
739 const struct anv_image
*image
,
740 VkImageAspectFlagBits aspect
,
741 uint32_t level
, uint32_t array_layer
,
742 enum isl_aux_op resolve_op
,
743 enum anv_fast_clear_type fast_clear_supported
)
745 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
748 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
749 aspect
, level
, array_layer
,
750 resolve_op
, fast_clear_supported
);
751 #else /* GEN_GEN <= 8 */
752 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
753 aspect
, level
, array_layer
,
754 resolve_op
, fast_clear_supported
);
757 /* CCS_D only supports full resolves and BLORP will assert on us if we try
758 * to do a partial resolve on a CCS_D surface.
760 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
761 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
762 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
764 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
765 array_layer
, 1, resolve_op
, NULL
, true);
769 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
770 const struct anv_image
*image
,
771 VkImageAspectFlagBits aspect
,
772 uint32_t array_layer
,
773 enum isl_aux_op resolve_op
,
774 enum anv_fast_clear_type fast_clear_supported
)
776 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
777 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
779 #if GEN_GEN >= 8 || GEN_IS_HASWELL
780 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
781 aspect
, 0, array_layer
,
782 resolve_op
, fast_clear_supported
);
784 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
785 array_layer
, 1, resolve_op
, NULL
, true);
787 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
792 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
793 const struct anv_image
*image
,
794 VkImageAspectFlagBits aspect
,
795 enum isl_aux_usage aux_usage
,
798 uint32_t layer_count
)
800 /* The aspect must be exactly one of the image aspects. */
801 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
803 /* The only compression types with more than just fast-clears are MCS,
804 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
805 * track the current fast-clear and compression state. This leaves us
806 * with just MCS and CCS_E.
808 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
809 aux_usage
!= ISL_AUX_USAGE_MCS
)
812 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
813 level
, base_layer
, layer_count
, true);
817 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
818 const struct anv_image
*image
,
819 VkImageAspectFlagBits aspect
)
821 assert(cmd_buffer
&& image
);
822 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
824 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
825 ANV_FAST_CLEAR_NONE
);
827 /* The fast clear value dword(s) will be copied into a surface state object.
828 * Ensure that the restrictions of the fields in the dword(s) are followed.
830 * CCS buffers on SKL+ can have any value set for the clear colors.
832 if (image
->samples
== 1 && GEN_GEN
>= 9)
835 /* Other combinations of auxiliary buffers and platforms require specific
836 * values in the clear value dword(s).
838 struct anv_address addr
=
839 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
842 for (unsigned i
= 0; i
< 4; i
++) {
843 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
845 sdi
.Address
.offset
+= i
* 4;
846 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
847 assert(image
->samples
> 1);
848 sdi
.ImmediateData
= 0;
852 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
854 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
855 /* Pre-SKL, the dword containing the clear values also contains
856 * other fields, so we need to initialize those fields to match the
857 * values that would be in a color attachment.
859 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
860 ISL_CHANNEL_SELECT_GREEN
<< 22 |
861 ISL_CHANNEL_SELECT_BLUE
<< 19 |
862 ISL_CHANNEL_SELECT_ALPHA
<< 16;
863 } else if (GEN_GEN
== 7) {
864 /* On IVB, the dword containing the clear values also contains
865 * other fields that must be zero or can be zero.
867 sdi
.ImmediateData
= 0;
873 /* Copy the fast-clear value dword(s) between a surface state object and an
874 * image's fast clear state buffer.
877 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
878 struct anv_state surface_state
,
879 const struct anv_image
*image
,
880 VkImageAspectFlagBits aspect
,
881 bool copy_from_surface_state
)
883 assert(cmd_buffer
&& image
);
884 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
886 struct anv_address ss_clear_addr
= {
887 .bo
= &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
888 .offset
= surface_state
.offset
+
889 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
891 const struct anv_address entry_addr
=
892 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
893 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
895 if (copy_from_surface_state
) {
896 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
,
897 ss_clear_addr
, copy_size
);
899 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_clear_addr
,
900 entry_addr
, copy_size
);
902 /* Updating a surface state object may require that the state cache be
903 * invalidated. From the SKL PRM, Shared Functions -> State -> State
906 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
907 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
908 * modified [...], the L1 state cache must be invalidated to ensure
909 * the new surface or sampler state is fetched from system memory.
911 * In testing, SKL doesn't actually seem to need this, but HSW does.
913 cmd_buffer
->state
.pending_pipe_bits
|=
914 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
919 * @brief Transitions a color buffer from one layout to another.
921 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
924 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
925 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
926 * this represents the maximum layers to transition at each
927 * specified miplevel.
930 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
931 const struct anv_image
*image
,
932 VkImageAspectFlagBits aspect
,
933 const uint32_t base_level
, uint32_t level_count
,
934 uint32_t base_layer
, uint32_t layer_count
,
935 VkImageLayout initial_layout
,
936 VkImageLayout final_layout
)
938 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
939 /* Validate the inputs. */
941 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
942 /* These values aren't supported for simplicity's sake. */
943 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
944 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
945 /* Ensure the subresource range is valid. */
946 uint64_t last_level_num
= base_level
+ level_count
;
947 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
948 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
949 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
950 assert(last_level_num
<= image
->levels
);
951 /* The spec disallows these final layouts. */
952 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
953 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
955 /* No work is necessary if the layout stays the same or if this subresource
956 * range lacks auxiliary data.
958 if (initial_layout
== final_layout
)
961 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
963 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
964 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
965 /* This surface is a linear compressed image with a tiled shadow surface
966 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
967 * we need to ensure the shadow copy is up-to-date.
969 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
970 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
971 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
972 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
974 anv_image_copy_to_shadow(cmd_buffer
, image
,
975 base_level
, level_count
,
976 base_layer
, layer_count
);
979 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
982 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
984 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
985 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
986 /* A subresource in the undefined layout may have been aliased and
987 * populated with any arrangement of bits. Therefore, we must initialize
988 * the related aux buffer and clear buffer entry with desirable values.
989 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
990 * images with VK_IMAGE_TILING_OPTIMAL.
992 * Initialize the relevant clear buffer entries.
994 if (base_level
== 0 && base_layer
== 0)
995 init_fast_clear_color(cmd_buffer
, image
, aspect
);
997 /* Initialize the aux buffers to enable correct rendering. In order to
998 * ensure that things such as storage images work correctly, aux buffers
999 * need to be initialized to valid data.
1001 * Having an aux buffer with invalid data is a problem for two reasons:
1003 * 1) Having an invalid value in the buffer can confuse the hardware.
1004 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1005 * invalid and leads to the hardware doing strange things. It
1006 * doesn't hang as far as we can tell but rendering corruption can
1009 * 2) If this transition is into the GENERAL layout and we then use the
1010 * image as a storage image, then we must have the aux buffer in the
1011 * pass-through state so that, if we then go to texture from the
1012 * image, we get the results of our storage image writes and not the
1013 * fast clear color or other random data.
1015 * For CCS both of the problems above are real demonstrable issues. In
1016 * that case, the only thing we can do is to perform an ambiguate to
1017 * transition the aux surface into the pass-through state.
1019 * For MCS, (2) is never an issue because we don't support multisampled
1020 * storage images. In theory, issue (1) is a problem with MCS but we've
1021 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1022 * theory, be interpreted as something but we don't know that all bit
1023 * patterns are actually valid. For 2x and 8x, you could easily end up
1024 * with the MCS referring to an invalid plane because not all bits of
1025 * the MCS value are actually used. Even though we've never seen issues
1026 * in the wild, it's best to play it safe and initialize the MCS. We
1027 * can use a fast-clear for MCS because we only ever touch from render
1028 * and texture (no image load store).
1030 if (image
->samples
== 1) {
1031 for (uint32_t l
= 0; l
< level_count
; l
++) {
1032 const uint32_t level
= base_level
+ l
;
1034 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1035 if (base_layer
>= aux_layers
)
1036 break; /* We will only get fewer layers as level increases */
1037 uint32_t level_layer_count
=
1038 MIN2(layer_count
, aux_layers
- base_layer
);
1040 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
1041 base_layer
, level_layer_count
,
1042 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1044 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1045 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1046 level
, base_layer
, level_layer_count
,
1051 if (image
->samples
== 4 || image
->samples
== 16) {
1052 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1053 "Doing a potentially unnecessary fast-clear to "
1054 "define an MCS buffer.");
1057 assert(base_level
== 0 && level_count
== 1);
1058 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
1059 base_layer
, layer_count
,
1060 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1065 const enum isl_aux_usage initial_aux_usage
=
1066 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1067 const enum isl_aux_usage final_aux_usage
=
1068 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1070 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1071 * We can handle transitions between CCS_D/E to and from NONE. What we
1072 * don't yet handle is switching between CCS_E and CCS_D within a given
1073 * image. Doing so in a performant way requires more detailed aux state
1074 * tracking such as what is done in i965. For now, just assume that we
1075 * only have one type of compression.
1077 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1078 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1079 initial_aux_usage
== final_aux_usage
);
1081 /* If initial aux usage is NONE, there is nothing to resolve */
1082 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1085 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1087 /* If the initial layout supports more fast clear than the final layout
1088 * then we need at least a partial resolve.
1090 const enum anv_fast_clear_type initial_fast_clear
=
1091 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1092 const enum anv_fast_clear_type final_fast_clear
=
1093 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1094 if (final_fast_clear
< initial_fast_clear
)
1095 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1097 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1098 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1099 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1101 if (resolve_op
== ISL_AUX_OP_NONE
)
1104 /* Perform a resolve to synchronize data between the main and aux buffer.
1105 * Before we begin, we must satisfy the cache flushing requirement specified
1106 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1108 * Any transition from any value in {Clear, Render, Resolve} to a
1109 * different value in {Clear, Render, Resolve} requires end of pipe
1112 * We perform a flush of the write cache before and after the clear and
1113 * resolve operations to meet this requirement.
1115 * Unlike other drawing, fast clear operations are not properly
1116 * synchronized. The first PIPE_CONTROL here likely ensures that the
1117 * contents of the previous render or clear hit the render target before we
1118 * resolve and the second likely ensures that the resolve is complete before
1119 * we do any more rendering or clearing.
1121 cmd_buffer
->state
.pending_pipe_bits
|=
1122 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1124 for (uint32_t l
= 0; l
< level_count
; l
++) {
1125 uint32_t level
= base_level
+ l
;
1127 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1128 if (base_layer
>= aux_layers
)
1129 break; /* We will only get fewer layers as level increases */
1130 uint32_t level_layer_count
=
1131 MIN2(layer_count
, aux_layers
- base_layer
);
1133 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1134 uint32_t array_layer
= base_layer
+ a
;
1135 if (image
->samples
== 1) {
1136 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
, aspect
,
1137 level
, array_layer
, resolve_op
,
1140 /* We only support fast-clear on the first layer so partial
1141 * resolves should not be used on other layers as they will use
1142 * the clear color stored in memory that is only valid for layer0.
1144 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1148 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
, aspect
,
1149 array_layer
, resolve_op
,
1155 cmd_buffer
->state
.pending_pipe_bits
|=
1156 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1160 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1163 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1164 struct anv_render_pass
*pass
,
1165 const VkRenderPassBeginInfo
*begin
)
1167 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1168 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1170 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1172 if (pass
->attachment_count
> 0) {
1173 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1174 pass
->attachment_count
*
1175 sizeof(state
->attachments
[0]),
1176 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1177 if (state
->attachments
== NULL
) {
1178 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1179 return anv_batch_set_error(&cmd_buffer
->batch
,
1180 VK_ERROR_OUT_OF_HOST_MEMORY
);
1183 state
->attachments
= NULL
;
1186 /* Reserve one for the NULL state. */
1187 unsigned num_states
= 1;
1188 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1189 if (vk_format_is_color(pass
->attachments
[i
].format
))
1192 if (need_input_attachment_state(&pass
->attachments
[i
]))
1196 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1197 state
->render_pass_states
=
1198 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1199 num_states
* ss_stride
, isl_dev
->ss
.align
);
1201 struct anv_state next_state
= state
->render_pass_states
;
1202 next_state
.alloc_size
= isl_dev
->ss
.size
;
1204 state
->null_surface_state
= next_state
;
1205 next_state
.offset
+= ss_stride
;
1206 next_state
.map
+= ss_stride
;
1208 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1209 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1210 state
->attachments
[i
].color
.state
= next_state
;
1211 next_state
.offset
+= ss_stride
;
1212 next_state
.map
+= ss_stride
;
1215 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1216 state
->attachments
[i
].input
.state
= next_state
;
1217 next_state
.offset
+= ss_stride
;
1218 next_state
.map
+= ss_stride
;
1221 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1222 state
->render_pass_states
.alloc_size
);
1225 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1226 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1228 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1229 isl_extent3d(framebuffer
->width
,
1230 framebuffer
->height
,
1231 framebuffer
->layers
));
1233 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1234 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1235 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1236 VkImageAspectFlags clear_aspects
= 0;
1237 VkImageAspectFlags load_aspects
= 0;
1239 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1240 /* color attachment */
1241 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1242 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1243 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1244 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1247 /* depthstencil attachment */
1248 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1249 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1250 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1251 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1252 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1255 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1256 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1257 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1258 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1259 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1264 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1265 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1266 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1268 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1270 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1271 anv_assert(iview
->vk_format
== att
->format
);
1273 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1274 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1276 union isl_color_value clear_color
= { .u32
= { 0, } };
1277 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1278 anv_assert(iview
->n_planes
== 1);
1279 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1280 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1281 state
, i
, begin
->renderArea
,
1284 anv_image_fill_surface_state(cmd_buffer
->device
,
1286 VK_IMAGE_ASPECT_COLOR_BIT
,
1287 &iview
->planes
[0].isl
,
1288 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1289 state
->attachments
[i
].aux_usage
,
1292 &state
->attachments
[i
].color
,
1295 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1297 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1302 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1303 anv_image_fill_surface_state(cmd_buffer
->device
,
1305 VK_IMAGE_ASPECT_COLOR_BIT
,
1306 &iview
->planes
[0].isl
,
1307 ISL_SURF_USAGE_TEXTURE_BIT
,
1308 state
->attachments
[i
].input_aux_usage
,
1311 &state
->attachments
[i
].input
,
1314 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1323 genX(BeginCommandBuffer
)(
1324 VkCommandBuffer commandBuffer
,
1325 const VkCommandBufferBeginInfo
* pBeginInfo
)
1327 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1329 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1330 * command buffer's state. Otherwise, we must *reset* its state. In both
1331 * cases we reset it.
1333 * From the Vulkan 1.0 spec:
1335 * If a command buffer is in the executable state and the command buffer
1336 * was allocated from a command pool with the
1337 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1338 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1339 * as if vkResetCommandBuffer had been called with
1340 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1341 * the command buffer in the recording state.
1343 anv_cmd_buffer_reset(cmd_buffer
);
1345 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1347 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1348 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1350 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1352 /* We sometimes store vertex data in the dynamic state buffer for blorp
1353 * operations and our dynamic state stream may re-use data from previous
1354 * command buffers. In order to prevent stale cache data, we flush the VF
1355 * cache. We could do this on every blorp call but that's not really
1356 * needed as all of the data will get written by the CPU prior to the GPU
1357 * executing anything. The chances are fairly high that they will use
1358 * blorp at least once per primary command buffer so it shouldn't be
1361 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1362 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1364 /* We send an "Indirect State Pointers Disable" packet at
1365 * EndCommandBuffer, so all push contant packets are ignored during a
1366 * context restore. Documentation says after that command, we need to
1367 * emit push constants again before any rendering operation. So we
1368 * flag them dirty here to make sure they get emitted.
1370 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1372 VkResult result
= VK_SUCCESS
;
1373 if (cmd_buffer
->usage_flags
&
1374 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1375 assert(pBeginInfo
->pInheritanceInfo
);
1376 cmd_buffer
->state
.pass
=
1377 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1378 cmd_buffer
->state
.subpass
=
1379 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1381 /* This is optional in the inheritance info. */
1382 cmd_buffer
->state
.framebuffer
=
1383 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1385 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1386 cmd_buffer
->state
.pass
, NULL
);
1388 /* Record that HiZ is enabled if we can. */
1389 if (cmd_buffer
->state
.framebuffer
) {
1390 const struct anv_image_view
* const iview
=
1391 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1394 VkImageLayout layout
=
1395 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1397 enum isl_aux_usage aux_usage
=
1398 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1399 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1401 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1405 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1411 /* From the PRM, Volume 2a:
1413 * "Indirect State Pointers Disable
1415 * At the completion of the post-sync operation associated with this pipe
1416 * control packet, the indirect state pointers in the hardware are
1417 * considered invalid; the indirect pointers are not saved in the context.
1418 * If any new indirect state commands are executed in the command stream
1419 * while the pipe control is pending, the new indirect state commands are
1422 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1423 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1424 * commands are only considered as Indirect State Pointers. Once ISP is
1425 * issued in a context, SW must initialize by programming push constant
1426 * commands for all the shaders (at least to zero length) before attempting
1427 * any rendering operation for the same context."
1429 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1430 * even though they point to a BO that has been already unreferenced at
1431 * the end of the previous batch buffer. This has been fine so far since
1432 * we are protected by these scratch page (every address not covered by
1433 * a BO should be pointing to the scratch page). But on CNL, it is
1434 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1437 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1438 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1439 * context restore, so the mentioned hang doesn't happen. However,
1440 * software must program push constant commands for all stages prior to
1441 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1443 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1444 * constants have been loaded into the EUs prior to disable the push constants
1445 * so that it doesn't hang a previous 3DPRIMITIVE.
1448 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1450 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1451 pc
.StallAtPixelScoreboard
= true;
1452 pc
.CommandStreamerStallEnable
= true;
1454 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1455 pc
.IndirectStatePointersDisable
= true;
1456 pc
.CommandStreamerStallEnable
= true;
1461 genX(EndCommandBuffer
)(
1462 VkCommandBuffer commandBuffer
)
1464 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1466 if (anv_batch_has_error(&cmd_buffer
->batch
))
1467 return cmd_buffer
->batch
.status
;
1469 /* We want every command buffer to start with the PMA fix in a known state,
1470 * so we disable it at the end of the command buffer.
1472 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1474 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1476 emit_isp_disable(cmd_buffer
);
1478 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1484 genX(CmdExecuteCommands
)(
1485 VkCommandBuffer commandBuffer
,
1486 uint32_t commandBufferCount
,
1487 const VkCommandBuffer
* pCmdBuffers
)
1489 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1491 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1493 if (anv_batch_has_error(&primary
->batch
))
1496 /* The secondary command buffers will assume that the PMA fix is disabled
1497 * when they begin executing. Make sure this is true.
1499 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1501 /* The secondary command buffer doesn't know which textures etc. have been
1502 * flushed prior to their execution. Apply those flushes now.
1504 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1506 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1507 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1509 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1510 assert(!anv_batch_has_error(&secondary
->batch
));
1512 if (secondary
->usage_flags
&
1513 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1514 /* If we're continuing a render pass from the primary, we need to
1515 * copy the surface states for the current subpass into the storage
1516 * we allocated for them in BeginCommandBuffer.
1518 struct anv_bo
*ss_bo
=
1519 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1520 struct anv_state src_state
= primary
->state
.render_pass_states
;
1521 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1522 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1524 genX(cmd_buffer_so_memcpy
)(primary
,
1525 (struct anv_address
) {
1527 .offset
= dst_state
.offset
,
1529 (struct anv_address
) {
1531 .offset
= src_state
.offset
,
1533 src_state
.alloc_size
);
1536 anv_cmd_buffer_add_secondary(primary
, secondary
);
1539 /* The secondary may have selected a different pipeline (3D or compute) and
1540 * may have changed the current L3$ configuration. Reset our tracking
1541 * variables to invalid values to ensure that we re-emit these in the case
1542 * where we do any draws or compute dispatches from the primary after the
1543 * secondary has returned.
1545 primary
->state
.current_pipeline
= UINT32_MAX
;
1546 primary
->state
.current_l3_config
= NULL
;
1548 /* Each of the secondary command buffers will use its own state base
1549 * address. We need to re-emit state base address for the primary after
1550 * all of the secondaries are done.
1552 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1555 genX(cmd_buffer_emit_state_base_address
)(primary
);
1558 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1559 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1560 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1563 * Program the hardware to use the specified L3 configuration.
1566 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1567 const struct gen_l3_config
*cfg
)
1570 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1573 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1574 intel_logd("L3 config transition: ");
1575 gen_dump_l3_config(cfg
, stderr
);
1578 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1580 /* According to the hardware docs, the L3 partitioning can only be changed
1581 * while the pipeline is completely drained and the caches are flushed,
1582 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1584 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1585 pc
.DCFlushEnable
= true;
1586 pc
.PostSyncOperation
= NoWrite
;
1587 pc
.CommandStreamerStallEnable
= true;
1590 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1591 * invalidation of the relevant caches. Note that because RO invalidation
1592 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1593 * command is processed by the CS) we cannot combine it with the previous
1594 * stalling flush as the hardware documentation suggests, because that
1595 * would cause the CS to stall on previous rendering *after* RO
1596 * invalidation and wouldn't prevent the RO caches from being polluted by
1597 * concurrent rendering before the stall completes. This intentionally
1598 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1599 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1600 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1601 * already guarantee that there is no concurrent GPGPU kernel execution
1602 * (see SKL HSD 2132585).
1604 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1605 pc
.TextureCacheInvalidationEnable
= true;
1606 pc
.ConstantCacheInvalidationEnable
= true;
1607 pc
.InstructionCacheInvalidateEnable
= true;
1608 pc
.StateCacheInvalidationEnable
= true;
1609 pc
.PostSyncOperation
= NoWrite
;
1612 /* Now send a third stalling flush to make sure that invalidation is
1613 * complete when the L3 configuration registers are modified.
1615 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1616 pc
.DCFlushEnable
= true;
1617 pc
.PostSyncOperation
= NoWrite
;
1618 pc
.CommandStreamerStallEnable
= true;
1623 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1626 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1627 .SLMEnable
= has_slm
,
1629 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1630 * in L3CNTLREG register. The default setting of the bit is not the
1631 * desirable behavior.
1633 .ErrorDetectionBehaviorControl
= true,
1634 .UseFullWays
= true,
1636 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1637 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1638 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1639 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1641 /* Set up the L3 partitioning. */
1642 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1646 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1647 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1648 cfg
->n
[GEN_L3P_ALL
];
1649 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1650 cfg
->n
[GEN_L3P_ALL
];
1651 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1652 cfg
->n
[GEN_L3P_ALL
];
1654 assert(!cfg
->n
[GEN_L3P_ALL
]);
1656 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1657 * the matching space on the remaining banks has to be allocated to a
1658 * client (URB for all validated configurations) set to the
1659 * lower-bandwidth 2-bank address hashing mode.
1661 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1662 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1663 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1665 /* Minimum number of ways that can be allocated to the URB. */
1666 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1667 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1669 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1670 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1671 .ConvertDC_UC
= !has_dc
,
1672 .ConvertIS_UC
= !has_is
,
1673 .ConvertC_UC
= !has_c
,
1674 .ConvertT_UC
= !has_t
);
1676 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1677 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1678 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1680 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1681 .SLMEnable
= has_slm
,
1682 .URBLowBandwidth
= urb_low_bw
,
1683 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1685 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1687 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1688 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1690 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1691 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1692 .ISLowBandwidth
= 0,
1693 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1695 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1696 .TLowBandwidth
= 0);
1698 /* Set up the L3 partitioning. */
1699 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1700 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1701 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1704 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1705 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1706 * them disabled to avoid crashing the system hard.
1708 uint32_t scratch1
, chicken3
;
1709 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1710 .L3AtomicDisable
= !has_dc
);
1711 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1712 .L3AtomicDisableMask
= true,
1713 .L3AtomicDisable
= !has_dc
);
1714 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1715 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1721 cmd_buffer
->state
.current_l3_config
= cfg
;
1725 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1727 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1729 /* Flushes are pipelined while invalidations are handled immediately.
1730 * Therefore, if we're flushing anything then we need to schedule a stall
1731 * before any invalidations can happen.
1733 if (bits
& ANV_PIPE_FLUSH_BITS
)
1734 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1736 /* If we're going to do an invalidate and we have a pending CS stall that
1737 * has yet to be resolved, we do the CS stall now.
1739 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1740 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1741 bits
|= ANV_PIPE_CS_STALL_BIT
;
1742 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1745 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1746 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1747 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1748 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1749 pipe
.RenderTargetCacheFlushEnable
=
1750 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1752 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1753 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1754 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1757 * According to the Broadwell documentation, any PIPE_CONTROL with the
1758 * "Command Streamer Stall" bit set must also have another bit set,
1759 * with five different options:
1761 * - Render Target Cache Flush
1762 * - Depth Cache Flush
1763 * - Stall at Pixel Scoreboard
1764 * - Post-Sync Operation
1768 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1769 * mesa and it seems to work fine. The choice is fairly arbitrary.
1771 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1772 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1773 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1774 pipe
.StallAtPixelScoreboard
= true;
1777 /* If a render target flush was emitted, then we can toggle off the bit
1778 * saying that render target writes are ongoing.
1780 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1781 bits
&= ~(ANV_PIPE_RENDER_TARGET_WRITES
);
1783 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1786 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1787 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1789 * "If the VF Cache Invalidation Enable is set to a 1 in a
1790 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1791 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1792 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1795 * This appears to hang Broadwell, so we restrict it to just gen9.
1797 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1798 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1800 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1801 pipe
.StateCacheInvalidationEnable
=
1802 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1803 pipe
.ConstantCacheInvalidationEnable
=
1804 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1805 pipe
.VFCacheInvalidationEnable
=
1806 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1807 pipe
.TextureCacheInvalidationEnable
=
1808 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1809 pipe
.InstructionCacheInvalidateEnable
=
1810 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1812 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1814 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1815 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1816 * “Write Timestamp”.
1818 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1819 pipe
.PostSyncOperation
= WriteImmediateData
;
1821 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1825 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1828 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1831 void genX(CmdPipelineBarrier
)(
1832 VkCommandBuffer commandBuffer
,
1833 VkPipelineStageFlags srcStageMask
,
1834 VkPipelineStageFlags destStageMask
,
1836 uint32_t memoryBarrierCount
,
1837 const VkMemoryBarrier
* pMemoryBarriers
,
1838 uint32_t bufferMemoryBarrierCount
,
1839 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1840 uint32_t imageMemoryBarrierCount
,
1841 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1843 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1845 /* XXX: Right now, we're really dumb and just flush whatever categories
1846 * the app asks for. One of these days we may make this a bit better
1847 * but right now that's all the hardware allows for in most areas.
1849 VkAccessFlags src_flags
= 0;
1850 VkAccessFlags dst_flags
= 0;
1852 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1853 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1854 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1857 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1858 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1859 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1862 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1863 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1864 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1865 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1866 const VkImageSubresourceRange
*range
=
1867 &pImageMemoryBarriers
[i
].subresourceRange
;
1869 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1870 transition_depth_buffer(cmd_buffer
, image
,
1871 pImageMemoryBarriers
[i
].oldLayout
,
1872 pImageMemoryBarriers
[i
].newLayout
);
1873 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1874 VkImageAspectFlags color_aspects
=
1875 anv_image_expand_aspects(image
, range
->aspectMask
);
1876 uint32_t aspect_bit
;
1878 uint32_t base_layer
, layer_count
;
1879 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1881 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1883 base_layer
= range
->baseArrayLayer
;
1884 layer_count
= anv_get_layerCount(image
, range
);
1887 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1888 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1889 range
->baseMipLevel
,
1890 anv_get_levelCount(image
, range
),
1891 base_layer
, layer_count
,
1892 pImageMemoryBarriers
[i
].oldLayout
,
1893 pImageMemoryBarriers
[i
].newLayout
);
1898 cmd_buffer
->state
.pending_pipe_bits
|=
1899 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1900 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1904 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1906 VkShaderStageFlags stages
=
1907 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1909 /* In order to avoid thrash, we assume that vertex and fragment stages
1910 * always exist. In the rare case where one is missing *and* the other
1911 * uses push concstants, this may be suboptimal. However, avoiding stalls
1912 * seems more important.
1914 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1916 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1920 const unsigned push_constant_kb
= 32;
1921 #elif GEN_IS_HASWELL
1922 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1924 const unsigned push_constant_kb
= 16;
1927 const unsigned num_stages
=
1928 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1929 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1931 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1932 * units of 2KB. Incidentally, these are the same platforms that have
1933 * 32KB worth of push constant space.
1935 if (push_constant_kb
== 32)
1936 size_per_stage
&= ~1u;
1938 uint32_t kb_used
= 0;
1939 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1940 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1941 anv_batch_emit(&cmd_buffer
->batch
,
1942 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1943 alloc
._3DCommandSubOpcode
= 18 + i
;
1944 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1945 alloc
.ConstantBufferSize
= push_size
;
1947 kb_used
+= push_size
;
1950 anv_batch_emit(&cmd_buffer
->batch
,
1951 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1952 alloc
.ConstantBufferOffset
= kb_used
;
1953 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1956 cmd_buffer
->state
.push_constant_stages
= stages
;
1958 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1960 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1961 * the next 3DPRIMITIVE command after programming the
1962 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1964 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1965 * pipeline setup, we need to dirty push constants.
1967 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1970 static const struct anv_descriptor
*
1971 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1972 const struct anv_pipeline_binding
*binding
)
1974 assert(binding
->set
< MAX_SETS
);
1975 const struct anv_descriptor_set
*set
=
1976 pipe_state
->descriptors
[binding
->set
];
1977 const uint32_t offset
=
1978 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1979 return &set
->descriptors
[offset
+ binding
->index
];
1983 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1984 const struct anv_pipeline_binding
*binding
)
1986 assert(binding
->set
< MAX_SETS
);
1987 const struct anv_descriptor_set
*set
=
1988 pipe_state
->descriptors
[binding
->set
];
1990 uint32_t dynamic_offset_idx
=
1991 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1992 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1995 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1999 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2000 gl_shader_stage stage
,
2001 struct anv_state
*bt_state
)
2003 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2004 struct anv_cmd_pipeline_state
*pipe_state
;
2005 struct anv_pipeline
*pipeline
;
2006 uint32_t bias
, state_offset
;
2009 case MESA_SHADER_COMPUTE
:
2010 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2014 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2018 pipeline
= pipe_state
->pipeline
;
2020 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2021 *bt_state
= (struct anv_state
) { 0, };
2025 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2026 if (bias
+ map
->surface_count
== 0) {
2027 *bt_state
= (struct anv_state
) { 0, };
2031 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2032 bias
+ map
->surface_count
,
2034 uint32_t *bt_map
= bt_state
->map
;
2036 if (bt_state
->map
== NULL
)
2037 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2039 if (stage
== MESA_SHADER_COMPUTE
&&
2040 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
2041 struct anv_state surface_state
;
2043 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2045 const enum isl_format format
=
2046 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2047 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2049 cmd_buffer
->state
.compute
.num_workgroups
,
2052 bt_map
[0] = surface_state
.offset
+ state_offset
;
2053 add_surface_reloc(cmd_buffer
, surface_state
,
2054 cmd_buffer
->state
.compute
.num_workgroups
);
2057 if (map
->surface_count
== 0)
2060 if (map
->image_count
> 0) {
2062 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
2063 if (result
!= VK_SUCCESS
)
2066 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2070 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2071 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2073 struct anv_state surface_state
;
2075 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2076 /* Color attachment binding */
2077 assert(stage
== MESA_SHADER_FRAGMENT
);
2078 assert(binding
->binding
== 0);
2079 if (binding
->index
< subpass
->color_count
) {
2080 const unsigned att
=
2081 subpass
->color_attachments
[binding
->index
].attachment
;
2083 /* From the Vulkan 1.0.46 spec:
2085 * "If any color or depth/stencil attachments are
2086 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2089 if (att
== VK_ATTACHMENT_UNUSED
) {
2090 surface_state
= cmd_buffer
->state
.null_surface_state
;
2092 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2095 surface_state
= cmd_buffer
->state
.null_surface_state
;
2098 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2100 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2101 struct anv_state surface_state
=
2102 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2104 struct anv_address constant_data
= {
2105 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2106 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2108 unsigned constant_data_size
=
2109 pipeline
->shaders
[stage
]->constant_data_size
;
2111 const enum isl_format format
=
2112 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2113 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2114 surface_state
, format
,
2115 constant_data
, constant_data_size
, 1);
2117 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2118 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2122 const struct anv_descriptor
*desc
=
2123 anv_descriptor_for_binding(pipe_state
, binding
);
2125 switch (desc
->type
) {
2126 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2127 /* Nothing for us to do here */
2130 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2131 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2132 struct anv_surface_state sstate
=
2133 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2134 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2135 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2136 surface_state
= sstate
.state
;
2137 assert(surface_state
.alloc_size
);
2138 add_surface_state_relocs(cmd_buffer
, sstate
);
2141 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2142 assert(stage
== MESA_SHADER_FRAGMENT
);
2143 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2144 /* For depth and stencil input attachments, we treat it like any
2145 * old texture that a user may have bound.
2147 struct anv_surface_state sstate
=
2148 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2149 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2150 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2151 surface_state
= sstate
.state
;
2152 assert(surface_state
.alloc_size
);
2153 add_surface_state_relocs(cmd_buffer
, sstate
);
2155 /* For color input attachments, we create the surface state at
2156 * vkBeginRenderPass time so that we can include aux and clear
2157 * color information.
2159 assert(binding
->input_attachment_index
< subpass
->input_count
);
2160 const unsigned subpass_att
= binding
->input_attachment_index
;
2161 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2162 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2166 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2167 struct anv_surface_state sstate
= (binding
->write_only
)
2168 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2169 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2170 surface_state
= sstate
.state
;
2171 assert(surface_state
.alloc_size
);
2172 add_surface_state_relocs(cmd_buffer
, sstate
);
2174 struct brw_image_param
*image_param
=
2175 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2177 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2181 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2182 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2183 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2184 surface_state
= desc
->buffer_view
->surface_state
;
2185 assert(surface_state
.alloc_size
);
2186 add_surface_reloc(cmd_buffer
, surface_state
,
2187 desc
->buffer_view
->address
);
2190 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2191 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2192 /* Compute the offset within the buffer */
2193 uint32_t dynamic_offset
=
2194 dynamic_offset_for_binding(pipe_state
, binding
);
2195 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2196 /* Clamp to the buffer size */
2197 offset
= MIN2(offset
, desc
->buffer
->size
);
2198 /* Clamp the range to the buffer size */
2199 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2201 struct anv_address address
=
2202 anv_address_add(desc
->buffer
->address
, offset
);
2205 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2206 enum isl_format format
=
2207 anv_isl_format_for_descriptor_type(desc
->type
);
2209 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2210 format
, address
, range
, 1);
2211 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2215 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2216 surface_state
= (binding
->write_only
)
2217 ? desc
->buffer_view
->writeonly_storage_surface_state
2218 : desc
->buffer_view
->storage_surface_state
;
2219 assert(surface_state
.alloc_size
);
2220 add_surface_reloc(cmd_buffer
, surface_state
,
2221 desc
->buffer_view
->address
);
2223 struct brw_image_param
*image_param
=
2224 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2226 *image_param
= desc
->buffer_view
->storage_image_param
;
2230 assert(!"Invalid descriptor type");
2234 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2236 assert(image
== map
->image_count
);
2239 anv_state_flush(cmd_buffer
->device
, *bt_state
);
2242 /* The PIPE_CONTROL command description says:
2244 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2245 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2246 * Target Cache Flush by enabling this bit. When render target flush
2247 * is set due to new association of BTI, PS Scoreboard Stall bit must
2248 * be set in this packet."
2250 * FINISHME: Currently we shuffle around the surface states in the binding
2251 * table based on if they are getting used or not. So, we've to do below
2252 * pipe control flush for every binding table upload. Make changes so
2253 * that we do it only when we modify render target surface states.
2255 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2256 pc
.RenderTargetCacheFlushEnable
= true;
2257 pc
.StallAtPixelScoreboard
= true;
2265 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2266 gl_shader_stage stage
,
2267 struct anv_state
*state
)
2269 struct anv_cmd_pipeline_state
*pipe_state
=
2270 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2271 &cmd_buffer
->state
.gfx
.base
;
2272 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2274 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2275 *state
= (struct anv_state
) { 0, };
2279 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2280 if (map
->sampler_count
== 0) {
2281 *state
= (struct anv_state
) { 0, };
2285 uint32_t size
= map
->sampler_count
* 16;
2286 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2288 if (state
->map
== NULL
)
2289 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2291 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2292 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2293 const struct anv_descriptor
*desc
=
2294 anv_descriptor_for_binding(pipe_state
, binding
);
2296 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2297 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2300 struct anv_sampler
*sampler
= desc
->sampler
;
2302 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2303 * happens to be zero.
2305 if (sampler
== NULL
)
2308 memcpy(state
->map
+ (s
* 16),
2309 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2312 anv_state_flush(cmd_buffer
->device
, *state
);
2318 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2320 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2322 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2323 pipeline
->active_stages
;
2325 VkResult result
= VK_SUCCESS
;
2326 anv_foreach_stage(s
, dirty
) {
2327 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2328 if (result
!= VK_SUCCESS
)
2330 result
= emit_binding_table(cmd_buffer
, s
,
2331 &cmd_buffer
->state
.binding_tables
[s
]);
2332 if (result
!= VK_SUCCESS
)
2336 if (result
!= VK_SUCCESS
) {
2337 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2339 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2340 if (result
!= VK_SUCCESS
)
2343 /* Re-emit state base addresses so we get the new surface state base
2344 * address before we start emitting binding tables etc.
2346 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2348 /* Re-emit all active binding tables */
2349 dirty
|= pipeline
->active_stages
;
2350 anv_foreach_stage(s
, dirty
) {
2351 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2352 if (result
!= VK_SUCCESS
) {
2353 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2356 result
= emit_binding_table(cmd_buffer
, s
,
2357 &cmd_buffer
->state
.binding_tables
[s
]);
2358 if (result
!= VK_SUCCESS
) {
2359 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2365 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2371 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2374 static const uint32_t sampler_state_opcodes
[] = {
2375 [MESA_SHADER_VERTEX
] = 43,
2376 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2377 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2378 [MESA_SHADER_GEOMETRY
] = 46,
2379 [MESA_SHADER_FRAGMENT
] = 47,
2380 [MESA_SHADER_COMPUTE
] = 0,
2383 static const uint32_t binding_table_opcodes
[] = {
2384 [MESA_SHADER_VERTEX
] = 38,
2385 [MESA_SHADER_TESS_CTRL
] = 39,
2386 [MESA_SHADER_TESS_EVAL
] = 40,
2387 [MESA_SHADER_GEOMETRY
] = 41,
2388 [MESA_SHADER_FRAGMENT
] = 42,
2389 [MESA_SHADER_COMPUTE
] = 0,
2392 anv_foreach_stage(s
, stages
) {
2393 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2394 assert(binding_table_opcodes
[s
] > 0);
2396 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2397 anv_batch_emit(&cmd_buffer
->batch
,
2398 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2399 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2400 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2404 /* Always emit binding table pointers if we're asked to, since on SKL
2405 * this is what flushes push constants. */
2406 anv_batch_emit(&cmd_buffer
->batch
,
2407 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2408 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2409 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2415 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2416 VkShaderStageFlags dirty_stages
)
2418 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2419 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2421 static const uint32_t push_constant_opcodes
[] = {
2422 [MESA_SHADER_VERTEX
] = 21,
2423 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2424 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2425 [MESA_SHADER_GEOMETRY
] = 22,
2426 [MESA_SHADER_FRAGMENT
] = 23,
2427 [MESA_SHADER_COMPUTE
] = 0,
2430 VkShaderStageFlags flushed
= 0;
2432 anv_foreach_stage(stage
, dirty_stages
) {
2433 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2434 assert(push_constant_opcodes
[stage
] > 0);
2436 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2437 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2439 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2440 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2441 const struct brw_stage_prog_data
*prog_data
=
2442 pipeline
->shaders
[stage
]->prog_data
;
2443 const struct anv_pipeline_bind_map
*bind_map
=
2444 &pipeline
->shaders
[stage
]->bind_map
;
2446 /* The Skylake PRM contains the following restriction:
2448 * "The driver must ensure The following case does not occur
2449 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2450 * buffer 3 read length equal to zero committed followed by a
2451 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2454 * To avoid this, we program the buffers in the highest slots.
2455 * This way, slot 0 is only used if slot 3 is also used.
2459 for (int i
= 3; i
>= 0; i
--) {
2460 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2461 if (range
->length
== 0)
2464 const unsigned surface
=
2465 prog_data
->binding_table
.ubo_start
+ range
->block
;
2467 assert(surface
<= bind_map
->surface_count
);
2468 const struct anv_pipeline_binding
*binding
=
2469 &bind_map
->surface_to_descriptor
[surface
];
2471 struct anv_address read_addr
;
2473 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2474 struct anv_address constant_data
= {
2475 .bo
= &pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2476 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2478 unsigned constant_data_size
=
2479 pipeline
->shaders
[stage
]->constant_data_size
;
2481 read_len
= MIN2(range
->length
,
2482 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2483 read_addr
= anv_address_add(constant_data
,
2486 const struct anv_descriptor
*desc
=
2487 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2489 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2490 read_len
= MIN2(range
->length
,
2491 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2492 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2495 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2497 uint32_t dynamic_offset
=
2498 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2499 uint32_t buf_offset
=
2500 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2501 uint32_t buf_range
=
2502 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2504 read_len
= MIN2(range
->length
,
2505 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2506 read_addr
= anv_address_add(desc
->buffer
->address
,
2507 buf_offset
+ range
->start
* 32);
2512 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2513 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2518 struct anv_state state
=
2519 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2521 if (state
.alloc_size
> 0) {
2522 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2523 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2524 .offset
= state
.offset
,
2526 c
.ConstantBody
.ReadLength
[n
] =
2527 DIV_ROUND_UP(state
.alloc_size
, 32);
2530 /* For Ivy Bridge, the push constants packets have a different
2531 * rule that would require us to iterate in the other direction
2532 * and possibly mess around with dynamic state base address.
2533 * Don't bother; just emit regular push constants at n = 0.
2535 struct anv_state state
=
2536 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2538 if (state
.alloc_size
> 0) {
2539 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2540 c
.ConstantBody
.ReadLength
[0] =
2541 DIV_ROUND_UP(state
.alloc_size
, 32);
2547 flushed
|= mesa_to_vk_shader_stage(stage
);
2550 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2554 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2556 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2559 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2560 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2561 vb_emit
|= pipeline
->vb_used
;
2563 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2565 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2567 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2570 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2571 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2573 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2574 GENX(3DSTATE_VERTEX_BUFFERS
));
2576 for_each_bit(vb
, vb_emit
) {
2577 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2578 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2580 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2581 .VertexBufferIndex
= vb
,
2583 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2585 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2586 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2589 .AddressModifyEnable
= true,
2590 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2591 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2594 .BufferSize
= buffer
->size
- offset
2596 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2600 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2605 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2607 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2608 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2610 /* The exact descriptor layout is pulled from the pipeline, so we need
2611 * to re-emit binding tables on every pipeline change.
2613 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2615 /* If the pipeline changed, we may need to re-allocate push constant
2618 cmd_buffer_alloc_push_constants(cmd_buffer
);
2622 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2623 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2624 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2626 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2627 * stall needs to be sent just prior to any 3DSTATE_VS,
2628 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2629 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2630 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2631 * PIPE_CONTROL needs to be sent before any combination of VS
2632 * associated 3DSTATE."
2634 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2635 pc
.DepthStallEnable
= true;
2636 pc
.PostSyncOperation
= WriteImmediateData
;
2638 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2643 /* Render targets live in the same binding table as fragment descriptors */
2644 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2645 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2647 /* We emit the binding tables and sampler tables first, then emit push
2648 * constants and then finally emit binding table and sampler table
2649 * pointers. It has to happen in this order, since emitting the binding
2650 * tables may change the push constants (in case of storage images). After
2651 * emitting push constants, on SKL+ we have to emit the corresponding
2652 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2655 if (cmd_buffer
->state
.descriptors_dirty
)
2656 dirty
= flush_descriptor_sets(cmd_buffer
);
2658 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2659 /* Because we're pushing UBOs, we have to push whenever either
2660 * descriptors or push constants is dirty.
2662 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2663 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2664 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2668 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2670 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2671 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2673 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2674 ANV_CMD_DIRTY_PIPELINE
)) {
2675 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2676 pipeline
->depth_clamp_enable
);
2679 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2680 ANV_CMD_DIRTY_RENDER_TARGETS
))
2681 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2683 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2685 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2689 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2690 struct anv_address addr
,
2691 uint32_t size
, uint32_t index
)
2693 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2694 GENX(3DSTATE_VERTEX_BUFFERS
));
2696 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2697 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2698 .VertexBufferIndex
= index
,
2699 .AddressModifyEnable
= true,
2701 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2703 .BufferStartingAddress
= addr
,
2706 .BufferStartingAddress
= addr
,
2707 .EndAddress
= anv_address_add(addr
, size
),
2713 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2714 struct anv_address addr
)
2716 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2720 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2721 uint32_t base_vertex
, uint32_t base_instance
)
2723 struct anv_state id_state
=
2724 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2726 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2727 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2729 anv_state_flush(cmd_buffer
->device
, id_state
);
2731 struct anv_address addr
= {
2732 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2733 .offset
= id_state
.offset
,
2736 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2740 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2742 struct anv_state state
=
2743 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2745 ((uint32_t *)state
.map
)[0] = draw_index
;
2747 anv_state_flush(cmd_buffer
->device
, state
);
2749 struct anv_address addr
= {
2750 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2751 .offset
= state
.offset
,
2754 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2758 VkCommandBuffer commandBuffer
,
2759 uint32_t vertexCount
,
2760 uint32_t instanceCount
,
2761 uint32_t firstVertex
,
2762 uint32_t firstInstance
)
2764 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2765 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2766 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2768 if (anv_batch_has_error(&cmd_buffer
->batch
))
2771 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2773 if (vs_prog_data
->uses_firstvertex
||
2774 vs_prog_data
->uses_baseinstance
)
2775 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2776 if (vs_prog_data
->uses_drawid
)
2777 emit_draw_index(cmd_buffer
, 0);
2779 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2780 * different views. We need to multiply instanceCount by the view count.
2782 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2784 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2785 prim
.VertexAccessType
= SEQUENTIAL
;
2786 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2787 prim
.VertexCountPerInstance
= vertexCount
;
2788 prim
.StartVertexLocation
= firstVertex
;
2789 prim
.InstanceCount
= instanceCount
;
2790 prim
.StartInstanceLocation
= firstInstance
;
2791 prim
.BaseVertexLocation
= 0;
2794 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_WRITES
;
2797 void genX(CmdDrawIndexed
)(
2798 VkCommandBuffer commandBuffer
,
2799 uint32_t indexCount
,
2800 uint32_t instanceCount
,
2801 uint32_t firstIndex
,
2802 int32_t vertexOffset
,
2803 uint32_t firstInstance
)
2805 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2806 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2807 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2809 if (anv_batch_has_error(&cmd_buffer
->batch
))
2812 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2814 if (vs_prog_data
->uses_firstvertex
||
2815 vs_prog_data
->uses_baseinstance
)
2816 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2817 if (vs_prog_data
->uses_drawid
)
2818 emit_draw_index(cmd_buffer
, 0);
2820 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2821 * different views. We need to multiply instanceCount by the view count.
2823 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2825 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2826 prim
.VertexAccessType
= RANDOM
;
2827 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2828 prim
.VertexCountPerInstance
= indexCount
;
2829 prim
.StartVertexLocation
= firstIndex
;
2830 prim
.InstanceCount
= instanceCount
;
2831 prim
.StartInstanceLocation
= firstInstance
;
2832 prim
.BaseVertexLocation
= vertexOffset
;
2835 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_WRITES
;
2838 /* Auto-Draw / Indirect Registers */
2839 #define GEN7_3DPRIM_END_OFFSET 0x2420
2840 #define GEN7_3DPRIM_START_VERTEX 0x2430
2841 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2842 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2843 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2844 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2846 /* MI_MATH only exists on Haswell+ */
2847 #if GEN_IS_HASWELL || GEN_GEN >= 8
2849 /* Emit dwords to multiply GPR0 by N */
2851 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2853 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2855 #define append_alu(opcode, operand1, operand2) \
2856 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2859 unsigned top_bit
= 31 - __builtin_clz(N
);
2860 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2861 /* We get our initial data in GPR0 and we write the final data out to
2862 * GPR0 but we use GPR1 as our scratch register.
2864 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2865 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2867 /* Shift the current value left by 1 */
2868 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2869 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2870 append_alu(MI_ALU_ADD
, 0, 0);
2873 /* Store ACCU to R1 and add R0 to R1 */
2874 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2875 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2876 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2877 append_alu(MI_ALU_ADD
, 0, 0);
2880 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2887 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2889 uint32_t num_dwords
;
2890 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2892 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2893 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2896 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2899 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2900 struct anv_address addr
,
2903 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2905 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, anv_address_add(addr
, 0));
2907 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2908 if (view_count
> 1) {
2909 #if GEN_IS_HASWELL || GEN_GEN >= 8
2910 emit_lrm(batch
, CS_GPR(0), anv_address_add(addr
, 4));
2911 emit_mul_gpr0(batch
, view_count
);
2912 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2914 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2915 "MI_MATH is not supported on Ivy Bridge");
2916 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
2919 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, anv_address_add(addr
, 4));
2922 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, anv_address_add(addr
, 8));
2925 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, anv_address_add(addr
, 12));
2926 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 16));
2928 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, anv_address_add(addr
, 12));
2929 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2933 void genX(CmdDrawIndirect
)(
2934 VkCommandBuffer commandBuffer
,
2936 VkDeviceSize offset
,
2940 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2941 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2942 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2943 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2945 if (anv_batch_has_error(&cmd_buffer
->batch
))
2948 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2950 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2951 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2953 if (vs_prog_data
->uses_firstvertex
||
2954 vs_prog_data
->uses_baseinstance
)
2955 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
2956 if (vs_prog_data
->uses_drawid
)
2957 emit_draw_index(cmd_buffer
, i
);
2959 load_indirect_parameters(cmd_buffer
, draw
, false);
2961 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2962 prim
.IndirectParameterEnable
= true;
2963 prim
.VertexAccessType
= SEQUENTIAL
;
2964 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2970 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_WRITES
;
2973 void genX(CmdDrawIndexedIndirect
)(
2974 VkCommandBuffer commandBuffer
,
2976 VkDeviceSize offset
,
2980 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2981 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2982 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2983 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2985 if (anv_batch_has_error(&cmd_buffer
->batch
))
2988 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2990 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2991 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2993 /* TODO: We need to stomp base vertex to 0 somehow */
2994 if (vs_prog_data
->uses_firstvertex
||
2995 vs_prog_data
->uses_baseinstance
)
2996 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
2997 if (vs_prog_data
->uses_drawid
)
2998 emit_draw_index(cmd_buffer
, i
);
3000 load_indirect_parameters(cmd_buffer
, draw
, true);
3002 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3003 prim
.IndirectParameterEnable
= true;
3004 prim
.VertexAccessType
= RANDOM
;
3005 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3011 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_WRITES
;
3015 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3017 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3018 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3021 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3022 if (result
!= VK_SUCCESS
) {
3023 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3025 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3026 if (result
!= VK_SUCCESS
)
3029 /* Re-emit state base addresses so we get the new surface state base
3030 * address before we start emitting binding tables etc.
3032 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3034 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3035 if (result
!= VK_SUCCESS
) {
3036 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3041 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3042 if (result
!= VK_SUCCESS
) {
3043 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3047 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3048 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3049 .BindingTablePointer
= surfaces
.offset
,
3050 .SamplerStatePointer
= samplers
.offset
,
3052 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3054 struct anv_state state
=
3055 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3056 pipeline
->interface_descriptor_data
,
3057 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3060 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3061 anv_batch_emit(&cmd_buffer
->batch
,
3062 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3063 mid
.InterfaceDescriptorTotalLength
= size
;
3064 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3071 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3073 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3074 MAYBE_UNUSED VkResult result
;
3076 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3078 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3080 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3082 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3083 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3085 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3086 * the only bits that are changed are scoreboard related: Scoreboard
3087 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3088 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3091 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3092 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3094 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3097 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3098 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3099 /* FIXME: figure out descriptors for gen7 */
3100 result
= flush_compute_descriptor_set(cmd_buffer
);
3101 if (result
!= VK_SUCCESS
)
3104 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3107 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3108 struct anv_state push_state
=
3109 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3111 if (push_state
.alloc_size
) {
3112 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3113 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3114 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3118 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3121 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3123 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3129 verify_cmd_parser(const struct anv_device
*device
,
3130 int required_version
,
3131 const char *function
)
3133 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3134 return vk_errorf(device
->instance
, device
->instance
,
3135 VK_ERROR_FEATURE_NOT_PRESENT
,
3136 "cmd parser version %d is required for %s",
3137 required_version
, function
);
3146 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3147 uint32_t baseGroupX
,
3148 uint32_t baseGroupY
,
3149 uint32_t baseGroupZ
)
3151 if (anv_batch_has_error(&cmd_buffer
->batch
))
3155 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3156 base_work_group_id
);
3157 if (result
!= VK_SUCCESS
) {
3158 cmd_buffer
->batch
.status
= result
;
3162 struct anv_push_constants
*push
=
3163 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3164 if (push
->base_work_group_id
[0] != baseGroupX
||
3165 push
->base_work_group_id
[1] != baseGroupY
||
3166 push
->base_work_group_id
[2] != baseGroupZ
) {
3167 push
->base_work_group_id
[0] = baseGroupX
;
3168 push
->base_work_group_id
[1] = baseGroupY
;
3169 push
->base_work_group_id
[2] = baseGroupZ
;
3171 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3175 void genX(CmdDispatch
)(
3176 VkCommandBuffer commandBuffer
,
3181 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3184 void genX(CmdDispatchBase
)(
3185 VkCommandBuffer commandBuffer
,
3186 uint32_t baseGroupX
,
3187 uint32_t baseGroupY
,
3188 uint32_t baseGroupZ
,
3189 uint32_t groupCountX
,
3190 uint32_t groupCountY
,
3191 uint32_t groupCountZ
)
3193 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3194 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3195 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3197 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3198 baseGroupY
, baseGroupZ
);
3200 if (anv_batch_has_error(&cmd_buffer
->batch
))
3203 if (prog_data
->uses_num_work_groups
) {
3204 struct anv_state state
=
3205 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3206 uint32_t *sizes
= state
.map
;
3207 sizes
[0] = groupCountX
;
3208 sizes
[1] = groupCountY
;
3209 sizes
[2] = groupCountZ
;
3210 anv_state_flush(cmd_buffer
->device
, state
);
3211 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3212 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3213 .offset
= state
.offset
,
3217 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3219 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3220 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3221 ggw
.ThreadDepthCounterMaximum
= 0;
3222 ggw
.ThreadHeightCounterMaximum
= 0;
3223 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3224 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3225 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3226 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3227 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3228 ggw
.BottomExecutionMask
= 0xffffffff;
3231 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3234 #define GPGPU_DISPATCHDIMX 0x2500
3235 #define GPGPU_DISPATCHDIMY 0x2504
3236 #define GPGPU_DISPATCHDIMZ 0x2508
3238 void genX(CmdDispatchIndirect
)(
3239 VkCommandBuffer commandBuffer
,
3241 VkDeviceSize offset
)
3243 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3244 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3245 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3246 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3247 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3248 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3250 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3253 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3254 * indirect dispatch registers to be written.
3256 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3257 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3261 if (prog_data
->uses_num_work_groups
)
3262 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3264 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3266 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, anv_address_add(addr
, 0));
3267 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, anv_address_add(addr
, 4));
3268 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, anv_address_add(addr
, 8));
3271 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3272 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3273 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3274 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3276 /* Load compute_dispatch_indirect_x_size into SRC0 */
3277 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 0));
3279 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3280 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3281 mip
.LoadOperation
= LOAD_LOAD
;
3282 mip
.CombineOperation
= COMBINE_SET
;
3283 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3286 /* Load compute_dispatch_indirect_y_size into SRC0 */
3287 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 4));
3289 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3290 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3291 mip
.LoadOperation
= LOAD_LOAD
;
3292 mip
.CombineOperation
= COMBINE_OR
;
3293 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3296 /* Load compute_dispatch_indirect_z_size into SRC0 */
3297 emit_lrm(batch
, MI_PREDICATE_SRC0
, anv_address_add(addr
, 8));
3299 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3300 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3301 mip
.LoadOperation
= LOAD_LOAD
;
3302 mip
.CombineOperation
= COMBINE_OR
;
3303 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3306 /* predicate = !predicate; */
3307 #define COMPARE_FALSE 1
3308 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3309 mip
.LoadOperation
= LOAD_LOADINV
;
3310 mip
.CombineOperation
= COMBINE_OR
;
3311 mip
.CompareOperation
= COMPARE_FALSE
;
3315 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3316 ggw
.IndirectParameterEnable
= true;
3317 ggw
.PredicateEnable
= GEN_GEN
<= 7;
3318 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3319 ggw
.ThreadDepthCounterMaximum
= 0;
3320 ggw
.ThreadHeightCounterMaximum
= 0;
3321 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3322 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3323 ggw
.BottomExecutionMask
= 0xffffffff;
3326 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3330 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3333 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3335 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3338 #if GEN_GEN >= 8 && GEN_GEN < 10
3339 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3341 * Software must clear the COLOR_CALC_STATE Valid field in
3342 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3343 * with Pipeline Select set to GPGPU.
3345 * The internal hardware docs recommend the same workaround for Gen9
3348 if (pipeline
== GPGPU
)
3349 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3352 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3353 * PIPELINE_SELECT [DevBWR+]":
3357 * Software must ensure all the write caches are flushed through a
3358 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3359 * command to invalidate read only caches prior to programming
3360 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3362 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3363 pc
.RenderTargetCacheFlushEnable
= true;
3364 pc
.DepthCacheFlushEnable
= true;
3365 pc
.DCFlushEnable
= true;
3366 pc
.PostSyncOperation
= NoWrite
;
3367 pc
.CommandStreamerStallEnable
= true;
3370 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3371 pc
.TextureCacheInvalidationEnable
= true;
3372 pc
.ConstantCacheInvalidationEnable
= true;
3373 pc
.StateCacheInvalidationEnable
= true;
3374 pc
.InstructionCacheInvalidateEnable
= true;
3375 pc
.PostSyncOperation
= NoWrite
;
3378 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3382 ps
.PipelineSelection
= pipeline
;
3386 if (devinfo
->is_geminilake
) {
3389 * "This chicken bit works around a hardware issue with barrier logic
3390 * encountered when switching between GPGPU and 3D pipelines. To
3391 * workaround the issue, this mode bit should be set after a pipeline
3395 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3397 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3398 : GLK_BARRIER_MODE_3D_HULL
,
3399 .GLKBarrierModeMask
= 1);
3400 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3404 cmd_buffer
->state
.current_pipeline
= pipeline
;
3408 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3410 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3414 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3416 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3420 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3425 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3427 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3428 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3429 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3430 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3431 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3432 * Depth Flush Bit set, followed by another pipelined depth stall
3433 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3434 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3435 * via a preceding MI_FLUSH)."
3437 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3438 pipe
.DepthStallEnable
= true;
3440 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3441 pipe
.DepthCacheFlushEnable
= true;
3443 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3444 pipe
.DepthStallEnable
= true;
3449 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3451 struct anv_device
*device
= cmd_buffer
->device
;
3452 const struct anv_image_view
*iview
=
3453 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3454 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3456 /* FIXME: Width and Height are wrong */
3458 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3460 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3461 device
->isl_dev
.ds
.size
/ 4);
3465 struct isl_depth_stencil_hiz_emit_info info
= { };
3468 info
.view
= &iview
->planes
[0].isl
;
3470 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3471 uint32_t depth_plane
=
3472 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3473 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3475 info
.depth_surf
= &surface
->isl
;
3477 info
.depth_address
=
3478 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3479 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3480 image
->planes
[depth_plane
].address
.bo
,
3481 image
->planes
[depth_plane
].address
.offset
+
3484 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
3487 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3488 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3489 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3490 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3493 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3494 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3495 image
->planes
[depth_plane
].address
.bo
,
3496 image
->planes
[depth_plane
].address
.offset
+
3497 image
->planes
[depth_plane
].aux_surface
.offset
);
3499 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3503 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3504 uint32_t stencil_plane
=
3505 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3506 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3508 info
.stencil_surf
= &surface
->isl
;
3510 info
.stencil_address
=
3511 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3512 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3513 image
->planes
[stencil_plane
].address
.bo
,
3514 image
->planes
[stencil_plane
].address
.offset
+
3517 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
3520 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3522 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3526 * This ANDs the view mask of the current subpass with the pending clear
3527 * views in the attachment to get the mask of views active in the subpass
3528 * that still need to be cleared.
3530 static inline uint32_t
3531 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3532 const struct anv_attachment_state
*att_state
)
3534 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3538 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3539 const struct anv_attachment_state
*att_state
)
3541 if (!cmd_state
->subpass
->view_mask
)
3544 uint32_t pending_clear_mask
=
3545 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3547 return pending_clear_mask
& 1;
3551 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3554 const uint32_t last_subpass_idx
=
3555 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3556 const struct anv_subpass
*last_subpass
=
3557 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3558 return last_subpass
== cmd_state
->subpass
;
3562 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3563 uint32_t subpass_id
)
3565 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3566 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3567 cmd_state
->subpass
= subpass
;
3569 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3571 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3572 * different views. If the client asks for instancing, we need to use the
3573 * Instance Data Step Rate to ensure that we repeat the client's
3574 * per-instance data once for each view. Since this bit is in
3575 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3579 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3581 /* It is possible to start a render pass with an old pipeline. Because the
3582 * render pass and subpass index are both baked into the pipeline, this is
3583 * highly unlikely. In order to do so, it requires that you have a render
3584 * pass with a single subpass and that you use that render pass twice
3585 * back-to-back and use the same pipeline at the start of the second render
3586 * pass as at the end of the first. In order to avoid unpredictable issues
3587 * with this edge case, we just dirty the pipeline at the start of every
3590 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3592 /* Accumulate any subpass flushes that need to happen before the subpass */
3593 cmd_buffer
->state
.pending_pipe_bits
|=
3594 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3596 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3597 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3599 bool is_multiview
= subpass
->view_mask
!= 0;
3601 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3602 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3603 if (a
== VK_ATTACHMENT_UNUSED
)
3606 assert(a
< cmd_state
->pass
->attachment_count
);
3607 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3609 struct anv_image_view
*iview
= fb
->attachments
[a
];
3610 const struct anv_image
*image
= iview
->image
;
3612 /* A resolve is necessary before use as an input attachment if the clear
3613 * color or auxiliary buffer usage isn't supported by the sampler.
3615 const bool input_needs_resolve
=
3616 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3617 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3619 VkImageLayout target_layout
;
3620 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3621 !input_needs_resolve
) {
3622 /* Layout transitions before the final only help to enable sampling
3623 * as an input attachment. If the input attachment supports sampling
3624 * using the auxiliary surface, we can skip such transitions by
3625 * making the target layout one that is CCS-aware.
3627 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3629 target_layout
= subpass
->attachments
[i
].layout
;
3632 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3633 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3635 uint32_t base_layer
, layer_count
;
3636 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3638 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3639 iview
->planes
[0].isl
.base_level
);
3641 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3642 layer_count
= fb
->layers
;
3645 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3646 iview
->planes
[0].isl
.base_level
, 1,
3647 base_layer
, layer_count
,
3648 att_state
->current_layout
, target_layout
);
3649 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3650 transition_depth_buffer(cmd_buffer
, image
,
3651 att_state
->current_layout
, target_layout
);
3652 att_state
->aux_usage
=
3653 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3654 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3656 att_state
->current_layout
= target_layout
;
3658 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3659 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3661 /* Multi-planar images are not supported as attachments */
3662 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3663 assert(image
->n_planes
== 1);
3665 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
3666 uint32_t clear_layer_count
= fb
->layers
;
3668 if (att_state
->fast_clear
&&
3669 do_first_layer_clear(cmd_state
, att_state
)) {
3670 /* We only support fast-clears on the first layer */
3671 assert(iview
->planes
[0].isl
.base_level
== 0);
3672 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3674 union isl_color_value clear_color
= {};
3675 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
3676 if (iview
->image
->samples
== 1) {
3677 anv_image_ccs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3678 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3682 anv_image_mcs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3683 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3688 clear_layer_count
--;
3690 att_state
->pending_clear_views
&= ~1;
3692 if (att_state
->clear_color_is_zero
) {
3693 /* This image has the auxiliary buffer enabled. We can mark the
3694 * subresource as not needing a resolve because the clear color
3695 * will match what's in every RENDER_SURFACE_STATE object when
3696 * it's being used for sampling.
3698 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3699 VK_IMAGE_ASPECT_COLOR_BIT
,
3700 ANV_FAST_CLEAR_DEFAULT_VALUE
);
3702 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3703 VK_IMAGE_ASPECT_COLOR_BIT
,
3704 ANV_FAST_CLEAR_ANY
);
3708 /* From the VkFramebufferCreateInfo spec:
3710 * "If the render pass uses multiview, then layers must be one and each
3711 * attachment requires a number of layers that is greater than the
3712 * maximum bit index set in the view mask in the subpasses in which it
3715 * So if multiview is active we ignore the number of layers in the
3716 * framebuffer and instead we honor the view mask from the subpass.
3719 assert(image
->n_planes
== 1);
3720 uint32_t pending_clear_mask
=
3721 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3724 for_each_bit(layer_idx
, pending_clear_mask
) {
3726 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3728 anv_image_clear_color(cmd_buffer
, image
,
3729 VK_IMAGE_ASPECT_COLOR_BIT
,
3730 att_state
->aux_usage
,
3731 iview
->planes
[0].isl
.format
,
3732 iview
->planes
[0].isl
.swizzle
,
3733 iview
->planes
[0].isl
.base_level
,
3736 vk_to_isl_color(att_state
->clear_value
.color
));
3739 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3740 } else if (clear_layer_count
> 0) {
3741 assert(image
->n_planes
== 1);
3742 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3743 att_state
->aux_usage
,
3744 iview
->planes
[0].isl
.format
,
3745 iview
->planes
[0].isl
.swizzle
,
3746 iview
->planes
[0].isl
.base_level
,
3747 base_clear_layer
, clear_layer_count
,
3749 vk_to_isl_color(att_state
->clear_value
.color
));
3751 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
3752 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3753 if (att_state
->fast_clear
&& !is_multiview
) {
3754 /* We currently only support HiZ for single-layer images */
3755 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3756 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
3757 assert(iview
->planes
[0].isl
.base_level
== 0);
3758 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3759 assert(fb
->layers
== 1);
3762 anv_image_hiz_clear(cmd_buffer
, image
,
3763 att_state
->pending_clear_aspects
,
3764 iview
->planes
[0].isl
.base_level
,
3765 iview
->planes
[0].isl
.base_array_layer
,
3766 fb
->layers
, render_area
,
3767 att_state
->clear_value
.depthStencil
.stencil
);
3768 } else if (is_multiview
) {
3769 uint32_t pending_clear_mask
=
3770 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3773 for_each_bit(layer_idx
, pending_clear_mask
) {
3775 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3777 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3778 att_state
->pending_clear_aspects
,
3779 att_state
->aux_usage
,
3780 iview
->planes
[0].isl
.base_level
,
3783 att_state
->clear_value
.depthStencil
.depth
,
3784 att_state
->clear_value
.depthStencil
.stencil
);
3787 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3789 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3790 att_state
->pending_clear_aspects
,
3791 att_state
->aux_usage
,
3792 iview
->planes
[0].isl
.base_level
,
3793 iview
->planes
[0].isl
.base_array_layer
,
3794 fb
->layers
, render_area
,
3795 att_state
->clear_value
.depthStencil
.depth
,
3796 att_state
->clear_value
.depthStencil
.stencil
);
3799 assert(att_state
->pending_clear_aspects
== 0);
3803 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
3804 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
3805 iview
->planes
[0].isl
.base_level
== 0 &&
3806 iview
->planes
[0].isl
.base_array_layer
== 0) {
3807 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
3808 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3809 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3810 false /* copy to ss */);
3813 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
3814 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3815 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3816 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3817 false /* copy to ss */);
3821 if (subpass
->attachments
[i
].usage
==
3822 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
3823 /* We assume that if we're starting a subpass, we're going to do some
3824 * rendering so we may end up with compressed data.
3826 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
3827 VK_IMAGE_ASPECT_COLOR_BIT
,
3828 att_state
->aux_usage
,
3829 iview
->planes
[0].isl
.base_level
,
3830 iview
->planes
[0].isl
.base_array_layer
,
3832 } else if (subpass
->attachments
[i
].usage
==
3833 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
3834 /* We may be writing depth or stencil so we need to mark the surface.
3835 * Unfortunately, there's no way to know at this point whether the
3836 * depth or stencil tests used will actually write to the surface.
3838 * Even though stencil may be plane 1, it always shares a base_level
3841 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
3842 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3843 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3844 VK_IMAGE_ASPECT_DEPTH_BIT
,
3845 att_state
->aux_usage
,
3846 ds_view
->base_level
,
3847 ds_view
->base_array_layer
,
3850 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
3851 /* Even though stencil may be plane 1, it always shares a
3852 * base_level with depth.
3854 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3855 VK_IMAGE_ASPECT_STENCIL_BIT
,
3857 ds_view
->base_level
,
3858 ds_view
->base_array_layer
,
3863 /* If multiview is enabled, then we are only done clearing when we no
3864 * longer have pending layers to clear, or when we have processed the
3865 * last subpass that uses this attachment.
3867 if (!is_multiview
||
3868 att_state
->pending_clear_views
== 0 ||
3869 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
3870 att_state
->pending_clear_aspects
= 0;
3873 att_state
->pending_load_aspects
= 0;
3876 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3880 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
3882 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3883 struct anv_subpass
*subpass
= cmd_state
->subpass
;
3884 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3886 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3888 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3889 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3890 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3891 if (a
== VK_ATTACHMENT_UNUSED
)
3894 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3897 assert(a
< cmd_state
->pass
->attachment_count
);
3898 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3899 struct anv_image_view
*iview
= fb
->attachments
[a
];
3900 const struct anv_image
*image
= iview
->image
;
3902 /* Transition the image into the final layout for this render pass */
3903 VkImageLayout target_layout
=
3904 cmd_state
->pass
->attachments
[a
].final_layout
;
3906 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3907 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3909 uint32_t base_layer
, layer_count
;
3910 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3912 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3913 iview
->planes
[0].isl
.base_level
);
3915 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3916 layer_count
= fb
->layers
;
3919 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3920 iview
->planes
[0].isl
.base_level
, 1,
3921 base_layer
, layer_count
,
3922 att_state
->current_layout
, target_layout
);
3923 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3924 transition_depth_buffer(cmd_buffer
, image
,
3925 att_state
->current_layout
, target_layout
);
3929 /* Accumulate any subpass flushes that need to happen after the subpass.
3930 * Yes, they do get accumulated twice in the NextSubpass case but since
3931 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
3932 * ORing the bits in twice so it's harmless.
3934 cmd_buffer
->state
.pending_pipe_bits
|=
3935 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
3938 void genX(CmdBeginRenderPass
)(
3939 VkCommandBuffer commandBuffer
,
3940 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3941 VkSubpassContents contents
)
3943 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3944 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3945 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3947 cmd_buffer
->state
.framebuffer
= framebuffer
;
3948 cmd_buffer
->state
.pass
= pass
;
3949 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3951 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3953 /* If we failed to setup the attachments we should not try to go further */
3954 if (result
!= VK_SUCCESS
) {
3955 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3959 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3961 cmd_buffer_begin_subpass(cmd_buffer
, 0);
3964 void genX(CmdBeginRenderPass2KHR
)(
3965 VkCommandBuffer commandBuffer
,
3966 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
3967 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
3969 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
3970 pSubpassBeginInfo
->contents
);
3973 void genX(CmdNextSubpass
)(
3974 VkCommandBuffer commandBuffer
,
3975 VkSubpassContents contents
)
3977 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3979 if (anv_batch_has_error(&cmd_buffer
->batch
))
3982 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3984 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
3985 cmd_buffer_end_subpass(cmd_buffer
);
3986 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3989 void genX(CmdNextSubpass2KHR
)(
3990 VkCommandBuffer commandBuffer
,
3991 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
3992 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
3994 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
3997 void genX(CmdEndRenderPass
)(
3998 VkCommandBuffer commandBuffer
)
4000 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4002 if (anv_batch_has_error(&cmd_buffer
->batch
))
4005 cmd_buffer_end_subpass(cmd_buffer
);
4007 cmd_buffer
->state
.hiz_enabled
= false;
4010 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
4013 /* Remove references to render pass specific state. This enables us to
4014 * detect whether or not we're in a renderpass.
4016 cmd_buffer
->state
.framebuffer
= NULL
;
4017 cmd_buffer
->state
.pass
= NULL
;
4018 cmd_buffer
->state
.subpass
= NULL
;
4021 void genX(CmdEndRenderPass2KHR
)(
4022 VkCommandBuffer commandBuffer
,
4023 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4025 genX(CmdEndRenderPass
)(commandBuffer
);