2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
37 /* We reserve GPR 14 and 15 for conditional rendering */
38 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
39 #define __gen_get_batch_dwords anv_batch_emit_dwords
40 #define __gen_address_offset anv_address_add
41 #include "common/gen_mi_builder.h"
43 static void genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
47 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
49 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
50 lri
.RegisterOffset
= reg
;
56 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
58 struct anv_device
*device
= cmd_buffer
->device
;
59 UNUSED
const struct gen_device_info
*devinfo
= &device
->info
;
60 uint32_t mocs
= device
->isl_dev
.mocs
.internal
;
62 /* If we are emitting a new state base address we probably need to re-emit
65 cmd_buffer
->state
.descriptors_dirty
|= ~0;
67 /* Emit a render target cache flush.
69 * This isn't documented anywhere in the PRM. However, it seems to be
70 * necessary prior to changing the surface state base adress. Without
71 * this, we get GPU hangs when using multi-level command buffers which
72 * clear depth, reset state base address, and then go render stuff.
74 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
75 pc
.DCFlushEnable
= true;
76 pc
.RenderTargetCacheFlushEnable
= true;
77 pc
.CommandStreamerStallEnable
= true;
79 pc
.TileCacheFlushEnable
= true;
82 /* GEN:BUG:1606662791:
84 * Software must program PIPE_CONTROL command with "HDC Pipeline
85 * Flush" prior to programming of the below two non-pipeline state :
86 * * STATE_BASE_ADDRESS
87 * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
89 if (devinfo
->revision
== 0 /* A0 */)
90 pc
.HDCPipelineFlushEnable
= true;
95 /* GEN:BUG:1607854226:
97 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
98 * mode by putting the pipeline temporarily in 3D mode.
100 uint32_t gen12_wa_pipeline
= cmd_buffer
->state
.current_pipeline
;
101 genX(flush_pipeline_select_3d
)(cmd_buffer
);
104 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
105 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
106 sba
.GeneralStateMOCS
= mocs
;
107 sba
.GeneralStateBaseAddressModifyEnable
= true;
109 sba
.StatelessDataPortAccessMOCS
= mocs
;
111 sba
.SurfaceStateBaseAddress
=
112 anv_cmd_buffer_surface_base_address(cmd_buffer
);
113 sba
.SurfaceStateMOCS
= mocs
;
114 sba
.SurfaceStateBaseAddressModifyEnable
= true;
116 sba
.DynamicStateBaseAddress
=
117 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
118 sba
.DynamicStateMOCS
= mocs
;
119 sba
.DynamicStateBaseAddressModifyEnable
= true;
121 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
122 sba
.IndirectObjectMOCS
= mocs
;
123 sba
.IndirectObjectBaseAddressModifyEnable
= true;
125 sba
.InstructionBaseAddress
=
126 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
127 sba
.InstructionMOCS
= mocs
;
128 sba
.InstructionBaseAddressModifyEnable
= true;
131 /* Broadwell requires that we specify a buffer size for a bunch of
132 * these fields. However, since we will be growing the BO's live, we
133 * just set them all to the maximum.
135 sba
.GeneralStateBufferSize
= 0xfffff;
136 sba
.IndirectObjectBufferSize
= 0xfffff;
137 if (device
->physical
->use_softpin
) {
138 /* With softpin, we use fixed addresses so we actually know how big
139 * our base addresses are.
141 sba
.DynamicStateBufferSize
= DYNAMIC_STATE_POOL_SIZE
/ 4096;
142 sba
.InstructionBufferSize
= INSTRUCTION_STATE_POOL_SIZE
/ 4096;
144 sba
.DynamicStateBufferSize
= 0xfffff;
145 sba
.InstructionBufferSize
= 0xfffff;
147 sba
.GeneralStateBufferSizeModifyEnable
= true;
148 sba
.IndirectObjectBufferSizeModifyEnable
= true;
149 sba
.DynamicStateBufferSizeModifyEnable
= true;
150 sba
.InstructionBuffersizeModifyEnable
= true;
152 /* On gen7, we have upper bounds instead. According to the docs,
153 * setting an upper bound of zero means that no bounds checking is
154 * performed so, in theory, we should be able to leave them zero.
155 * However, border color is broken and the GPU bounds-checks anyway.
156 * To avoid this and other potential problems, we may as well set it
159 sba
.GeneralStateAccessUpperBound
=
160 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
161 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
162 sba
.DynamicStateAccessUpperBound
=
163 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
164 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
165 sba
.InstructionAccessUpperBound
=
166 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
167 sba
.InstructionAccessUpperBoundModifyEnable
= true;
170 if (cmd_buffer
->device
->physical
->use_softpin
) {
171 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
172 .bo
= device
->surface_state_pool
.block_pool
.bo
,
175 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
177 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
178 sba
.BindlessSurfaceStateSize
= 0;
180 sba
.BindlessSurfaceStateMOCS
= mocs
;
181 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
184 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
185 sba
.BindlessSamplerStateMOCS
= mocs
;
186 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
187 sba
.BindlessSamplerStateBufferSize
= 0;
192 /* GEN:BUG:1607854226:
194 * Put the pipeline back into its current mode.
196 if (gen12_wa_pipeline
!= UINT32_MAX
)
197 genX(flush_pipeline_select
)(cmd_buffer
, gen12_wa_pipeline
);
200 /* After re-setting the surface state base address, we have to do some
201 * cache flusing so that the sampler engine will pick up the new
202 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
203 * Shared Function > 3D Sampler > State > State Caching (page 96):
205 * Coherency with system memory in the state cache, like the texture
206 * cache is handled partially by software. It is expected that the
207 * command stream or shader will issue Cache Flush operation or
208 * Cache_Flush sampler message to ensure that the L1 cache remains
209 * coherent with system memory.
213 * Whenever the value of the Dynamic_State_Base_Addr,
214 * Surface_State_Base_Addr are altered, the L1 state cache must be
215 * invalidated to ensure the new surface or sampler state is fetched
216 * from system memory.
218 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
219 * which, according the PIPE_CONTROL instruction documentation in the
222 * Setting this bit is independent of any other bit in this packet.
223 * This bit controls the invalidation of the L1 and L2 state caches
224 * at the top of the pipe i.e. at the parsing time.
226 * Unfortunately, experimentation seems to indicate that state cache
227 * invalidation through a PIPE_CONTROL does nothing whatsoever in
228 * regards to surface state and binding tables. In stead, it seems that
229 * invalidating the texture cache is what is actually needed.
231 * XXX: As far as we have been able to determine through
232 * experimentation, shows that flush the texture cache appears to be
233 * sufficient. The theory here is that all of the sampling/rendering
234 * units cache the binding table in the texture cache. However, we have
235 * yet to be able to actually confirm this.
237 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
238 pc
.TextureCacheInvalidationEnable
= true;
239 pc
.ConstantCacheInvalidationEnable
= true;
240 pc
.StateCacheInvalidationEnable
= true;
245 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
246 struct anv_state state
, struct anv_address addr
)
248 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
251 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
252 state
.offset
+ isl_dev
->ss
.addr_offset
,
253 addr
.bo
, addr
.offset
, NULL
);
254 if (result
!= VK_SUCCESS
)
255 anv_batch_set_error(&cmd_buffer
->batch
, result
);
259 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
260 struct anv_surface_state state
)
262 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
264 assert(!anv_address_is_null(state
.address
));
265 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
267 if (!anv_address_is_null(state
.aux_address
)) {
269 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
270 &cmd_buffer
->pool
->alloc
,
271 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
272 state
.aux_address
.bo
,
273 state
.aux_address
.offset
,
275 if (result
!= VK_SUCCESS
)
276 anv_batch_set_error(&cmd_buffer
->batch
, result
);
279 if (!anv_address_is_null(state
.clear_address
)) {
281 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
282 &cmd_buffer
->pool
->alloc
,
284 isl_dev
->ss
.clear_color_state_offset
,
285 state
.clear_address
.bo
,
286 state
.clear_address
.offset
,
288 if (result
!= VK_SUCCESS
)
289 anv_batch_set_error(&cmd_buffer
->batch
, result
);
294 color_attachment_compute_aux_usage(struct anv_device
* device
,
295 struct anv_cmd_state
* cmd_state
,
296 uint32_t att
, VkRect2D render_area
,
297 union isl_color_value
*fast_clear_color
)
299 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
300 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
302 assert(iview
->n_planes
== 1);
304 if (iview
->planes
[0].isl
.base_array_layer
>=
305 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
306 iview
->planes
[0].isl
.base_level
)) {
307 /* There is no aux buffer which corresponds to the level and layer(s)
310 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
311 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
312 att_state
->fast_clear
= false;
316 att_state
->aux_usage
=
317 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
318 VK_IMAGE_ASPECT_COLOR_BIT
,
319 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
,
320 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
322 /* If we don't have aux, then we should have returned early in the layer
323 * check above. If we got here, we must have something.
325 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
327 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
328 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
329 att_state
->input_aux_usage
= att_state
->aux_usage
;
331 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
333 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
334 * setting is only allowed if Surface Format supported for Fast
335 * Clear. In addition, if the surface is bound to the sampling
336 * engine, Surface Format must be supported for Render Target
337 * Compression for surfaces bound to the sampling engine."
339 * In other words, we can only sample from a fast-cleared image if it
340 * also supports color compression.
342 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
) &&
343 isl_format_supports_ccs_d(&device
->info
, iview
->planes
[0].isl
.format
)) {
344 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
346 /* While fast-clear resolves and partial resolves are fairly cheap in the
347 * case where you render to most of the pixels, full resolves are not
348 * because they potentially involve reading and writing the entire
349 * framebuffer. If we can't texture with CCS_E, we should leave it off and
350 * limit ourselves to fast clears.
352 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
353 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
354 anv_perf_warn(device
, iview
->image
,
355 "Not temporarily enabling CCS_E.");
358 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
362 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
363 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
365 union isl_color_value clear_color
= {};
366 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
368 att_state
->clear_color_is_zero_one
=
369 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
370 att_state
->clear_color_is_zero
=
371 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
373 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
374 /* Start by getting the fast clear type. We use the first subpass
375 * layout here because we don't want to fast-clear if the first subpass
376 * to use the attachment can't handle fast-clears.
378 enum anv_fast_clear_type fast_clear_type
=
379 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
380 VK_IMAGE_ASPECT_COLOR_BIT
,
381 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
382 switch (fast_clear_type
) {
383 case ANV_FAST_CLEAR_NONE
:
384 att_state
->fast_clear
= false;
386 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
387 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
389 case ANV_FAST_CLEAR_ANY
:
390 att_state
->fast_clear
= true;
394 /* Potentially, we could do partial fast-clears but doing so has crazy
395 * alignment restrictions. It's easier to just restrict to full size
396 * fast clears for now.
398 if (render_area
.offset
.x
!= 0 ||
399 render_area
.offset
.y
!= 0 ||
400 render_area
.extent
.width
!= iview
->extent
.width
||
401 render_area
.extent
.height
!= iview
->extent
.height
)
402 att_state
->fast_clear
= false;
404 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
405 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
406 att_state
->fast_clear
= false;
408 /* We only allow fast clears to the first slice of an image (level 0,
409 * layer 0) and only for the entire slice. This guarantees us that, at
410 * any given time, there is only one clear color on any given image at
411 * any given time. At the time of our testing (Jan 17, 2018), there
412 * were no known applications which would benefit from fast-clearing
413 * more than just the first slice.
415 if (att_state
->fast_clear
&&
416 (iview
->planes
[0].isl
.base_level
> 0 ||
417 iview
->planes
[0].isl
.base_array_layer
> 0)) {
418 anv_perf_warn(device
, iview
->image
,
419 "Rendering with multi-lod or multi-layer framebuffer "
420 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
421 "baseArrayLayer > 0. Not fast clearing.");
422 att_state
->fast_clear
= false;
423 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
424 anv_perf_warn(device
, iview
->image
,
425 "Rendering to a multi-layer framebuffer with "
426 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
429 if (att_state
->fast_clear
)
430 *fast_clear_color
= clear_color
;
432 att_state
->fast_clear
= false;
437 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
438 struct anv_cmd_state
*cmd_state
,
439 uint32_t att
, VkRect2D render_area
)
441 struct anv_render_pass_attachment
*pass_att
=
442 &cmd_state
->pass
->attachments
[att
];
443 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
444 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
446 /* These will be initialized after the first subpass transition. */
447 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
448 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
450 /* This is unused for depth/stencil but valgrind complains if it
453 att_state
->clear_color_is_zero_one
= false;
456 /* We don't do any HiZ or depth fast-clears on gen7 yet */
457 att_state
->fast_clear
= false;
461 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
462 /* If we're just clearing stencil, we can always HiZ clear */
463 att_state
->fast_clear
= true;
467 /* Default to false for now */
468 att_state
->fast_clear
= false;
470 /* We must have depth in order to have HiZ */
471 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
474 const enum isl_aux_usage first_subpass_aux_usage
=
475 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
476 VK_IMAGE_ASPECT_DEPTH_BIT
,
477 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
478 pass_att
->first_subpass_layout
);
479 if (!blorp_can_hiz_clear_depth(&device
->info
,
480 &iview
->image
->planes
[0].surface
.isl
,
481 first_subpass_aux_usage
,
482 iview
->planes
[0].isl
.base_level
,
483 iview
->planes
[0].isl
.base_array_layer
,
484 render_area
.offset
.x
,
485 render_area
.offset
.y
,
486 render_area
.offset
.x
+
487 render_area
.extent
.width
,
488 render_area
.offset
.y
+
489 render_area
.extent
.height
))
492 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
495 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
496 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
497 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
498 * only supports returning 0.0f. Gens prior to gen8 do not support this
504 /* If we got here, then we can fast clear */
505 att_state
->fast_clear
= true;
509 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
511 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
514 /* We only allocate input attachment states for color surfaces. Compression
515 * is not yet enabled for depth textures and stencil doesn't allow
516 * compression so we can just use the texture surface state from the view.
518 return vk_format_is_color(att
->format
);
521 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
522 * the initial layout is undefined, the HiZ buffer and depth buffer will
523 * represent the same data at the end of this operation.
526 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
527 const struct anv_image
*image
,
528 uint32_t base_layer
, uint32_t layer_count
,
529 VkImageLayout initial_layout
,
530 VkImageLayout final_layout
)
532 uint32_t depth_plane
=
533 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
534 if (image
->planes
[depth_plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
537 const enum isl_aux_state initial_state
=
538 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
539 VK_IMAGE_ASPECT_DEPTH_BIT
,
541 const enum isl_aux_state final_state
=
542 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
543 VK_IMAGE_ASPECT_DEPTH_BIT
,
546 const bool initial_depth_valid
=
547 isl_aux_state_has_valid_primary(initial_state
);
548 const bool initial_hiz_valid
=
549 isl_aux_state_has_valid_aux(initial_state
);
550 const bool final_needs_depth
=
551 isl_aux_state_has_valid_primary(final_state
);
552 const bool final_needs_hiz
=
553 isl_aux_state_has_valid_aux(final_state
);
555 /* Getting into the pass-through state for Depth is tricky and involves
556 * both a resolve and an ambiguate. We don't handle that state right now
557 * as anv_layout_to_aux_state never returns it.
559 assert(final_state
!= ISL_AUX_STATE_PASS_THROUGH
);
561 if (final_needs_depth
&& !initial_depth_valid
) {
562 assert(initial_hiz_valid
);
563 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
564 0, base_layer
, layer_count
, ISL_AUX_OP_FULL_RESOLVE
);
565 } else if (final_needs_hiz
&& !initial_hiz_valid
) {
566 assert(initial_depth_valid
);
567 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
568 0, base_layer
, layer_count
, ISL_AUX_OP_AMBIGUATE
);
573 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
575 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
576 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
||
577 layout
== VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
;
580 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
581 * the initial layout is undefined, the HiZ buffer and depth buffer will
582 * represent the same data at the end of this operation.
585 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
586 const struct anv_image
*image
,
587 uint32_t base_level
, uint32_t level_count
,
588 uint32_t base_layer
, uint32_t layer_count
,
589 VkImageLayout initial_layout
,
590 VkImageLayout final_layout
)
593 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
594 VK_IMAGE_ASPECT_STENCIL_BIT
);
596 /* On gen7, we have to store a texturable version of the stencil buffer in
597 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
598 * forth at strategic points. Stencil writes are only allowed in following
601 * - VK_IMAGE_LAYOUT_GENERAL
602 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
603 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
604 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
605 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
607 * For general, we have no nice opportunity to transition so we do the copy
608 * to the shadow unconditionally at the end of the subpass. For transfer
609 * destinations, we can update it as part of the transfer op. For the other
610 * layouts, we delay the copy until a transition into some other layout.
612 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
613 vk_image_layout_stencil_write_optimal(initial_layout
) &&
614 !vk_image_layout_stencil_write_optimal(final_layout
)) {
615 anv_image_copy_to_shadow(cmd_buffer
, image
,
616 VK_IMAGE_ASPECT_STENCIL_BIT
,
617 base_level
, level_count
,
618 base_layer
, layer_count
);
620 #endif /* GEN_GEN == 7 */
623 #define MI_PREDICATE_SRC0 0x2400
624 #define MI_PREDICATE_SRC1 0x2408
625 #define MI_PREDICATE_RESULT 0x2418
628 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
629 const struct anv_image
*image
,
630 VkImageAspectFlagBits aspect
,
632 uint32_t base_layer
, uint32_t layer_count
,
635 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
637 /* We only have compression tracking for CCS_E */
638 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
641 for (uint32_t a
= 0; a
< layer_count
; a
++) {
642 uint32_t layer
= base_layer
+ a
;
643 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
644 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
647 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
653 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
654 const struct anv_image
*image
,
655 VkImageAspectFlagBits aspect
,
656 enum anv_fast_clear_type fast_clear
)
658 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
659 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
661 sdi
.ImmediateData
= fast_clear
;
664 /* Whenever we have fast-clear, we consider that slice to be compressed.
665 * This makes building predicates much easier.
667 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
668 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
671 /* This is only really practical on haswell and above because it requires
672 * MI math in order to get it correct.
674 #if GEN_GEN >= 8 || GEN_IS_HASWELL
676 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
677 const struct anv_image
*image
,
678 VkImageAspectFlagBits aspect
,
679 uint32_t level
, uint32_t array_layer
,
680 enum isl_aux_op resolve_op
,
681 enum anv_fast_clear_type fast_clear_supported
)
683 struct gen_mi_builder b
;
684 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
686 const struct gen_mi_value fast_clear_type
=
687 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
690 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
691 /* In this case, we're doing a full resolve which means we want the
692 * resolve to happen if any compression (including fast-clears) is
695 * In order to simplify the logic a bit, we make the assumption that,
696 * if the first slice has been fast-cleared, it is also marked as
697 * compressed. See also set_image_fast_clear_state.
699 const struct gen_mi_value compression_state
=
700 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
702 level
, array_layer
));
703 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
705 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
707 if (level
== 0 && array_layer
== 0) {
708 /* If the predicate is true, we want to write 0 to the fast clear type
709 * and, if it's false, leave it alone. We can do this by writing
711 * clear_type = clear_type & ~predicate;
713 struct gen_mi_value new_fast_clear_type
=
714 gen_mi_iand(&b
, fast_clear_type
,
715 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
716 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
718 } else if (level
== 0 && array_layer
== 0) {
719 /* In this case, we are doing a partial resolve to get rid of fast-clear
720 * colors. We don't care about the compression state but we do care
721 * about how much fast clear is allowed by the final layout.
723 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
724 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
726 /* We need to compute (fast_clear_supported < image->fast_clear) */
727 struct gen_mi_value pred
=
728 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
729 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
730 gen_mi_value_ref(&b
, pred
));
732 /* If the predicate is true, we want to write 0 to the fast clear type
733 * and, if it's false, leave it alone. We can do this by writing
735 * clear_type = clear_type & ~predicate;
737 struct gen_mi_value new_fast_clear_type
=
738 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
739 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
741 /* In this case, we're trying to do a partial resolve on a slice that
742 * doesn't have clear color. There's nothing to do.
744 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
748 /* Set src1 to 0 and use a != condition */
749 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
751 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
752 mip
.LoadOperation
= LOAD_LOADINV
;
753 mip
.CombineOperation
= COMBINE_SET
;
754 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
757 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
761 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
762 const struct anv_image
*image
,
763 VkImageAspectFlagBits aspect
,
764 uint32_t level
, uint32_t array_layer
,
765 enum isl_aux_op resolve_op
,
766 enum anv_fast_clear_type fast_clear_supported
)
768 struct gen_mi_builder b
;
769 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
771 struct gen_mi_value fast_clear_type_mem
=
772 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
775 /* This only works for partial resolves and only when the clear color is
776 * all or nothing. On the upside, this emits less command streamer code
777 * and works on Ivybridge and Bay Trail.
779 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
780 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
782 /* We don't support fast clears on anything other than the first slice. */
783 if (level
> 0 || array_layer
> 0)
786 /* On gen8, we don't have a concept of default clear colors because we
787 * can't sample from CCS surfaces. It's enough to just load the fast clear
788 * state into the predicate register.
790 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
791 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
792 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
794 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
795 mip
.LoadOperation
= LOAD_LOADINV
;
796 mip
.CombineOperation
= COMBINE_SET
;
797 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
800 #endif /* GEN_GEN <= 8 */
803 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
804 const struct anv_image
*image
,
805 enum isl_format format
,
806 struct isl_swizzle swizzle
,
807 VkImageAspectFlagBits aspect
,
808 uint32_t level
, uint32_t array_layer
,
809 enum isl_aux_op resolve_op
,
810 enum anv_fast_clear_type fast_clear_supported
)
812 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
815 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
816 aspect
, level
, array_layer
,
817 resolve_op
, fast_clear_supported
);
818 #else /* GEN_GEN <= 8 */
819 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
820 aspect
, level
, array_layer
,
821 resolve_op
, fast_clear_supported
);
824 /* CCS_D only supports full resolves and BLORP will assert on us if we try
825 * to do a partial resolve on a CCS_D surface.
827 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
828 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_D
)
829 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
831 anv_image_ccs_op(cmd_buffer
, image
, format
, swizzle
, aspect
,
832 level
, array_layer
, 1, resolve_op
, NULL
, true);
836 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
837 const struct anv_image
*image
,
838 enum isl_format format
,
839 struct isl_swizzle swizzle
,
840 VkImageAspectFlagBits aspect
,
841 uint32_t array_layer
,
842 enum isl_aux_op resolve_op
,
843 enum anv_fast_clear_type fast_clear_supported
)
845 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
846 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
848 #if GEN_GEN >= 8 || GEN_IS_HASWELL
849 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
850 aspect
, 0, array_layer
,
851 resolve_op
, fast_clear_supported
);
853 anv_image_mcs_op(cmd_buffer
, image
, format
, swizzle
, aspect
,
854 array_layer
, 1, resolve_op
, NULL
, true);
856 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
861 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
862 const struct anv_image
*image
,
863 VkImageAspectFlagBits aspect
,
864 enum isl_aux_usage aux_usage
,
867 uint32_t layer_count
)
869 /* The aspect must be exactly one of the image aspects. */
870 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
872 /* The only compression types with more than just fast-clears are MCS,
873 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
874 * track the current fast-clear and compression state. This leaves us
875 * with just MCS and CCS_E.
877 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
878 aux_usage
!= ISL_AUX_USAGE_MCS
)
881 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
882 level
, base_layer
, layer_count
, true);
886 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
887 const struct anv_image
*image
,
888 VkImageAspectFlagBits aspect
)
890 assert(cmd_buffer
&& image
);
891 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
893 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
894 ANV_FAST_CLEAR_NONE
);
896 /* Initialize the struct fields that are accessed for fast-clears so that
897 * the HW restrictions on the field values are satisfied.
899 struct anv_address addr
=
900 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
903 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
904 const unsigned num_dwords
= GEN_GEN
>= 10 ?
905 isl_dev
->ss
.clear_color_state_size
/ 4 :
906 isl_dev
->ss
.clear_value_size
/ 4;
907 for (unsigned i
= 0; i
< num_dwords
; i
++) {
908 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
910 sdi
.Address
.offset
+= i
* 4;
911 sdi
.ImmediateData
= 0;
915 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
917 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
918 /* Pre-SKL, the dword containing the clear values also contains
919 * other fields, so we need to initialize those fields to match the
920 * values that would be in a color attachment.
922 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
923 ISL_CHANNEL_SELECT_GREEN
<< 22 |
924 ISL_CHANNEL_SELECT_BLUE
<< 19 |
925 ISL_CHANNEL_SELECT_ALPHA
<< 16;
926 } else if (GEN_GEN
== 7) {
927 /* On IVB, the dword containing the clear values also contains
928 * other fields that must be zero or can be zero.
930 sdi
.ImmediateData
= 0;
936 /* Copy the fast-clear value dword(s) between a surface state object and an
937 * image's fast clear state buffer.
940 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
941 struct anv_state surface_state
,
942 const struct anv_image
*image
,
943 VkImageAspectFlagBits aspect
,
944 bool copy_from_surface_state
)
946 assert(cmd_buffer
&& image
);
947 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
949 struct anv_address ss_clear_addr
= {
950 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
951 .offset
= surface_state
.offset
+
952 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
954 const struct anv_address entry_addr
=
955 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
956 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
959 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
960 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
961 * in-flight when they are issued even if the memory touched is not
962 * currently active for rendering. The weird bit is that it is not the
963 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
964 * rendering hangs such that the next stalling command after the
965 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
967 * It is unclear exactly why this hang occurs. Both MI commands come with
968 * warnings about the 3D pipeline but that doesn't seem to fully explain
969 * it. My (Jason's) best theory is that it has something to do with the
970 * fact that we're using a GPU state register as our temporary and that
971 * something with reading/writing it is causing problems.
973 * In order to work around this issue, we emit a PIPE_CONTROL with the
974 * command streamer stall bit set.
976 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
977 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
980 struct gen_mi_builder b
;
981 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
983 if (copy_from_surface_state
) {
984 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
986 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
988 /* Updating a surface state object may require that the state cache be
989 * invalidated. From the SKL PRM, Shared Functions -> State -> State
992 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
993 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
994 * modified [...], the L1 state cache must be invalidated to ensure
995 * the new surface or sampler state is fetched from system memory.
997 * In testing, SKL doesn't actually seem to need this, but HSW does.
999 cmd_buffer
->state
.pending_pipe_bits
|=
1000 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1004 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
1008 anv_image_init_aux_tt(struct anv_cmd_buffer
*cmd_buffer
,
1009 const struct anv_image
*image
,
1010 VkImageAspectFlagBits aspect
,
1011 uint32_t base_level
, uint32_t level_count
,
1012 uint32_t base_layer
, uint32_t layer_count
)
1014 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1016 uint64_t base_address
=
1017 anv_address_physical(image
->planes
[plane
].address
);
1019 const struct isl_surf
*isl_surf
= &image
->planes
[plane
].surface
.isl
;
1020 uint64_t format_bits
= gen_aux_map_format_bits_for_isl_surf(isl_surf
);
1022 /* We're about to live-update the AUX-TT. We really don't want anyone else
1023 * trying to read it while we're doing this. We could probably get away
1024 * with not having this stall in some cases if we were really careful but
1025 * it's better to play it safe. Full stall the GPU.
1027 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1028 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1030 struct gen_mi_builder b
;
1031 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
1033 for (uint32_t a
= 0; a
< layer_count
; a
++) {
1034 const uint32_t layer
= base_layer
+ a
;
1036 uint64_t start_offset_B
= UINT64_MAX
, end_offset_B
= 0;
1037 for (uint32_t l
= 0; l
< level_count
; l
++) {
1038 const uint32_t level
= base_level
+ l
;
1040 uint32_t logical_array_layer
, logical_z_offset_px
;
1041 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1042 logical_array_layer
= 0;
1044 /* If the given miplevel does not have this layer, then any higher
1045 * miplevels won't either because miplevels only get smaller the
1048 assert(layer
< image
->extent
.depth
);
1049 if (layer
>= anv_minify(image
->extent
.depth
, level
))
1051 logical_z_offset_px
= layer
;
1053 assert(layer
< image
->array_size
);
1054 logical_array_layer
= layer
;
1055 logical_z_offset_px
= 0;
1058 uint32_t slice_start_offset_B
, slice_end_offset_B
;
1059 isl_surf_get_image_range_B_tile(isl_surf
, level
,
1060 logical_array_layer
,
1061 logical_z_offset_px
,
1062 &slice_start_offset_B
,
1063 &slice_end_offset_B
);
1065 start_offset_B
= MIN2(start_offset_B
, slice_start_offset_B
);
1066 end_offset_B
= MAX2(end_offset_B
, slice_end_offset_B
);
1069 /* Aux operates 64K at a time */
1070 start_offset_B
= align_down_u64(start_offset_B
, 64 * 1024);
1071 end_offset_B
= align_u64(end_offset_B
, 64 * 1024);
1073 for (uint64_t offset
= start_offset_B
;
1074 offset
< end_offset_B
; offset
+= 64 * 1024) {
1075 uint64_t address
= base_address
+ offset
;
1077 uint64_t aux_entry_addr64
, *aux_entry_map
;
1078 aux_entry_map
= gen_aux_map_get_entry(cmd_buffer
->device
->aux_map_ctx
,
1079 address
, &aux_entry_addr64
);
1081 assert(cmd_buffer
->device
->physical
->use_softpin
);
1082 struct anv_address aux_entry_address
= {
1084 .offset
= aux_entry_addr64
,
1087 const uint64_t old_aux_entry
= READ_ONCE(*aux_entry_map
);
1088 uint64_t new_aux_entry
=
1089 (old_aux_entry
& GEN_AUX_MAP_ADDRESS_MASK
) | format_bits
;
1091 if (isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
))
1092 new_aux_entry
|= GEN_AUX_MAP_ENTRY_VALID_BIT
;
1094 gen_mi_store(&b
, gen_mi_mem64(aux_entry_address
),
1095 gen_mi_imm(new_aux_entry
));
1099 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
1101 #endif /* GEN_GEN == 12 */
1104 * @brief Transitions a color buffer from one layout to another.
1106 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
1109 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
1110 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
1111 * this represents the maximum layers to transition at each
1112 * specified miplevel.
1115 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
1116 const struct anv_image
*image
,
1117 VkImageAspectFlagBits aspect
,
1118 const uint32_t base_level
, uint32_t level_count
,
1119 uint32_t base_layer
, uint32_t layer_count
,
1120 VkImageLayout initial_layout
,
1121 VkImageLayout final_layout
)
1123 struct anv_device
*device
= cmd_buffer
->device
;
1124 const struct gen_device_info
*devinfo
= &device
->info
;
1125 /* Validate the inputs. */
1127 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
1128 /* These values aren't supported for simplicity's sake. */
1129 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
1130 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
1131 /* Ensure the subresource range is valid. */
1132 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
1133 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
1134 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
1135 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
1136 assert(last_level_num
<= image
->levels
);
1137 /* The spec disallows these final layouts. */
1138 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
1139 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
1141 /* No work is necessary if the layout stays the same or if this subresource
1142 * range lacks auxiliary data.
1144 if (initial_layout
== final_layout
)
1147 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1149 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
1150 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
1151 /* This surface is a linear compressed image with a tiled shadow surface
1152 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
1153 * we need to ensure the shadow copy is up-to-date.
1155 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1156 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
1157 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1158 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
1160 anv_image_copy_to_shadow(cmd_buffer
, image
,
1161 VK_IMAGE_ASPECT_COLOR_BIT
,
1162 base_level
, level_count
,
1163 base_layer
, layer_count
);
1166 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1169 assert(image
->planes
[plane
].surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1171 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1172 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1174 if (device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
) {
1175 anv_image_init_aux_tt(cmd_buffer
, image
, aspect
,
1176 base_level
, level_count
,
1177 base_layer
, layer_count
);
1180 assert(!(device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
));
1183 /* A subresource in the undefined layout may have been aliased and
1184 * populated with any arrangement of bits. Therefore, we must initialize
1185 * the related aux buffer and clear buffer entry with desirable values.
1186 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1187 * images with VK_IMAGE_TILING_OPTIMAL.
1189 * Initialize the relevant clear buffer entries.
1191 if (base_level
== 0 && base_layer
== 0)
1192 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1194 /* Initialize the aux buffers to enable correct rendering. In order to
1195 * ensure that things such as storage images work correctly, aux buffers
1196 * need to be initialized to valid data.
1198 * Having an aux buffer with invalid data is a problem for two reasons:
1200 * 1) Having an invalid value in the buffer can confuse the hardware.
1201 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1202 * invalid and leads to the hardware doing strange things. It
1203 * doesn't hang as far as we can tell but rendering corruption can
1206 * 2) If this transition is into the GENERAL layout and we then use the
1207 * image as a storage image, then we must have the aux buffer in the
1208 * pass-through state so that, if we then go to texture from the
1209 * image, we get the results of our storage image writes and not the
1210 * fast clear color or other random data.
1212 * For CCS both of the problems above are real demonstrable issues. In
1213 * that case, the only thing we can do is to perform an ambiguate to
1214 * transition the aux surface into the pass-through state.
1216 * For MCS, (2) is never an issue because we don't support multisampled
1217 * storage images. In theory, issue (1) is a problem with MCS but we've
1218 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1219 * theory, be interpreted as something but we don't know that all bit
1220 * patterns are actually valid. For 2x and 8x, you could easily end up
1221 * with the MCS referring to an invalid plane because not all bits of
1222 * the MCS value are actually used. Even though we've never seen issues
1223 * in the wild, it's best to play it safe and initialize the MCS. We
1224 * can use a fast-clear for MCS because we only ever touch from render
1225 * and texture (no image load store).
1227 if (image
->samples
== 1) {
1228 for (uint32_t l
= 0; l
< level_count
; l
++) {
1229 const uint32_t level
= base_level
+ l
;
1231 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1232 if (base_layer
>= aux_layers
)
1233 break; /* We will only get fewer layers as level increases */
1234 uint32_t level_layer_count
=
1235 MIN2(layer_count
, aux_layers
- base_layer
);
1237 anv_image_ccs_op(cmd_buffer
, image
,
1238 image
->planes
[plane
].surface
.isl
.format
,
1239 ISL_SWIZZLE_IDENTITY
,
1240 aspect
, level
, base_layer
, level_layer_count
,
1241 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1243 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1244 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1245 level
, base_layer
, level_layer_count
,
1250 if (image
->samples
== 4 || image
->samples
== 16) {
1251 anv_perf_warn(cmd_buffer
->device
, image
,
1252 "Doing a potentially unnecessary fast-clear to "
1253 "define an MCS buffer.");
1256 assert(base_level
== 0 && level_count
== 1);
1257 anv_image_mcs_op(cmd_buffer
, image
,
1258 image
->planes
[plane
].surface
.isl
.format
,
1259 ISL_SWIZZLE_IDENTITY
,
1260 aspect
, base_layer
, layer_count
,
1261 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1266 const enum isl_aux_usage initial_aux_usage
=
1267 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, initial_layout
);
1268 const enum isl_aux_usage final_aux_usage
=
1269 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, final_layout
);
1271 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1272 * We can handle transitions between CCS_D/E to and from NONE. What we
1273 * don't yet handle is switching between CCS_E and CCS_D within a given
1274 * image. Doing so in a performant way requires more detailed aux state
1275 * tracking such as what is done in i965. For now, just assume that we
1276 * only have one type of compression.
1278 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1279 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1280 initial_aux_usage
== final_aux_usage
);
1282 /* If initial aux usage is NONE, there is nothing to resolve */
1283 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1286 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1288 /* If the initial layout supports more fast clear than the final layout
1289 * then we need at least a partial resolve.
1291 const enum anv_fast_clear_type initial_fast_clear
=
1292 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1293 const enum anv_fast_clear_type final_fast_clear
=
1294 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1295 if (final_fast_clear
< initial_fast_clear
)
1296 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1298 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1299 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1300 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1302 if (resolve_op
== ISL_AUX_OP_NONE
)
1305 /* Perform a resolve to synchronize data between the main and aux buffer.
1306 * Before we begin, we must satisfy the cache flushing requirement specified
1307 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1309 * Any transition from any value in {Clear, Render, Resolve} to a
1310 * different value in {Clear, Render, Resolve} requires end of pipe
1313 * We perform a flush of the write cache before and after the clear and
1314 * resolve operations to meet this requirement.
1316 * Unlike other drawing, fast clear operations are not properly
1317 * synchronized. The first PIPE_CONTROL here likely ensures that the
1318 * contents of the previous render or clear hit the render target before we
1319 * resolve and the second likely ensures that the resolve is complete before
1320 * we do any more rendering or clearing.
1322 cmd_buffer
->state
.pending_pipe_bits
|=
1323 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1325 for (uint32_t l
= 0; l
< level_count
; l
++) {
1326 uint32_t level
= base_level
+ l
;
1328 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1329 if (base_layer
>= aux_layers
)
1330 break; /* We will only get fewer layers as level increases */
1331 uint32_t level_layer_count
=
1332 MIN2(layer_count
, aux_layers
- base_layer
);
1334 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1335 uint32_t array_layer
= base_layer
+ a
;
1336 if (image
->samples
== 1) {
1337 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1338 image
->planes
[plane
].surface
.isl
.format
,
1339 ISL_SWIZZLE_IDENTITY
,
1340 aspect
, level
, array_layer
, resolve_op
,
1343 /* We only support fast-clear on the first layer so partial
1344 * resolves should not be used on other layers as they will use
1345 * the clear color stored in memory that is only valid for layer0.
1347 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1351 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1352 image
->planes
[plane
].surface
.isl
.format
,
1353 ISL_SWIZZLE_IDENTITY
,
1354 aspect
, array_layer
, resolve_op
,
1360 cmd_buffer
->state
.pending_pipe_bits
|=
1361 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1365 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1368 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1369 struct anv_render_pass
*pass
,
1370 const VkRenderPassBeginInfo
*begin
)
1372 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1373 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1374 struct anv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1376 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1378 if (pass
->attachment_count
> 0) {
1379 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1380 pass
->attachment_count
*
1381 sizeof(state
->attachments
[0]),
1382 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1383 if (state
->attachments
== NULL
) {
1384 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1385 return anv_batch_set_error(&cmd_buffer
->batch
,
1386 VK_ERROR_OUT_OF_HOST_MEMORY
);
1389 state
->attachments
= NULL
;
1392 /* Reserve one for the NULL state. */
1393 unsigned num_states
= 1;
1394 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1395 if (vk_format_is_color(pass
->attachments
[i
].format
))
1398 if (need_input_attachment_state(&pass
->attachments
[i
]))
1402 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1403 state
->render_pass_states
=
1404 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1405 num_states
* ss_stride
, isl_dev
->ss
.align
);
1407 struct anv_state next_state
= state
->render_pass_states
;
1408 next_state
.alloc_size
= isl_dev
->ss
.size
;
1410 state
->null_surface_state
= next_state
;
1411 next_state
.offset
+= ss_stride
;
1412 next_state
.map
+= ss_stride
;
1414 const VkRenderPassAttachmentBeginInfoKHR
*begin_attachment
=
1415 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1417 if (begin
&& !begin_attachment
)
1418 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1420 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1421 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1422 state
->attachments
[i
].color
.state
= next_state
;
1423 next_state
.offset
+= ss_stride
;
1424 next_state
.map
+= ss_stride
;
1427 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1428 state
->attachments
[i
].input
.state
= next_state
;
1429 next_state
.offset
+= ss_stride
;
1430 next_state
.map
+= ss_stride
;
1433 if (begin_attachment
&& begin_attachment
->attachmentCount
!= 0) {
1434 assert(begin_attachment
->attachmentCount
== pass
->attachment_count
);
1435 ANV_FROM_HANDLE(anv_image_view
, iview
, begin_attachment
->pAttachments
[i
]);
1436 cmd_buffer
->state
.attachments
[i
].image_view
= iview
;
1437 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1438 cmd_buffer
->state
.attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1441 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1442 state
->render_pass_states
.alloc_size
);
1445 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1446 isl_extent3d(framebuffer
->width
,
1447 framebuffer
->height
,
1448 framebuffer
->layers
));
1450 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1451 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1452 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1453 VkImageAspectFlags clear_aspects
= 0;
1454 VkImageAspectFlags load_aspects
= 0;
1456 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1457 /* color attachment */
1458 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1459 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1460 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1461 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1464 /* depthstencil attachment */
1465 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1466 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1467 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1468 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1469 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1472 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1473 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1474 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1475 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1476 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1481 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1482 state
->attachments
[i
].current_stencil_layout
= att
->stencil_initial_layout
;
1483 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1484 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1486 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1488 struct anv_image_view
*iview
= cmd_buffer
->state
.attachments
[i
].image_view
;
1489 anv_assert(iview
->vk_format
== att
->format
);
1491 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1492 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1494 union isl_color_value clear_color
= { .u32
= { 0, } };
1495 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1496 anv_assert(iview
->n_planes
== 1);
1497 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1498 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1499 state
, i
, begin
->renderArea
,
1502 anv_image_fill_surface_state(cmd_buffer
->device
,
1504 VK_IMAGE_ASPECT_COLOR_BIT
,
1505 &iview
->planes
[0].isl
,
1506 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1507 state
->attachments
[i
].aux_usage
,
1510 &state
->attachments
[i
].color
,
1513 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1515 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1520 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1521 anv_image_fill_surface_state(cmd_buffer
->device
,
1523 VK_IMAGE_ASPECT_COLOR_BIT
,
1524 &iview
->planes
[0].isl
,
1525 ISL_SURF_USAGE_TEXTURE_BIT
,
1526 state
->attachments
[i
].input_aux_usage
,
1529 &state
->attachments
[i
].input
,
1532 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1541 genX(BeginCommandBuffer
)(
1542 VkCommandBuffer commandBuffer
,
1543 const VkCommandBufferBeginInfo
* pBeginInfo
)
1545 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1547 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1548 * command buffer's state. Otherwise, we must *reset* its state. In both
1549 * cases we reset it.
1551 * From the Vulkan 1.0 spec:
1553 * If a command buffer is in the executable state and the command buffer
1554 * was allocated from a command pool with the
1555 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1556 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1557 * as if vkResetCommandBuffer had been called with
1558 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1559 * the command buffer in the recording state.
1561 anv_cmd_buffer_reset(cmd_buffer
);
1563 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1565 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1566 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1568 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1570 /* We sometimes store vertex data in the dynamic state buffer for blorp
1571 * operations and our dynamic state stream may re-use data from previous
1572 * command buffers. In order to prevent stale cache data, we flush the VF
1573 * cache. We could do this on every blorp call but that's not really
1574 * needed as all of the data will get written by the CPU prior to the GPU
1575 * executing anything. The chances are fairly high that they will use
1576 * blorp at least once per primary command buffer so it shouldn't be
1579 * There is also a workaround on gen8 which requires us to invalidate the
1580 * VF cache occasionally. It's easier if we can assume we start with a
1581 * fresh cache (See also genX(cmd_buffer_set_binding_for_gen8_vb_flush).)
1583 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1585 /* Re-emit the aux table register in every command buffer. This way we're
1586 * ensured that we have the table even if this command buffer doesn't
1587 * initialize any images.
1589 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
1591 /* We send an "Indirect State Pointers Disable" packet at
1592 * EndCommandBuffer, so all push contant packets are ignored during a
1593 * context restore. Documentation says after that command, we need to
1594 * emit push constants again before any rendering operation. So we
1595 * flag them dirty here to make sure they get emitted.
1597 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1599 VkResult result
= VK_SUCCESS
;
1600 if (cmd_buffer
->usage_flags
&
1601 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1602 assert(pBeginInfo
->pInheritanceInfo
);
1603 cmd_buffer
->state
.pass
=
1604 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1605 cmd_buffer
->state
.subpass
=
1606 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1608 /* This is optional in the inheritance info. */
1609 cmd_buffer
->state
.framebuffer
=
1610 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1612 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1613 cmd_buffer
->state
.pass
, NULL
);
1615 /* Record that HiZ is enabled if we can. */
1616 if (cmd_buffer
->state
.framebuffer
) {
1617 const struct anv_image_view
* const iview
=
1618 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1621 VkImageLayout layout
=
1622 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1624 enum isl_aux_usage aux_usage
=
1625 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1626 VK_IMAGE_ASPECT_DEPTH_BIT
,
1627 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
1630 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1634 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1637 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1638 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1639 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1640 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1642 /* If secondary buffer supports conditional rendering
1643 * we should emit commands as if conditional rendering is enabled.
1645 cmd_buffer
->state
.conditional_render_enabled
=
1646 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1653 /* From the PRM, Volume 2a:
1655 * "Indirect State Pointers Disable
1657 * At the completion of the post-sync operation associated with this pipe
1658 * control packet, the indirect state pointers in the hardware are
1659 * considered invalid; the indirect pointers are not saved in the context.
1660 * If any new indirect state commands are executed in the command stream
1661 * while the pipe control is pending, the new indirect state commands are
1664 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1665 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1666 * commands are only considered as Indirect State Pointers. Once ISP is
1667 * issued in a context, SW must initialize by programming push constant
1668 * commands for all the shaders (at least to zero length) before attempting
1669 * any rendering operation for the same context."
1671 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1672 * even though they point to a BO that has been already unreferenced at
1673 * the end of the previous batch buffer. This has been fine so far since
1674 * we are protected by these scratch page (every address not covered by
1675 * a BO should be pointing to the scratch page). But on CNL, it is
1676 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1679 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1680 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1681 * context restore, so the mentioned hang doesn't happen. However,
1682 * software must program push constant commands for all stages prior to
1683 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1685 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1686 * constants have been loaded into the EUs prior to disable the push constants
1687 * so that it doesn't hang a previous 3DPRIMITIVE.
1690 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1692 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1693 pc
.StallAtPixelScoreboard
= true;
1694 pc
.CommandStreamerStallEnable
= true;
1696 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1697 pc
.IndirectStatePointersDisable
= true;
1698 pc
.CommandStreamerStallEnable
= true;
1703 genX(EndCommandBuffer
)(
1704 VkCommandBuffer commandBuffer
)
1706 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1708 if (anv_batch_has_error(&cmd_buffer
->batch
))
1709 return cmd_buffer
->batch
.status
;
1711 /* We want every command buffer to start with the PMA fix in a known state,
1712 * so we disable it at the end of the command buffer.
1714 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1716 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1718 emit_isp_disable(cmd_buffer
);
1720 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1726 genX(CmdExecuteCommands
)(
1727 VkCommandBuffer commandBuffer
,
1728 uint32_t commandBufferCount
,
1729 const VkCommandBuffer
* pCmdBuffers
)
1731 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1733 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1735 if (anv_batch_has_error(&primary
->batch
))
1738 /* The secondary command buffers will assume that the PMA fix is disabled
1739 * when they begin executing. Make sure this is true.
1741 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1743 /* The secondary command buffer doesn't know which textures etc. have been
1744 * flushed prior to their execution. Apply those flushes now.
1746 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1748 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1749 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1751 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1752 assert(!anv_batch_has_error(&secondary
->batch
));
1754 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1755 if (secondary
->state
.conditional_render_enabled
) {
1756 if (!primary
->state
.conditional_render_enabled
) {
1757 /* Secondary buffer is constructed as if it will be executed
1758 * with conditional rendering, we should satisfy this dependency
1759 * regardless of conditional rendering being enabled in primary.
1761 struct gen_mi_builder b
;
1762 gen_mi_builder_init(&b
, &primary
->batch
);
1763 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1764 gen_mi_imm(UINT64_MAX
));
1769 if (secondary
->usage_flags
&
1770 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1771 /* If we're continuing a render pass from the primary, we need to
1772 * copy the surface states for the current subpass into the storage
1773 * we allocated for them in BeginCommandBuffer.
1775 struct anv_bo
*ss_bo
=
1776 primary
->device
->surface_state_pool
.block_pool
.bo
;
1777 struct anv_state src_state
= primary
->state
.render_pass_states
;
1778 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1779 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1781 genX(cmd_buffer_so_memcpy
)(primary
,
1782 (struct anv_address
) {
1784 .offset
= dst_state
.offset
,
1786 (struct anv_address
) {
1788 .offset
= src_state
.offset
,
1790 src_state
.alloc_size
);
1793 anv_cmd_buffer_add_secondary(primary
, secondary
);
1796 /* The secondary isn't counted in our VF cache tracking so we need to
1797 * invalidate the whole thing.
1799 if (GEN_GEN
>= 8 && GEN_GEN
<= 9) {
1800 primary
->state
.pending_pipe_bits
|=
1801 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1804 /* The secondary may have selected a different pipeline (3D or compute) and
1805 * may have changed the current L3$ configuration. Reset our tracking
1806 * variables to invalid values to ensure that we re-emit these in the case
1807 * where we do any draws or compute dispatches from the primary after the
1808 * secondary has returned.
1810 primary
->state
.current_pipeline
= UINT32_MAX
;
1811 primary
->state
.current_l3_config
= NULL
;
1812 primary
->state
.current_hash_scale
= 0;
1814 /* Each of the secondary command buffers will use its own state base
1815 * address. We need to re-emit state base address for the primary after
1816 * all of the secondaries are done.
1818 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1821 genX(cmd_buffer_emit_state_base_address
)(primary
);
1824 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1825 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1826 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1829 * Program the hardware to use the specified L3 configuration.
1832 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1833 const struct gen_l3_config
*cfg
)
1836 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1839 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1840 intel_logd("L3 config transition: ");
1841 gen_dump_l3_config(cfg
, stderr
);
1844 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1846 /* According to the hardware docs, the L3 partitioning can only be changed
1847 * while the pipeline is completely drained and the caches are flushed,
1848 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1850 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1851 pc
.DCFlushEnable
= true;
1852 pc
.PostSyncOperation
= NoWrite
;
1853 pc
.CommandStreamerStallEnable
= true;
1856 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1857 * invalidation of the relevant caches. Note that because RO invalidation
1858 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1859 * command is processed by the CS) we cannot combine it with the previous
1860 * stalling flush as the hardware documentation suggests, because that
1861 * would cause the CS to stall on previous rendering *after* RO
1862 * invalidation and wouldn't prevent the RO caches from being polluted by
1863 * concurrent rendering before the stall completes. This intentionally
1864 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1865 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1866 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1867 * already guarantee that there is no concurrent GPGPU kernel execution
1868 * (see SKL HSD 2132585).
1870 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1871 pc
.TextureCacheInvalidationEnable
= true;
1872 pc
.ConstantCacheInvalidationEnable
= true;
1873 pc
.InstructionCacheInvalidateEnable
= true;
1874 pc
.StateCacheInvalidationEnable
= true;
1875 pc
.PostSyncOperation
= NoWrite
;
1878 /* Now send a third stalling flush to make sure that invalidation is
1879 * complete when the L3 configuration registers are modified.
1881 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1882 pc
.DCFlushEnable
= true;
1883 pc
.PostSyncOperation
= NoWrite
;
1884 pc
.CommandStreamerStallEnable
= true;
1889 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1892 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1893 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1895 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1896 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1900 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1902 .SLMEnable
= has_slm
,
1905 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1906 * in L3CNTLREG register. The default setting of the bit is not the
1907 * desirable behavior.
1909 .ErrorDetectionBehaviorControl
= true,
1910 .UseFullWays
= true,
1912 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1913 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1914 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1915 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1917 /* Set up the L3 partitioning. */
1918 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1922 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1923 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1924 cfg
->n
[GEN_L3P_ALL
];
1925 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1926 cfg
->n
[GEN_L3P_ALL
];
1927 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1928 cfg
->n
[GEN_L3P_ALL
];
1930 assert(!cfg
->n
[GEN_L3P_ALL
]);
1932 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1933 * the matching space on the remaining banks has to be allocated to a
1934 * client (URB for all validated configurations) set to the
1935 * lower-bandwidth 2-bank address hashing mode.
1937 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1938 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1939 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1941 /* Minimum number of ways that can be allocated to the URB. */
1942 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1943 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1945 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1946 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1947 .ConvertDC_UC
= !has_dc
,
1948 .ConvertIS_UC
= !has_is
,
1949 .ConvertC_UC
= !has_c
,
1950 .ConvertT_UC
= !has_t
);
1952 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1953 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1954 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1956 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1957 .SLMEnable
= has_slm
,
1958 .URBLowBandwidth
= urb_low_bw
,
1959 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1961 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1963 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1964 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1966 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1967 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1968 .ISLowBandwidth
= 0,
1969 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1971 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1972 .TLowBandwidth
= 0);
1974 /* Set up the L3 partitioning. */
1975 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1976 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1977 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1980 if (cmd_buffer
->device
->physical
->cmd_parser_version
>= 4) {
1981 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1982 * them disabled to avoid crashing the system hard.
1984 uint32_t scratch1
, chicken3
;
1985 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1986 .L3AtomicDisable
= !has_dc
);
1987 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1988 .L3AtomicDisableMask
= true,
1989 .L3AtomicDisable
= !has_dc
);
1990 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1991 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1997 cmd_buffer
->state
.current_l3_config
= cfg
;
2001 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
2003 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
2004 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
2006 if (cmd_buffer
->device
->physical
->always_flush_cache
)
2007 bits
|= ANV_PIPE_FLUSH_BITS
| ANV_PIPE_INVALIDATE_BITS
;
2010 * From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
2012 * Write synchronization is a special case of end-of-pipe
2013 * synchronization that requires that the render cache and/or depth
2014 * related caches are flushed to memory, where the data will become
2015 * globally visible. This type of synchronization is required prior to
2016 * SW (CPU) actually reading the result data from memory, or initiating
2017 * an operation that will use as a read surface (such as a texture
2018 * surface) a previous render target and/or depth/stencil buffer
2021 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
2023 * Exercising the write cache flush bits (Render Target Cache Flush
2024 * Enable, Depth Cache Flush Enable, DC Flush) in PIPE_CONTROL only
2025 * ensures the write caches are flushed and doesn't guarantee the data
2026 * is globally visible.
2028 * SW can track the completion of the end-of-pipe-synchronization by
2029 * using "Notify Enable" and "PostSync Operation - Write Immediate
2030 * Data" in the PIPE_CONTROL command.
2032 * In other words, flushes are pipelined while invalidations are handled
2033 * immediately. Therefore, if we're flushing anything then we need to
2034 * schedule an end-of-pipe sync before any invalidations can happen.
2036 if (bits
& ANV_PIPE_FLUSH_BITS
)
2037 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2040 /* HSD 1209978178: docs say that before programming the aux table:
2042 * "Driver must ensure that the engine is IDLE but ensure it doesn't
2043 * add extra flushes in the case it knows that the engine is already
2046 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
))
2047 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2049 /* If we're going to do an invalidate and we have a pending end-of-pipe
2050 * sync that has yet to be resolved, we do the end-of-pipe sync now.
2052 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
2053 (bits
& ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
)) {
2054 bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
2055 bits
&= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2058 if (GEN_GEN
>= 12 &&
2059 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
2060 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
2061 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
2064 * Unified Cache (Tile Cache Disabled):
2066 * When the Color and Depth (Z) streams are enabled to be cached in
2067 * the DC space of L2, Software must use "Render Target Cache Flush
2068 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
2069 * Flush" for getting the color and depth (Z) write data to be
2070 * globally observable. In this mode of operation it is not required
2071 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
2073 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2076 /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
2077 * invalidates the instruction cache
2079 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
))
2080 bits
|= ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2082 if ((GEN_GEN
>= 8 && GEN_GEN
<= 9) &&
2083 (bits
& ANV_PIPE_CS_STALL_BIT
) &&
2084 (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
)) {
2085 /* If we are doing a VF cache invalidate AND a CS stall (it must be
2086 * both) then we can reset our vertex cache tracking.
2088 memset(cmd_buffer
->state
.gfx
.vb_dirty_ranges
, 0,
2089 sizeof(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
2090 memset(&cmd_buffer
->state
.gfx
.ib_dirty_range
, 0,
2091 sizeof(cmd_buffer
->state
.gfx
.ib_dirty_range
));
2094 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2096 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2097 * programmed prior to programming a PIPECONTROL command with "LRI
2098 * Post Sync Operation" in GPGPU mode of operation (i.e when
2099 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2101 * The same text exists a few rows below for Post Sync Op.
2103 * On Gen12 this is GEN:BUG:1607156449.
2105 if (bits
& ANV_PIPE_POST_SYNC_BIT
) {
2106 if ((GEN_GEN
== 9 || (GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0 */)) &&
2107 cmd_buffer
->state
.current_pipeline
== GPGPU
)
2108 bits
|= ANV_PIPE_CS_STALL_BIT
;
2109 bits
&= ~ANV_PIPE_POST_SYNC_BIT
;
2112 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2113 ANV_PIPE_END_OF_PIPE_SYNC_BIT
)) {
2114 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2116 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2118 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2119 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2120 pipe
.RenderTargetCacheFlushEnable
=
2121 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2123 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
2124 * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
2127 pipe
.DepthStallEnable
=
2128 pipe
.DepthCacheFlushEnable
|| (bits
& ANV_PIPE_DEPTH_STALL_BIT
);
2130 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
2133 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
2134 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2136 /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":
2138 * "The most common action to perform upon reaching a
2139 * synchronization point is to write a value out to memory. An
2140 * immediate value (included with the synchronization command) may
2144 * From Broadwell PRM, volume 7, "End-of-Pipe Synchronization":
2146 * "In case the data flushed out by the render engine is to be
2147 * read back in to the render engine in coherent manner, then the
2148 * render engine has to wait for the fence completion before
2149 * accessing the flushed data. This can be achieved by following
2150 * means on various products: PIPE_CONTROL command with CS Stall
2151 * and the required write caches flushed with Post-Sync-Operation
2152 * as Write Immediate Data.
2155 * - Workload-1 (3D/GPGPU/MEDIA)
2156 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2157 * Immediate Data, Required Write Cache Flush bits set)
2158 * - Workload-2 (Can use the data produce or output by
2161 if (bits
& ANV_PIPE_END_OF_PIPE_SYNC_BIT
) {
2162 pipe
.CommandStreamerStallEnable
= true;
2163 pipe
.PostSyncOperation
= WriteImmediateData
;
2164 pipe
.Address
= (struct anv_address
) {
2165 .bo
= cmd_buffer
->device
->workaround_bo
,
2171 * According to the Broadwell documentation, any PIPE_CONTROL with the
2172 * "Command Streamer Stall" bit set must also have another bit set,
2173 * with five different options:
2175 * - Render Target Cache Flush
2176 * - Depth Cache Flush
2177 * - Stall at Pixel Scoreboard
2178 * - Post-Sync Operation
2182 * I chose "Stall at Pixel Scoreboard" since that's what we use in
2183 * mesa and it seems to work fine. The choice is fairly arbitrary.
2185 if (pipe
.CommandStreamerStallEnable
&&
2186 !pipe
.RenderTargetCacheFlushEnable
&&
2187 !pipe
.DepthCacheFlushEnable
&&
2188 !pipe
.StallAtPixelScoreboard
&&
2189 !pipe
.PostSyncOperation
&&
2190 !pipe
.DepthStallEnable
&&
2191 !pipe
.DCFlushEnable
)
2192 pipe
.StallAtPixelScoreboard
= true;
2195 /* If a render target flush was emitted, then we can toggle off the bit
2196 * saying that render target writes are ongoing.
2198 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
2199 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
2201 if (GEN_IS_HASWELL
) {
2202 /* Haswell needs addition work-arounds:
2204 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
2207 * PIPE_CONTROL command with the CS Stall and the required write
2208 * caches flushed with Post-SyncOperation as Write Immediate Data
2209 * followed by eight dummy MI_STORE_DATA_IMM (write to scratch
2214 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2215 * Immediate Data, Required Write Cache Flush bits set)
2216 * - MI_STORE_DATA_IMM (8 times) (Dummy data, Scratch Address)
2217 * - Workload-2 (Can use the data produce or output by
2220 * Unfortunately, both the PRMs and the internal docs are a bit
2221 * out-of-date in this regard. What the windows driver does (and
2222 * this appears to actually work) is to emit a register read from the
2223 * memory address written by the pipe control above.
2225 * What register we load into doesn't matter. We choose an indirect
2226 * rendering register because we know it always exists and it's one
2227 * of the first registers the command parser allows us to write. If
2228 * you don't have command parser support in your kernel (pre-4.2),
2229 * this will get turned into MI_NOOP and you won't get the
2230 * workaround. Unfortunately, there's just not much we can do in
2231 * that case. This register is perfectly safe to write since we
2232 * always re-load all of the indirect draw registers right before
2233 * 3DPRIMITIVE when needed anyway.
2235 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2236 lrm
.RegisterAddress
= 0x243C; /* GEN7_3DPRIM_START_INSTANCE */
2237 lrm
.MemoryAddress
= (struct anv_address
) {
2238 .bo
= cmd_buffer
->device
->workaround_bo
,
2244 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2245 ANV_PIPE_END_OF_PIPE_SYNC_BIT
);
2248 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
2249 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2251 * "If the VF Cache Invalidation Enable is set to a 1 in a
2252 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
2253 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
2254 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
2257 * This appears to hang Broadwell, so we restrict it to just gen9.
2259 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
2260 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
2262 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2263 pipe
.StateCacheInvalidationEnable
=
2264 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
2265 pipe
.ConstantCacheInvalidationEnable
=
2266 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2267 pipe
.VFCacheInvalidationEnable
=
2268 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2269 pipe
.TextureCacheInvalidationEnable
=
2270 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2271 pipe
.InstructionCacheInvalidateEnable
=
2272 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
2274 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2276 * "When VF Cache Invalidate is set “Post Sync Operation” must be
2277 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
2278 * “Write Timestamp”.
2280 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
2281 pipe
.PostSyncOperation
= WriteImmediateData
;
2283 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
2288 if ((bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
) &&
2289 cmd_buffer
->device
->info
.has_aux_map
) {
2290 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2291 lri
.RegisterOffset
= GENX(GFX_CCS_AUX_INV_num
);
2297 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
2300 cmd_buffer
->state
.pending_pipe_bits
= bits
;
2303 void genX(CmdPipelineBarrier
)(
2304 VkCommandBuffer commandBuffer
,
2305 VkPipelineStageFlags srcStageMask
,
2306 VkPipelineStageFlags destStageMask
,
2308 uint32_t memoryBarrierCount
,
2309 const VkMemoryBarrier
* pMemoryBarriers
,
2310 uint32_t bufferMemoryBarrierCount
,
2311 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
2312 uint32_t imageMemoryBarrierCount
,
2313 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
2315 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2317 /* XXX: Right now, we're really dumb and just flush whatever categories
2318 * the app asks for. One of these days we may make this a bit better
2319 * but right now that's all the hardware allows for in most areas.
2321 VkAccessFlags src_flags
= 0;
2322 VkAccessFlags dst_flags
= 0;
2324 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
2325 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
2326 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
2329 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
2330 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
2331 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
2334 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
2335 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
2336 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
2337 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
2338 const VkImageSubresourceRange
*range
=
2339 &pImageMemoryBarriers
[i
].subresourceRange
;
2341 uint32_t base_layer
, layer_count
;
2342 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2344 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
2346 base_layer
= range
->baseArrayLayer
;
2347 layer_count
= anv_get_layerCount(image
, range
);
2350 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2351 transition_depth_buffer(cmd_buffer
, image
,
2352 base_layer
, layer_count
,
2353 pImageMemoryBarriers
[i
].oldLayout
,
2354 pImageMemoryBarriers
[i
].newLayout
);
2357 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
2358 transition_stencil_buffer(cmd_buffer
, image
,
2359 range
->baseMipLevel
,
2360 anv_get_levelCount(image
, range
),
2361 base_layer
, layer_count
,
2362 pImageMemoryBarriers
[i
].oldLayout
,
2363 pImageMemoryBarriers
[i
].newLayout
);
2366 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2367 VkImageAspectFlags color_aspects
=
2368 anv_image_expand_aspects(image
, range
->aspectMask
);
2369 uint32_t aspect_bit
;
2370 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
2371 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
2372 range
->baseMipLevel
,
2373 anv_get_levelCount(image
, range
),
2374 base_layer
, layer_count
,
2375 pImageMemoryBarriers
[i
].oldLayout
,
2376 pImageMemoryBarriers
[i
].newLayout
);
2381 cmd_buffer
->state
.pending_pipe_bits
|=
2382 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2383 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2387 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2389 VkShaderStageFlags stages
=
2390 cmd_buffer
->state
.gfx
.pipeline
->active_stages
;
2392 /* In order to avoid thrash, we assume that vertex and fragment stages
2393 * always exist. In the rare case where one is missing *and* the other
2394 * uses push concstants, this may be suboptimal. However, avoiding stalls
2395 * seems more important.
2397 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2399 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2403 const unsigned push_constant_kb
= 32;
2404 #elif GEN_IS_HASWELL
2405 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2407 const unsigned push_constant_kb
= 16;
2410 const unsigned num_stages
=
2411 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2412 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2414 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2415 * units of 2KB. Incidentally, these are the same platforms that have
2416 * 32KB worth of push constant space.
2418 if (push_constant_kb
== 32)
2419 size_per_stage
&= ~1u;
2421 uint32_t kb_used
= 0;
2422 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2423 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2424 anv_batch_emit(&cmd_buffer
->batch
,
2425 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2426 alloc
._3DCommandSubOpcode
= 18 + i
;
2427 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2428 alloc
.ConstantBufferSize
= push_size
;
2430 kb_used
+= push_size
;
2433 anv_batch_emit(&cmd_buffer
->batch
,
2434 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2435 alloc
.ConstantBufferOffset
= kb_used
;
2436 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2439 cmd_buffer
->state
.push_constant_stages
= stages
;
2441 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2443 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2444 * the next 3DPRIMITIVE command after programming the
2445 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2447 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2448 * pipeline setup, we need to dirty push constants.
2450 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2453 static struct anv_address
2454 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2455 struct anv_descriptor_set
*set
)
2458 /* This is a normal descriptor set */
2459 return (struct anv_address
) {
2460 .bo
= set
->pool
->bo
,
2461 .offset
= set
->desc_mem
.offset
,
2464 /* This is a push descriptor set. We have to flag it as used on the GPU
2465 * so that the next time we push descriptors, we grab a new memory.
2467 struct anv_push_descriptor_set
*push_set
=
2468 (struct anv_push_descriptor_set
*)set
;
2469 push_set
->set_used_on_gpu
= true;
2471 return (struct anv_address
) {
2472 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2473 .offset
= set
->desc_mem
.offset
,
2479 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2480 struct anv_cmd_pipeline_state
*pipe_state
,
2481 struct anv_shader_bin
*shader
,
2482 struct anv_state
*bt_state
)
2484 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2485 uint32_t state_offset
;
2487 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2488 if (map
->surface_count
== 0) {
2489 *bt_state
= (struct anv_state
) { 0, };
2493 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2496 uint32_t *bt_map
= bt_state
->map
;
2498 if (bt_state
->map
== NULL
)
2499 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2501 /* We only need to emit relocs if we're not using softpin. If we are using
2502 * softpin then we always keep all user-allocated memory objects resident.
2504 const bool need_client_mem_relocs
=
2505 !cmd_buffer
->device
->physical
->use_softpin
;
2507 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2508 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2510 struct anv_state surface_state
;
2512 switch (binding
->set
) {
2513 case ANV_DESCRIPTOR_SET_NULL
:
2517 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
:
2518 /* Color attachment binding */
2519 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2520 if (binding
->index
< subpass
->color_count
) {
2521 const unsigned att
=
2522 subpass
->color_attachments
[binding
->index
].attachment
;
2524 /* From the Vulkan 1.0.46 spec:
2526 * "If any color or depth/stencil attachments are
2527 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2530 if (att
== VK_ATTACHMENT_UNUSED
) {
2531 surface_state
= cmd_buffer
->state
.null_surface_state
;
2533 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2536 surface_state
= cmd_buffer
->state
.null_surface_state
;
2539 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2542 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
: {
2543 struct anv_state surface_state
=
2544 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2546 struct anv_address constant_data
= {
2547 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2548 .offset
= shader
->constant_data
.offset
,
2550 unsigned constant_data_size
= shader
->constant_data_size
;
2552 const enum isl_format format
=
2553 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2554 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2555 surface_state
, format
,
2556 constant_data
, constant_data_size
, 1);
2558 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2559 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2563 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
: {
2564 /* This is always the first binding for compute shaders */
2565 assert(shader
->stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2567 struct anv_state surface_state
=
2568 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2570 const enum isl_format format
=
2571 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2572 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2574 cmd_buffer
->state
.compute
.num_workgroups
,
2576 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2577 if (need_client_mem_relocs
) {
2578 add_surface_reloc(cmd_buffer
, surface_state
,
2579 cmd_buffer
->state
.compute
.num_workgroups
);
2584 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2585 /* This is a descriptor set buffer so the set index is actually
2586 * given by binding->binding. (Yes, that's confusing.)
2588 struct anv_descriptor_set
*set
=
2589 pipe_state
->descriptors
[binding
->index
];
2590 assert(set
->desc_mem
.alloc_size
);
2591 assert(set
->desc_surface_state
.alloc_size
);
2592 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2593 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2594 anv_descriptor_set_address(cmd_buffer
, set
));
2599 assert(binding
->set
< MAX_SETS
);
2600 const struct anv_descriptor
*desc
=
2601 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2603 switch (desc
->type
) {
2604 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2605 /* Nothing for us to do here */
2608 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2609 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2610 struct anv_surface_state sstate
=
2611 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2612 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2613 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2614 surface_state
= sstate
.state
;
2615 assert(surface_state
.alloc_size
);
2616 if (need_client_mem_relocs
)
2617 add_surface_state_relocs(cmd_buffer
, sstate
);
2620 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2621 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2622 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2623 /* For depth and stencil input attachments, we treat it like any
2624 * old texture that a user may have bound.
2626 assert(desc
->image_view
->n_planes
== 1);
2627 struct anv_surface_state sstate
=
2628 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2629 desc
->image_view
->planes
[0].general_sampler_surface_state
:
2630 desc
->image_view
->planes
[0].optimal_sampler_surface_state
;
2631 surface_state
= sstate
.state
;
2632 assert(surface_state
.alloc_size
);
2633 if (need_client_mem_relocs
)
2634 add_surface_state_relocs(cmd_buffer
, sstate
);
2636 /* For color input attachments, we create the surface state at
2637 * vkBeginRenderPass time so that we can include aux and clear
2638 * color information.
2640 assert(binding
->input_attachment_index
< subpass
->input_count
);
2641 const unsigned subpass_att
= binding
->input_attachment_index
;
2642 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2643 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2647 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2648 struct anv_surface_state sstate
= (binding
->write_only
)
2649 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2650 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2651 surface_state
= sstate
.state
;
2652 assert(surface_state
.alloc_size
);
2653 if (need_client_mem_relocs
)
2654 add_surface_state_relocs(cmd_buffer
, sstate
);
2658 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2659 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2660 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2661 surface_state
= desc
->buffer_view
->surface_state
;
2662 assert(surface_state
.alloc_size
);
2663 if (need_client_mem_relocs
) {
2664 add_surface_reloc(cmd_buffer
, surface_state
,
2665 desc
->buffer_view
->address
);
2669 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2670 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2671 /* Compute the offset within the buffer */
2672 struct anv_push_constants
*push
=
2673 &cmd_buffer
->state
.push_constants
[shader
->stage
];
2675 uint32_t dynamic_offset
=
2676 push
->dynamic_offsets
[binding
->dynamic_offset_index
];
2677 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2678 /* Clamp to the buffer size */
2679 offset
= MIN2(offset
, desc
->buffer
->size
);
2680 /* Clamp the range to the buffer size */
2681 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2683 /* Align the range for consistency */
2684 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
)
2685 range
= align_u32(range
, ANV_UBO_BOUNDS_CHECK_ALIGNMENT
);
2687 struct anv_address address
=
2688 anv_address_add(desc
->buffer
->address
, offset
);
2691 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2692 enum isl_format format
=
2693 anv_isl_format_for_descriptor_type(desc
->type
);
2695 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2696 format
, address
, range
, 1);
2697 if (need_client_mem_relocs
)
2698 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2702 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2703 surface_state
= (binding
->write_only
)
2704 ? desc
->buffer_view
->writeonly_storage_surface_state
2705 : desc
->buffer_view
->storage_surface_state
;
2706 assert(surface_state
.alloc_size
);
2707 if (need_client_mem_relocs
) {
2708 add_surface_reloc(cmd_buffer
, surface_state
,
2709 desc
->buffer_view
->address
);
2714 assert(!"Invalid descriptor type");
2717 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2727 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2728 struct anv_cmd_pipeline_state
*pipe_state
,
2729 struct anv_shader_bin
*shader
,
2730 struct anv_state
*state
)
2732 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2733 if (map
->sampler_count
== 0) {
2734 *state
= (struct anv_state
) { 0, };
2738 uint32_t size
= map
->sampler_count
* 16;
2739 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2741 if (state
->map
== NULL
)
2742 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2744 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2745 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2746 const struct anv_descriptor
*desc
=
2747 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2749 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2750 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2753 struct anv_sampler
*sampler
= desc
->sampler
;
2755 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2756 * happens to be zero.
2758 if (sampler
== NULL
)
2761 memcpy(state
->map
+ (s
* 16),
2762 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2769 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
,
2770 struct anv_cmd_pipeline_state
*pipe_state
,
2771 struct anv_shader_bin
**shaders
,
2772 uint32_t num_shaders
)
2774 const VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
;
2775 VkShaderStageFlags flushed
= 0;
2777 VkResult result
= VK_SUCCESS
;
2778 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2782 gl_shader_stage stage
= shaders
[i
]->stage
;
2783 VkShaderStageFlags vk_stage
= mesa_to_vk_shader_stage(stage
);
2784 if ((vk_stage
& dirty
) == 0)
2787 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2788 &cmd_buffer
->state
.samplers
[stage
]);
2789 if (result
!= VK_SUCCESS
)
2791 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2792 &cmd_buffer
->state
.binding_tables
[stage
]);
2793 if (result
!= VK_SUCCESS
)
2796 flushed
|= vk_stage
;
2799 if (result
!= VK_SUCCESS
) {
2800 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2802 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2803 if (result
!= VK_SUCCESS
)
2806 /* Re-emit state base addresses so we get the new surface state base
2807 * address before we start emitting binding tables etc.
2809 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2811 /* Re-emit all active binding tables */
2814 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2818 gl_shader_stage stage
= shaders
[i
]->stage
;
2820 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2821 &cmd_buffer
->state
.samplers
[stage
]);
2822 if (result
!= VK_SUCCESS
) {
2823 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2826 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2827 &cmd_buffer
->state
.binding_tables
[stage
]);
2828 if (result
!= VK_SUCCESS
) {
2829 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2833 flushed
|= mesa_to_vk_shader_stage(stage
);
2837 cmd_buffer
->state
.descriptors_dirty
&= ~flushed
;
2843 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2846 static const uint32_t sampler_state_opcodes
[] = {
2847 [MESA_SHADER_VERTEX
] = 43,
2848 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2849 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2850 [MESA_SHADER_GEOMETRY
] = 46,
2851 [MESA_SHADER_FRAGMENT
] = 47,
2852 [MESA_SHADER_COMPUTE
] = 0,
2855 static const uint32_t binding_table_opcodes
[] = {
2856 [MESA_SHADER_VERTEX
] = 38,
2857 [MESA_SHADER_TESS_CTRL
] = 39,
2858 [MESA_SHADER_TESS_EVAL
] = 40,
2859 [MESA_SHADER_GEOMETRY
] = 41,
2860 [MESA_SHADER_FRAGMENT
] = 42,
2861 [MESA_SHADER_COMPUTE
] = 0,
2864 anv_foreach_stage(s
, stages
) {
2865 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2866 assert(binding_table_opcodes
[s
] > 0);
2868 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2869 anv_batch_emit(&cmd_buffer
->batch
,
2870 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2871 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2872 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2876 /* Always emit binding table pointers if we're asked to, since on SKL
2877 * this is what flushes push constants. */
2878 anv_batch_emit(&cmd_buffer
->batch
,
2879 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2880 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2881 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2886 static struct anv_address
2887 get_push_range_address(struct anv_cmd_buffer
*cmd_buffer
,
2888 gl_shader_stage stage
,
2889 const struct anv_push_range
*range
)
2891 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2892 switch (range
->set
) {
2893 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2894 /* This is a descriptor set buffer so the set index is
2895 * actually given by binding->binding. (Yes, that's
2898 struct anv_descriptor_set
*set
=
2899 gfx_state
->base
.descriptors
[range
->index
];
2900 return anv_descriptor_set_address(cmd_buffer
, set
);
2903 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
: {
2904 struct anv_state state
=
2905 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2906 return (struct anv_address
) {
2907 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2908 .offset
= state
.offset
,
2913 assert(range
->set
< MAX_SETS
);
2914 struct anv_descriptor_set
*set
=
2915 gfx_state
->base
.descriptors
[range
->set
];
2916 const struct anv_descriptor
*desc
=
2917 &set
->descriptors
[range
->index
];
2919 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2920 return desc
->buffer_view
->address
;
2922 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2923 struct anv_push_constants
*push
=
2924 &cmd_buffer
->state
.push_constants
[stage
];
2925 uint32_t dynamic_offset
=
2926 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2927 return anv_address_add(desc
->buffer
->address
,
2928 desc
->offset
+ dynamic_offset
);
2935 /** Returns the size in bytes of the bound buffer
2937 * The range is relative to the start of the buffer, not the start of the
2938 * range. The returned range may be smaller than
2940 * (range->start + range->length) * 32;
2943 get_push_range_bound_size(struct anv_cmd_buffer
*cmd_buffer
,
2944 gl_shader_stage stage
,
2945 const struct anv_push_range
*range
)
2947 assert(stage
!= MESA_SHADER_COMPUTE
);
2948 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2949 switch (range
->set
) {
2950 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2951 struct anv_descriptor_set
*set
=
2952 gfx_state
->base
.descriptors
[range
->index
];
2953 assert(range
->start
* 32 < set
->desc_mem
.alloc_size
);
2954 assert((range
->start
+ range
->length
) * 32 <= set
->desc_mem
.alloc_size
);
2955 return set
->desc_mem
.alloc_size
;
2958 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
:
2959 return (range
->start
+ range
->length
) * 32;
2962 assert(range
->set
< MAX_SETS
);
2963 struct anv_descriptor_set
*set
=
2964 gfx_state
->base
.descriptors
[range
->set
];
2965 const struct anv_descriptor
*desc
=
2966 &set
->descriptors
[range
->index
];
2968 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2969 return desc
->buffer_view
->range
;
2971 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2972 /* Compute the offset within the buffer */
2973 struct anv_push_constants
*push
=
2974 &cmd_buffer
->state
.push_constants
[stage
];
2975 uint32_t dynamic_offset
=
2976 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2977 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2978 /* Clamp to the buffer size */
2979 offset
= MIN2(offset
, desc
->buffer
->size
);
2980 /* Clamp the range to the buffer size */
2981 uint32_t bound_range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2983 /* Align the range for consistency */
2984 bound_range
= align_u32(bound_range
, ANV_UBO_BOUNDS_CHECK_ALIGNMENT
);
2993 cmd_buffer_emit_push_constant(struct anv_cmd_buffer
*cmd_buffer
,
2994 gl_shader_stage stage
,
2995 struct anv_address
*buffers
,
2996 unsigned buffer_count
)
2998 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2999 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3001 static const uint32_t push_constant_opcodes
[] = {
3002 [MESA_SHADER_VERTEX
] = 21,
3003 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3004 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3005 [MESA_SHADER_GEOMETRY
] = 22,
3006 [MESA_SHADER_FRAGMENT
] = 23,
3007 [MESA_SHADER_COMPUTE
] = 0,
3010 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3011 assert(push_constant_opcodes
[stage
] > 0);
3013 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
3014 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3016 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3017 const struct anv_pipeline_bind_map
*bind_map
=
3018 &pipeline
->shaders
[stage
]->bind_map
;
3021 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3024 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3025 /* The Skylake PRM contains the following restriction:
3027 * "The driver must ensure The following case does not occur
3028 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3029 * buffer 3 read length equal to zero committed followed by a
3030 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3033 * To avoid this, we program the buffers in the highest slots.
3034 * This way, slot 0 is only used if slot 3 is also used.
3036 assert(buffer_count
<= 4);
3037 const unsigned shift
= 4 - buffer_count
;
3038 for (unsigned i
= 0; i
< buffer_count
; i
++) {
3039 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3041 /* At this point we only have non-empty ranges */
3042 assert(range
->length
> 0);
3044 /* For Ivy Bridge, make sure we only set the first range (actual
3047 assert((GEN_GEN
>= 8 || GEN_IS_HASWELL
) || i
== 0);
3049 c
.ConstantBody
.ReadLength
[i
+ shift
] = range
->length
;
3050 c
.ConstantBody
.Buffer
[i
+ shift
] =
3051 anv_address_add(buffers
[i
], range
->start
* 32);
3054 /* For Ivy Bridge, push constants are relative to dynamic state
3055 * base address and we only ever push actual push constants.
3057 if (bind_map
->push_ranges
[0].length
> 0) {
3058 assert(buffer_count
== 1);
3059 assert(bind_map
->push_ranges
[0].set
==
3060 ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
);
3061 assert(buffers
[0].bo
==
3062 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
);
3063 c
.ConstantBody
.ReadLength
[0] = bind_map
->push_ranges
[0].length
;
3064 c
.ConstantBody
.Buffer
[0].bo
= NULL
;
3065 c
.ConstantBody
.Buffer
[0].offset
= buffers
[0].offset
;
3067 assert(bind_map
->push_ranges
[1].length
== 0);
3068 assert(bind_map
->push_ranges
[2].length
== 0);
3069 assert(bind_map
->push_ranges
[3].length
== 0);
3077 cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer
*cmd_buffer
,
3078 uint32_t shader_mask
,
3079 struct anv_address
*buffers
,
3080 uint32_t buffer_count
)
3082 if (buffer_count
== 0) {
3083 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_ALL
), c
) {
3084 c
.ShaderUpdateEnable
= shader_mask
;
3085 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3090 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3091 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3093 static const uint32_t push_constant_opcodes
[] = {
3094 [MESA_SHADER_VERTEX
] = 21,
3095 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3096 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3097 [MESA_SHADER_GEOMETRY
] = 22,
3098 [MESA_SHADER_FRAGMENT
] = 23,
3099 [MESA_SHADER_COMPUTE
] = 0,
3102 gl_shader_stage stage
= vk_to_mesa_shader_stage(shader_mask
);
3103 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3104 assert(push_constant_opcodes
[stage
] > 0);
3106 const struct anv_pipeline_bind_map
*bind_map
=
3107 &pipeline
->shaders
[stage
]->bind_map
;
3110 const uint32_t buffer_mask
= (1 << buffer_count
) - 1;
3111 const uint32_t num_dwords
= 2 + 2 * buffer_count
;
3113 dw
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3114 GENX(3DSTATE_CONSTANT_ALL
),
3115 .ShaderUpdateEnable
= shader_mask
,
3116 .PointerBufferMask
= buffer_mask
,
3117 .MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
);
3119 for (int i
= 0; i
< buffer_count
; i
++) {
3120 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3121 GENX(3DSTATE_CONSTANT_ALL_DATA_pack
)(
3122 &cmd_buffer
->batch
, dw
+ 2 + i
* 2,
3123 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA
)) {
3124 .PointerToConstantBuffer
=
3125 anv_address_add(buffers
[i
], range
->start
* 32),
3126 .ConstantBufferReadLength
= range
->length
,
3133 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
3134 VkShaderStageFlags dirty_stages
)
3136 VkShaderStageFlags flushed
= 0;
3137 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3138 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3141 uint32_t nobuffer_stages
= 0;
3144 anv_foreach_stage(stage
, dirty_stages
) {
3145 unsigned buffer_count
= 0;
3146 flushed
|= mesa_to_vk_shader_stage(stage
);
3147 UNUSED
uint32_t max_push_range
= 0;
3149 struct anv_address buffers
[4] = {};
3150 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3151 const struct anv_pipeline_bind_map
*bind_map
=
3152 &pipeline
->shaders
[stage
]->bind_map
;
3153 struct anv_push_constants
*push
=
3154 &cmd_buffer
->state
.push_constants
[stage
];
3156 if (cmd_buffer
->device
->robust_buffer_access
) {
3157 push
->push_reg_mask
= 0;
3158 /* Start of the current range in the shader, relative to the start
3159 * of push constants in the shader.
3161 unsigned range_start_reg
= 0;
3162 for (unsigned i
= 0; i
< 4; i
++) {
3163 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3164 if (range
->length
== 0)
3167 unsigned bound_size
=
3168 get_push_range_bound_size(cmd_buffer
, stage
, range
);
3169 if (bound_size
>= range
->start
* 32) {
3170 unsigned bound_regs
=
3171 MIN2(DIV_ROUND_UP(bound_size
, 32) - range
->start
,
3173 assert(range_start_reg
+ bound_regs
<= 64);
3174 push
->push_reg_mask
|= BITFIELD64_RANGE(range_start_reg
,
3178 cmd_buffer
->state
.push_constants_dirty
|=
3179 mesa_to_vk_shader_stage(stage
);
3181 range_start_reg
+= range
->length
;
3185 /* We have to gather buffer addresses as a second step because the
3186 * loop above puts data into the push constant area and the call to
3187 * get_push_range_address is what locks our push constants and copies
3188 * them into the actual GPU buffer. If we did the two loops at the
3189 * same time, we'd risk only having some of the sizes in the push
3190 * constant buffer when we did the copy.
3192 for (unsigned i
= 0; i
< 4; i
++) {
3193 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3194 if (range
->length
== 0)
3197 buffers
[i
] = get_push_range_address(cmd_buffer
, stage
, range
);
3198 max_push_range
= MAX2(max_push_range
, range
->length
);
3202 /* We have at most 4 buffers but they should be tightly packed */
3203 for (unsigned i
= buffer_count
; i
< 4; i
++)
3204 assert(bind_map
->push_ranges
[i
].length
== 0);
3208 /* If this stage doesn't have any push constants, emit it later in a
3209 * single CONSTANT_ALL packet.
3211 if (buffer_count
== 0) {
3212 nobuffer_stages
|= 1 << stage
;
3216 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
3217 * contains only 5 bits, so we can only use it for buffers smaller than
3220 if (max_push_range
< 32) {
3221 cmd_buffer_emit_push_constant_all(cmd_buffer
, 1 << stage
,
3222 buffers
, buffer_count
);
3227 cmd_buffer_emit_push_constant(cmd_buffer
, stage
, buffers
, buffer_count
);
3231 if (nobuffer_stages
)
3232 cmd_buffer_emit_push_constant_all(cmd_buffer
, nobuffer_stages
, NULL
, 0);
3235 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
3239 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3241 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3244 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
3246 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
3248 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
3250 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3252 /* Apply any pending pipeline flushes we may have. We want to apply them
3253 * now because, if any of those flushes are for things like push constants,
3254 * the GPU will read the state at weird times.
3256 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3258 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
3259 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
3260 vb_emit
|= pipeline
->vb_used
;
3263 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
3264 const uint32_t num_dwords
= 1 + num_buffers
* 4;
3266 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3267 GENX(3DSTATE_VERTEX_BUFFERS
));
3269 for_each_bit(vb
, vb_emit
) {
3270 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
3271 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
3273 struct GENX(VERTEX_BUFFER_STATE
) state
= {
3274 .VertexBufferIndex
= vb
,
3276 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
3278 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
3279 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
3282 .AddressModifyEnable
= true,
3283 .BufferPitch
= pipeline
->vb
[vb
].stride
,
3284 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
3287 .BufferSize
= buffer
->size
- offset
3289 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
3293 #if GEN_GEN >= 8 && GEN_GEN <= 9
3294 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
, vb
,
3295 state
.BufferStartingAddress
,
3299 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
3304 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
3307 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
3308 /* We don't need any per-buffer dirty tracking because you're not
3309 * allowed to bind different XFB buffers while XFB is enabled.
3311 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3312 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
3313 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3315 sob
.SOBufferIndex
= idx
;
3317 sob
._3DCommandOpcode
= 0;
3318 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
3321 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
3322 sob
.SOBufferEnable
= true;
3323 sob
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
,
3324 sob
.StreamOffsetWriteEnable
= false;
3325 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
3327 /* Size is in DWords - 1 */
3328 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
3333 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
3335 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3339 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
3340 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
3342 /* If the pipeline changed, we may need to re-allocate push constant
3345 cmd_buffer_alloc_push_constants(cmd_buffer
);
3349 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
3350 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
3351 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
3353 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
3354 * stall needs to be sent just prior to any 3DSTATE_VS,
3355 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
3356 * 3DSTATE_BINDING_TABLE_POINTER_VS,
3357 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
3358 * PIPE_CONTROL needs to be sent before any combination of VS
3359 * associated 3DSTATE."
3361 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3362 pc
.DepthStallEnable
= true;
3363 pc
.PostSyncOperation
= WriteImmediateData
;
3365 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
3370 /* Render targets live in the same binding table as fragment descriptors */
3371 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
3372 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
3374 /* We emit the binding tables and sampler tables first, then emit push
3375 * constants and then finally emit binding table and sampler table
3376 * pointers. It has to happen in this order, since emitting the binding
3377 * tables may change the push constants (in case of storage images). After
3378 * emitting push constants, on SKL+ we have to emit the corresponding
3379 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
3382 if (cmd_buffer
->state
.descriptors_dirty
) {
3383 dirty
= flush_descriptor_sets(cmd_buffer
,
3384 &cmd_buffer
->state
.gfx
.base
,
3386 ARRAY_SIZE(pipeline
->shaders
));
3389 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
3390 /* Because we're pushing UBOs, we have to push whenever either
3391 * descriptors or push constants is dirty.
3393 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
3394 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
3395 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
3399 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
3401 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
3402 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
3404 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
3405 ANV_CMD_DIRTY_PIPELINE
)) {
3406 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
3407 pipeline
->depth_clamp_enable
);
3410 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
3411 ANV_CMD_DIRTY_RENDER_TARGETS
))
3412 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
3414 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
3418 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
3419 struct anv_address addr
,
3420 uint32_t size
, uint32_t index
)
3422 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
3423 GENX(3DSTATE_VERTEX_BUFFERS
));
3425 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
3426 &(struct GENX(VERTEX_BUFFER_STATE
)) {
3427 .VertexBufferIndex
= index
,
3428 .AddressModifyEnable
= true,
3430 .MOCS
= addr
.bo
? anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
) : 0,
3431 .NullVertexBuffer
= size
== 0,
3433 .BufferStartingAddress
= addr
,
3436 .BufferStartingAddress
= addr
,
3437 .EndAddress
= anv_address_add(addr
, size
),
3441 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
,
3446 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
3447 struct anv_address addr
)
3449 emit_vertex_bo(cmd_buffer
, addr
, addr
.bo
? 8 : 0, ANV_SVGS_VB_INDEX
);
3453 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
3454 uint32_t base_vertex
, uint32_t base_instance
)
3456 if (base_vertex
== 0 && base_instance
== 0) {
3457 emit_base_vertex_instance_bo(cmd_buffer
, ANV_NULL_ADDRESS
);
3459 struct anv_state id_state
=
3460 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
3462 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
3463 ((uint32_t *)id_state
.map
)[1] = base_instance
;
3465 struct anv_address addr
= {
3466 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3467 .offset
= id_state
.offset
,
3470 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
3475 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
3477 struct anv_state state
=
3478 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
3480 ((uint32_t *)state
.map
)[0] = draw_index
;
3482 struct anv_address addr
= {
3483 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3484 .offset
= state
.offset
,
3487 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
3491 update_dirty_vbs_for_gen8_vb_flush(struct anv_cmd_buffer
*cmd_buffer
,
3492 uint32_t access_type
)
3494 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3495 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3497 uint64_t vb_used
= pipeline
->vb_used
;
3498 if (vs_prog_data
->uses_firstvertex
||
3499 vs_prog_data
->uses_baseinstance
)
3500 vb_used
|= 1ull << ANV_SVGS_VB_INDEX
;
3501 if (vs_prog_data
->uses_drawid
)
3502 vb_used
|= 1ull << ANV_DRAWID_VB_INDEX
;
3504 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(cmd_buffer
,
3505 access_type
== RANDOM
,
3510 VkCommandBuffer commandBuffer
,
3511 uint32_t vertexCount
,
3512 uint32_t instanceCount
,
3513 uint32_t firstVertex
,
3514 uint32_t firstInstance
)
3516 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3517 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3518 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3520 if (anv_batch_has_error(&cmd_buffer
->batch
))
3523 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3525 if (cmd_buffer
->state
.conditional_render_enabled
)
3526 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3528 if (vs_prog_data
->uses_firstvertex
||
3529 vs_prog_data
->uses_baseinstance
)
3530 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3531 if (vs_prog_data
->uses_drawid
)
3532 emit_draw_index(cmd_buffer
, 0);
3534 /* Emitting draw index or vertex index BOs may result in needing
3535 * additional VF cache flushes.
3537 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3539 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3540 * different views. We need to multiply instanceCount by the view count.
3542 if (!pipeline
->use_primitive_replication
)
3543 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3545 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3546 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3547 prim
.VertexAccessType
= SEQUENTIAL
;
3548 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3549 prim
.VertexCountPerInstance
= vertexCount
;
3550 prim
.StartVertexLocation
= firstVertex
;
3551 prim
.InstanceCount
= instanceCount
;
3552 prim
.StartInstanceLocation
= firstInstance
;
3553 prim
.BaseVertexLocation
= 0;
3556 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3559 void genX(CmdDrawIndexed
)(
3560 VkCommandBuffer commandBuffer
,
3561 uint32_t indexCount
,
3562 uint32_t instanceCount
,
3563 uint32_t firstIndex
,
3564 int32_t vertexOffset
,
3565 uint32_t firstInstance
)
3567 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3568 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3569 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3571 if (anv_batch_has_error(&cmd_buffer
->batch
))
3574 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3576 if (cmd_buffer
->state
.conditional_render_enabled
)
3577 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3579 if (vs_prog_data
->uses_firstvertex
||
3580 vs_prog_data
->uses_baseinstance
)
3581 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
3582 if (vs_prog_data
->uses_drawid
)
3583 emit_draw_index(cmd_buffer
, 0);
3585 /* Emitting draw index or vertex index BOs may result in needing
3586 * additional VF cache flushes.
3588 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3590 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3591 * different views. We need to multiply instanceCount by the view count.
3593 if (!pipeline
->use_primitive_replication
)
3594 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3596 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3597 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3598 prim
.VertexAccessType
= RANDOM
;
3599 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3600 prim
.VertexCountPerInstance
= indexCount
;
3601 prim
.StartVertexLocation
= firstIndex
;
3602 prim
.InstanceCount
= instanceCount
;
3603 prim
.StartInstanceLocation
= firstInstance
;
3604 prim
.BaseVertexLocation
= vertexOffset
;
3607 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3610 /* Auto-Draw / Indirect Registers */
3611 #define GEN7_3DPRIM_END_OFFSET 0x2420
3612 #define GEN7_3DPRIM_START_VERTEX 0x2430
3613 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3614 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3615 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3616 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3618 void genX(CmdDrawIndirectByteCountEXT
)(
3619 VkCommandBuffer commandBuffer
,
3620 uint32_t instanceCount
,
3621 uint32_t firstInstance
,
3622 VkBuffer counterBuffer
,
3623 VkDeviceSize counterBufferOffset
,
3624 uint32_t counterOffset
,
3625 uint32_t vertexStride
)
3627 #if GEN_IS_HASWELL || GEN_GEN >= 8
3628 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3629 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3630 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3631 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3633 /* firstVertex is always zero for this draw function */
3634 const uint32_t firstVertex
= 0;
3636 if (anv_batch_has_error(&cmd_buffer
->batch
))
3639 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3641 if (vs_prog_data
->uses_firstvertex
||
3642 vs_prog_data
->uses_baseinstance
)
3643 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3644 if (vs_prog_data
->uses_drawid
)
3645 emit_draw_index(cmd_buffer
, 0);
3647 /* Emitting draw index or vertex index BOs may result in needing
3648 * additional VF cache flushes.
3650 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3652 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3653 * different views. We need to multiply instanceCount by the view count.
3655 if (!pipeline
->use_primitive_replication
)
3656 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3658 struct gen_mi_builder b
;
3659 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3660 struct gen_mi_value count
=
3661 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3662 counterBufferOffset
));
3664 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3665 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3666 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3668 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3669 gen_mi_imm(firstVertex
));
3670 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3671 gen_mi_imm(instanceCount
));
3672 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3673 gen_mi_imm(firstInstance
));
3674 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3676 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3677 prim
.IndirectParameterEnable
= true;
3678 prim
.VertexAccessType
= SEQUENTIAL
;
3679 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3682 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3683 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3687 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3688 struct anv_address addr
,
3691 struct gen_mi_builder b
;
3692 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3694 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3695 gen_mi_mem32(anv_address_add(addr
, 0)));
3697 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3698 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3699 if (view_count
> 1) {
3700 #if GEN_IS_HASWELL || GEN_GEN >= 8
3701 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3703 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3704 "MI_MATH is not supported on Ivy Bridge");
3707 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3709 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3710 gen_mi_mem32(anv_address_add(addr
, 8)));
3713 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3714 gen_mi_mem32(anv_address_add(addr
, 12)));
3715 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3716 gen_mi_mem32(anv_address_add(addr
, 16)));
3718 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3719 gen_mi_mem32(anv_address_add(addr
, 12)));
3720 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3724 void genX(CmdDrawIndirect
)(
3725 VkCommandBuffer commandBuffer
,
3727 VkDeviceSize offset
,
3731 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3732 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3733 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3734 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3736 if (anv_batch_has_error(&cmd_buffer
->batch
))
3739 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3741 if (cmd_buffer
->state
.conditional_render_enabled
)
3742 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3744 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3745 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3747 if (vs_prog_data
->uses_firstvertex
||
3748 vs_prog_data
->uses_baseinstance
)
3749 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3750 if (vs_prog_data
->uses_drawid
)
3751 emit_draw_index(cmd_buffer
, i
);
3753 /* Emitting draw index or vertex index BOs may result in needing
3754 * additional VF cache flushes.
3756 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3758 load_indirect_parameters(cmd_buffer
, draw
, false);
3760 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3761 prim
.IndirectParameterEnable
= true;
3762 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3763 prim
.VertexAccessType
= SEQUENTIAL
;
3764 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3767 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3773 void genX(CmdDrawIndexedIndirect
)(
3774 VkCommandBuffer commandBuffer
,
3776 VkDeviceSize offset
,
3780 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3781 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3782 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3783 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3785 if (anv_batch_has_error(&cmd_buffer
->batch
))
3788 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3790 if (cmd_buffer
->state
.conditional_render_enabled
)
3791 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3793 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3794 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3796 /* TODO: We need to stomp base vertex to 0 somehow */
3797 if (vs_prog_data
->uses_firstvertex
||
3798 vs_prog_data
->uses_baseinstance
)
3799 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3800 if (vs_prog_data
->uses_drawid
)
3801 emit_draw_index(cmd_buffer
, i
);
3803 /* Emitting draw index or vertex index BOs may result in needing
3804 * additional VF cache flushes.
3806 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3808 load_indirect_parameters(cmd_buffer
, draw
, true);
3810 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3811 prim
.IndirectParameterEnable
= true;
3812 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3813 prim
.VertexAccessType
= RANDOM
;
3814 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3817 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3823 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3826 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3827 struct anv_address count_address
,
3828 const bool conditional_render_enabled
)
3830 struct gen_mi_builder b
;
3831 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3833 if (conditional_render_enabled
) {
3834 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3835 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3836 gen_mi_mem32(count_address
));
3839 /* Upload the current draw count from the draw parameters buffer to
3840 * MI_PREDICATE_SRC0.
3842 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3843 gen_mi_mem32(count_address
));
3845 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3850 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3851 uint32_t draw_index
)
3853 struct gen_mi_builder b
;
3854 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3856 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3857 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3859 if (draw_index
== 0) {
3860 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3861 mip
.LoadOperation
= LOAD_LOADINV
;
3862 mip
.CombineOperation
= COMBINE_SET
;
3863 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3866 /* While draw_index < draw_count the predicate's result will be
3867 * (draw_index == draw_count) ^ TRUE = TRUE
3868 * When draw_index == draw_count the result is
3869 * (TRUE) ^ TRUE = FALSE
3870 * After this all results will be:
3871 * (FALSE) ^ FALSE = FALSE
3873 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3874 mip
.LoadOperation
= LOAD_LOAD
;
3875 mip
.CombineOperation
= COMBINE_XOR
;
3876 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3881 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3883 emit_draw_count_predicate_with_conditional_render(
3884 struct anv_cmd_buffer
*cmd_buffer
,
3885 uint32_t draw_index
)
3887 struct gen_mi_builder b
;
3888 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3890 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3891 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3892 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3895 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3897 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3898 * so we emit MI_PREDICATE to set it.
3901 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3902 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3904 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3905 mip
.LoadOperation
= LOAD_LOADINV
;
3906 mip
.CombineOperation
= COMBINE_SET
;
3907 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3913 void genX(CmdDrawIndirectCount
)(
3914 VkCommandBuffer commandBuffer
,
3916 VkDeviceSize offset
,
3917 VkBuffer _countBuffer
,
3918 VkDeviceSize countBufferOffset
,
3919 uint32_t maxDrawCount
,
3922 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3923 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3924 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3925 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3926 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
3927 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3929 if (anv_batch_has_error(&cmd_buffer
->batch
))
3932 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3934 struct anv_address count_address
=
3935 anv_address_add(count_buffer
->address
, countBufferOffset
);
3937 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3938 cmd_state
->conditional_render_enabled
);
3940 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3941 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3943 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3944 if (cmd_state
->conditional_render_enabled
) {
3945 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3947 emit_draw_count_predicate(cmd_buffer
, i
);
3950 emit_draw_count_predicate(cmd_buffer
, i
);
3953 if (vs_prog_data
->uses_firstvertex
||
3954 vs_prog_data
->uses_baseinstance
)
3955 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3956 if (vs_prog_data
->uses_drawid
)
3957 emit_draw_index(cmd_buffer
, i
);
3959 /* Emitting draw index or vertex index BOs may result in needing
3960 * additional VF cache flushes.
3962 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3964 load_indirect_parameters(cmd_buffer
, draw
, false);
3966 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3967 prim
.IndirectParameterEnable
= true;
3968 prim
.PredicateEnable
= true;
3969 prim
.VertexAccessType
= SEQUENTIAL
;
3970 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3973 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3979 void genX(CmdDrawIndexedIndirectCount
)(
3980 VkCommandBuffer commandBuffer
,
3982 VkDeviceSize offset
,
3983 VkBuffer _countBuffer
,
3984 VkDeviceSize countBufferOffset
,
3985 uint32_t maxDrawCount
,
3988 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3989 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3990 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3991 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3992 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
3993 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3995 if (anv_batch_has_error(&cmd_buffer
->batch
))
3998 genX(cmd_buffer_flush_state
)(cmd_buffer
);
4000 struct anv_address count_address
=
4001 anv_address_add(count_buffer
->address
, countBufferOffset
);
4003 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
4004 cmd_state
->conditional_render_enabled
);
4006 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
4007 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
4009 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4010 if (cmd_state
->conditional_render_enabled
) {
4011 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
4013 emit_draw_count_predicate(cmd_buffer
, i
);
4016 emit_draw_count_predicate(cmd_buffer
, i
);
4019 /* TODO: We need to stomp base vertex to 0 somehow */
4020 if (vs_prog_data
->uses_firstvertex
||
4021 vs_prog_data
->uses_baseinstance
)
4022 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
4023 if (vs_prog_data
->uses_drawid
)
4024 emit_draw_index(cmd_buffer
, i
);
4026 /* Emitting draw index or vertex index BOs may result in needing
4027 * additional VF cache flushes.
4029 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4031 load_indirect_parameters(cmd_buffer
, draw
, true);
4033 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
4034 prim
.IndirectParameterEnable
= true;
4035 prim
.PredicateEnable
= true;
4036 prim
.VertexAccessType
= RANDOM
;
4037 prim
.PrimitiveTopologyType
= pipeline
->topology
;
4040 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
4046 void genX(CmdBeginTransformFeedbackEXT
)(
4047 VkCommandBuffer commandBuffer
,
4048 uint32_t firstCounterBuffer
,
4049 uint32_t counterBufferCount
,
4050 const VkBuffer
* pCounterBuffers
,
4051 const VkDeviceSize
* pCounterBufferOffsets
)
4053 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4055 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4056 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4057 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4059 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4061 * "Ssoftware must ensure that no HW stream output operations can be in
4062 * process or otherwise pending at the point that the MI_LOAD/STORE
4063 * commands are processed. This will likely require a pipeline flush."
4065 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4066 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4068 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
4069 /* If we have a counter buffer, this is a resume so we need to load the
4070 * value into the streamout offset register. Otherwise, this is a begin
4071 * and we need to reset it to zero.
4073 if (pCounterBuffers
&&
4074 idx
>= firstCounterBuffer
&&
4075 idx
- firstCounterBuffer
< counterBufferCount
&&
4076 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
4077 uint32_t cb_idx
= idx
- firstCounterBuffer
;
4078 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4079 uint64_t offset
= pCounterBufferOffsets
?
4080 pCounterBufferOffsets
[cb_idx
] : 0;
4082 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4083 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4084 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4088 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4089 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4095 cmd_buffer
->state
.xfb_enabled
= true;
4096 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4099 void genX(CmdEndTransformFeedbackEXT
)(
4100 VkCommandBuffer commandBuffer
,
4101 uint32_t firstCounterBuffer
,
4102 uint32_t counterBufferCount
,
4103 const VkBuffer
* pCounterBuffers
,
4104 const VkDeviceSize
* pCounterBufferOffsets
)
4106 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4108 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4109 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4110 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4112 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4114 * "Ssoftware must ensure that no HW stream output operations can be in
4115 * process or otherwise pending at the point that the MI_LOAD/STORE
4116 * commands are processed. This will likely require a pipeline flush."
4118 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4119 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4121 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
4122 unsigned idx
= firstCounterBuffer
+ cb_idx
;
4124 /* If we have a counter buffer, this is a resume so we need to load the
4125 * value into the streamout offset register. Otherwise, this is a begin
4126 * and we need to reset it to zero.
4128 if (pCounterBuffers
&&
4129 cb_idx
< counterBufferCount
&&
4130 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
4131 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4132 uint64_t offset
= pCounterBufferOffsets
?
4133 pCounterBufferOffsets
[cb_idx
] : 0;
4135 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4136 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4138 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4143 cmd_buffer
->state
.xfb_enabled
= false;
4144 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4148 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
4150 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4152 assert(pipeline
->cs
);
4154 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
4156 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
4158 /* Apply any pending pipeline flushes we may have. We want to apply them
4159 * now because, if any of those flushes are for things like push constants,
4160 * the GPU will read the state at weird times.
4162 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4164 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
4165 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
4167 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4168 * the only bits that are changed are scoreboard related: Scoreboard
4169 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4170 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4173 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4174 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4176 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
4178 /* The workgroup size of the pipeline affects our push constant layout
4179 * so flag push constants as dirty if we change the pipeline.
4181 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4184 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
4185 cmd_buffer
->state
.compute
.pipeline_dirty
) {
4186 flush_descriptor_sets(cmd_buffer
,
4187 &cmd_buffer
->state
.compute
.base
,
4190 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4191 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
4192 .BindingTablePointer
=
4193 cmd_buffer
->state
.binding_tables
[MESA_SHADER_COMPUTE
].offset
,
4194 .SamplerStatePointer
=
4195 cmd_buffer
->state
.samplers
[MESA_SHADER_COMPUTE
].offset
,
4197 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
4199 struct anv_state state
=
4200 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
4201 pipeline
->interface_descriptor_data
,
4202 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
4205 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4206 anv_batch_emit(&cmd_buffer
->batch
,
4207 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
4208 mid
.InterfaceDescriptorTotalLength
= size
;
4209 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
4213 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
4214 struct anv_state push_state
=
4215 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
4217 if (push_state
.alloc_size
) {
4218 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4219 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
4220 curbe
.CURBEDataStartAddress
= push_state
.offset
;
4224 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
4227 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
4229 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4235 verify_cmd_parser(const struct anv_device
*device
,
4236 int required_version
,
4237 const char *function
)
4239 if (device
->physical
->cmd_parser_version
< required_version
) {
4240 return vk_errorf(device
, device
->physical
,
4241 VK_ERROR_FEATURE_NOT_PRESENT
,
4242 "cmd parser version %d is required for %s",
4243 required_version
, function
);
4252 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
4253 uint32_t baseGroupX
,
4254 uint32_t baseGroupY
,
4255 uint32_t baseGroupZ
)
4257 if (anv_batch_has_error(&cmd_buffer
->batch
))
4260 struct anv_push_constants
*push
=
4261 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
4262 if (push
->cs
.base_work_group_id
[0] != baseGroupX
||
4263 push
->cs
.base_work_group_id
[1] != baseGroupY
||
4264 push
->cs
.base_work_group_id
[2] != baseGroupZ
) {
4265 push
->cs
.base_work_group_id
[0] = baseGroupX
;
4266 push
->cs
.base_work_group_id
[1] = baseGroupY
;
4267 push
->cs
.base_work_group_id
[2] = baseGroupZ
;
4269 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4273 void genX(CmdDispatch
)(
4274 VkCommandBuffer commandBuffer
,
4279 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
4282 void genX(CmdDispatchBase
)(
4283 VkCommandBuffer commandBuffer
,
4284 uint32_t baseGroupX
,
4285 uint32_t baseGroupY
,
4286 uint32_t baseGroupZ
,
4287 uint32_t groupCountX
,
4288 uint32_t groupCountY
,
4289 uint32_t groupCountZ
)
4291 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4292 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4293 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4295 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
4296 baseGroupY
, baseGroupZ
);
4298 if (anv_batch_has_error(&cmd_buffer
->batch
))
4301 if (prog_data
->uses_num_work_groups
) {
4302 struct anv_state state
=
4303 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
4304 uint32_t *sizes
= state
.map
;
4305 sizes
[0] = groupCountX
;
4306 sizes
[1] = groupCountY
;
4307 sizes
[2] = groupCountZ
;
4308 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
4309 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4310 .offset
= state
.offset
,
4313 /* The num_workgroups buffer goes in the binding table */
4314 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4317 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4319 if (cmd_buffer
->state
.conditional_render_enabled
)
4320 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4322 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
4323 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
4324 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4325 ggw
.ThreadDepthCounterMaximum
= 0;
4326 ggw
.ThreadHeightCounterMaximum
= 0;
4327 ggw
.ThreadWidthCounterMaximum
= anv_cs_threads(pipeline
) - 1;
4328 ggw
.ThreadGroupIDXDimension
= groupCountX
;
4329 ggw
.ThreadGroupIDYDimension
= groupCountY
;
4330 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
4331 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4332 ggw
.BottomExecutionMask
= 0xffffffff;
4335 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4338 #define GPGPU_DISPATCHDIMX 0x2500
4339 #define GPGPU_DISPATCHDIMY 0x2504
4340 #define GPGPU_DISPATCHDIMZ 0x2508
4342 void genX(CmdDispatchIndirect
)(
4343 VkCommandBuffer commandBuffer
,
4345 VkDeviceSize offset
)
4347 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4348 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
4349 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4350 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4351 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
4352 struct anv_batch
*batch
= &cmd_buffer
->batch
;
4354 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
4357 /* Linux 4.4 added command parser version 5 which allows the GPGPU
4358 * indirect dispatch registers to be written.
4360 if (verify_cmd_parser(cmd_buffer
->device
, 5,
4361 "vkCmdDispatchIndirect") != VK_SUCCESS
)
4365 if (prog_data
->uses_num_work_groups
) {
4366 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
4368 /* The num_workgroups buffer goes in the binding table */
4369 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4372 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4374 struct gen_mi_builder b
;
4375 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4377 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
4378 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
4379 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
4381 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
4382 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
4383 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
4386 /* predicate = (compute_dispatch_indirect_x_size == 0); */
4387 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
4388 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4389 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4390 mip
.LoadOperation
= LOAD_LOAD
;
4391 mip
.CombineOperation
= COMBINE_SET
;
4392 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4395 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
4396 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
4397 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4398 mip
.LoadOperation
= LOAD_LOAD
;
4399 mip
.CombineOperation
= COMBINE_OR
;
4400 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4403 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
4404 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
4405 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4406 mip
.LoadOperation
= LOAD_LOAD
;
4407 mip
.CombineOperation
= COMBINE_OR
;
4408 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4411 /* predicate = !predicate; */
4412 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4413 mip
.LoadOperation
= LOAD_LOADINV
;
4414 mip
.CombineOperation
= COMBINE_OR
;
4415 mip
.CompareOperation
= COMPARE_FALSE
;
4419 if (cmd_buffer
->state
.conditional_render_enabled
) {
4420 /* predicate &= !(conditional_rendering_predicate == 0); */
4421 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
4422 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4423 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4424 mip
.LoadOperation
= LOAD_LOADINV
;
4425 mip
.CombineOperation
= COMBINE_AND
;
4426 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4431 #else /* GEN_GEN > 7 */
4432 if (cmd_buffer
->state
.conditional_render_enabled
)
4433 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4436 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
4437 ggw
.IndirectParameterEnable
= true;
4438 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
4439 cmd_buffer
->state
.conditional_render_enabled
;
4440 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4441 ggw
.ThreadDepthCounterMaximum
= 0;
4442 ggw
.ThreadHeightCounterMaximum
= 0;
4443 ggw
.ThreadWidthCounterMaximum
= anv_cs_threads(pipeline
) - 1;
4444 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4445 ggw
.BottomExecutionMask
= 0xffffffff;
4448 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4452 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
4455 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4457 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
4460 #if GEN_GEN >= 8 && GEN_GEN < 10
4461 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
4463 * Software must clear the COLOR_CALC_STATE Valid field in
4464 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
4465 * with Pipeline Select set to GPGPU.
4467 * The internal hardware docs recommend the same workaround for Gen9
4470 if (pipeline
== GPGPU
)
4471 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
4475 if (pipeline
== _3D
) {
4476 /* There is a mid-object preemption workaround which requires you to
4477 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
4478 * even without preemption, we have issues with geometry flickering when
4479 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
4482 const uint32_t subslices
=
4483 MAX2(cmd_buffer
->device
->physical
->subslice_total
, 1);
4484 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4485 vfe
.MaximumNumberofThreads
=
4486 devinfo
->max_cs_threads
* subslices
- 1;
4487 vfe
.NumberofURBEntries
= 2;
4488 vfe
.URBEntryAllocationSize
= 2;
4491 /* We just emitted a dummy MEDIA_VFE_STATE so now that packet is
4492 * invalid. Set the compute pipeline to dirty to force a re-emit of the
4493 * pipeline in case we get back-to-back dispatch calls with the same
4494 * pipeline and a PIPELINE_SELECT in between.
4496 cmd_buffer
->state
.compute
.pipeline_dirty
= true;
4500 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
4501 * PIPELINE_SELECT [DevBWR+]":
4505 * Software must ensure all the write caches are flushed through a
4506 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
4507 * command to invalidate read only caches prior to programming
4508 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
4510 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4511 pc
.RenderTargetCacheFlushEnable
= true;
4512 pc
.DepthCacheFlushEnable
= true;
4513 pc
.DCFlushEnable
= true;
4514 pc
.PostSyncOperation
= NoWrite
;
4515 pc
.CommandStreamerStallEnable
= true;
4517 pc
.TileCacheFlushEnable
= true;
4519 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
4520 * set with any PIPE_CONTROL with Depth Flush Enable bit set.
4522 pc
.DepthStallEnable
= true;
4526 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4527 pc
.TextureCacheInvalidationEnable
= true;
4528 pc
.ConstantCacheInvalidationEnable
= true;
4529 pc
.StateCacheInvalidationEnable
= true;
4530 pc
.InstructionCacheInvalidateEnable
= true;
4531 pc
.PostSyncOperation
= NoWrite
;
4533 pc
.TileCacheFlushEnable
= true;
4537 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
4541 ps
.PipelineSelection
= pipeline
;
4545 if (devinfo
->is_geminilake
) {
4548 * "This chicken bit works around a hardware issue with barrier logic
4549 * encountered when switching between GPGPU and 3D pipelines. To
4550 * workaround the issue, this mode bit should be set after a pipeline
4554 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
4556 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
4557 : GLK_BARRIER_MODE_3D_HULL
,
4558 .GLKBarrierModeMask
= 1);
4559 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
4563 cmd_buffer
->state
.current_pipeline
= pipeline
;
4567 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
4569 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
4573 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
4575 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
4579 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
4584 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
4586 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
4587 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
4588 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
4589 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
4590 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
4591 * Depth Flush Bit set, followed by another pipelined depth stall
4592 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
4593 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
4594 * via a preceding MI_FLUSH)."
4596 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4597 pipe
.DepthStallEnable
= true;
4599 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4600 pipe
.DepthCacheFlushEnable
= true;
4602 pipe
.TileCacheFlushEnable
= true;
4605 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4606 pipe
.DepthStallEnable
= true;
4610 /* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
4612 * "The VF cache needs to be invalidated before binding and then using
4613 * Vertex Buffers that overlap with any previously bound Vertex Buffer
4614 * (at a 64B granularity) since the last invalidation. A VF cache
4615 * invalidate is performed by setting the "VF Cache Invalidation Enable"
4616 * bit in PIPE_CONTROL."
4618 * This is implemented by carefully tracking all vertex and index buffer
4619 * bindings and flushing if the cache ever ends up with a range in the cache
4620 * that would exceed 4 GiB. This is implemented in three parts:
4622 * 1. genX(cmd_buffer_set_binding_for_gen8_vb_flush)() which must be called
4623 * every time a 3DSTATE_VERTEX_BUFFER packet is emitted and informs the
4624 * tracking code of the new binding. If this new binding would cause
4625 * the cache to have a too-large range on the next draw call, a pipeline
4626 * stall and VF cache invalidate are added to pending_pipeline_bits.
4628 * 2. genX(cmd_buffer_apply_pipe_flushes)() resets the cache tracking to
4629 * empty whenever we emit a VF invalidate.
4631 * 3. genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)() must be called
4632 * after every 3DPRIMITIVE and copies the bound range into the dirty
4633 * range for each used buffer. This has to be a separate step because
4634 * we don't always re-bind all buffers and so 1. can't know which
4635 * buffers are actually bound.
4638 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4640 struct anv_address vb_address
,
4643 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4644 !cmd_buffer
->device
->physical
->use_softpin
)
4647 struct anv_vb_cache_range
*bound
, *dirty
;
4648 if (vb_index
== -1) {
4649 bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4650 dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4652 assert(vb_index
>= 0);
4653 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4654 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4655 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[vb_index
];
4656 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[vb_index
];
4665 assert(vb_address
.bo
&& (vb_address
.bo
->flags
& EXEC_OBJECT_PINNED
));
4666 bound
->start
= gen_48b_address(anv_address_physical(vb_address
));
4667 bound
->end
= bound
->start
+ vb_size
;
4668 assert(bound
->end
> bound
->start
); /* No overflow */
4670 /* Align everything to a cache line */
4671 bound
->start
&= ~(64ull - 1ull);
4672 bound
->end
= align_u64(bound
->end
, 64);
4674 /* Compute the dirty range */
4675 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4676 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4678 /* If our range is larger than 32 bits, we have to flush */
4679 assert(bound
->end
- bound
->start
<= (1ull << 32));
4680 if (dirty
->end
- dirty
->start
> (1ull << 32)) {
4681 cmd_buffer
->state
.pending_pipe_bits
|=
4682 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
4687 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4688 uint32_t access_type
,
4691 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4692 !cmd_buffer
->device
->physical
->use_softpin
)
4695 if (access_type
== RANDOM
) {
4696 /* We have an index buffer */
4697 struct anv_vb_cache_range
*bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4698 struct anv_vb_cache_range
*dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4700 if (bound
->end
> bound
->start
) {
4701 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4702 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4706 uint64_t mask
= vb_used
;
4708 int i
= u_bit_scan64(&mask
);
4710 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4711 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4713 struct anv_vb_cache_range
*bound
, *dirty
;
4714 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[i
];
4715 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[i
];
4717 if (bound
->end
> bound
->start
) {
4718 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4719 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4725 * Update the pixel hashing modes that determine the balancing of PS threads
4726 * across subslices and slices.
4728 * \param width Width bound of the rendering area (already scaled down if \p
4729 * scale is greater than 1).
4730 * \param height Height bound of the rendering area (already scaled down if \p
4731 * scale is greater than 1).
4732 * \param scale The number of framebuffer samples that could potentially be
4733 * affected by an individual channel of the PS thread. This is
4734 * typically one for single-sampled rendering, but for operations
4735 * like CCS resolves and fast clears a single PS invocation may
4736 * update a huge number of pixels, in which case a finer
4737 * balancing is desirable in order to maximally utilize the
4738 * bandwidth available. UINT_MAX can be used as shorthand for
4739 * "finest hashing mode available".
4742 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4743 unsigned width
, unsigned height
,
4747 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4748 const unsigned slice_hashing
[] = {
4749 /* Because all Gen9 platforms with more than one slice require
4750 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4751 * block is guaranteed to suffer from substantial imbalance, with one
4752 * subslice receiving twice as much work as the other two in the
4755 * The performance impact of that would be particularly severe when
4756 * three-way hashing is also in use for slice balancing (which is the
4757 * case for all Gen9 GT4 platforms), because one of the slices
4758 * receives one every three 16x16 blocks in either direction, which
4759 * is roughly the periodicity of the underlying subslice imbalance
4760 * pattern ("roughly" because in reality the hardware's
4761 * implementation of three-way hashing doesn't do exact modulo 3
4762 * arithmetic, which somewhat decreases the magnitude of this effect
4763 * in practice). This leads to a systematic subslice imbalance
4764 * within that slice regardless of the size of the primitive. The
4765 * 32x32 hashing mode guarantees that the subslice imbalance within a
4766 * single slice hashing block is minimal, largely eliminating this
4770 /* Finest slice hashing mode available. */
4773 const unsigned subslice_hashing
[] = {
4774 /* 16x16 would provide a slight cache locality benefit especially
4775 * visible in the sampler L1 cache efficiency of low-bandwidth
4776 * non-LLC platforms, but it comes at the cost of greater subslice
4777 * imbalance for primitives of dimensions approximately intermediate
4778 * between 16x4 and 16x16.
4781 /* Finest subslice hashing mode available. */
4784 /* Dimensions of the smallest hashing block of a given hashing mode. If
4785 * the rendering area is smaller than this there can't possibly be any
4786 * benefit from switching to this mode, so we optimize out the
4789 const unsigned min_size
[][2] = {
4793 const unsigned idx
= scale
> 1;
4795 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4796 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4799 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4800 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4801 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4802 .SubsliceHashing
= subslice_hashing
[idx
],
4803 .SubsliceHashingMask
= -1);
4805 cmd_buffer
->state
.pending_pipe_bits
|=
4806 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4807 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4809 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4811 cmd_buffer
->state
.current_hash_scale
= scale
;
4817 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4819 struct anv_device
*device
= cmd_buffer
->device
;
4820 const struct anv_image_view
*iview
=
4821 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4822 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4824 /* FIXME: Width and Height are wrong */
4826 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4828 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4829 device
->isl_dev
.ds
.size
/ 4);
4833 struct isl_depth_stencil_hiz_emit_info info
= { };
4836 info
.view
= &iview
->planes
[0].isl
;
4838 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4839 uint32_t depth_plane
=
4840 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4841 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4843 info
.depth_surf
= &surface
->isl
;
4845 info
.depth_address
=
4846 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4847 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4848 image
->planes
[depth_plane
].address
.bo
,
4849 image
->planes
[depth_plane
].address
.offset
+
4852 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4855 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4856 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4857 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
4858 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4861 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4862 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4863 image
->planes
[depth_plane
].address
.bo
,
4864 image
->planes
[depth_plane
].address
.offset
+
4865 image
->planes
[depth_plane
].aux_surface
.offset
);
4867 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4871 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4872 uint32_t stencil_plane
=
4873 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4874 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4876 info
.stencil_surf
= &surface
->isl
;
4878 info
.stencil_address
=
4879 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4880 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4881 image
->planes
[stencil_plane
].address
.bo
,
4882 image
->planes
[stencil_plane
].address
.offset
+
4885 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4888 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4890 if (GEN_GEN
>= 12) {
4891 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
4892 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4894 /* GEN:BUG:1408224581
4896 * Workaround: Gen12LP Astep only An additional pipe control with
4897 * post-sync = store dword operation would be required.( w/a is to
4898 * have an additional pipe control after the stencil state whenever
4899 * the surface state bits of this state is changing).
4901 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4902 pc
.PostSyncOperation
= WriteImmediateData
;
4904 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
4907 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
4911 * This ANDs the view mask of the current subpass with the pending clear
4912 * views in the attachment to get the mask of views active in the subpass
4913 * that still need to be cleared.
4915 static inline uint32_t
4916 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4917 const struct anv_attachment_state
*att_state
)
4919 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4923 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4924 const struct anv_attachment_state
*att_state
)
4926 if (!cmd_state
->subpass
->view_mask
)
4929 uint32_t pending_clear_mask
=
4930 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4932 return pending_clear_mask
& 1;
4936 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4939 const uint32_t last_subpass_idx
=
4940 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4941 const struct anv_subpass
*last_subpass
=
4942 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4943 return last_subpass
== cmd_state
->subpass
;
4947 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4948 uint32_t subpass_id
)
4950 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4951 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4952 cmd_state
->subpass
= subpass
;
4954 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4956 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4957 * different views. If the client asks for instancing, we need to use the
4958 * Instance Data Step Rate to ensure that we repeat the client's
4959 * per-instance data once for each view. Since this bit is in
4960 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4964 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4966 /* It is possible to start a render pass with an old pipeline. Because the
4967 * render pass and subpass index are both baked into the pipeline, this is
4968 * highly unlikely. In order to do so, it requires that you have a render
4969 * pass with a single subpass and that you use that render pass twice
4970 * back-to-back and use the same pipeline at the start of the second render
4971 * pass as at the end of the first. In order to avoid unpredictable issues
4972 * with this edge case, we just dirty the pipeline at the start of every
4975 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4977 /* Accumulate any subpass flushes that need to happen before the subpass */
4978 cmd_buffer
->state
.pending_pipe_bits
|=
4979 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4981 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4982 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4984 bool is_multiview
= subpass
->view_mask
!= 0;
4986 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4987 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4988 if (a
== VK_ATTACHMENT_UNUSED
)
4991 assert(a
< cmd_state
->pass
->attachment_count
);
4992 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4994 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4995 const struct anv_image
*image
= iview
->image
;
4997 /* A resolve is necessary before use as an input attachment if the clear
4998 * color or auxiliary buffer usage isn't supported by the sampler.
5000 const bool input_needs_resolve
=
5001 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
5002 att_state
->input_aux_usage
!= att_state
->aux_usage
;
5004 VkImageLayout target_layout
;
5005 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
5006 !input_needs_resolve
) {
5007 /* Layout transitions before the final only help to enable sampling
5008 * as an input attachment. If the input attachment supports sampling
5009 * using the auxiliary surface, we can skip such transitions by
5010 * making the target layout one that is CCS-aware.
5012 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
5014 target_layout
= subpass
->attachments
[i
].layout
;
5017 VkImageLayout target_stencil_layout
=
5018 subpass
->attachments
[i
].stencil_layout
;
5020 uint32_t base_layer
, layer_count
;
5021 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5023 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5024 iview
->planes
[0].isl
.base_level
);
5026 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5027 layer_count
= fb
->layers
;
5030 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5031 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5032 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5033 iview
->planes
[0].isl
.base_level
, 1,
5034 base_layer
, layer_count
,
5035 att_state
->current_layout
, target_layout
);
5038 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5039 transition_depth_buffer(cmd_buffer
, image
,
5040 base_layer
, layer_count
,
5041 att_state
->current_layout
, target_layout
);
5042 att_state
->aux_usage
=
5043 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
5044 VK_IMAGE_ASPECT_DEPTH_BIT
,
5045 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
5049 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5050 transition_stencil_buffer(cmd_buffer
, image
,
5051 iview
->planes
[0].isl
.base_level
, 1,
5052 base_layer
, layer_count
,
5053 att_state
->current_stencil_layout
,
5054 target_stencil_layout
);
5056 att_state
->current_layout
= target_layout
;
5057 att_state
->current_stencil_layout
= target_stencil_layout
;
5059 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
5060 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5062 /* Multi-planar images are not supported as attachments */
5063 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5064 assert(image
->n_planes
== 1);
5066 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
5067 uint32_t clear_layer_count
= fb
->layers
;
5069 if (att_state
->fast_clear
&&
5070 do_first_layer_clear(cmd_state
, att_state
)) {
5071 /* We only support fast-clears on the first layer */
5072 assert(iview
->planes
[0].isl
.base_level
== 0);
5073 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
5075 union isl_color_value clear_color
= {};
5076 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
5077 if (iview
->image
->samples
== 1) {
5078 anv_image_ccs_op(cmd_buffer
, image
,
5079 iview
->planes
[0].isl
.format
,
5080 iview
->planes
[0].isl
.swizzle
,
5081 VK_IMAGE_ASPECT_COLOR_BIT
,
5082 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5086 anv_image_mcs_op(cmd_buffer
, image
,
5087 iview
->planes
[0].isl
.format
,
5088 iview
->planes
[0].isl
.swizzle
,
5089 VK_IMAGE_ASPECT_COLOR_BIT
,
5090 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5095 clear_layer_count
--;
5097 att_state
->pending_clear_views
&= ~1;
5099 if (att_state
->clear_color_is_zero
) {
5100 /* This image has the auxiliary buffer enabled. We can mark the
5101 * subresource as not needing a resolve because the clear color
5102 * will match what's in every RENDER_SURFACE_STATE object when
5103 * it's being used for sampling.
5105 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5106 VK_IMAGE_ASPECT_COLOR_BIT
,
5107 ANV_FAST_CLEAR_DEFAULT_VALUE
);
5109 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5110 VK_IMAGE_ASPECT_COLOR_BIT
,
5111 ANV_FAST_CLEAR_ANY
);
5115 /* From the VkFramebufferCreateInfo spec:
5117 * "If the render pass uses multiview, then layers must be one and each
5118 * attachment requires a number of layers that is greater than the
5119 * maximum bit index set in the view mask in the subpasses in which it
5122 * So if multiview is active we ignore the number of layers in the
5123 * framebuffer and instead we honor the view mask from the subpass.
5126 assert(image
->n_planes
== 1);
5127 uint32_t pending_clear_mask
=
5128 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5131 for_each_bit(layer_idx
, pending_clear_mask
) {
5133 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5135 anv_image_clear_color(cmd_buffer
, image
,
5136 VK_IMAGE_ASPECT_COLOR_BIT
,
5137 att_state
->aux_usage
,
5138 iview
->planes
[0].isl
.format
,
5139 iview
->planes
[0].isl
.swizzle
,
5140 iview
->planes
[0].isl
.base_level
,
5143 vk_to_isl_color(att_state
->clear_value
.color
));
5146 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5147 } else if (clear_layer_count
> 0) {
5148 assert(image
->n_planes
== 1);
5149 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5150 att_state
->aux_usage
,
5151 iview
->planes
[0].isl
.format
,
5152 iview
->planes
[0].isl
.swizzle
,
5153 iview
->planes
[0].isl
.base_level
,
5154 base_clear_layer
, clear_layer_count
,
5156 vk_to_isl_color(att_state
->clear_value
.color
));
5158 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
5159 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
5160 if (att_state
->fast_clear
&& !is_multiview
) {
5161 /* We currently only support HiZ for single-LOD images */
5162 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5163 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
5164 assert(iview
->planes
[0].isl
.base_level
== 0);
5167 anv_image_hiz_clear(cmd_buffer
, image
,
5168 att_state
->pending_clear_aspects
,
5169 iview
->planes
[0].isl
.base_level
,
5170 iview
->planes
[0].isl
.base_array_layer
,
5171 fb
->layers
, render_area
,
5172 att_state
->clear_value
.depthStencil
.stencil
);
5173 } else if (is_multiview
) {
5174 uint32_t pending_clear_mask
=
5175 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5178 for_each_bit(layer_idx
, pending_clear_mask
) {
5180 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5182 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5183 att_state
->pending_clear_aspects
,
5184 att_state
->aux_usage
,
5185 iview
->planes
[0].isl
.base_level
,
5188 att_state
->clear_value
.depthStencil
.depth
,
5189 att_state
->clear_value
.depthStencil
.stencil
);
5192 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5194 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5195 att_state
->pending_clear_aspects
,
5196 att_state
->aux_usage
,
5197 iview
->planes
[0].isl
.base_level
,
5198 iview
->planes
[0].isl
.base_array_layer
,
5199 fb
->layers
, render_area
,
5200 att_state
->clear_value
.depthStencil
.depth
,
5201 att_state
->clear_value
.depthStencil
.stencil
);
5204 assert(att_state
->pending_clear_aspects
== 0);
5208 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
5209 image
->planes
[0].aux_usage
!= ISL_AUX_USAGE_NONE
&&
5210 iview
->planes
[0].isl
.base_level
== 0 &&
5211 iview
->planes
[0].isl
.base_array_layer
== 0) {
5212 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
5213 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
5214 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5215 false /* copy to ss */);
5218 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
5219 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
5220 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
5221 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5222 false /* copy to ss */);
5226 if (subpass
->attachments
[i
].usage
==
5227 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
5228 /* We assume that if we're starting a subpass, we're going to do some
5229 * rendering so we may end up with compressed data.
5231 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5232 VK_IMAGE_ASPECT_COLOR_BIT
,
5233 att_state
->aux_usage
,
5234 iview
->planes
[0].isl
.base_level
,
5235 iview
->planes
[0].isl
.base_array_layer
,
5237 } else if (subpass
->attachments
[i
].usage
==
5238 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
5239 /* We may be writing depth or stencil so we need to mark the surface.
5240 * Unfortunately, there's no way to know at this point whether the
5241 * depth or stencil tests used will actually write to the surface.
5243 * Even though stencil may be plane 1, it always shares a base_level
5246 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
5247 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5248 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
5249 VK_IMAGE_ASPECT_DEPTH_BIT
,
5250 att_state
->aux_usage
,
5251 ds_view
->base_level
,
5252 ds_view
->base_array_layer
,
5255 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5256 /* Even though stencil may be plane 1, it always shares a
5257 * base_level with depth.
5259 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
5260 VK_IMAGE_ASPECT_STENCIL_BIT
,
5262 ds_view
->base_level
,
5263 ds_view
->base_array_layer
,
5268 /* If multiview is enabled, then we are only done clearing when we no
5269 * longer have pending layers to clear, or when we have processed the
5270 * last subpass that uses this attachment.
5272 if (!is_multiview
||
5273 att_state
->pending_clear_views
== 0 ||
5274 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
5275 att_state
->pending_clear_aspects
= 0;
5278 att_state
->pending_load_aspects
= 0;
5282 /* The PIPE_CONTROL command description says:
5284 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
5285 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
5286 * Target Cache Flush by enabling this bit. When render target flush
5287 * is set due to new association of BTI, PS Scoreboard Stall bit must
5288 * be set in this packet."
5290 cmd_buffer
->state
.pending_pipe_bits
|=
5291 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
|
5292 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
5296 /* GEN:BUG:14010455700
5298 * ISL will change some CHICKEN registers depending on the depth surface
5299 * format, along with emitting the depth and stencil packets. In that case,
5300 * we want to do a depth flush and stall, so the pipeline is not using these
5301 * settings while we change the registers.
5303 cmd_buffer
->state
.pending_pipe_bits
|=
5304 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
|
5305 ANV_PIPE_DEPTH_STALL_BIT
|
5306 ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
5307 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5310 cmd_buffer_emit_depth_stencil(cmd_buffer
);
5313 static enum blorp_filter
5314 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
5317 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
5318 return BLORP_FILTER_SAMPLE_0
;
5319 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
5320 return BLORP_FILTER_AVERAGE
;
5321 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
5322 return BLORP_FILTER_MIN_SAMPLE
;
5323 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
5324 return BLORP_FILTER_MAX_SAMPLE
;
5326 return BLORP_FILTER_NONE
;
5331 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
5333 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5334 struct anv_subpass
*subpass
= cmd_state
->subpass
;
5335 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
5336 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
5338 if (subpass
->has_color_resolve
) {
5339 /* We are about to do some MSAA resolves. We need to flush so that the
5340 * result of writes to the MSAA color attachments show up in the sampler
5341 * when we blit to the single-sampled resolve target.
5343 cmd_buffer
->state
.pending_pipe_bits
|=
5344 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5345 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
5347 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
5348 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
5349 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
5351 if (dst_att
== VK_ATTACHMENT_UNUSED
)
5354 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5355 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5357 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5358 /* From the Vulkan 1.0 spec:
5360 * If the first use of an attachment in a render pass is as a
5361 * resolve attachment, then the loadOp is effectively ignored
5362 * as the resolve is guaranteed to overwrite all pixels in the
5365 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5368 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5369 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5371 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5373 enum isl_aux_usage src_aux_usage
=
5374 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
5375 enum isl_aux_usage dst_aux_usage
=
5376 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
5378 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
5379 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
5381 anv_image_msaa_resolve(cmd_buffer
,
5382 src_iview
->image
, src_aux_usage
,
5383 src_iview
->planes
[0].isl
.base_level
,
5384 src_iview
->planes
[0].isl
.base_array_layer
,
5385 dst_iview
->image
, dst_aux_usage
,
5386 dst_iview
->planes
[0].isl
.base_level
,
5387 dst_iview
->planes
[0].isl
.base_array_layer
,
5388 VK_IMAGE_ASPECT_COLOR_BIT
,
5389 render_area
.offset
.x
, render_area
.offset
.y
,
5390 render_area
.offset
.x
, render_area
.offset
.y
,
5391 render_area
.extent
.width
,
5392 render_area
.extent
.height
,
5393 fb
->layers
, BLORP_FILTER_NONE
);
5397 if (subpass
->ds_resolve_attachment
) {
5398 /* We are about to do some MSAA resolves. We need to flush so that the
5399 * result of writes to the MSAA depth attachments show up in the sampler
5400 * when we blit to the single-sampled resolve target.
5402 cmd_buffer
->state
.pending_pipe_bits
|=
5403 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5404 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
5406 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
5407 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
5409 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5410 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5412 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5413 /* From the Vulkan 1.0 spec:
5415 * If the first use of an attachment in a render pass is as a
5416 * resolve attachment, then the loadOp is effectively ignored
5417 * as the resolve is guaranteed to overwrite all pixels in the
5420 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5423 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5424 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5426 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5428 struct anv_attachment_state
*src_state
=
5429 &cmd_state
->attachments
[src_att
];
5430 struct anv_attachment_state
*dst_state
=
5431 &cmd_state
->attachments
[dst_att
];
5433 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
5434 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5436 /* MSAA resolves sample from the source attachment. Transition the
5437 * depth attachment first to get rid of any HiZ that we may not be
5440 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
5441 src_iview
->planes
[0].isl
.base_array_layer
,
5443 src_state
->current_layout
,
5444 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5445 src_state
->aux_usage
=
5446 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
5447 VK_IMAGE_ASPECT_DEPTH_BIT
,
5448 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
,
5449 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5450 src_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5452 /* MSAA resolves write to the resolve attachment as if it were any
5453 * other transfer op. Transition the resolve attachment accordingly.
5455 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
5457 /* If our render area is the entire size of the image, we're going to
5458 * blow it all away so we can claim the initial layout is UNDEFINED
5459 * and we'll get a HiZ ambiguate instead of a resolve.
5461 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
5462 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
5463 render_area
.extent
.width
== dst_iview
->extent
.width
&&
5464 render_area
.extent
.height
== dst_iview
->extent
.height
)
5465 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
5467 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
5468 dst_iview
->planes
[0].isl
.base_array_layer
,
5471 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5472 dst_state
->aux_usage
=
5473 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
5474 VK_IMAGE_ASPECT_DEPTH_BIT
,
5475 VK_IMAGE_USAGE_TRANSFER_DST_BIT
,
5476 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5477 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5479 enum blorp_filter filter
=
5480 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
5482 anv_image_msaa_resolve(cmd_buffer
,
5483 src_iview
->image
, src_state
->aux_usage
,
5484 src_iview
->planes
[0].isl
.base_level
,
5485 src_iview
->planes
[0].isl
.base_array_layer
,
5486 dst_iview
->image
, dst_state
->aux_usage
,
5487 dst_iview
->planes
[0].isl
.base_level
,
5488 dst_iview
->planes
[0].isl
.base_array_layer
,
5489 VK_IMAGE_ASPECT_DEPTH_BIT
,
5490 render_area
.offset
.x
, render_area
.offset
.y
,
5491 render_area
.offset
.x
, render_area
.offset
.y
,
5492 render_area
.extent
.width
,
5493 render_area
.extent
.height
,
5494 fb
->layers
, filter
);
5497 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
5498 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5500 src_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5501 dst_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5503 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
5504 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
5506 enum blorp_filter filter
=
5507 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
5509 anv_image_msaa_resolve(cmd_buffer
,
5510 src_iview
->image
, src_aux_usage
,
5511 src_iview
->planes
[0].isl
.base_level
,
5512 src_iview
->planes
[0].isl
.base_array_layer
,
5513 dst_iview
->image
, dst_aux_usage
,
5514 dst_iview
->planes
[0].isl
.base_level
,
5515 dst_iview
->planes
[0].isl
.base_array_layer
,
5516 VK_IMAGE_ASPECT_STENCIL_BIT
,
5517 render_area
.offset
.x
, render_area
.offset
.y
,
5518 render_area
.offset
.x
, render_area
.offset
.y
,
5519 render_area
.extent
.width
,
5520 render_area
.extent
.height
,
5521 fb
->layers
, filter
);
5526 /* On gen7, we have to store a texturable version of the stencil buffer in
5527 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
5528 * forth at strategic points. Stencil writes are only allowed in following
5531 * - VK_IMAGE_LAYOUT_GENERAL
5532 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
5533 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
5534 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
5535 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
5537 * For general, we have no nice opportunity to transition so we do the copy
5538 * to the shadow unconditionally at the end of the subpass. For transfer
5539 * destinations, we can update it as part of the transfer op. For the other
5540 * layouts, we delay the copy until a transition into some other layout.
5542 if (subpass
->depth_stencil_attachment
) {
5543 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
5544 assert(a
!= VK_ATTACHMENT_UNUSED
);
5546 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5547 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
5548 const struct anv_image
*image
= iview
->image
;
5550 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5551 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
5552 VK_IMAGE_ASPECT_STENCIL_BIT
);
5554 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
5555 att_state
->current_stencil_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5556 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
5557 anv_image_copy_to_shadow(cmd_buffer
, image
,
5558 VK_IMAGE_ASPECT_STENCIL_BIT
,
5559 iview
->planes
[plane
].isl
.base_level
, 1,
5560 iview
->planes
[plane
].isl
.base_array_layer
,
5565 #endif /* GEN_GEN == 7 */
5567 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5568 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5569 if (a
== VK_ATTACHMENT_UNUSED
)
5572 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
5575 assert(a
< cmd_state
->pass
->attachment_count
);
5576 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5577 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5578 const struct anv_image
*image
= iview
->image
;
5580 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
5581 image
->vk_format
!= iview
->vk_format
) {
5582 enum anv_fast_clear_type fast_clear_type
=
5583 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
5584 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5585 att_state
->current_layout
);
5587 /* If any clear color was used, flush it down the aux surfaces. If we
5588 * don't do it now using the view's format we might use the clear
5589 * color incorrectly in the following resolves (for example with an
5590 * SRGB view & a UNORM image).
5592 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
5593 anv_perf_warn(cmd_buffer
->device
, iview
,
5594 "Doing a partial resolve to get rid of clear color at the "
5595 "end of a renderpass due to an image/view format mismatch");
5597 uint32_t base_layer
, layer_count
;
5598 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5600 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5601 iview
->planes
[0].isl
.base_level
);
5603 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5604 layer_count
= fb
->layers
;
5607 for (uint32_t a
= 0; a
< layer_count
; a
++) {
5608 uint32_t array_layer
= base_layer
+ a
;
5609 if (image
->samples
== 1) {
5610 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
5611 iview
->planes
[0].isl
.format
,
5612 iview
->planes
[0].isl
.swizzle
,
5613 VK_IMAGE_ASPECT_COLOR_BIT
,
5614 iview
->planes
[0].isl
.base_level
,
5616 ISL_AUX_OP_PARTIAL_RESOLVE
,
5617 ANV_FAST_CLEAR_NONE
);
5619 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
5620 iview
->planes
[0].isl
.format
,
5621 iview
->planes
[0].isl
.swizzle
,
5622 VK_IMAGE_ASPECT_COLOR_BIT
,
5624 ISL_AUX_OP_PARTIAL_RESOLVE
,
5625 ANV_FAST_CLEAR_NONE
);
5631 /* Transition the image into the final layout for this render pass */
5632 VkImageLayout target_layout
=
5633 cmd_state
->pass
->attachments
[a
].final_layout
;
5634 VkImageLayout target_stencil_layout
=
5635 cmd_state
->pass
->attachments
[a
].stencil_final_layout
;
5637 uint32_t base_layer
, layer_count
;
5638 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5640 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5641 iview
->planes
[0].isl
.base_level
);
5643 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5644 layer_count
= fb
->layers
;
5647 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5648 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5649 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5650 iview
->planes
[0].isl
.base_level
, 1,
5651 base_layer
, layer_count
,
5652 att_state
->current_layout
, target_layout
);
5655 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5656 transition_depth_buffer(cmd_buffer
, image
,
5657 base_layer
, layer_count
,
5658 att_state
->current_layout
, target_layout
);
5661 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5662 transition_stencil_buffer(cmd_buffer
, image
,
5663 iview
->planes
[0].isl
.base_level
, 1,
5664 base_layer
, layer_count
,
5665 att_state
->current_stencil_layout
,
5666 target_stencil_layout
);
5670 /* Accumulate any subpass flushes that need to happen after the subpass.
5671 * Yes, they do get accumulated twice in the NextSubpass case but since
5672 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
5673 * ORing the bits in twice so it's harmless.
5675 cmd_buffer
->state
.pending_pipe_bits
|=
5676 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
5679 void genX(CmdBeginRenderPass
)(
5680 VkCommandBuffer commandBuffer
,
5681 const VkRenderPassBeginInfo
* pRenderPassBegin
,
5682 VkSubpassContents contents
)
5684 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5685 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
5686 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
5688 cmd_buffer
->state
.framebuffer
= framebuffer
;
5689 cmd_buffer
->state
.pass
= pass
;
5690 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
5692 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
5694 /* If we failed to setup the attachments we should not try to go further */
5695 if (result
!= VK_SUCCESS
) {
5696 assert(anv_batch_has_error(&cmd_buffer
->batch
));
5700 genX(flush_pipeline_select_3d
)(cmd_buffer
);
5702 cmd_buffer_begin_subpass(cmd_buffer
, 0);
5705 void genX(CmdBeginRenderPass2
)(
5706 VkCommandBuffer commandBuffer
,
5707 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
5708 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
5710 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
5711 pSubpassBeginInfo
->contents
);
5714 void genX(CmdNextSubpass
)(
5715 VkCommandBuffer commandBuffer
,
5716 VkSubpassContents contents
)
5718 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5720 if (anv_batch_has_error(&cmd_buffer
->batch
))
5723 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
5725 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
5726 cmd_buffer_end_subpass(cmd_buffer
);
5727 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
5730 void genX(CmdNextSubpass2
)(
5731 VkCommandBuffer commandBuffer
,
5732 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
5733 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5735 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
5738 void genX(CmdEndRenderPass
)(
5739 VkCommandBuffer commandBuffer
)
5741 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5743 if (anv_batch_has_error(&cmd_buffer
->batch
))
5746 cmd_buffer_end_subpass(cmd_buffer
);
5748 cmd_buffer
->state
.hiz_enabled
= false;
5751 anv_dump_add_attachments(cmd_buffer
);
5754 /* Remove references to render pass specific state. This enables us to
5755 * detect whether or not we're in a renderpass.
5757 cmd_buffer
->state
.framebuffer
= NULL
;
5758 cmd_buffer
->state
.pass
= NULL
;
5759 cmd_buffer
->state
.subpass
= NULL
;
5762 void genX(CmdEndRenderPass2
)(
5763 VkCommandBuffer commandBuffer
,
5764 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5766 genX(CmdEndRenderPass
)(commandBuffer
);
5770 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5772 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5773 struct gen_mi_builder b
;
5774 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5776 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5777 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5778 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5780 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5781 mip
.LoadOperation
= LOAD_LOADINV
;
5782 mip
.CombineOperation
= COMBINE_SET
;
5783 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5788 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5789 void genX(CmdBeginConditionalRenderingEXT
)(
5790 VkCommandBuffer commandBuffer
,
5791 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5793 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5794 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5795 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5796 struct anv_address value_address
=
5797 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5799 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5800 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5802 cmd_state
->conditional_render_enabled
= true;
5804 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5806 struct gen_mi_builder b
;
5807 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5809 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5811 * If the value of the predicate in buffer memory changes
5812 * while conditional rendering is active, the rendering commands
5813 * may be discarded in an implementation-dependent way.
5814 * Some implementations may latch the value of the predicate
5815 * upon beginning conditional rendering while others
5816 * may read it before every rendering command.
5818 * So it's perfectly fine to read a value from the buffer once.
5820 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5822 /* Precompute predicate result, it is necessary to support secondary
5823 * command buffers since it is unknown if conditional rendering is
5824 * inverted when populating them.
5826 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5827 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5828 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5831 void genX(CmdEndConditionalRenderingEXT
)(
5832 VkCommandBuffer commandBuffer
)
5834 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5835 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5837 cmd_state
->conditional_render_enabled
= false;
5841 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5842 * command streamer for later execution.
5844 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5845 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5846 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5847 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5848 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5849 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5850 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5851 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5852 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5853 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5854 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5855 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5856 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5857 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5858 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5860 void genX(CmdSetEvent
)(
5861 VkCommandBuffer commandBuffer
,
5863 VkPipelineStageFlags stageMask
)
5865 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5866 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5868 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5869 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5871 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5872 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5873 pc
.StallAtPixelScoreboard
= true;
5874 pc
.CommandStreamerStallEnable
= true;
5877 pc
.DestinationAddressType
= DAT_PPGTT
,
5878 pc
.PostSyncOperation
= WriteImmediateData
,
5879 pc
.Address
= (struct anv_address
) {
5880 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5883 pc
.ImmediateData
= VK_EVENT_SET
;
5887 void genX(CmdResetEvent
)(
5888 VkCommandBuffer commandBuffer
,
5890 VkPipelineStageFlags stageMask
)
5892 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5893 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5895 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5896 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5898 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5899 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5900 pc
.StallAtPixelScoreboard
= true;
5901 pc
.CommandStreamerStallEnable
= true;
5904 pc
.DestinationAddressType
= DAT_PPGTT
;
5905 pc
.PostSyncOperation
= WriteImmediateData
;
5906 pc
.Address
= (struct anv_address
) {
5907 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5910 pc
.ImmediateData
= VK_EVENT_RESET
;
5914 void genX(CmdWaitEvents
)(
5915 VkCommandBuffer commandBuffer
,
5916 uint32_t eventCount
,
5917 const VkEvent
* pEvents
,
5918 VkPipelineStageFlags srcStageMask
,
5919 VkPipelineStageFlags destStageMask
,
5920 uint32_t memoryBarrierCount
,
5921 const VkMemoryBarrier
* pMemoryBarriers
,
5922 uint32_t bufferMemoryBarrierCount
,
5923 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5924 uint32_t imageMemoryBarrierCount
,
5925 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5928 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5930 for (uint32_t i
= 0; i
< eventCount
; i
++) {
5931 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
5933 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
5934 sem
.WaitMode
= PollingMode
,
5935 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
5936 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
5937 sem
.SemaphoreAddress
= (struct anv_address
) {
5938 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5944 anv_finishme("Implement events on gen7");
5947 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
5948 false, /* byRegion */
5949 memoryBarrierCount
, pMemoryBarriers
,
5950 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5951 imageMemoryBarrierCount
, pImageMemoryBarriers
);
5954 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
5955 VkCommandBuffer commandBuffer
,
5956 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
5958 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5960 switch (pOverrideInfo
->type
) {
5961 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
5965 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
5966 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5967 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5968 ._3DRenderingInstructionDisableMask
= true,
5969 .MediaInstructionDisableMask
= true);
5970 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
5972 anv_pack_struct(&dw
, GENX(INSTPM
),
5973 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5974 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5975 ._3DRenderingInstructionDisableMask
= true,
5976 .MediaInstructionDisableMask
= true);
5977 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
5982 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
5983 if (pOverrideInfo
->enable
) {
5984 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
5985 cmd_buffer
->state
.pending_pipe_bits
|=
5986 ANV_PIPE_FLUSH_BITS
|
5987 ANV_PIPE_INVALIDATE_BITS
;
5988 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5993 unreachable("Invalid override");
5999 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
6000 VkCommandBuffer commandBuffer
,
6001 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
6003 /* TODO: Waiting on the register to write, might depend on generation. */