2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_l3_config.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
36 /* We reserve GPR 14 and 15 for conditional rendering */
37 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
38 #define __gen_get_batch_dwords anv_batch_emit_dwords
39 #define __gen_address_offset anv_address_add
40 #include "common/gen_mi_builder.h"
43 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
45 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
46 lri
.RegisterOffset
= reg
;
52 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
54 struct anv_device
*device
= cmd_buffer
->device
;
56 /* If we are emitting a new state base address we probably need to re-emit
59 cmd_buffer
->state
.descriptors_dirty
|= ~0;
61 /* Emit a render target cache flush.
63 * This isn't documented anywhere in the PRM. However, it seems to be
64 * necessary prior to changing the surface state base adress. Without
65 * this, we get GPU hangs when using multi-level command buffers which
66 * clear depth, reset state base address, and then go render stuff.
68 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
69 pc
.DCFlushEnable
= true;
70 pc
.RenderTargetCacheFlushEnable
= true;
71 pc
.CommandStreamerStallEnable
= true;
74 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
75 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
76 sba
.GeneralStateMOCS
= GENX(MOCS
);
77 sba
.GeneralStateBaseAddressModifyEnable
= true;
79 sba
.SurfaceStateBaseAddress
=
80 anv_cmd_buffer_surface_base_address(cmd_buffer
);
81 sba
.SurfaceStateMOCS
= GENX(MOCS
);
82 sba
.SurfaceStateBaseAddressModifyEnable
= true;
84 sba
.DynamicStateBaseAddress
=
85 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
86 sba
.DynamicStateMOCS
= GENX(MOCS
);
87 sba
.DynamicStateBaseAddressModifyEnable
= true;
89 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
90 sba
.IndirectObjectMOCS
= GENX(MOCS
);
91 sba
.IndirectObjectBaseAddressModifyEnable
= true;
93 sba
.InstructionBaseAddress
=
94 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
95 sba
.InstructionMOCS
= GENX(MOCS
);
96 sba
.InstructionBaseAddressModifyEnable
= true;
99 /* Broadwell requires that we specify a buffer size for a bunch of
100 * these fields. However, since we will be growing the BO's live, we
101 * just set them all to the maximum.
103 sba
.GeneralStateBufferSize
= 0xfffff;
104 sba
.GeneralStateBufferSizeModifyEnable
= true;
105 sba
.DynamicStateBufferSize
= 0xfffff;
106 sba
.DynamicStateBufferSizeModifyEnable
= true;
107 sba
.IndirectObjectBufferSize
= 0xfffff;
108 sba
.IndirectObjectBufferSizeModifyEnable
= true;
109 sba
.InstructionBufferSize
= 0xfffff;
110 sba
.InstructionBuffersizeModifyEnable
= true;
113 if (cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
) {
114 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
115 .bo
= device
->surface_state_pool
.block_pool
.bo
,
118 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
120 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
121 sba
.BindlessSurfaceStateSize
= 0;
123 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
124 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
127 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
128 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
129 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
130 sba
.BindlessSamplerStateBufferSize
= 0;
134 /* After re-setting the surface state base address, we have to do some
135 * cache flusing so that the sampler engine will pick up the new
136 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
137 * Shared Function > 3D Sampler > State > State Caching (page 96):
139 * Coherency with system memory in the state cache, like the texture
140 * cache is handled partially by software. It is expected that the
141 * command stream or shader will issue Cache Flush operation or
142 * Cache_Flush sampler message to ensure that the L1 cache remains
143 * coherent with system memory.
147 * Whenever the value of the Dynamic_State_Base_Addr,
148 * Surface_State_Base_Addr are altered, the L1 state cache must be
149 * invalidated to ensure the new surface or sampler state is fetched
150 * from system memory.
152 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
153 * which, according the PIPE_CONTROL instruction documentation in the
156 * Setting this bit is independent of any other bit in this packet.
157 * This bit controls the invalidation of the L1 and L2 state caches
158 * at the top of the pipe i.e. at the parsing time.
160 * Unfortunately, experimentation seems to indicate that state cache
161 * invalidation through a PIPE_CONTROL does nothing whatsoever in
162 * regards to surface state and binding tables. In stead, it seems that
163 * invalidating the texture cache is what is actually needed.
165 * XXX: As far as we have been able to determine through
166 * experimentation, shows that flush the texture cache appears to be
167 * sufficient. The theory here is that all of the sampling/rendering
168 * units cache the binding table in the texture cache. However, we have
169 * yet to be able to actually confirm this.
171 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
172 pc
.TextureCacheInvalidationEnable
= true;
173 pc
.ConstantCacheInvalidationEnable
= true;
174 pc
.StateCacheInvalidationEnable
= true;
179 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
180 struct anv_state state
, struct anv_address addr
)
182 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
185 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
186 state
.offset
+ isl_dev
->ss
.addr_offset
,
187 addr
.bo
, addr
.offset
);
188 if (result
!= VK_SUCCESS
)
189 anv_batch_set_error(&cmd_buffer
->batch
, result
);
193 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
194 struct anv_surface_state state
)
196 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
198 assert(!anv_address_is_null(state
.address
));
199 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
201 if (!anv_address_is_null(state
.aux_address
)) {
203 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
204 &cmd_buffer
->pool
->alloc
,
205 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
206 state
.aux_address
.bo
, state
.aux_address
.offset
);
207 if (result
!= VK_SUCCESS
)
208 anv_batch_set_error(&cmd_buffer
->batch
, result
);
211 if (!anv_address_is_null(state
.clear_address
)) {
213 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
214 &cmd_buffer
->pool
->alloc
,
216 isl_dev
->ss
.clear_color_state_offset
,
217 state
.clear_address
.bo
, state
.clear_address
.offset
);
218 if (result
!= VK_SUCCESS
)
219 anv_batch_set_error(&cmd_buffer
->batch
, result
);
224 color_attachment_compute_aux_usage(struct anv_device
* device
,
225 struct anv_cmd_state
* cmd_state
,
226 uint32_t att
, VkRect2D render_area
,
227 union isl_color_value
*fast_clear_color
)
229 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
230 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
232 assert(iview
->n_planes
== 1);
234 if (iview
->planes
[0].isl
.base_array_layer
>=
235 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
236 iview
->planes
[0].isl
.base_level
)) {
237 /* There is no aux buffer which corresponds to the level and layer(s)
240 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
241 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
242 att_state
->fast_clear
= false;
246 att_state
->aux_usage
=
247 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
248 VK_IMAGE_ASPECT_COLOR_BIT
,
249 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
251 /* If we don't have aux, then we should have returned early in the layer
252 * check above. If we got here, we must have something.
254 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
256 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
257 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
258 att_state
->input_aux_usage
= att_state
->aux_usage
;
260 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
262 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
263 * setting is only allowed if Surface Format supported for Fast
264 * Clear. In addition, if the surface is bound to the sampling
265 * engine, Surface Format must be supported for Render Target
266 * Compression for surfaces bound to the sampling engine."
268 * In other words, we can only sample from a fast-cleared image if it
269 * also supports color compression.
271 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
272 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
274 /* While fast-clear resolves and partial resolves are fairly cheap in the
275 * case where you render to most of the pixels, full resolves are not
276 * because they potentially involve reading and writing the entire
277 * framebuffer. If we can't texture with CCS_E, we should leave it off and
278 * limit ourselves to fast clears.
280 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
281 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
282 anv_perf_warn(device
->instance
, iview
->image
,
283 "Not temporarily enabling CCS_E.");
286 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
290 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
291 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
293 union isl_color_value clear_color
= {};
294 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
296 att_state
->clear_color_is_zero_one
=
297 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
298 att_state
->clear_color_is_zero
=
299 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
301 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
302 /* Start by getting the fast clear type. We use the first subpass
303 * layout here because we don't want to fast-clear if the first subpass
304 * to use the attachment can't handle fast-clears.
306 enum anv_fast_clear_type fast_clear_type
=
307 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
308 VK_IMAGE_ASPECT_COLOR_BIT
,
309 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
310 switch (fast_clear_type
) {
311 case ANV_FAST_CLEAR_NONE
:
312 att_state
->fast_clear
= false;
314 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
315 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
317 case ANV_FAST_CLEAR_ANY
:
318 att_state
->fast_clear
= true;
322 /* Potentially, we could do partial fast-clears but doing so has crazy
323 * alignment restrictions. It's easier to just restrict to full size
324 * fast clears for now.
326 if (render_area
.offset
.x
!= 0 ||
327 render_area
.offset
.y
!= 0 ||
328 render_area
.extent
.width
!= iview
->extent
.width
||
329 render_area
.extent
.height
!= iview
->extent
.height
)
330 att_state
->fast_clear
= false;
332 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
333 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
334 att_state
->fast_clear
= false;
336 /* We only allow fast clears to the first slice of an image (level 0,
337 * layer 0) and only for the entire slice. This guarantees us that, at
338 * any given time, there is only one clear color on any given image at
339 * any given time. At the time of our testing (Jan 17, 2018), there
340 * were no known applications which would benefit from fast-clearing
341 * more than just the first slice.
343 if (att_state
->fast_clear
&&
344 (iview
->planes
[0].isl
.base_level
> 0 ||
345 iview
->planes
[0].isl
.base_array_layer
> 0)) {
346 anv_perf_warn(device
->instance
, iview
->image
,
347 "Rendering with multi-lod or multi-layer framebuffer "
348 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
349 "baseArrayLayer > 0. Not fast clearing.");
350 att_state
->fast_clear
= false;
351 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
352 anv_perf_warn(device
->instance
, iview
->image
,
353 "Rendering to a multi-layer framebuffer with "
354 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
357 if (att_state
->fast_clear
)
358 *fast_clear_color
= clear_color
;
360 att_state
->fast_clear
= false;
365 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
366 struct anv_cmd_state
*cmd_state
,
367 uint32_t att
, VkRect2D render_area
)
369 struct anv_render_pass_attachment
*pass_att
=
370 &cmd_state
->pass
->attachments
[att
];
371 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
372 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
374 /* These will be initialized after the first subpass transition. */
375 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
376 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
379 /* We don't do any HiZ or depth fast-clears on gen7 yet */
380 att_state
->fast_clear
= false;
384 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
385 /* If we're just clearing stencil, we can always HiZ clear */
386 att_state
->fast_clear
= true;
390 /* Default to false for now */
391 att_state
->fast_clear
= false;
393 /* We must have depth in order to have HiZ */
394 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
397 const enum isl_aux_usage first_subpass_aux_usage
=
398 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
399 VK_IMAGE_ASPECT_DEPTH_BIT
,
400 pass_att
->first_subpass_layout
);
401 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
404 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
405 iview
->planes
[0].isl
.format
,
406 iview
->image
->samples
,
407 render_area
.offset
.x
,
408 render_area
.offset
.y
,
409 render_area
.offset
.x
+
410 render_area
.extent
.width
,
411 render_area
.offset
.y
+
412 render_area
.extent
.height
))
415 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
418 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
419 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
420 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
421 * only supports returning 0.0f. Gens prior to gen8 do not support this
427 /* If we got here, then we can fast clear */
428 att_state
->fast_clear
= true;
432 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
434 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
437 /* We only allocate input attachment states for color surfaces. Compression
438 * is not yet enabled for depth textures and stencil doesn't allow
439 * compression so we can just use the texture surface state from the view.
441 return vk_format_is_color(att
->format
);
444 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
445 * the initial layout is undefined, the HiZ buffer and depth buffer will
446 * represent the same data at the end of this operation.
449 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
450 const struct anv_image
*image
,
451 VkImageLayout initial_layout
,
452 VkImageLayout final_layout
)
454 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
455 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
456 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
457 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
458 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
459 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
461 enum isl_aux_op hiz_op
;
462 if (hiz_enabled
&& !enable_hiz
) {
463 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
464 } else if (!hiz_enabled
&& enable_hiz
) {
465 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
467 assert(hiz_enabled
== enable_hiz
);
468 /* If the same buffer will be used, no resolves are necessary. */
469 hiz_op
= ISL_AUX_OP_NONE
;
472 if (hiz_op
!= ISL_AUX_OP_NONE
)
473 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
478 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
480 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
481 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
;
484 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
485 * the initial layout is undefined, the HiZ buffer and depth buffer will
486 * represent the same data at the end of this operation.
489 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
490 const struct anv_image
*image
,
491 uint32_t base_level
, uint32_t level_count
,
492 uint32_t base_layer
, uint32_t layer_count
,
493 VkImageLayout initial_layout
,
494 VkImageLayout final_layout
)
497 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
498 VK_IMAGE_ASPECT_STENCIL_BIT
);
500 /* On gen7, we have to store a texturable version of the stencil buffer in
501 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
502 * forth at strategic points. Stencil writes are only allowed in three
505 * - VK_IMAGE_LAYOUT_GENERAL
506 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
507 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
508 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
510 * For general, we have no nice opportunity to transition so we do the copy
511 * to the shadow unconditionally at the end of the subpass. For transfer
512 * destinations, we can update it as part of the transfer op. For the
513 * other two, we delay the copy until a transition into some other layout.
515 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
516 vk_image_layout_stencil_write_optimal(initial_layout
) &&
517 !vk_image_layout_stencil_write_optimal(final_layout
)) {
518 anv_image_copy_to_shadow(cmd_buffer
, image
,
519 VK_IMAGE_ASPECT_STENCIL_BIT
,
520 base_level
, level_count
,
521 base_layer
, layer_count
);
523 #endif /* GEN_GEN == 7 */
526 #define MI_PREDICATE_SRC0 0x2400
527 #define MI_PREDICATE_SRC1 0x2408
528 #define MI_PREDICATE_RESULT 0x2418
531 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
532 const struct anv_image
*image
,
533 VkImageAspectFlagBits aspect
,
535 uint32_t base_layer
, uint32_t layer_count
,
538 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
540 /* We only have compression tracking for CCS_E */
541 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
544 for (uint32_t a
= 0; a
< layer_count
; a
++) {
545 uint32_t layer
= base_layer
+ a
;
546 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
547 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
550 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
556 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
557 const struct anv_image
*image
,
558 VkImageAspectFlagBits aspect
,
559 enum anv_fast_clear_type fast_clear
)
561 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
562 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
564 sdi
.ImmediateData
= fast_clear
;
567 /* Whenever we have fast-clear, we consider that slice to be compressed.
568 * This makes building predicates much easier.
570 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
571 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
574 #if GEN_IS_HASWELL || GEN_GEN >= 8
575 static inline uint32_t
576 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
578 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
580 .Operand1
= operand1
,
581 .Operand2
= operand2
,
585 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
591 /* This is only really practical on haswell and above because it requires
592 * MI math in order to get it correct.
594 #if GEN_GEN >= 8 || GEN_IS_HASWELL
596 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
597 const struct anv_image
*image
,
598 VkImageAspectFlagBits aspect
,
599 uint32_t level
, uint32_t array_layer
,
600 enum isl_aux_op resolve_op
,
601 enum anv_fast_clear_type fast_clear_supported
)
603 struct gen_mi_builder b
;
604 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
606 const struct gen_mi_value fast_clear_type
=
607 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
610 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
611 /* In this case, we're doing a full resolve which means we want the
612 * resolve to happen if any compression (including fast-clears) is
615 * In order to simplify the logic a bit, we make the assumption that,
616 * if the first slice has been fast-cleared, it is also marked as
617 * compressed. See also set_image_fast_clear_state.
619 const struct gen_mi_value compression_state
=
620 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
622 level
, array_layer
));
623 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
625 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
627 if (level
== 0 && array_layer
== 0) {
628 /* If the predicate is true, we want to write 0 to the fast clear type
629 * and, if it's false, leave it alone. We can do this by writing
631 * clear_type = clear_type & ~predicate;
633 struct gen_mi_value new_fast_clear_type
=
634 gen_mi_iand(&b
, fast_clear_type
,
635 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
636 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
638 } else if (level
== 0 && array_layer
== 0) {
639 /* In this case, we are doing a partial resolve to get rid of fast-clear
640 * colors. We don't care about the compression state but we do care
641 * about how much fast clear is allowed by the final layout.
643 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
644 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
646 /* We need to compute (fast_clear_supported < image->fast_clear) */
647 struct gen_mi_value pred
=
648 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
649 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
650 gen_mi_value_ref(&b
, pred
));
652 /* If the predicate is true, we want to write 0 to the fast clear type
653 * and, if it's false, leave it alone. We can do this by writing
655 * clear_type = clear_type & ~predicate;
657 struct gen_mi_value new_fast_clear_type
=
658 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
659 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
661 /* In this case, we're trying to do a partial resolve on a slice that
662 * doesn't have clear color. There's nothing to do.
664 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
668 /* Set src1 to 0 and use a != condition */
669 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
671 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
672 mip
.LoadOperation
= LOAD_LOADINV
;
673 mip
.CombineOperation
= COMBINE_SET
;
674 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
677 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
681 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
682 const struct anv_image
*image
,
683 VkImageAspectFlagBits aspect
,
684 uint32_t level
, uint32_t array_layer
,
685 enum isl_aux_op resolve_op
,
686 enum anv_fast_clear_type fast_clear_supported
)
688 struct gen_mi_builder b
;
689 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
691 struct gen_mi_value fast_clear_type_mem
=
692 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
695 /* This only works for partial resolves and only when the clear color is
696 * all or nothing. On the upside, this emits less command streamer code
697 * and works on Ivybridge and Bay Trail.
699 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
700 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
702 /* We don't support fast clears on anything other than the first slice. */
703 if (level
> 0 || array_layer
> 0)
706 /* On gen8, we don't have a concept of default clear colors because we
707 * can't sample from CCS surfaces. It's enough to just load the fast clear
708 * state into the predicate register.
710 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
711 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
712 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
714 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
715 mip
.LoadOperation
= LOAD_LOADINV
;
716 mip
.CombineOperation
= COMBINE_SET
;
717 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
720 #endif /* GEN_GEN <= 8 */
723 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
724 const struct anv_image
*image
,
725 enum isl_format format
,
726 VkImageAspectFlagBits aspect
,
727 uint32_t level
, uint32_t array_layer
,
728 enum isl_aux_op resolve_op
,
729 enum anv_fast_clear_type fast_clear_supported
)
731 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
734 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
735 aspect
, level
, array_layer
,
736 resolve_op
, fast_clear_supported
);
737 #else /* GEN_GEN <= 8 */
738 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
739 aspect
, level
, array_layer
,
740 resolve_op
, fast_clear_supported
);
743 /* CCS_D only supports full resolves and BLORP will assert on us if we try
744 * to do a partial resolve on a CCS_D surface.
746 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
747 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
748 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
750 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
751 array_layer
, 1, resolve_op
, NULL
, true);
755 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
756 const struct anv_image
*image
,
757 enum isl_format format
,
758 VkImageAspectFlagBits aspect
,
759 uint32_t array_layer
,
760 enum isl_aux_op resolve_op
,
761 enum anv_fast_clear_type fast_clear_supported
)
763 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
764 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
766 #if GEN_GEN >= 8 || GEN_IS_HASWELL
767 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
768 aspect
, 0, array_layer
,
769 resolve_op
, fast_clear_supported
);
771 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
772 array_layer
, 1, resolve_op
, NULL
, true);
774 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
779 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
780 const struct anv_image
*image
,
781 VkImageAspectFlagBits aspect
,
782 enum isl_aux_usage aux_usage
,
785 uint32_t layer_count
)
787 /* The aspect must be exactly one of the image aspects. */
788 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
790 /* The only compression types with more than just fast-clears are MCS,
791 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
792 * track the current fast-clear and compression state. This leaves us
793 * with just MCS and CCS_E.
795 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
796 aux_usage
!= ISL_AUX_USAGE_MCS
)
799 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
800 level
, base_layer
, layer_count
, true);
804 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
805 const struct anv_image
*image
,
806 VkImageAspectFlagBits aspect
)
808 assert(cmd_buffer
&& image
);
809 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
811 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
812 ANV_FAST_CLEAR_NONE
);
814 /* Initialize the struct fields that are accessed for fast-clears so that
815 * the HW restrictions on the field values are satisfied.
817 struct anv_address addr
=
818 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
821 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
822 const unsigned num_dwords
= GEN_GEN
>= 10 ?
823 isl_dev
->ss
.clear_color_state_size
/ 4 :
824 isl_dev
->ss
.clear_value_size
/ 4;
825 for (unsigned i
= 0; i
< num_dwords
; i
++) {
826 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
828 sdi
.Address
.offset
+= i
* 4;
829 sdi
.ImmediateData
= 0;
833 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
835 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
836 /* Pre-SKL, the dword containing the clear values also contains
837 * other fields, so we need to initialize those fields to match the
838 * values that would be in a color attachment.
840 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
841 ISL_CHANNEL_SELECT_GREEN
<< 22 |
842 ISL_CHANNEL_SELECT_BLUE
<< 19 |
843 ISL_CHANNEL_SELECT_ALPHA
<< 16;
844 } else if (GEN_GEN
== 7) {
845 /* On IVB, the dword containing the clear values also contains
846 * other fields that must be zero or can be zero.
848 sdi
.ImmediateData
= 0;
854 /* Copy the fast-clear value dword(s) between a surface state object and an
855 * image's fast clear state buffer.
858 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
859 struct anv_state surface_state
,
860 const struct anv_image
*image
,
861 VkImageAspectFlagBits aspect
,
862 bool copy_from_surface_state
)
864 assert(cmd_buffer
&& image
);
865 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
867 struct anv_address ss_clear_addr
= {
868 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
869 .offset
= surface_state
.offset
+
870 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
872 const struct anv_address entry_addr
=
873 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
874 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
877 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
878 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
879 * in-flight when they are issued even if the memory touched is not
880 * currently active for rendering. The weird bit is that it is not the
881 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
882 * rendering hangs such that the next stalling command after the
883 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
885 * It is unclear exactly why this hang occurs. Both MI commands come with
886 * warnings about the 3D pipeline but that doesn't seem to fully explain
887 * it. My (Jason's) best theory is that it has something to do with the
888 * fact that we're using a GPU state register as our temporary and that
889 * something with reading/writing it is causing problems.
891 * In order to work around this issue, we emit a PIPE_CONTROL with the
892 * command streamer stall bit set.
894 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
895 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
898 struct gen_mi_builder b
;
899 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
901 if (copy_from_surface_state
) {
902 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
904 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
906 /* Updating a surface state object may require that the state cache be
907 * invalidated. From the SKL PRM, Shared Functions -> State -> State
910 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
911 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
912 * modified [...], the L1 state cache must be invalidated to ensure
913 * the new surface or sampler state is fetched from system memory.
915 * In testing, SKL doesn't actually seem to need this, but HSW does.
917 cmd_buffer
->state
.pending_pipe_bits
|=
918 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
923 * @brief Transitions a color buffer from one layout to another.
925 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
928 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
929 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
930 * this represents the maximum layers to transition at each
931 * specified miplevel.
934 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
935 const struct anv_image
*image
,
936 VkImageAspectFlagBits aspect
,
937 const uint32_t base_level
, uint32_t level_count
,
938 uint32_t base_layer
, uint32_t layer_count
,
939 VkImageLayout initial_layout
,
940 VkImageLayout final_layout
)
942 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
943 /* Validate the inputs. */
945 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
946 /* These values aren't supported for simplicity's sake. */
947 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
948 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
949 /* Ensure the subresource range is valid. */
950 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
951 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
952 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
953 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
954 assert(last_level_num
<= image
->levels
);
955 /* The spec disallows these final layouts. */
956 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
957 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
959 /* No work is necessary if the layout stays the same or if this subresource
960 * range lacks auxiliary data.
962 if (initial_layout
== final_layout
)
965 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
967 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
968 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
969 /* This surface is a linear compressed image with a tiled shadow surface
970 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
971 * we need to ensure the shadow copy is up-to-date.
973 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
974 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
975 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
976 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
978 anv_image_copy_to_shadow(cmd_buffer
, image
,
979 VK_IMAGE_ASPECT_COLOR_BIT
,
980 base_level
, level_count
,
981 base_layer
, layer_count
);
984 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
987 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
989 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
990 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
991 /* A subresource in the undefined layout may have been aliased and
992 * populated with any arrangement of bits. Therefore, we must initialize
993 * the related aux buffer and clear buffer entry with desirable values.
994 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
995 * images with VK_IMAGE_TILING_OPTIMAL.
997 * Initialize the relevant clear buffer entries.
999 if (base_level
== 0 && base_layer
== 0)
1000 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1002 /* Initialize the aux buffers to enable correct rendering. In order to
1003 * ensure that things such as storage images work correctly, aux buffers
1004 * need to be initialized to valid data.
1006 * Having an aux buffer with invalid data is a problem for two reasons:
1008 * 1) Having an invalid value in the buffer can confuse the hardware.
1009 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1010 * invalid and leads to the hardware doing strange things. It
1011 * doesn't hang as far as we can tell but rendering corruption can
1014 * 2) If this transition is into the GENERAL layout and we then use the
1015 * image as a storage image, then we must have the aux buffer in the
1016 * pass-through state so that, if we then go to texture from the
1017 * image, we get the results of our storage image writes and not the
1018 * fast clear color or other random data.
1020 * For CCS both of the problems above are real demonstrable issues. In
1021 * that case, the only thing we can do is to perform an ambiguate to
1022 * transition the aux surface into the pass-through state.
1024 * For MCS, (2) is never an issue because we don't support multisampled
1025 * storage images. In theory, issue (1) is a problem with MCS but we've
1026 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1027 * theory, be interpreted as something but we don't know that all bit
1028 * patterns are actually valid. For 2x and 8x, you could easily end up
1029 * with the MCS referring to an invalid plane because not all bits of
1030 * the MCS value are actually used. Even though we've never seen issues
1031 * in the wild, it's best to play it safe and initialize the MCS. We
1032 * can use a fast-clear for MCS because we only ever touch from render
1033 * and texture (no image load store).
1035 if (image
->samples
== 1) {
1036 for (uint32_t l
= 0; l
< level_count
; l
++) {
1037 const uint32_t level
= base_level
+ l
;
1039 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1040 if (base_layer
>= aux_layers
)
1041 break; /* We will only get fewer layers as level increases */
1042 uint32_t level_layer_count
=
1043 MIN2(layer_count
, aux_layers
- base_layer
);
1045 anv_image_ccs_op(cmd_buffer
, image
,
1046 image
->planes
[plane
].surface
.isl
.format
,
1047 aspect
, level
, base_layer
, level_layer_count
,
1048 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1050 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1051 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1052 level
, base_layer
, level_layer_count
,
1057 if (image
->samples
== 4 || image
->samples
== 16) {
1058 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1059 "Doing a potentially unnecessary fast-clear to "
1060 "define an MCS buffer.");
1063 assert(base_level
== 0 && level_count
== 1);
1064 anv_image_mcs_op(cmd_buffer
, image
,
1065 image
->planes
[plane
].surface
.isl
.format
,
1066 aspect
, base_layer
, layer_count
,
1067 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1072 const enum isl_aux_usage initial_aux_usage
=
1073 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1074 const enum isl_aux_usage final_aux_usage
=
1075 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1077 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1078 * We can handle transitions between CCS_D/E to and from NONE. What we
1079 * don't yet handle is switching between CCS_E and CCS_D within a given
1080 * image. Doing so in a performant way requires more detailed aux state
1081 * tracking such as what is done in i965. For now, just assume that we
1082 * only have one type of compression.
1084 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1085 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1086 initial_aux_usage
== final_aux_usage
);
1088 /* If initial aux usage is NONE, there is nothing to resolve */
1089 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1092 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1094 /* If the initial layout supports more fast clear than the final layout
1095 * then we need at least a partial resolve.
1097 const enum anv_fast_clear_type initial_fast_clear
=
1098 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1099 const enum anv_fast_clear_type final_fast_clear
=
1100 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1101 if (final_fast_clear
< initial_fast_clear
)
1102 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1104 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1105 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1106 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1108 if (resolve_op
== ISL_AUX_OP_NONE
)
1111 /* Perform a resolve to synchronize data between the main and aux buffer.
1112 * Before we begin, we must satisfy the cache flushing requirement specified
1113 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1115 * Any transition from any value in {Clear, Render, Resolve} to a
1116 * different value in {Clear, Render, Resolve} requires end of pipe
1119 * We perform a flush of the write cache before and after the clear and
1120 * resolve operations to meet this requirement.
1122 * Unlike other drawing, fast clear operations are not properly
1123 * synchronized. The first PIPE_CONTROL here likely ensures that the
1124 * contents of the previous render or clear hit the render target before we
1125 * resolve and the second likely ensures that the resolve is complete before
1126 * we do any more rendering or clearing.
1128 cmd_buffer
->state
.pending_pipe_bits
|=
1129 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1131 for (uint32_t l
= 0; l
< level_count
; l
++) {
1132 uint32_t level
= base_level
+ l
;
1134 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1135 if (base_layer
>= aux_layers
)
1136 break; /* We will only get fewer layers as level increases */
1137 uint32_t level_layer_count
=
1138 MIN2(layer_count
, aux_layers
- base_layer
);
1140 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1141 uint32_t array_layer
= base_layer
+ a
;
1142 if (image
->samples
== 1) {
1143 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1144 image
->planes
[plane
].surface
.isl
.format
,
1145 aspect
, level
, array_layer
, resolve_op
,
1148 /* We only support fast-clear on the first layer so partial
1149 * resolves should not be used on other layers as they will use
1150 * the clear color stored in memory that is only valid for layer0.
1152 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1156 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1157 image
->planes
[plane
].surface
.isl
.format
,
1158 aspect
, array_layer
, resolve_op
,
1164 cmd_buffer
->state
.pending_pipe_bits
|=
1165 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1169 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1172 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1173 struct anv_render_pass
*pass
,
1174 const VkRenderPassBeginInfo
*begin
)
1176 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1177 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1179 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1181 if (pass
->attachment_count
> 0) {
1182 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1183 pass
->attachment_count
*
1184 sizeof(state
->attachments
[0]),
1185 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1186 if (state
->attachments
== NULL
) {
1187 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1188 return anv_batch_set_error(&cmd_buffer
->batch
,
1189 VK_ERROR_OUT_OF_HOST_MEMORY
);
1192 state
->attachments
= NULL
;
1195 /* Reserve one for the NULL state. */
1196 unsigned num_states
= 1;
1197 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1198 if (vk_format_is_color(pass
->attachments
[i
].format
))
1201 if (need_input_attachment_state(&pass
->attachments
[i
]))
1205 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1206 state
->render_pass_states
=
1207 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1208 num_states
* ss_stride
, isl_dev
->ss
.align
);
1210 struct anv_state next_state
= state
->render_pass_states
;
1211 next_state
.alloc_size
= isl_dev
->ss
.size
;
1213 state
->null_surface_state
= next_state
;
1214 next_state
.offset
+= ss_stride
;
1215 next_state
.map
+= ss_stride
;
1217 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1218 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1219 state
->attachments
[i
].color
.state
= next_state
;
1220 next_state
.offset
+= ss_stride
;
1221 next_state
.map
+= ss_stride
;
1224 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1225 state
->attachments
[i
].input
.state
= next_state
;
1226 next_state
.offset
+= ss_stride
;
1227 next_state
.map
+= ss_stride
;
1230 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1231 state
->render_pass_states
.alloc_size
);
1234 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1235 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1237 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1238 isl_extent3d(framebuffer
->width
,
1239 framebuffer
->height
,
1240 framebuffer
->layers
));
1242 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1243 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1244 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1245 VkImageAspectFlags clear_aspects
= 0;
1246 VkImageAspectFlags load_aspects
= 0;
1248 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1249 /* color attachment */
1250 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1251 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1252 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1253 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1256 /* depthstencil attachment */
1257 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1258 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1259 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1260 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1261 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1264 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1265 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1266 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1267 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1268 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1273 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1274 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1275 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1277 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1279 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1280 anv_assert(iview
->vk_format
== att
->format
);
1282 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1283 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1285 union isl_color_value clear_color
= { .u32
= { 0, } };
1286 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1287 anv_assert(iview
->n_planes
== 1);
1288 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1289 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1290 state
, i
, begin
->renderArea
,
1293 anv_image_fill_surface_state(cmd_buffer
->device
,
1295 VK_IMAGE_ASPECT_COLOR_BIT
,
1296 &iview
->planes
[0].isl
,
1297 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1298 state
->attachments
[i
].aux_usage
,
1301 &state
->attachments
[i
].color
,
1304 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1306 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1311 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1312 anv_image_fill_surface_state(cmd_buffer
->device
,
1314 VK_IMAGE_ASPECT_COLOR_BIT
,
1315 &iview
->planes
[0].isl
,
1316 ISL_SURF_USAGE_TEXTURE_BIT
,
1317 state
->attachments
[i
].input_aux_usage
,
1320 &state
->attachments
[i
].input
,
1323 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1332 genX(BeginCommandBuffer
)(
1333 VkCommandBuffer commandBuffer
,
1334 const VkCommandBufferBeginInfo
* pBeginInfo
)
1336 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1338 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1339 * command buffer's state. Otherwise, we must *reset* its state. In both
1340 * cases we reset it.
1342 * From the Vulkan 1.0 spec:
1344 * If a command buffer is in the executable state and the command buffer
1345 * was allocated from a command pool with the
1346 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1347 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1348 * as if vkResetCommandBuffer had been called with
1349 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1350 * the command buffer in the recording state.
1352 anv_cmd_buffer_reset(cmd_buffer
);
1354 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1356 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1357 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1359 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1361 /* We sometimes store vertex data in the dynamic state buffer for blorp
1362 * operations and our dynamic state stream may re-use data from previous
1363 * command buffers. In order to prevent stale cache data, we flush the VF
1364 * cache. We could do this on every blorp call but that's not really
1365 * needed as all of the data will get written by the CPU prior to the GPU
1366 * executing anything. The chances are fairly high that they will use
1367 * blorp at least once per primary command buffer so it shouldn't be
1370 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1371 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1373 /* We send an "Indirect State Pointers Disable" packet at
1374 * EndCommandBuffer, so all push contant packets are ignored during a
1375 * context restore. Documentation says after that command, we need to
1376 * emit push constants again before any rendering operation. So we
1377 * flag them dirty here to make sure they get emitted.
1379 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1381 VkResult result
= VK_SUCCESS
;
1382 if (cmd_buffer
->usage_flags
&
1383 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1384 assert(pBeginInfo
->pInheritanceInfo
);
1385 cmd_buffer
->state
.pass
=
1386 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1387 cmd_buffer
->state
.subpass
=
1388 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1390 /* This is optional in the inheritance info. */
1391 cmd_buffer
->state
.framebuffer
=
1392 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1394 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1395 cmd_buffer
->state
.pass
, NULL
);
1397 /* Record that HiZ is enabled if we can. */
1398 if (cmd_buffer
->state
.framebuffer
) {
1399 const struct anv_image_view
* const iview
=
1400 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1403 VkImageLayout layout
=
1404 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1406 enum isl_aux_usage aux_usage
=
1407 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1408 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1410 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1414 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1417 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1418 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1419 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1420 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1422 /* If secondary buffer supports conditional rendering
1423 * we should emit commands as if conditional rendering is enabled.
1425 cmd_buffer
->state
.conditional_render_enabled
=
1426 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1433 /* From the PRM, Volume 2a:
1435 * "Indirect State Pointers Disable
1437 * At the completion of the post-sync operation associated with this pipe
1438 * control packet, the indirect state pointers in the hardware are
1439 * considered invalid; the indirect pointers are not saved in the context.
1440 * If any new indirect state commands are executed in the command stream
1441 * while the pipe control is pending, the new indirect state commands are
1444 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1445 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1446 * commands are only considered as Indirect State Pointers. Once ISP is
1447 * issued in a context, SW must initialize by programming push constant
1448 * commands for all the shaders (at least to zero length) before attempting
1449 * any rendering operation for the same context."
1451 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1452 * even though they point to a BO that has been already unreferenced at
1453 * the end of the previous batch buffer. This has been fine so far since
1454 * we are protected by these scratch page (every address not covered by
1455 * a BO should be pointing to the scratch page). But on CNL, it is
1456 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1459 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1460 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1461 * context restore, so the mentioned hang doesn't happen. However,
1462 * software must program push constant commands for all stages prior to
1463 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1465 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1466 * constants have been loaded into the EUs prior to disable the push constants
1467 * so that it doesn't hang a previous 3DPRIMITIVE.
1470 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1472 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1473 pc
.StallAtPixelScoreboard
= true;
1474 pc
.CommandStreamerStallEnable
= true;
1476 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1477 pc
.IndirectStatePointersDisable
= true;
1478 pc
.CommandStreamerStallEnable
= true;
1483 genX(EndCommandBuffer
)(
1484 VkCommandBuffer commandBuffer
)
1486 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1488 if (anv_batch_has_error(&cmd_buffer
->batch
))
1489 return cmd_buffer
->batch
.status
;
1491 /* We want every command buffer to start with the PMA fix in a known state,
1492 * so we disable it at the end of the command buffer.
1494 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1496 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1498 emit_isp_disable(cmd_buffer
);
1500 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1506 genX(CmdExecuteCommands
)(
1507 VkCommandBuffer commandBuffer
,
1508 uint32_t commandBufferCount
,
1509 const VkCommandBuffer
* pCmdBuffers
)
1511 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1513 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1515 if (anv_batch_has_error(&primary
->batch
))
1518 /* The secondary command buffers will assume that the PMA fix is disabled
1519 * when they begin executing. Make sure this is true.
1521 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1523 /* The secondary command buffer doesn't know which textures etc. have been
1524 * flushed prior to their execution. Apply those flushes now.
1526 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1528 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1529 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1531 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1532 assert(!anv_batch_has_error(&secondary
->batch
));
1534 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1535 if (secondary
->state
.conditional_render_enabled
) {
1536 if (!primary
->state
.conditional_render_enabled
) {
1537 /* Secondary buffer is constructed as if it will be executed
1538 * with conditional rendering, we should satisfy this dependency
1539 * regardless of conditional rendering being enabled in primary.
1541 struct gen_mi_builder b
;
1542 gen_mi_builder_init(&b
, &primary
->batch
);
1543 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1544 gen_mi_imm(UINT64_MAX
));
1549 if (secondary
->usage_flags
&
1550 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1551 /* If we're continuing a render pass from the primary, we need to
1552 * copy the surface states for the current subpass into the storage
1553 * we allocated for them in BeginCommandBuffer.
1555 struct anv_bo
*ss_bo
=
1556 primary
->device
->surface_state_pool
.block_pool
.bo
;
1557 struct anv_state src_state
= primary
->state
.render_pass_states
;
1558 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1559 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1561 genX(cmd_buffer_so_memcpy
)(primary
,
1562 (struct anv_address
) {
1564 .offset
= dst_state
.offset
,
1566 (struct anv_address
) {
1568 .offset
= src_state
.offset
,
1570 src_state
.alloc_size
);
1573 anv_cmd_buffer_add_secondary(primary
, secondary
);
1576 /* The secondary may have selected a different pipeline (3D or compute) and
1577 * may have changed the current L3$ configuration. Reset our tracking
1578 * variables to invalid values to ensure that we re-emit these in the case
1579 * where we do any draws or compute dispatches from the primary after the
1580 * secondary has returned.
1582 primary
->state
.current_pipeline
= UINT32_MAX
;
1583 primary
->state
.current_l3_config
= NULL
;
1585 /* Each of the secondary command buffers will use its own state base
1586 * address. We need to re-emit state base address for the primary after
1587 * all of the secondaries are done.
1589 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1592 genX(cmd_buffer_emit_state_base_address
)(primary
);
1595 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1596 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1597 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1600 * Program the hardware to use the specified L3 configuration.
1603 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1604 const struct gen_l3_config
*cfg
)
1607 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1610 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1611 intel_logd("L3 config transition: ");
1612 gen_dump_l3_config(cfg
, stderr
);
1615 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1617 /* According to the hardware docs, the L3 partitioning can only be changed
1618 * while the pipeline is completely drained and the caches are flushed,
1619 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1621 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1622 pc
.DCFlushEnable
= true;
1623 pc
.PostSyncOperation
= NoWrite
;
1624 pc
.CommandStreamerStallEnable
= true;
1627 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1628 * invalidation of the relevant caches. Note that because RO invalidation
1629 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1630 * command is processed by the CS) we cannot combine it with the previous
1631 * stalling flush as the hardware documentation suggests, because that
1632 * would cause the CS to stall on previous rendering *after* RO
1633 * invalidation and wouldn't prevent the RO caches from being polluted by
1634 * concurrent rendering before the stall completes. This intentionally
1635 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1636 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1637 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1638 * already guarantee that there is no concurrent GPGPU kernel execution
1639 * (see SKL HSD 2132585).
1641 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1642 pc
.TextureCacheInvalidationEnable
= true;
1643 pc
.ConstantCacheInvalidationEnable
= true;
1644 pc
.InstructionCacheInvalidateEnable
= true;
1645 pc
.StateCacheInvalidationEnable
= true;
1646 pc
.PostSyncOperation
= NoWrite
;
1649 /* Now send a third stalling flush to make sure that invalidation is
1650 * complete when the L3 configuration registers are modified.
1652 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1653 pc
.DCFlushEnable
= true;
1654 pc
.PostSyncOperation
= NoWrite
;
1655 pc
.CommandStreamerStallEnable
= true;
1660 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1663 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1664 .SLMEnable
= has_slm
,
1666 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1667 * in L3CNTLREG register. The default setting of the bit is not the
1668 * desirable behavior.
1670 .ErrorDetectionBehaviorControl
= true,
1671 .UseFullWays
= true,
1673 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1674 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1675 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1676 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1678 /* Set up the L3 partitioning. */
1679 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1683 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1684 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1685 cfg
->n
[GEN_L3P_ALL
];
1686 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1687 cfg
->n
[GEN_L3P_ALL
];
1688 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1689 cfg
->n
[GEN_L3P_ALL
];
1691 assert(!cfg
->n
[GEN_L3P_ALL
]);
1693 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1694 * the matching space on the remaining banks has to be allocated to a
1695 * client (URB for all validated configurations) set to the
1696 * lower-bandwidth 2-bank address hashing mode.
1698 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1699 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1700 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1702 /* Minimum number of ways that can be allocated to the URB. */
1703 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1704 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1706 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1707 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1708 .ConvertDC_UC
= !has_dc
,
1709 .ConvertIS_UC
= !has_is
,
1710 .ConvertC_UC
= !has_c
,
1711 .ConvertT_UC
= !has_t
);
1713 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1714 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1715 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1717 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1718 .SLMEnable
= has_slm
,
1719 .URBLowBandwidth
= urb_low_bw
,
1720 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1722 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1724 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1725 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1727 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1728 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1729 .ISLowBandwidth
= 0,
1730 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1732 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1733 .TLowBandwidth
= 0);
1735 /* Set up the L3 partitioning. */
1736 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1737 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1738 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1741 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1742 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1743 * them disabled to avoid crashing the system hard.
1745 uint32_t scratch1
, chicken3
;
1746 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1747 .L3AtomicDisable
= !has_dc
);
1748 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1749 .L3AtomicDisableMask
= true,
1750 .L3AtomicDisable
= !has_dc
);
1751 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1752 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1758 cmd_buffer
->state
.current_l3_config
= cfg
;
1762 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1764 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1766 /* Flushes are pipelined while invalidations are handled immediately.
1767 * Therefore, if we're flushing anything then we need to schedule a stall
1768 * before any invalidations can happen.
1770 if (bits
& ANV_PIPE_FLUSH_BITS
)
1771 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1773 /* If we're going to do an invalidate and we have a pending CS stall that
1774 * has yet to be resolved, we do the CS stall now.
1776 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1777 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1778 bits
|= ANV_PIPE_CS_STALL_BIT
;
1779 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1782 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1783 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1784 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1785 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1786 pipe
.RenderTargetCacheFlushEnable
=
1787 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1789 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1790 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1791 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1794 * According to the Broadwell documentation, any PIPE_CONTROL with the
1795 * "Command Streamer Stall" bit set must also have another bit set,
1796 * with five different options:
1798 * - Render Target Cache Flush
1799 * - Depth Cache Flush
1800 * - Stall at Pixel Scoreboard
1801 * - Post-Sync Operation
1805 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1806 * mesa and it seems to work fine. The choice is fairly arbitrary.
1808 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1809 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1810 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1811 pipe
.StallAtPixelScoreboard
= true;
1814 /* If a render target flush was emitted, then we can toggle off the bit
1815 * saying that render target writes are ongoing.
1817 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1818 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1820 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1823 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1824 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1826 * "If the VF Cache Invalidation Enable is set to a 1 in a
1827 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1828 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1829 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1832 * This appears to hang Broadwell, so we restrict it to just gen9.
1834 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1835 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1837 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1838 pipe
.StateCacheInvalidationEnable
=
1839 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1840 pipe
.ConstantCacheInvalidationEnable
=
1841 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1842 pipe
.VFCacheInvalidationEnable
=
1843 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1844 pipe
.TextureCacheInvalidationEnable
=
1845 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1846 pipe
.InstructionCacheInvalidateEnable
=
1847 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1849 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1851 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1852 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1853 * “Write Timestamp”.
1855 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1856 pipe
.PostSyncOperation
= WriteImmediateData
;
1858 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1862 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1865 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1868 void genX(CmdPipelineBarrier
)(
1869 VkCommandBuffer commandBuffer
,
1870 VkPipelineStageFlags srcStageMask
,
1871 VkPipelineStageFlags destStageMask
,
1873 uint32_t memoryBarrierCount
,
1874 const VkMemoryBarrier
* pMemoryBarriers
,
1875 uint32_t bufferMemoryBarrierCount
,
1876 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1877 uint32_t imageMemoryBarrierCount
,
1878 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1880 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1882 /* XXX: Right now, we're really dumb and just flush whatever categories
1883 * the app asks for. One of these days we may make this a bit better
1884 * but right now that's all the hardware allows for in most areas.
1886 VkAccessFlags src_flags
= 0;
1887 VkAccessFlags dst_flags
= 0;
1889 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1890 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1891 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1894 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1895 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1896 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1899 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1900 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1901 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1902 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1903 const VkImageSubresourceRange
*range
=
1904 &pImageMemoryBarriers
[i
].subresourceRange
;
1906 uint32_t base_layer
, layer_count
;
1907 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1909 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1911 base_layer
= range
->baseArrayLayer
;
1912 layer_count
= anv_get_layerCount(image
, range
);
1915 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1916 transition_depth_buffer(cmd_buffer
, image
,
1917 pImageMemoryBarriers
[i
].oldLayout
,
1918 pImageMemoryBarriers
[i
].newLayout
);
1921 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1922 transition_stencil_buffer(cmd_buffer
, image
,
1923 range
->baseMipLevel
,
1924 anv_get_levelCount(image
, range
),
1925 base_layer
, layer_count
,
1926 pImageMemoryBarriers
[i
].oldLayout
,
1927 pImageMemoryBarriers
[i
].newLayout
);
1930 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1931 VkImageAspectFlags color_aspects
=
1932 anv_image_expand_aspects(image
, range
->aspectMask
);
1933 uint32_t aspect_bit
;
1934 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1935 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1936 range
->baseMipLevel
,
1937 anv_get_levelCount(image
, range
),
1938 base_layer
, layer_count
,
1939 pImageMemoryBarriers
[i
].oldLayout
,
1940 pImageMemoryBarriers
[i
].newLayout
);
1945 cmd_buffer
->state
.pending_pipe_bits
|=
1946 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1947 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1951 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1953 VkShaderStageFlags stages
=
1954 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1956 /* In order to avoid thrash, we assume that vertex and fragment stages
1957 * always exist. In the rare case where one is missing *and* the other
1958 * uses push concstants, this may be suboptimal. However, avoiding stalls
1959 * seems more important.
1961 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1963 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1967 const unsigned push_constant_kb
= 32;
1968 #elif GEN_IS_HASWELL
1969 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1971 const unsigned push_constant_kb
= 16;
1974 const unsigned num_stages
=
1975 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1976 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1978 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1979 * units of 2KB. Incidentally, these are the same platforms that have
1980 * 32KB worth of push constant space.
1982 if (push_constant_kb
== 32)
1983 size_per_stage
&= ~1u;
1985 uint32_t kb_used
= 0;
1986 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1987 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1988 anv_batch_emit(&cmd_buffer
->batch
,
1989 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1990 alloc
._3DCommandSubOpcode
= 18 + i
;
1991 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1992 alloc
.ConstantBufferSize
= push_size
;
1994 kb_used
+= push_size
;
1997 anv_batch_emit(&cmd_buffer
->batch
,
1998 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1999 alloc
.ConstantBufferOffset
= kb_used
;
2000 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2003 cmd_buffer
->state
.push_constant_stages
= stages
;
2005 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2007 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2008 * the next 3DPRIMITIVE command after programming the
2009 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2011 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2012 * pipeline setup, we need to dirty push constants.
2014 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2017 static const struct anv_descriptor
*
2018 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2019 const struct anv_pipeline_binding
*binding
)
2021 assert(binding
->set
< MAX_SETS
);
2022 const struct anv_descriptor_set
*set
=
2023 pipe_state
->descriptors
[binding
->set
];
2024 const uint32_t offset
=
2025 set
->layout
->binding
[binding
->binding
].descriptor_index
;
2026 return &set
->descriptors
[offset
+ binding
->index
];
2030 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
2031 const struct anv_pipeline_binding
*binding
)
2033 assert(binding
->set
< MAX_SETS
);
2034 const struct anv_descriptor_set
*set
=
2035 pipe_state
->descriptors
[binding
->set
];
2037 uint32_t dynamic_offset_idx
=
2038 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
2039 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
2042 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
2045 static struct anv_address
2046 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2047 struct anv_descriptor_set
*set
)
2050 /* This is a normal descriptor set */
2051 return (struct anv_address
) {
2052 .bo
= &set
->pool
->bo
,
2053 .offset
= set
->desc_mem
.offset
,
2056 /* This is a push descriptor set. We have to flag it as used on the GPU
2057 * so that the next time we push descriptors, we grab a new memory.
2059 struct anv_push_descriptor_set
*push_set
=
2060 (struct anv_push_descriptor_set
*)set
;
2061 push_set
->set_used_on_gpu
= true;
2063 return (struct anv_address
) {
2064 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2065 .offset
= set
->desc_mem
.offset
,
2071 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2072 gl_shader_stage stage
,
2073 struct anv_state
*bt_state
)
2075 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2076 struct anv_cmd_pipeline_state
*pipe_state
;
2077 struct anv_pipeline
*pipeline
;
2078 uint32_t state_offset
;
2081 case MESA_SHADER_COMPUTE
:
2082 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2085 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2088 pipeline
= pipe_state
->pipeline
;
2090 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2091 *bt_state
= (struct anv_state
) { 0, };
2095 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2096 if (map
->surface_count
== 0) {
2097 *bt_state
= (struct anv_state
) { 0, };
2101 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2104 uint32_t *bt_map
= bt_state
->map
;
2106 if (bt_state
->map
== NULL
)
2107 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2109 /* We only need to emit relocs if we're not using softpin. If we are using
2110 * softpin then we always keep all user-allocated memory objects resident.
2112 const bool need_client_mem_relocs
=
2113 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
;
2115 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2116 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2118 struct anv_state surface_state
;
2120 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2121 /* Color attachment binding */
2122 assert(stage
== MESA_SHADER_FRAGMENT
);
2123 assert(binding
->binding
== 0);
2124 if (binding
->index
< subpass
->color_count
) {
2125 const unsigned att
=
2126 subpass
->color_attachments
[binding
->index
].attachment
;
2128 /* From the Vulkan 1.0.46 spec:
2130 * "If any color or depth/stencil attachments are
2131 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2134 if (att
== VK_ATTACHMENT_UNUSED
) {
2135 surface_state
= cmd_buffer
->state
.null_surface_state
;
2137 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2140 surface_state
= cmd_buffer
->state
.null_surface_state
;
2143 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2145 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2146 struct anv_state surface_state
=
2147 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2149 struct anv_address constant_data
= {
2150 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2151 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2153 unsigned constant_data_size
=
2154 pipeline
->shaders
[stage
]->constant_data_size
;
2156 const enum isl_format format
=
2157 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2158 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2159 surface_state
, format
,
2160 constant_data
, constant_data_size
, 1);
2162 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2163 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2165 } else if (binding
->set
== ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
) {
2166 /* This is always the first binding for compute shaders */
2167 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2168 if (!get_cs_prog_data(pipeline
)->uses_num_work_groups
)
2171 struct anv_state surface_state
=
2172 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2174 const enum isl_format format
=
2175 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2176 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2178 cmd_buffer
->state
.compute
.num_workgroups
,
2180 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2181 if (need_client_mem_relocs
) {
2182 add_surface_reloc(cmd_buffer
, surface_state
,
2183 cmd_buffer
->state
.compute
.num_workgroups
);
2186 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2187 /* This is a descriptor set buffer so the set index is actually
2188 * given by binding->binding. (Yes, that's confusing.)
2190 struct anv_descriptor_set
*set
=
2191 pipe_state
->descriptors
[binding
->binding
];
2192 assert(set
->desc_mem
.alloc_size
);
2193 assert(set
->desc_surface_state
.alloc_size
);
2194 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2195 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2196 anv_descriptor_set_address(cmd_buffer
, set
));
2200 const struct anv_descriptor
*desc
=
2201 anv_descriptor_for_binding(pipe_state
, binding
);
2203 switch (desc
->type
) {
2204 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2205 /* Nothing for us to do here */
2208 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2209 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2210 struct anv_surface_state sstate
=
2211 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2212 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2213 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2214 surface_state
= sstate
.state
;
2215 assert(surface_state
.alloc_size
);
2216 if (need_client_mem_relocs
)
2217 add_surface_state_relocs(cmd_buffer
, sstate
);
2220 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2221 assert(stage
== MESA_SHADER_FRAGMENT
);
2222 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2223 /* For depth and stencil input attachments, we treat it like any
2224 * old texture that a user may have bound.
2226 struct anv_surface_state sstate
=
2227 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2228 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2229 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2230 surface_state
= sstate
.state
;
2231 assert(surface_state
.alloc_size
);
2232 if (need_client_mem_relocs
)
2233 add_surface_state_relocs(cmd_buffer
, sstate
);
2235 /* For color input attachments, we create the surface state at
2236 * vkBeginRenderPass time so that we can include aux and clear
2237 * color information.
2239 assert(binding
->input_attachment_index
< subpass
->input_count
);
2240 const unsigned subpass_att
= binding
->input_attachment_index
;
2241 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2242 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2246 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2247 struct anv_surface_state sstate
= (binding
->write_only
)
2248 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2249 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2250 surface_state
= sstate
.state
;
2251 assert(surface_state
.alloc_size
);
2252 if (need_client_mem_relocs
)
2253 add_surface_state_relocs(cmd_buffer
, sstate
);
2257 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2258 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2259 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2260 surface_state
= desc
->buffer_view
->surface_state
;
2261 assert(surface_state
.alloc_size
);
2262 if (need_client_mem_relocs
) {
2263 add_surface_reloc(cmd_buffer
, surface_state
,
2264 desc
->buffer_view
->address
);
2268 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2269 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2270 /* Compute the offset within the buffer */
2271 uint32_t dynamic_offset
=
2272 dynamic_offset_for_binding(pipe_state
, binding
);
2273 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2274 /* Clamp to the buffer size */
2275 offset
= MIN2(offset
, desc
->buffer
->size
);
2276 /* Clamp the range to the buffer size */
2277 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2279 struct anv_address address
=
2280 anv_address_add(desc
->buffer
->address
, offset
);
2283 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2284 enum isl_format format
=
2285 anv_isl_format_for_descriptor_type(desc
->type
);
2287 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2288 format
, address
, range
, 1);
2289 if (need_client_mem_relocs
)
2290 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2294 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2295 surface_state
= (binding
->write_only
)
2296 ? desc
->buffer_view
->writeonly_storage_surface_state
2297 : desc
->buffer_view
->storage_surface_state
;
2298 assert(surface_state
.alloc_size
);
2299 if (need_client_mem_relocs
) {
2300 add_surface_reloc(cmd_buffer
, surface_state
,
2301 desc
->buffer_view
->address
);
2306 assert(!"Invalid descriptor type");
2310 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2314 /* The PIPE_CONTROL command description says:
2316 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2317 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2318 * Target Cache Flush by enabling this bit. When render target flush
2319 * is set due to new association of BTI, PS Scoreboard Stall bit must
2320 * be set in this packet."
2322 * FINISHME: Currently we shuffle around the surface states in the binding
2323 * table based on if they are getting used or not. So, we've to do below
2324 * pipe control flush for every binding table upload. Make changes so
2325 * that we do it only when we modify render target surface states.
2327 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2328 pc
.RenderTargetCacheFlushEnable
= true;
2329 pc
.StallAtPixelScoreboard
= true;
2337 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2338 gl_shader_stage stage
,
2339 struct anv_state
*state
)
2341 struct anv_cmd_pipeline_state
*pipe_state
=
2342 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2343 &cmd_buffer
->state
.gfx
.base
;
2344 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2346 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2347 *state
= (struct anv_state
) { 0, };
2351 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2352 if (map
->sampler_count
== 0) {
2353 *state
= (struct anv_state
) { 0, };
2357 uint32_t size
= map
->sampler_count
* 16;
2358 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2360 if (state
->map
== NULL
)
2361 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2363 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2364 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2365 const struct anv_descriptor
*desc
=
2366 anv_descriptor_for_binding(pipe_state
, binding
);
2368 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2369 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2372 struct anv_sampler
*sampler
= desc
->sampler
;
2374 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2375 * happens to be zero.
2377 if (sampler
== NULL
)
2380 memcpy(state
->map
+ (s
* 16),
2381 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2388 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2390 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2392 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2393 pipeline
->active_stages
;
2395 VkResult result
= VK_SUCCESS
;
2396 anv_foreach_stage(s
, dirty
) {
2397 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2398 if (result
!= VK_SUCCESS
)
2400 result
= emit_binding_table(cmd_buffer
, s
,
2401 &cmd_buffer
->state
.binding_tables
[s
]);
2402 if (result
!= VK_SUCCESS
)
2406 if (result
!= VK_SUCCESS
) {
2407 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2409 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2410 if (result
!= VK_SUCCESS
)
2413 /* Re-emit state base addresses so we get the new surface state base
2414 * address before we start emitting binding tables etc.
2416 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2418 /* Re-emit all active binding tables */
2419 dirty
|= pipeline
->active_stages
;
2420 anv_foreach_stage(s
, dirty
) {
2421 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2422 if (result
!= VK_SUCCESS
) {
2423 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2426 result
= emit_binding_table(cmd_buffer
, s
,
2427 &cmd_buffer
->state
.binding_tables
[s
]);
2428 if (result
!= VK_SUCCESS
) {
2429 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2435 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2441 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2444 static const uint32_t sampler_state_opcodes
[] = {
2445 [MESA_SHADER_VERTEX
] = 43,
2446 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2447 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2448 [MESA_SHADER_GEOMETRY
] = 46,
2449 [MESA_SHADER_FRAGMENT
] = 47,
2450 [MESA_SHADER_COMPUTE
] = 0,
2453 static const uint32_t binding_table_opcodes
[] = {
2454 [MESA_SHADER_VERTEX
] = 38,
2455 [MESA_SHADER_TESS_CTRL
] = 39,
2456 [MESA_SHADER_TESS_EVAL
] = 40,
2457 [MESA_SHADER_GEOMETRY
] = 41,
2458 [MESA_SHADER_FRAGMENT
] = 42,
2459 [MESA_SHADER_COMPUTE
] = 0,
2462 anv_foreach_stage(s
, stages
) {
2463 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2464 assert(binding_table_opcodes
[s
] > 0);
2466 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2467 anv_batch_emit(&cmd_buffer
->batch
,
2468 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2469 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2470 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2474 /* Always emit binding table pointers if we're asked to, since on SKL
2475 * this is what flushes push constants. */
2476 anv_batch_emit(&cmd_buffer
->batch
,
2477 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2478 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2479 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2485 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2486 VkShaderStageFlags dirty_stages
)
2488 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2489 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2491 static const uint32_t push_constant_opcodes
[] = {
2492 [MESA_SHADER_VERTEX
] = 21,
2493 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2494 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2495 [MESA_SHADER_GEOMETRY
] = 22,
2496 [MESA_SHADER_FRAGMENT
] = 23,
2497 [MESA_SHADER_COMPUTE
] = 0,
2500 VkShaderStageFlags flushed
= 0;
2502 anv_foreach_stage(stage
, dirty_stages
) {
2503 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2504 assert(push_constant_opcodes
[stage
] > 0);
2506 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2507 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2509 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2510 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2511 const struct brw_stage_prog_data
*prog_data
=
2512 pipeline
->shaders
[stage
]->prog_data
;
2513 const struct anv_pipeline_bind_map
*bind_map
=
2514 &pipeline
->shaders
[stage
]->bind_map
;
2516 /* The Skylake PRM contains the following restriction:
2518 * "The driver must ensure The following case does not occur
2519 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2520 * buffer 3 read length equal to zero committed followed by a
2521 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2524 * To avoid this, we program the buffers in the highest slots.
2525 * This way, slot 0 is only used if slot 3 is also used.
2529 for (int i
= 3; i
>= 0; i
--) {
2530 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2531 if (range
->length
== 0)
2534 const unsigned surface
=
2535 prog_data
->binding_table
.ubo_start
+ range
->block
;
2537 assert(surface
<= bind_map
->surface_count
);
2538 const struct anv_pipeline_binding
*binding
=
2539 &bind_map
->surface_to_descriptor
[surface
];
2541 struct anv_address read_addr
;
2543 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2544 struct anv_address constant_data
= {
2545 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2546 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2548 unsigned constant_data_size
=
2549 pipeline
->shaders
[stage
]->constant_data_size
;
2551 read_len
= MIN2(range
->length
,
2552 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2553 read_addr
= anv_address_add(constant_data
,
2555 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2556 /* This is a descriptor set buffer so the set index is
2557 * actually given by binding->binding. (Yes, that's
2560 struct anv_descriptor_set
*set
=
2561 gfx_state
->base
.descriptors
[binding
->binding
];
2562 struct anv_address desc_buffer_addr
=
2563 anv_descriptor_set_address(cmd_buffer
, set
);
2564 const unsigned desc_buffer_size
= set
->desc_mem
.alloc_size
;
2566 read_len
= MIN2(range
->length
,
2567 DIV_ROUND_UP(desc_buffer_size
, 32) - range
->start
);
2568 read_addr
= anv_address_add(desc_buffer_addr
,
2571 const struct anv_descriptor
*desc
=
2572 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2574 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2575 read_len
= MIN2(range
->length
,
2576 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2577 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2580 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2582 uint32_t dynamic_offset
=
2583 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2584 uint32_t buf_offset
=
2585 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2586 uint32_t buf_range
=
2587 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2589 read_len
= MIN2(range
->length
,
2590 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2591 read_addr
= anv_address_add(desc
->buffer
->address
,
2592 buf_offset
+ range
->start
* 32);
2597 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2598 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2603 struct anv_state state
=
2604 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2606 if (state
.alloc_size
> 0) {
2607 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2608 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2609 .offset
= state
.offset
,
2611 c
.ConstantBody
.ReadLength
[n
] =
2612 DIV_ROUND_UP(state
.alloc_size
, 32);
2615 /* For Ivy Bridge, the push constants packets have a different
2616 * rule that would require us to iterate in the other direction
2617 * and possibly mess around with dynamic state base address.
2618 * Don't bother; just emit regular push constants at n = 0.
2620 struct anv_state state
=
2621 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2623 if (state
.alloc_size
> 0) {
2624 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2625 c
.ConstantBody
.ReadLength
[0] =
2626 DIV_ROUND_UP(state
.alloc_size
, 32);
2632 flushed
|= mesa_to_vk_shader_stage(stage
);
2635 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2639 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2641 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2644 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2645 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2646 vb_emit
|= pipeline
->vb_used
;
2648 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2650 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2652 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2655 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2656 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2658 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2659 GENX(3DSTATE_VERTEX_BUFFERS
));
2661 for_each_bit(vb
, vb_emit
) {
2662 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2663 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2665 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2666 .VertexBufferIndex
= vb
,
2668 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2670 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2671 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2674 .AddressModifyEnable
= true,
2675 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2676 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2679 .BufferSize
= buffer
->size
- offset
2681 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2685 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2690 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2693 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2694 /* We don't need any per-buffer dirty tracking because you're not
2695 * allowed to bind different XFB buffers while XFB is enabled.
2697 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2698 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2699 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2700 sob
.SOBufferIndex
= idx
;
2702 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2703 sob
.SOBufferEnable
= true;
2704 sob
.MOCS
= cmd_buffer
->device
->default_mocs
,
2705 sob
.StreamOffsetWriteEnable
= false;
2706 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2708 /* Size is in DWords - 1 */
2709 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2714 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2716 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2720 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2721 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2723 /* The exact descriptor layout is pulled from the pipeline, so we need
2724 * to re-emit binding tables on every pipeline change.
2726 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2728 /* If the pipeline changed, we may need to re-allocate push constant
2731 cmd_buffer_alloc_push_constants(cmd_buffer
);
2735 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2736 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2737 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2739 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2740 * stall needs to be sent just prior to any 3DSTATE_VS,
2741 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2742 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2743 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2744 * PIPE_CONTROL needs to be sent before any combination of VS
2745 * associated 3DSTATE."
2747 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2748 pc
.DepthStallEnable
= true;
2749 pc
.PostSyncOperation
= WriteImmediateData
;
2751 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2756 /* Render targets live in the same binding table as fragment descriptors */
2757 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2758 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2760 /* We emit the binding tables and sampler tables first, then emit push
2761 * constants and then finally emit binding table and sampler table
2762 * pointers. It has to happen in this order, since emitting the binding
2763 * tables may change the push constants (in case of storage images). After
2764 * emitting push constants, on SKL+ we have to emit the corresponding
2765 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2768 if (cmd_buffer
->state
.descriptors_dirty
)
2769 dirty
= flush_descriptor_sets(cmd_buffer
);
2771 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2772 /* Because we're pushing UBOs, we have to push whenever either
2773 * descriptors or push constants is dirty.
2775 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2776 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2777 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2781 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2783 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2784 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2786 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2787 ANV_CMD_DIRTY_PIPELINE
)) {
2788 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2789 pipeline
->depth_clamp_enable
);
2792 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2793 ANV_CMD_DIRTY_RENDER_TARGETS
))
2794 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2796 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2798 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2802 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2803 struct anv_address addr
,
2804 uint32_t size
, uint32_t index
)
2806 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2807 GENX(3DSTATE_VERTEX_BUFFERS
));
2809 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2810 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2811 .VertexBufferIndex
= index
,
2812 .AddressModifyEnable
= true,
2814 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2816 .BufferStartingAddress
= addr
,
2819 .BufferStartingAddress
= addr
,
2820 .EndAddress
= anv_address_add(addr
, size
),
2826 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2827 struct anv_address addr
)
2829 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2833 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2834 uint32_t base_vertex
, uint32_t base_instance
)
2836 struct anv_state id_state
=
2837 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2839 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2840 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2842 struct anv_address addr
= {
2843 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2844 .offset
= id_state
.offset
,
2847 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2851 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2853 struct anv_state state
=
2854 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2856 ((uint32_t *)state
.map
)[0] = draw_index
;
2858 struct anv_address addr
= {
2859 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2860 .offset
= state
.offset
,
2863 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2867 VkCommandBuffer commandBuffer
,
2868 uint32_t vertexCount
,
2869 uint32_t instanceCount
,
2870 uint32_t firstVertex
,
2871 uint32_t firstInstance
)
2873 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2874 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2875 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2877 if (anv_batch_has_error(&cmd_buffer
->batch
))
2880 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2882 if (cmd_buffer
->state
.conditional_render_enabled
)
2883 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2885 if (vs_prog_data
->uses_firstvertex
||
2886 vs_prog_data
->uses_baseinstance
)
2887 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2888 if (vs_prog_data
->uses_drawid
)
2889 emit_draw_index(cmd_buffer
, 0);
2891 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2892 * different views. We need to multiply instanceCount by the view count.
2894 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2896 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2897 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2898 prim
.VertexAccessType
= SEQUENTIAL
;
2899 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2900 prim
.VertexCountPerInstance
= vertexCount
;
2901 prim
.StartVertexLocation
= firstVertex
;
2902 prim
.InstanceCount
= instanceCount
;
2903 prim
.StartInstanceLocation
= firstInstance
;
2904 prim
.BaseVertexLocation
= 0;
2908 void genX(CmdDrawIndexed
)(
2909 VkCommandBuffer commandBuffer
,
2910 uint32_t indexCount
,
2911 uint32_t instanceCount
,
2912 uint32_t firstIndex
,
2913 int32_t vertexOffset
,
2914 uint32_t firstInstance
)
2916 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2917 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2918 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2920 if (anv_batch_has_error(&cmd_buffer
->batch
))
2923 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2925 if (cmd_buffer
->state
.conditional_render_enabled
)
2926 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2928 if (vs_prog_data
->uses_firstvertex
||
2929 vs_prog_data
->uses_baseinstance
)
2930 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2931 if (vs_prog_data
->uses_drawid
)
2932 emit_draw_index(cmd_buffer
, 0);
2934 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2935 * different views. We need to multiply instanceCount by the view count.
2937 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2939 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2940 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2941 prim
.VertexAccessType
= RANDOM
;
2942 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2943 prim
.VertexCountPerInstance
= indexCount
;
2944 prim
.StartVertexLocation
= firstIndex
;
2945 prim
.InstanceCount
= instanceCount
;
2946 prim
.StartInstanceLocation
= firstInstance
;
2947 prim
.BaseVertexLocation
= vertexOffset
;
2951 /* Auto-Draw / Indirect Registers */
2952 #define GEN7_3DPRIM_END_OFFSET 0x2420
2953 #define GEN7_3DPRIM_START_VERTEX 0x2430
2954 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2955 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2956 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2957 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2959 void genX(CmdDrawIndirectByteCountEXT
)(
2960 VkCommandBuffer commandBuffer
,
2961 uint32_t instanceCount
,
2962 uint32_t firstInstance
,
2963 VkBuffer counterBuffer
,
2964 VkDeviceSize counterBufferOffset
,
2965 uint32_t counterOffset
,
2966 uint32_t vertexStride
)
2968 #if GEN_IS_HASWELL || GEN_GEN >= 8
2969 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2970 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
2971 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2972 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2974 /* firstVertex is always zero for this draw function */
2975 const uint32_t firstVertex
= 0;
2977 if (anv_batch_has_error(&cmd_buffer
->batch
))
2980 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2982 if (vs_prog_data
->uses_firstvertex
||
2983 vs_prog_data
->uses_baseinstance
)
2984 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2985 if (vs_prog_data
->uses_drawid
)
2986 emit_draw_index(cmd_buffer
, 0);
2988 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2989 * different views. We need to multiply instanceCount by the view count.
2991 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2993 struct gen_mi_builder b
;
2994 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
2995 struct gen_mi_value count
=
2996 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
2997 counterBufferOffset
));
2999 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3000 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3001 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3003 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3004 gen_mi_imm(firstVertex
));
3005 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3006 gen_mi_imm(instanceCount
));
3007 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3008 gen_mi_imm(firstInstance
));
3009 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3011 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3012 prim
.IndirectParameterEnable
= true;
3013 prim
.VertexAccessType
= SEQUENTIAL
;
3014 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3016 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3020 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3021 struct anv_address addr
,
3024 struct gen_mi_builder b
;
3025 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3027 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3028 gen_mi_mem32(anv_address_add(addr
, 0)));
3030 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3031 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3032 if (view_count
> 1) {
3033 #if GEN_IS_HASWELL || GEN_GEN >= 8
3034 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3036 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3037 "MI_MATH is not supported on Ivy Bridge");
3040 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3042 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3043 gen_mi_mem32(anv_address_add(addr
, 8)));
3046 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3047 gen_mi_mem32(anv_address_add(addr
, 12)));
3048 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3049 gen_mi_mem32(anv_address_add(addr
, 16)));
3051 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3052 gen_mi_mem32(anv_address_add(addr
, 12)));
3053 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3057 void genX(CmdDrawIndirect
)(
3058 VkCommandBuffer commandBuffer
,
3060 VkDeviceSize offset
,
3064 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3065 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3066 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3067 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3069 if (anv_batch_has_error(&cmd_buffer
->batch
))
3072 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3074 if (cmd_buffer
->state
.conditional_render_enabled
)
3075 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3077 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3078 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3080 if (vs_prog_data
->uses_firstvertex
||
3081 vs_prog_data
->uses_baseinstance
)
3082 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3083 if (vs_prog_data
->uses_drawid
)
3084 emit_draw_index(cmd_buffer
, i
);
3086 load_indirect_parameters(cmd_buffer
, draw
, false);
3088 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3089 prim
.IndirectParameterEnable
= true;
3090 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3091 prim
.VertexAccessType
= SEQUENTIAL
;
3092 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3099 void genX(CmdDrawIndexedIndirect
)(
3100 VkCommandBuffer commandBuffer
,
3102 VkDeviceSize offset
,
3106 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3107 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3108 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3109 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3111 if (anv_batch_has_error(&cmd_buffer
->batch
))
3114 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3116 if (cmd_buffer
->state
.conditional_render_enabled
)
3117 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3119 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3120 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3122 /* TODO: We need to stomp base vertex to 0 somehow */
3123 if (vs_prog_data
->uses_firstvertex
||
3124 vs_prog_data
->uses_baseinstance
)
3125 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3126 if (vs_prog_data
->uses_drawid
)
3127 emit_draw_index(cmd_buffer
, i
);
3129 load_indirect_parameters(cmd_buffer
, draw
, true);
3131 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3132 prim
.IndirectParameterEnable
= true;
3133 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3134 prim
.VertexAccessType
= RANDOM
;
3135 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3142 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3145 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3146 struct anv_address count_address
,
3147 const bool conditional_render_enabled
)
3149 struct gen_mi_builder b
;
3150 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3152 if (conditional_render_enabled
) {
3153 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3154 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3155 gen_mi_mem32(count_address
));
3158 /* Upload the current draw count from the draw parameters buffer to
3159 * MI_PREDICATE_SRC0.
3161 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3162 gen_mi_mem32(count_address
));
3164 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3169 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3170 uint32_t draw_index
)
3172 struct gen_mi_builder b
;
3173 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3175 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3176 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3178 if (draw_index
== 0) {
3179 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3180 mip
.LoadOperation
= LOAD_LOADINV
;
3181 mip
.CombineOperation
= COMBINE_SET
;
3182 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3185 /* While draw_index < draw_count the predicate's result will be
3186 * (draw_index == draw_count) ^ TRUE = TRUE
3187 * When draw_index == draw_count the result is
3188 * (TRUE) ^ TRUE = FALSE
3189 * After this all results will be:
3190 * (FALSE) ^ FALSE = FALSE
3192 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3193 mip
.LoadOperation
= LOAD_LOAD
;
3194 mip
.CombineOperation
= COMBINE_XOR
;
3195 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3200 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3202 emit_draw_count_predicate_with_conditional_render(
3203 struct anv_cmd_buffer
*cmd_buffer
,
3204 uint32_t draw_index
)
3206 struct gen_mi_builder b
;
3207 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3209 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3210 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3211 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3214 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3216 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3217 * so we emit MI_PREDICATE to set it.
3220 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3221 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3223 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3224 mip
.LoadOperation
= LOAD_LOADINV
;
3225 mip
.CombineOperation
= COMBINE_SET
;
3226 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3232 void genX(CmdDrawIndirectCountKHR
)(
3233 VkCommandBuffer commandBuffer
,
3235 VkDeviceSize offset
,
3236 VkBuffer _countBuffer
,
3237 VkDeviceSize countBufferOffset
,
3238 uint32_t maxDrawCount
,
3241 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3242 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3243 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3244 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3245 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3246 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3248 if (anv_batch_has_error(&cmd_buffer
->batch
))
3251 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3253 struct anv_address count_address
=
3254 anv_address_add(count_buffer
->address
, countBufferOffset
);
3256 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3257 cmd_state
->conditional_render_enabled
);
3259 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3260 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3262 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3263 if (cmd_state
->conditional_render_enabled
) {
3264 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3266 emit_draw_count_predicate(cmd_buffer
, i
);
3269 emit_draw_count_predicate(cmd_buffer
, i
);
3272 if (vs_prog_data
->uses_firstvertex
||
3273 vs_prog_data
->uses_baseinstance
)
3274 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3275 if (vs_prog_data
->uses_drawid
)
3276 emit_draw_index(cmd_buffer
, i
);
3278 load_indirect_parameters(cmd_buffer
, draw
, false);
3280 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3281 prim
.IndirectParameterEnable
= true;
3282 prim
.PredicateEnable
= true;
3283 prim
.VertexAccessType
= SEQUENTIAL
;
3284 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3291 void genX(CmdDrawIndexedIndirectCountKHR
)(
3292 VkCommandBuffer commandBuffer
,
3294 VkDeviceSize offset
,
3295 VkBuffer _countBuffer
,
3296 VkDeviceSize countBufferOffset
,
3297 uint32_t maxDrawCount
,
3300 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3301 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3302 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3303 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3304 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3305 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3307 if (anv_batch_has_error(&cmd_buffer
->batch
))
3310 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3312 struct anv_address count_address
=
3313 anv_address_add(count_buffer
->address
, countBufferOffset
);
3315 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3316 cmd_state
->conditional_render_enabled
);
3318 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3319 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3321 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3322 if (cmd_state
->conditional_render_enabled
) {
3323 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3325 emit_draw_count_predicate(cmd_buffer
, i
);
3328 emit_draw_count_predicate(cmd_buffer
, i
);
3331 /* TODO: We need to stomp base vertex to 0 somehow */
3332 if (vs_prog_data
->uses_firstvertex
||
3333 vs_prog_data
->uses_baseinstance
)
3334 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3335 if (vs_prog_data
->uses_drawid
)
3336 emit_draw_index(cmd_buffer
, i
);
3338 load_indirect_parameters(cmd_buffer
, draw
, true);
3340 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3341 prim
.IndirectParameterEnable
= true;
3342 prim
.PredicateEnable
= true;
3343 prim
.VertexAccessType
= RANDOM
;
3344 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3351 void genX(CmdBeginTransformFeedbackEXT
)(
3352 VkCommandBuffer commandBuffer
,
3353 uint32_t firstCounterBuffer
,
3354 uint32_t counterBufferCount
,
3355 const VkBuffer
* pCounterBuffers
,
3356 const VkDeviceSize
* pCounterBufferOffsets
)
3358 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3360 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3361 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3362 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3364 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3366 * "Ssoftware must ensure that no HW stream output operations can be in
3367 * process or otherwise pending at the point that the MI_LOAD/STORE
3368 * commands are processed. This will likely require a pipeline flush."
3370 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3371 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3373 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3374 /* If we have a counter buffer, this is a resume so we need to load the
3375 * value into the streamout offset register. Otherwise, this is a begin
3376 * and we need to reset it to zero.
3378 if (pCounterBuffers
&&
3379 idx
>= firstCounterBuffer
&&
3380 idx
- firstCounterBuffer
< counterBufferCount
&&
3381 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3382 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3383 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3384 uint64_t offset
= pCounterBufferOffsets
?
3385 pCounterBufferOffsets
[cb_idx
] : 0;
3387 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3388 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3389 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3393 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3394 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3400 cmd_buffer
->state
.xfb_enabled
= true;
3401 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3404 void genX(CmdEndTransformFeedbackEXT
)(
3405 VkCommandBuffer commandBuffer
,
3406 uint32_t firstCounterBuffer
,
3407 uint32_t counterBufferCount
,
3408 const VkBuffer
* pCounterBuffers
,
3409 const VkDeviceSize
* pCounterBufferOffsets
)
3411 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3413 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3414 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3415 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3417 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3419 * "Ssoftware must ensure that no HW stream output operations can be in
3420 * process or otherwise pending at the point that the MI_LOAD/STORE
3421 * commands are processed. This will likely require a pipeline flush."
3423 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3424 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3426 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3427 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3429 /* If we have a counter buffer, this is a resume so we need to load the
3430 * value into the streamout offset register. Otherwise, this is a begin
3431 * and we need to reset it to zero.
3433 if (pCounterBuffers
&&
3434 cb_idx
< counterBufferCount
&&
3435 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3436 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3437 uint64_t offset
= pCounterBufferOffsets
?
3438 pCounterBufferOffsets
[cb_idx
] : 0;
3440 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3441 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3443 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3448 cmd_buffer
->state
.xfb_enabled
= false;
3449 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3453 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3455 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3456 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3459 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3460 if (result
!= VK_SUCCESS
) {
3461 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3463 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3464 if (result
!= VK_SUCCESS
)
3467 /* Re-emit state base addresses so we get the new surface state base
3468 * address before we start emitting binding tables etc.
3470 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3472 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3473 if (result
!= VK_SUCCESS
) {
3474 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3479 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3480 if (result
!= VK_SUCCESS
) {
3481 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3485 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3486 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3487 .BindingTablePointer
= surfaces
.offset
,
3488 .SamplerStatePointer
= samplers
.offset
,
3490 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3492 struct anv_state state
=
3493 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3494 pipeline
->interface_descriptor_data
,
3495 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3498 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3499 anv_batch_emit(&cmd_buffer
->batch
,
3500 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3501 mid
.InterfaceDescriptorTotalLength
= size
;
3502 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3509 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3511 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3512 MAYBE_UNUSED VkResult result
;
3514 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3516 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3518 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3520 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3521 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3523 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3524 * the only bits that are changed are scoreboard related: Scoreboard
3525 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3526 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3529 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3530 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3532 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3535 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3536 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3537 /* FIXME: figure out descriptors for gen7 */
3538 result
= flush_compute_descriptor_set(cmd_buffer
);
3539 if (result
!= VK_SUCCESS
)
3542 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3545 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3546 struct anv_state push_state
=
3547 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3549 if (push_state
.alloc_size
) {
3550 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3551 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3552 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3556 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3559 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3561 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3567 verify_cmd_parser(const struct anv_device
*device
,
3568 int required_version
,
3569 const char *function
)
3571 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3572 return vk_errorf(device
->instance
, device
->instance
,
3573 VK_ERROR_FEATURE_NOT_PRESENT
,
3574 "cmd parser version %d is required for %s",
3575 required_version
, function
);
3584 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3585 uint32_t baseGroupX
,
3586 uint32_t baseGroupY
,
3587 uint32_t baseGroupZ
)
3589 if (anv_batch_has_error(&cmd_buffer
->batch
))
3592 struct anv_push_constants
*push
=
3593 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3594 if (push
->base_work_group_id
[0] != baseGroupX
||
3595 push
->base_work_group_id
[1] != baseGroupY
||
3596 push
->base_work_group_id
[2] != baseGroupZ
) {
3597 push
->base_work_group_id
[0] = baseGroupX
;
3598 push
->base_work_group_id
[1] = baseGroupY
;
3599 push
->base_work_group_id
[2] = baseGroupZ
;
3601 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3605 void genX(CmdDispatch
)(
3606 VkCommandBuffer commandBuffer
,
3611 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3614 void genX(CmdDispatchBase
)(
3615 VkCommandBuffer commandBuffer
,
3616 uint32_t baseGroupX
,
3617 uint32_t baseGroupY
,
3618 uint32_t baseGroupZ
,
3619 uint32_t groupCountX
,
3620 uint32_t groupCountY
,
3621 uint32_t groupCountZ
)
3623 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3624 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3625 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3627 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3628 baseGroupY
, baseGroupZ
);
3630 if (anv_batch_has_error(&cmd_buffer
->batch
))
3633 if (prog_data
->uses_num_work_groups
) {
3634 struct anv_state state
=
3635 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3636 uint32_t *sizes
= state
.map
;
3637 sizes
[0] = groupCountX
;
3638 sizes
[1] = groupCountY
;
3639 sizes
[2] = groupCountZ
;
3640 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3641 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3642 .offset
= state
.offset
,
3646 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3648 if (cmd_buffer
->state
.conditional_render_enabled
)
3649 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3651 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3652 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3653 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3654 ggw
.ThreadDepthCounterMaximum
= 0;
3655 ggw
.ThreadHeightCounterMaximum
= 0;
3656 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3657 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3658 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3659 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3660 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3661 ggw
.BottomExecutionMask
= 0xffffffff;
3664 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3667 #define GPGPU_DISPATCHDIMX 0x2500
3668 #define GPGPU_DISPATCHDIMY 0x2504
3669 #define GPGPU_DISPATCHDIMZ 0x2508
3671 void genX(CmdDispatchIndirect
)(
3672 VkCommandBuffer commandBuffer
,
3674 VkDeviceSize offset
)
3676 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3677 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3678 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3679 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3680 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3681 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3683 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3686 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3687 * indirect dispatch registers to be written.
3689 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3690 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3694 if (prog_data
->uses_num_work_groups
)
3695 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3697 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3699 struct gen_mi_builder b
;
3700 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3702 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
3703 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
3704 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
3706 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
3707 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
3708 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
3711 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3712 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
3713 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3714 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3715 mip
.LoadOperation
= LOAD_LOAD
;
3716 mip
.CombineOperation
= COMBINE_SET
;
3717 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3720 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3721 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
3722 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3723 mip
.LoadOperation
= LOAD_LOAD
;
3724 mip
.CombineOperation
= COMBINE_OR
;
3725 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3728 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3729 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
3730 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3731 mip
.LoadOperation
= LOAD_LOAD
;
3732 mip
.CombineOperation
= COMBINE_OR
;
3733 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3736 /* predicate = !predicate; */
3737 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3738 mip
.LoadOperation
= LOAD_LOADINV
;
3739 mip
.CombineOperation
= COMBINE_OR
;
3740 mip
.CompareOperation
= COMPARE_FALSE
;
3744 if (cmd_buffer
->state
.conditional_render_enabled
) {
3745 /* predicate &= !(conditional_rendering_predicate == 0); */
3746 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
3747 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
3748 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3749 mip
.LoadOperation
= LOAD_LOADINV
;
3750 mip
.CombineOperation
= COMBINE_AND
;
3751 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3756 #else /* GEN_GEN > 7 */
3757 if (cmd_buffer
->state
.conditional_render_enabled
)
3758 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3761 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3762 ggw
.IndirectParameterEnable
= true;
3763 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3764 cmd_buffer
->state
.conditional_render_enabled
;
3765 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3766 ggw
.ThreadDepthCounterMaximum
= 0;
3767 ggw
.ThreadHeightCounterMaximum
= 0;
3768 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3769 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3770 ggw
.BottomExecutionMask
= 0xffffffff;
3773 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3777 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3780 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3782 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3785 #if GEN_GEN >= 8 && GEN_GEN < 10
3786 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3788 * Software must clear the COLOR_CALC_STATE Valid field in
3789 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3790 * with Pipeline Select set to GPGPU.
3792 * The internal hardware docs recommend the same workaround for Gen9
3795 if (pipeline
== GPGPU
)
3796 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3799 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3800 * PIPELINE_SELECT [DevBWR+]":
3804 * Software must ensure all the write caches are flushed through a
3805 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3806 * command to invalidate read only caches prior to programming
3807 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3809 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3810 pc
.RenderTargetCacheFlushEnable
= true;
3811 pc
.DepthCacheFlushEnable
= true;
3812 pc
.DCFlushEnable
= true;
3813 pc
.PostSyncOperation
= NoWrite
;
3814 pc
.CommandStreamerStallEnable
= true;
3817 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3818 pc
.TextureCacheInvalidationEnable
= true;
3819 pc
.ConstantCacheInvalidationEnable
= true;
3820 pc
.StateCacheInvalidationEnable
= true;
3821 pc
.InstructionCacheInvalidateEnable
= true;
3822 pc
.PostSyncOperation
= NoWrite
;
3825 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3829 ps
.PipelineSelection
= pipeline
;
3833 if (devinfo
->is_geminilake
) {
3836 * "This chicken bit works around a hardware issue with barrier logic
3837 * encountered when switching between GPGPU and 3D pipelines. To
3838 * workaround the issue, this mode bit should be set after a pipeline
3842 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3844 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3845 : GLK_BARRIER_MODE_3D_HULL
,
3846 .GLKBarrierModeMask
= 1);
3847 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3851 cmd_buffer
->state
.current_pipeline
= pipeline
;
3855 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3857 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3861 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3863 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3867 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3872 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3874 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3875 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3876 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3877 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3878 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3879 * Depth Flush Bit set, followed by another pipelined depth stall
3880 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3881 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3882 * via a preceding MI_FLUSH)."
3884 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3885 pipe
.DepthStallEnable
= true;
3887 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3888 pipe
.DepthCacheFlushEnable
= true;
3890 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3891 pipe
.DepthStallEnable
= true;
3896 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3898 struct anv_device
*device
= cmd_buffer
->device
;
3899 const struct anv_image_view
*iview
=
3900 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3901 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3903 /* FIXME: Width and Height are wrong */
3905 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3907 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3908 device
->isl_dev
.ds
.size
/ 4);
3912 struct isl_depth_stencil_hiz_emit_info info
= { };
3915 info
.view
= &iview
->planes
[0].isl
;
3917 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3918 uint32_t depth_plane
=
3919 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3920 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3922 info
.depth_surf
= &surface
->isl
;
3924 info
.depth_address
=
3925 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3926 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3927 image
->planes
[depth_plane
].address
.bo
,
3928 image
->planes
[depth_plane
].address
.offset
+
3931 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
3934 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3935 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3936 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3937 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3940 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3941 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3942 image
->planes
[depth_plane
].address
.bo
,
3943 image
->planes
[depth_plane
].address
.offset
+
3944 image
->planes
[depth_plane
].aux_surface
.offset
);
3946 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3950 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3951 uint32_t stencil_plane
=
3952 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3953 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3955 info
.stencil_surf
= &surface
->isl
;
3957 info
.stencil_address
=
3958 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3959 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3960 image
->planes
[stencil_plane
].address
.bo
,
3961 image
->planes
[stencil_plane
].address
.offset
+
3964 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
3967 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3969 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3973 * This ANDs the view mask of the current subpass with the pending clear
3974 * views in the attachment to get the mask of views active in the subpass
3975 * that still need to be cleared.
3977 static inline uint32_t
3978 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3979 const struct anv_attachment_state
*att_state
)
3981 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3985 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3986 const struct anv_attachment_state
*att_state
)
3988 if (!cmd_state
->subpass
->view_mask
)
3991 uint32_t pending_clear_mask
=
3992 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3994 return pending_clear_mask
& 1;
3998 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4001 const uint32_t last_subpass_idx
=
4002 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4003 const struct anv_subpass
*last_subpass
=
4004 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4005 return last_subpass
== cmd_state
->subpass
;
4009 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4010 uint32_t subpass_id
)
4012 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4013 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4014 cmd_state
->subpass
= subpass
;
4016 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4018 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4019 * different views. If the client asks for instancing, we need to use the
4020 * Instance Data Step Rate to ensure that we repeat the client's
4021 * per-instance data once for each view. Since this bit is in
4022 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4026 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4028 /* It is possible to start a render pass with an old pipeline. Because the
4029 * render pass and subpass index are both baked into the pipeline, this is
4030 * highly unlikely. In order to do so, it requires that you have a render
4031 * pass with a single subpass and that you use that render pass twice
4032 * back-to-back and use the same pipeline at the start of the second render
4033 * pass as at the end of the first. In order to avoid unpredictable issues
4034 * with this edge case, we just dirty the pipeline at the start of every
4037 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4039 /* Accumulate any subpass flushes that need to happen before the subpass */
4040 cmd_buffer
->state
.pending_pipe_bits
|=
4041 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4043 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4044 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4046 bool is_multiview
= subpass
->view_mask
!= 0;
4048 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4049 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4050 if (a
== VK_ATTACHMENT_UNUSED
)
4053 assert(a
< cmd_state
->pass
->attachment_count
);
4054 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4056 struct anv_image_view
*iview
= fb
->attachments
[a
];
4057 const struct anv_image
*image
= iview
->image
;
4059 /* A resolve is necessary before use as an input attachment if the clear
4060 * color or auxiliary buffer usage isn't supported by the sampler.
4062 const bool input_needs_resolve
=
4063 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4064 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4066 VkImageLayout target_layout
;
4067 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4068 !input_needs_resolve
) {
4069 /* Layout transitions before the final only help to enable sampling
4070 * as an input attachment. If the input attachment supports sampling
4071 * using the auxiliary surface, we can skip such transitions by
4072 * making the target layout one that is CCS-aware.
4074 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4076 target_layout
= subpass
->attachments
[i
].layout
;
4079 uint32_t base_layer
, layer_count
;
4080 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4082 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4083 iview
->planes
[0].isl
.base_level
);
4085 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4086 layer_count
= fb
->layers
;
4089 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4090 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4091 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4092 iview
->planes
[0].isl
.base_level
, 1,
4093 base_layer
, layer_count
,
4094 att_state
->current_layout
, target_layout
);
4097 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4098 transition_depth_buffer(cmd_buffer
, image
,
4099 att_state
->current_layout
, target_layout
);
4100 att_state
->aux_usage
=
4101 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4102 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4105 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4106 transition_stencil_buffer(cmd_buffer
, image
,
4107 iview
->planes
[0].isl
.base_level
, 1,
4108 base_layer
, layer_count
,
4109 att_state
->current_layout
, target_layout
);
4111 att_state
->current_layout
= target_layout
;
4113 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4114 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4116 /* Multi-planar images are not supported as attachments */
4117 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4118 assert(image
->n_planes
== 1);
4120 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4121 uint32_t clear_layer_count
= fb
->layers
;
4123 if (att_state
->fast_clear
&&
4124 do_first_layer_clear(cmd_state
, att_state
)) {
4125 /* We only support fast-clears on the first layer */
4126 assert(iview
->planes
[0].isl
.base_level
== 0);
4127 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4129 union isl_color_value clear_color
= {};
4130 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4131 if (iview
->image
->samples
== 1) {
4132 anv_image_ccs_op(cmd_buffer
, image
,
4133 iview
->planes
[0].isl
.format
,
4134 VK_IMAGE_ASPECT_COLOR_BIT
,
4135 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4139 anv_image_mcs_op(cmd_buffer
, image
,
4140 iview
->planes
[0].isl
.format
,
4141 VK_IMAGE_ASPECT_COLOR_BIT
,
4142 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4147 clear_layer_count
--;
4149 att_state
->pending_clear_views
&= ~1;
4151 if (att_state
->clear_color_is_zero
) {
4152 /* This image has the auxiliary buffer enabled. We can mark the
4153 * subresource as not needing a resolve because the clear color
4154 * will match what's in every RENDER_SURFACE_STATE object when
4155 * it's being used for sampling.
4157 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4158 VK_IMAGE_ASPECT_COLOR_BIT
,
4159 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4161 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4162 VK_IMAGE_ASPECT_COLOR_BIT
,
4163 ANV_FAST_CLEAR_ANY
);
4167 /* From the VkFramebufferCreateInfo spec:
4169 * "If the render pass uses multiview, then layers must be one and each
4170 * attachment requires a number of layers that is greater than the
4171 * maximum bit index set in the view mask in the subpasses in which it
4174 * So if multiview is active we ignore the number of layers in the
4175 * framebuffer and instead we honor the view mask from the subpass.
4178 assert(image
->n_planes
== 1);
4179 uint32_t pending_clear_mask
=
4180 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4183 for_each_bit(layer_idx
, pending_clear_mask
) {
4185 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4187 anv_image_clear_color(cmd_buffer
, image
,
4188 VK_IMAGE_ASPECT_COLOR_BIT
,
4189 att_state
->aux_usage
,
4190 iview
->planes
[0].isl
.format
,
4191 iview
->planes
[0].isl
.swizzle
,
4192 iview
->planes
[0].isl
.base_level
,
4195 vk_to_isl_color(att_state
->clear_value
.color
));
4198 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4199 } else if (clear_layer_count
> 0) {
4200 assert(image
->n_planes
== 1);
4201 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4202 att_state
->aux_usage
,
4203 iview
->planes
[0].isl
.format
,
4204 iview
->planes
[0].isl
.swizzle
,
4205 iview
->planes
[0].isl
.base_level
,
4206 base_clear_layer
, clear_layer_count
,
4208 vk_to_isl_color(att_state
->clear_value
.color
));
4210 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4211 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4212 if (att_state
->fast_clear
&& !is_multiview
) {
4213 /* We currently only support HiZ for single-layer images */
4214 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4215 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4216 assert(iview
->planes
[0].isl
.base_level
== 0);
4217 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4218 assert(fb
->layers
== 1);
4221 anv_image_hiz_clear(cmd_buffer
, image
,
4222 att_state
->pending_clear_aspects
,
4223 iview
->planes
[0].isl
.base_level
,
4224 iview
->planes
[0].isl
.base_array_layer
,
4225 fb
->layers
, render_area
,
4226 att_state
->clear_value
.depthStencil
.stencil
);
4227 } else if (is_multiview
) {
4228 uint32_t pending_clear_mask
=
4229 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4232 for_each_bit(layer_idx
, pending_clear_mask
) {
4234 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4236 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4237 att_state
->pending_clear_aspects
,
4238 att_state
->aux_usage
,
4239 iview
->planes
[0].isl
.base_level
,
4242 att_state
->clear_value
.depthStencil
.depth
,
4243 att_state
->clear_value
.depthStencil
.stencil
);
4246 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4248 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4249 att_state
->pending_clear_aspects
,
4250 att_state
->aux_usage
,
4251 iview
->planes
[0].isl
.base_level
,
4252 iview
->planes
[0].isl
.base_array_layer
,
4253 fb
->layers
, render_area
,
4254 att_state
->clear_value
.depthStencil
.depth
,
4255 att_state
->clear_value
.depthStencil
.stencil
);
4258 assert(att_state
->pending_clear_aspects
== 0);
4262 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4263 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4264 iview
->planes
[0].isl
.base_level
== 0 &&
4265 iview
->planes
[0].isl
.base_array_layer
== 0) {
4266 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4267 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4268 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4269 false /* copy to ss */);
4272 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4273 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4274 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4275 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4276 false /* copy to ss */);
4280 if (subpass
->attachments
[i
].usage
==
4281 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4282 /* We assume that if we're starting a subpass, we're going to do some
4283 * rendering so we may end up with compressed data.
4285 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4286 VK_IMAGE_ASPECT_COLOR_BIT
,
4287 att_state
->aux_usage
,
4288 iview
->planes
[0].isl
.base_level
,
4289 iview
->planes
[0].isl
.base_array_layer
,
4291 } else if (subpass
->attachments
[i
].usage
==
4292 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4293 /* We may be writing depth or stencil so we need to mark the surface.
4294 * Unfortunately, there's no way to know at this point whether the
4295 * depth or stencil tests used will actually write to the surface.
4297 * Even though stencil may be plane 1, it always shares a base_level
4300 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4301 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4302 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4303 VK_IMAGE_ASPECT_DEPTH_BIT
,
4304 att_state
->aux_usage
,
4305 ds_view
->base_level
,
4306 ds_view
->base_array_layer
,
4309 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4310 /* Even though stencil may be plane 1, it always shares a
4311 * base_level with depth.
4313 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4314 VK_IMAGE_ASPECT_STENCIL_BIT
,
4316 ds_view
->base_level
,
4317 ds_view
->base_array_layer
,
4322 /* If multiview is enabled, then we are only done clearing when we no
4323 * longer have pending layers to clear, or when we have processed the
4324 * last subpass that uses this attachment.
4326 if (!is_multiview
||
4327 att_state
->pending_clear_views
== 0 ||
4328 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4329 att_state
->pending_clear_aspects
= 0;
4332 att_state
->pending_load_aspects
= 0;
4335 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4338 static enum blorp_filter
4339 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4342 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4343 return BLORP_FILTER_SAMPLE_0
;
4344 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4345 return BLORP_FILTER_AVERAGE
;
4346 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4347 return BLORP_FILTER_MIN_SAMPLE
;
4348 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4349 return BLORP_FILTER_MAX_SAMPLE
;
4351 return BLORP_FILTER_NONE
;
4356 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4358 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4359 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4360 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4361 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4363 if (subpass
->has_color_resolve
) {
4364 /* We are about to do some MSAA resolves. We need to flush so that the
4365 * result of writes to the MSAA color attachments show up in the sampler
4366 * when we blit to the single-sampled resolve target.
4368 cmd_buffer
->state
.pending_pipe_bits
|=
4369 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4370 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4372 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4373 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4374 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4376 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4379 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4380 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4382 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4383 /* From the Vulkan 1.0 spec:
4385 * If the first use of an attachment in a render pass is as a
4386 * resolve attachment, then the loadOp is effectively ignored
4387 * as the resolve is guaranteed to overwrite all pixels in the
4390 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4393 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4394 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4396 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4398 enum isl_aux_usage src_aux_usage
=
4399 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4400 enum isl_aux_usage dst_aux_usage
=
4401 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4403 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4404 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4406 anv_image_msaa_resolve(cmd_buffer
,
4407 src_iview
->image
, src_aux_usage
,
4408 src_iview
->planes
[0].isl
.base_level
,
4409 src_iview
->planes
[0].isl
.base_array_layer
,
4410 dst_iview
->image
, dst_aux_usage
,
4411 dst_iview
->planes
[0].isl
.base_level
,
4412 dst_iview
->planes
[0].isl
.base_array_layer
,
4413 VK_IMAGE_ASPECT_COLOR_BIT
,
4414 render_area
.offset
.x
, render_area
.offset
.y
,
4415 render_area
.offset
.x
, render_area
.offset
.y
,
4416 render_area
.extent
.width
,
4417 render_area
.extent
.height
,
4418 fb
->layers
, BLORP_FILTER_NONE
);
4422 if (subpass
->ds_resolve_attachment
) {
4423 /* We are about to do some MSAA resolves. We need to flush so that the
4424 * result of writes to the MSAA depth attachments show up in the sampler
4425 * when we blit to the single-sampled resolve target.
4427 cmd_buffer
->state
.pending_pipe_bits
|=
4428 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4429 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4431 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4432 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4434 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4435 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4437 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4438 /* From the Vulkan 1.0 spec:
4440 * If the first use of an attachment in a render pass is as a
4441 * resolve attachment, then the loadOp is effectively ignored
4442 * as the resolve is guaranteed to overwrite all pixels in the
4445 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4448 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4449 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4451 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4453 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4454 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4456 struct anv_attachment_state
*src_state
=
4457 &cmd_state
->attachments
[src_att
];
4458 struct anv_attachment_state
*dst_state
=
4459 &cmd_state
->attachments
[dst_att
];
4461 /* MSAA resolves sample from the source attachment. Transition the
4462 * depth attachment first to get rid of any HiZ that we may not be
4465 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4466 src_state
->current_layout
,
4467 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4468 src_state
->aux_usage
=
4469 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4470 VK_IMAGE_ASPECT_DEPTH_BIT
,
4471 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4472 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4474 /* MSAA resolves write to the resolve attachment as if it were any
4475 * other transfer op. Transition the resolve attachment accordingly.
4477 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4479 /* If our render area is the entire size of the image, we're going to
4480 * blow it all away so we can claim the initial layout is UNDEFINED
4481 * and we'll get a HiZ ambiguate instead of a resolve.
4483 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4484 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4485 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4486 render_area
.extent
.height
== dst_iview
->extent
.height
)
4487 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4489 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4491 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4492 dst_state
->aux_usage
=
4493 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4494 VK_IMAGE_ASPECT_DEPTH_BIT
,
4495 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4496 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4498 enum blorp_filter filter
=
4499 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4501 anv_image_msaa_resolve(cmd_buffer
,
4502 src_iview
->image
, src_state
->aux_usage
,
4503 src_iview
->planes
[0].isl
.base_level
,
4504 src_iview
->planes
[0].isl
.base_array_layer
,
4505 dst_iview
->image
, dst_state
->aux_usage
,
4506 dst_iview
->planes
[0].isl
.base_level
,
4507 dst_iview
->planes
[0].isl
.base_array_layer
,
4508 VK_IMAGE_ASPECT_DEPTH_BIT
,
4509 render_area
.offset
.x
, render_area
.offset
.y
,
4510 render_area
.offset
.x
, render_area
.offset
.y
,
4511 render_area
.extent
.width
,
4512 render_area
.extent
.height
,
4513 fb
->layers
, filter
);
4516 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4517 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4519 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4520 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4522 enum blorp_filter filter
=
4523 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4525 anv_image_msaa_resolve(cmd_buffer
,
4526 src_iview
->image
, src_aux_usage
,
4527 src_iview
->planes
[0].isl
.base_level
,
4528 src_iview
->planes
[0].isl
.base_array_layer
,
4529 dst_iview
->image
, dst_aux_usage
,
4530 dst_iview
->planes
[0].isl
.base_level
,
4531 dst_iview
->planes
[0].isl
.base_array_layer
,
4532 VK_IMAGE_ASPECT_STENCIL_BIT
,
4533 render_area
.offset
.x
, render_area
.offset
.y
,
4534 render_area
.offset
.x
, render_area
.offset
.y
,
4535 render_area
.extent
.width
,
4536 render_area
.extent
.height
,
4537 fb
->layers
, filter
);
4542 /* On gen7, we have to store a texturable version of the stencil buffer in
4543 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
4544 * forth at strategic points. Stencil writes are only allowed in three
4547 * - VK_IMAGE_LAYOUT_GENERAL
4548 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
4549 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
4550 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
4552 * For general, we have no nice opportunity to transition so we do the copy
4553 * to the shadow unconditionally at the end of the subpass. For transfer
4554 * destinations, we can update it as part of the transfer op. For the
4555 * other two, we delay the copy until a transition into some other layout.
4557 if (subpass
->depth_stencil_attachment
) {
4558 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
4559 assert(a
!= VK_ATTACHMENT_UNUSED
);
4561 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4562 struct anv_image_view
*iview
= fb
->attachments
[a
];
4563 const struct anv_image
*image
= iview
->image
;
4565 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4566 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
4567 VK_IMAGE_ASPECT_STENCIL_BIT
);
4569 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
4570 att_state
->current_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
4571 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
4572 anv_image_copy_to_shadow(cmd_buffer
, image
,
4573 VK_IMAGE_ASPECT_STENCIL_BIT
,
4574 iview
->planes
[plane
].isl
.base_level
, 1,
4575 iview
->planes
[plane
].isl
.base_array_layer
,
4580 #endif /* GEN_GEN == 7 */
4582 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4583 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4584 if (a
== VK_ATTACHMENT_UNUSED
)
4587 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4590 assert(a
< cmd_state
->pass
->attachment_count
);
4591 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4592 struct anv_image_view
*iview
= fb
->attachments
[a
];
4593 const struct anv_image
*image
= iview
->image
;
4595 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4596 image
->vk_format
!= iview
->vk_format
) {
4597 enum anv_fast_clear_type fast_clear_type
=
4598 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4599 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4600 att_state
->current_layout
);
4602 /* If any clear color was used, flush it down the aux surfaces. If we
4603 * don't do it now using the view's format we might use the clear
4604 * color incorrectly in the following resolves (for example with an
4605 * SRGB view & a UNORM image).
4607 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4608 anv_perf_warn(cmd_buffer
->device
->instance
, fb
,
4609 "Doing a partial resolve to get rid of clear color at the "
4610 "end of a renderpass due to an image/view format mismatch");
4612 uint32_t base_layer
, layer_count
;
4613 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4615 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4616 iview
->planes
[0].isl
.base_level
);
4618 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4619 layer_count
= fb
->layers
;
4622 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4623 uint32_t array_layer
= base_layer
+ a
;
4624 if (image
->samples
== 1) {
4625 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4626 iview
->planes
[0].isl
.format
,
4627 VK_IMAGE_ASPECT_COLOR_BIT
,
4628 iview
->planes
[0].isl
.base_level
,
4630 ISL_AUX_OP_PARTIAL_RESOLVE
,
4631 ANV_FAST_CLEAR_NONE
);
4633 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4634 iview
->planes
[0].isl
.format
,
4635 VK_IMAGE_ASPECT_COLOR_BIT
,
4637 ISL_AUX_OP_PARTIAL_RESOLVE
,
4638 ANV_FAST_CLEAR_NONE
);
4644 /* Transition the image into the final layout for this render pass */
4645 VkImageLayout target_layout
=
4646 cmd_state
->pass
->attachments
[a
].final_layout
;
4648 uint32_t base_layer
, layer_count
;
4649 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4651 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4652 iview
->planes
[0].isl
.base_level
);
4654 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4655 layer_count
= fb
->layers
;
4658 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4659 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4660 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4661 iview
->planes
[0].isl
.base_level
, 1,
4662 base_layer
, layer_count
,
4663 att_state
->current_layout
, target_layout
);
4666 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4667 transition_depth_buffer(cmd_buffer
, image
,
4668 att_state
->current_layout
, target_layout
);
4671 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4672 transition_stencil_buffer(cmd_buffer
, image
,
4673 iview
->planes
[0].isl
.base_level
, 1,
4674 base_layer
, layer_count
,
4675 att_state
->current_layout
, target_layout
);
4679 /* Accumulate any subpass flushes that need to happen after the subpass.
4680 * Yes, they do get accumulated twice in the NextSubpass case but since
4681 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4682 * ORing the bits in twice so it's harmless.
4684 cmd_buffer
->state
.pending_pipe_bits
|=
4685 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4688 void genX(CmdBeginRenderPass
)(
4689 VkCommandBuffer commandBuffer
,
4690 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4691 VkSubpassContents contents
)
4693 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4694 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4695 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4697 cmd_buffer
->state
.framebuffer
= framebuffer
;
4698 cmd_buffer
->state
.pass
= pass
;
4699 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4701 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4703 /* If we failed to setup the attachments we should not try to go further */
4704 if (result
!= VK_SUCCESS
) {
4705 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4709 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4711 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4714 void genX(CmdBeginRenderPass2KHR
)(
4715 VkCommandBuffer commandBuffer
,
4716 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4717 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4719 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4720 pSubpassBeginInfo
->contents
);
4723 void genX(CmdNextSubpass
)(
4724 VkCommandBuffer commandBuffer
,
4725 VkSubpassContents contents
)
4727 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4729 if (anv_batch_has_error(&cmd_buffer
->batch
))
4732 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4734 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4735 cmd_buffer_end_subpass(cmd_buffer
);
4736 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4739 void genX(CmdNextSubpass2KHR
)(
4740 VkCommandBuffer commandBuffer
,
4741 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4742 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4744 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4747 void genX(CmdEndRenderPass
)(
4748 VkCommandBuffer commandBuffer
)
4750 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4752 if (anv_batch_has_error(&cmd_buffer
->batch
))
4755 cmd_buffer_end_subpass(cmd_buffer
);
4757 cmd_buffer
->state
.hiz_enabled
= false;
4760 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
4763 /* Remove references to render pass specific state. This enables us to
4764 * detect whether or not we're in a renderpass.
4766 cmd_buffer
->state
.framebuffer
= NULL
;
4767 cmd_buffer
->state
.pass
= NULL
;
4768 cmd_buffer
->state
.subpass
= NULL
;
4771 void genX(CmdEndRenderPass2KHR
)(
4772 VkCommandBuffer commandBuffer
,
4773 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4775 genX(CmdEndRenderPass
)(commandBuffer
);
4779 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
4781 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4782 struct gen_mi_builder b
;
4783 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4785 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
4786 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4787 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4789 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
4790 mip
.LoadOperation
= LOAD_LOADINV
;
4791 mip
.CombineOperation
= COMBINE_SET
;
4792 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4797 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4798 void genX(CmdBeginConditionalRenderingEXT
)(
4799 VkCommandBuffer commandBuffer
,
4800 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4802 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4803 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4804 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4805 struct anv_address value_address
=
4806 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
4808 const bool isInverted
= pConditionalRenderingBegin
->flags
&
4809 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
4811 cmd_state
->conditional_render_enabled
= true;
4813 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4815 struct gen_mi_builder b
;
4816 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4818 /* Section 19.4 of the Vulkan 1.1.85 spec says:
4820 * If the value of the predicate in buffer memory changes
4821 * while conditional rendering is active, the rendering commands
4822 * may be discarded in an implementation-dependent way.
4823 * Some implementations may latch the value of the predicate
4824 * upon beginning conditional rendering while others
4825 * may read it before every rendering command.
4827 * So it's perfectly fine to read a value from the buffer once.
4829 struct gen_mi_value value
= gen_mi_mem32(value_address
);
4831 /* Precompute predicate result, it is necessary to support secondary
4832 * command buffers since it is unknown if conditional rendering is
4833 * inverted when populating them.
4835 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
4836 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
4837 gen_mi_ult(&b
, gen_mi_imm(0), value
));
4840 void genX(CmdEndConditionalRenderingEXT
)(
4841 VkCommandBuffer commandBuffer
)
4843 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4844 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4846 cmd_state
->conditional_render_enabled
= false;
4850 /* Set of stage bits for which are pipelined, i.e. they get queued by the
4851 * command streamer for later execution.
4853 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
4854 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
4855 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
4856 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
4857 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
4858 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
4859 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
4860 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
4861 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
4862 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
4863 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
4864 VK_PIPELINE_STAGE_TRANSFER_BIT | \
4865 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
4866 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
4867 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
4869 void genX(CmdSetEvent
)(
4870 VkCommandBuffer commandBuffer
,
4872 VkPipelineStageFlags stageMask
)
4874 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4875 ANV_FROM_HANDLE(anv_event
, event
, _event
);
4877 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4878 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
4879 pc
.StallAtPixelScoreboard
= true;
4880 pc
.CommandStreamerStallEnable
= true;
4883 pc
.DestinationAddressType
= DAT_PPGTT
,
4884 pc
.PostSyncOperation
= WriteImmediateData
,
4885 pc
.Address
= (struct anv_address
) {
4886 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4889 pc
.ImmediateData
= VK_EVENT_SET
;
4893 void genX(CmdResetEvent
)(
4894 VkCommandBuffer commandBuffer
,
4896 VkPipelineStageFlags stageMask
)
4898 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4899 ANV_FROM_HANDLE(anv_event
, event
, _event
);
4901 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4902 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
4903 pc
.StallAtPixelScoreboard
= true;
4904 pc
.CommandStreamerStallEnable
= true;
4907 pc
.DestinationAddressType
= DAT_PPGTT
;
4908 pc
.PostSyncOperation
= WriteImmediateData
;
4909 pc
.Address
= (struct anv_address
) {
4910 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4913 pc
.ImmediateData
= VK_EVENT_RESET
;
4917 void genX(CmdWaitEvents
)(
4918 VkCommandBuffer commandBuffer
,
4919 uint32_t eventCount
,
4920 const VkEvent
* pEvents
,
4921 VkPipelineStageFlags srcStageMask
,
4922 VkPipelineStageFlags destStageMask
,
4923 uint32_t memoryBarrierCount
,
4924 const VkMemoryBarrier
* pMemoryBarriers
,
4925 uint32_t bufferMemoryBarrierCount
,
4926 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
4927 uint32_t imageMemoryBarrierCount
,
4928 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
4931 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4933 for (uint32_t i
= 0; i
< eventCount
; i
++) {
4934 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
4936 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
4937 sem
.WaitMode
= PollingMode
,
4938 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
4939 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
4940 sem
.SemaphoreAddress
= (struct anv_address
) {
4941 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4947 anv_finishme("Implement events on gen7");
4950 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
4951 false, /* byRegion */
4952 memoryBarrierCount
, pMemoryBarriers
,
4953 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
4954 imageMemoryBarrierCount
, pImageMemoryBarriers
);