2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
26 #include "genxml/gen_macros.h"
27 #include "genxml/genX_pack.h"
29 #include "common/gen_l3_config.h"
30 #include "common/gen_sample_positions.h"
31 #include "nir/nir_xfb_info.h"
33 #include "vk_format_info.h"
36 vertex_element_comp_control(enum isl_format format
, unsigned comp
)
40 case 0: bits
= isl_format_layouts
[format
].channels
.r
.bits
; break;
41 case 1: bits
= isl_format_layouts
[format
].channels
.g
.bits
; break;
42 case 2: bits
= isl_format_layouts
[format
].channels
.b
.bits
; break;
43 case 3: bits
= isl_format_layouts
[format
].channels
.a
.bits
; break;
44 default: unreachable("Invalid component");
48 * Take in account hardware restrictions when dealing with 64-bit floats.
50 * From Broadwell spec, command reference structures, page 586:
51 * "When SourceElementFormat is set to one of the *64*_PASSTHRU formats,
52 * 64-bit components are stored * in the URB without any conversion. In
53 * this case, vertex elements must be written as 128 or 256 bits, with
54 * VFCOMP_STORE_0 being used to pad the output as required. E.g., if
55 * R64_PASSTHRU is used to copy a 64-bit Red component into the URB,
56 * Component 1 must be specified as VFCOMP_STORE_0 (with Components 2,3
57 * set to VFCOMP_NOSTORE) in order to output a 128-bit vertex element, or
58 * Components 1-3 must be specified as VFCOMP_STORE_0 in order to output
59 * a 256-bit vertex element. Likewise, use of R64G64B64_PASSTHRU requires
60 * Component 3 to be specified as VFCOMP_STORE_0 in order to output a
61 * 256-bit vertex element."
64 return VFCOMP_STORE_SRC
;
65 } else if (comp
>= 2 &&
66 !isl_format_layouts
[format
].channels
.b
.bits
&&
67 isl_format_layouts
[format
].channels
.r
.type
== ISL_RAW
) {
68 /* When emitting 64-bit attributes, we need to write either 128 or 256
69 * bit chunks, using VFCOMP_NOSTORE when not writing the chunk, and
70 * VFCOMP_STORE_0 to pad the written chunk */
71 return VFCOMP_NOSTORE
;
72 } else if (comp
< 3 ||
73 isl_format_layouts
[format
].channels
.r
.type
== ISL_RAW
) {
74 /* Note we need to pad with value 0, not 1, due hardware restrictions
75 * (see comment above) */
76 return VFCOMP_STORE_0
;
77 } else if (isl_format_layouts
[format
].channels
.r
.type
== ISL_UINT
||
78 isl_format_layouts
[format
].channels
.r
.type
== ISL_SINT
) {
80 return VFCOMP_STORE_1_INT
;
83 return VFCOMP_STORE_1_FP
;
88 emit_vertex_input(struct anv_graphics_pipeline
*pipeline
,
89 const VkPipelineVertexInputStateCreateInfo
*info
)
91 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
93 /* Pull inputs_read out of the VS prog data */
94 const uint64_t inputs_read
= vs_prog_data
->inputs_read
;
95 const uint64_t double_inputs_read
=
96 vs_prog_data
->double_inputs_read
& inputs_read
;
97 assert((inputs_read
& ((1 << VERT_ATTRIB_GENERIC0
) - 1)) == 0);
98 const uint32_t elements
= inputs_read
>> VERT_ATTRIB_GENERIC0
;
99 const uint32_t elements_double
= double_inputs_read
>> VERT_ATTRIB_GENERIC0
;
100 const bool needs_svgs_elem
= vs_prog_data
->uses_vertexid
||
101 vs_prog_data
->uses_instanceid
||
102 vs_prog_data
->uses_firstvertex
||
103 vs_prog_data
->uses_baseinstance
;
105 uint32_t elem_count
= __builtin_popcount(elements
) -
106 __builtin_popcount(elements_double
) / 2;
108 const uint32_t total_elems
=
109 MAX2(1, elem_count
+ needs_svgs_elem
+ vs_prog_data
->uses_drawid
);
113 const uint32_t num_dwords
= 1 + total_elems
* 2;
114 p
= anv_batch_emitn(&pipeline
->base
.batch
, num_dwords
,
115 GENX(3DSTATE_VERTEX_ELEMENTS
));
119 for (uint32_t i
= 0; i
< total_elems
; i
++) {
120 /* The SKL docs for VERTEX_ELEMENT_STATE say:
122 * "All elements must be valid from Element[0] to the last valid
123 * element. (I.e. if Element[2] is valid then Element[1] and
124 * Element[0] must also be valid)."
126 * The SKL docs for 3D_Vertex_Component_Control say:
128 * "Don't store this component. (Not valid for Component 0, but can
129 * be used for Component 1-3)."
131 * So we can't just leave a vertex element blank and hope for the best.
132 * We have to tell the VF hardware to put something in it; so we just
133 * store a bunch of zero.
135 * TODO: Compact vertex elements so we never end up with holes.
137 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
139 .Component0Control
= VFCOMP_STORE_0
,
140 .Component1Control
= VFCOMP_STORE_0
,
141 .Component2Control
= VFCOMP_STORE_0
,
142 .Component3Control
= VFCOMP_STORE_0
,
144 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + i
* 2], &element
);
147 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
148 const VkVertexInputAttributeDescription
*desc
=
149 &info
->pVertexAttributeDescriptions
[i
];
150 enum isl_format format
= anv_get_isl_format(&pipeline
->base
.device
->info
,
152 VK_IMAGE_ASPECT_COLOR_BIT
,
153 VK_IMAGE_TILING_LINEAR
);
155 assert(desc
->binding
< MAX_VBS
);
157 if ((elements
& (1 << desc
->location
)) == 0)
158 continue; /* Binding unused */
161 __builtin_popcount(elements
& ((1 << desc
->location
) - 1)) -
162 DIV_ROUND_UP(__builtin_popcount(elements_double
&
163 ((1 << desc
->location
) -1)), 2);
165 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
166 .VertexBufferIndex
= desc
->binding
,
168 .SourceElementFormat
= format
,
169 .EdgeFlagEnable
= false,
170 .SourceElementOffset
= desc
->offset
,
171 .Component0Control
= vertex_element_comp_control(format
, 0),
172 .Component1Control
= vertex_element_comp_control(format
, 1),
173 .Component2Control
= vertex_element_comp_control(format
, 2),
174 .Component3Control
= vertex_element_comp_control(format
, 3),
176 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + slot
* 2], &element
);
179 /* On Broadwell and later, we have a separate VF_INSTANCING packet
180 * that controls instancing. On Haswell and prior, that's part of
181 * VERTEX_BUFFER_STATE which we emit later.
183 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
184 vfi
.InstancingEnable
= pipeline
->vb
[desc
->binding
].instanced
;
185 vfi
.VertexElementIndex
= slot
;
186 vfi
.InstanceDataStepRate
=
187 pipeline
->vb
[desc
->binding
].instance_divisor
;
192 const uint32_t id_slot
= elem_count
;
193 if (needs_svgs_elem
) {
194 /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
195 * "Within a VERTEX_ELEMENT_STATE structure, if a Component
196 * Control field is set to something other than VFCOMP_STORE_SRC,
197 * no higher-numbered Component Control fields may be set to
200 * This means, that if we have BaseInstance, we need BaseVertex as
201 * well. Just do all or nothing.
203 uint32_t base_ctrl
= (vs_prog_data
->uses_firstvertex
||
204 vs_prog_data
->uses_baseinstance
) ?
205 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
207 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
208 .VertexBufferIndex
= ANV_SVGS_VB_INDEX
,
210 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
211 .Component0Control
= base_ctrl
,
212 .Component1Control
= base_ctrl
,
214 .Component2Control
= VFCOMP_STORE_0
,
215 .Component3Control
= VFCOMP_STORE_0
,
217 .Component2Control
= VFCOMP_STORE_VID
,
218 .Component3Control
= VFCOMP_STORE_IID
,
221 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + id_slot
* 2], &element
);
224 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
225 vfi
.VertexElementIndex
= id_slot
;
231 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
232 sgvs
.VertexIDEnable
= vs_prog_data
->uses_vertexid
;
233 sgvs
.VertexIDComponentNumber
= 2;
234 sgvs
.VertexIDElementOffset
= id_slot
;
235 sgvs
.InstanceIDEnable
= vs_prog_data
->uses_instanceid
;
236 sgvs
.InstanceIDComponentNumber
= 3;
237 sgvs
.InstanceIDElementOffset
= id_slot
;
241 const uint32_t drawid_slot
= elem_count
+ needs_svgs_elem
;
242 if (vs_prog_data
->uses_drawid
) {
243 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
244 .VertexBufferIndex
= ANV_DRAWID_VB_INDEX
,
246 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
247 .Component0Control
= VFCOMP_STORE_SRC
,
248 .Component1Control
= VFCOMP_STORE_0
,
249 .Component2Control
= VFCOMP_STORE_0
,
250 .Component3Control
= VFCOMP_STORE_0
,
252 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
,
253 &p
[1 + drawid_slot
* 2],
257 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
258 vfi
.VertexElementIndex
= drawid_slot
;
265 genX(emit_urb_setup
)(struct anv_device
*device
, struct anv_batch
*batch
,
266 const struct gen_l3_config
*l3_config
,
267 VkShaderStageFlags active_stages
,
268 const unsigned entry_size
[4],
269 enum gen_urb_deref_block_size
*deref_block_size
)
271 const struct gen_device_info
*devinfo
= &device
->info
;
275 gen_get_urb_config(devinfo
, l3_config
,
277 VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
,
278 active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
,
279 entry_size
, entries
, start
, deref_block_size
);
281 #if GEN_GEN == 7 && !GEN_IS_HASWELL
282 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
284 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
285 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
286 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
287 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
288 * needs to be sent before any combination of VS associated 3DSTATE."
290 anv_batch_emit(batch
, GEN7_PIPE_CONTROL
, pc
) {
291 pc
.DepthStallEnable
= true;
292 pc
.PostSyncOperation
= WriteImmediateData
;
293 pc
.Address
= device
->workaround_address
;
297 for (int i
= 0; i
<= MESA_SHADER_GEOMETRY
; i
++) {
298 anv_batch_emit(batch
, GENX(3DSTATE_URB_VS
), urb
) {
299 urb
._3DCommandSubOpcode
+= i
;
300 urb
.VSURBStartingAddress
= start
[i
];
301 urb
.VSURBEntryAllocationSize
= entry_size
[i
] - 1;
302 urb
.VSNumberofURBEntries
= entries
[i
];
308 emit_urb_setup(struct anv_graphics_pipeline
*pipeline
,
309 enum gen_urb_deref_block_size
*deref_block_size
)
311 unsigned entry_size
[4];
312 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
313 const struct brw_vue_prog_data
*prog_data
=
314 !anv_pipeline_has_stage(pipeline
, i
) ? NULL
:
315 (const struct brw_vue_prog_data
*) pipeline
->shaders
[i
]->prog_data
;
317 entry_size
[i
] = prog_data
? prog_data
->urb_entry_size
: 1;
320 genX(emit_urb_setup
)(pipeline
->base
.device
, &pipeline
->base
.batch
,
321 pipeline
->base
.l3_config
,
322 pipeline
->active_stages
, entry_size
,
327 emit_3dstate_sbe(struct anv_graphics_pipeline
*pipeline
)
329 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
331 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
332 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_SBE
), sbe
);
334 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_SBE_SWIZ
), sbe
);
339 const struct brw_vue_map
*fs_input_map
=
340 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
342 struct GENX(3DSTATE_SBE
) sbe
= {
343 GENX(3DSTATE_SBE_header
),
344 .AttributeSwizzleEnable
= true,
345 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
,
346 .NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
,
347 .ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
,
351 for (unsigned i
= 0; i
< 32; i
++)
352 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
356 /* On Broadwell, they broke 3DSTATE_SBE into two packets */
357 struct GENX(3DSTATE_SBE_SWIZ
) swiz
= {
358 GENX(3DSTATE_SBE_SWIZ_header
),
364 int first_slot
= brw_compute_first_urb_slot_required(wm_prog_data
->inputs
,
366 assert(first_slot
% 2 == 0);
367 unsigned urb_entry_read_offset
= first_slot
/ 2;
368 int max_source_attr
= 0;
369 for (uint8_t idx
= 0; idx
< wm_prog_data
->urb_setup_attribs_count
; idx
++) {
370 uint8_t attr
= wm_prog_data
->urb_setup_attribs
[idx
];
371 int input_index
= wm_prog_data
->urb_setup
[attr
];
373 assert(0 <= input_index
);
375 /* gl_Viewport and gl_Layer are stored in the VUE header */
376 if (attr
== VARYING_SLOT_VIEWPORT
|| attr
== VARYING_SLOT_LAYER
) {
380 if (attr
== VARYING_SLOT_PNTC
) {
381 sbe
.PointSpriteTextureCoordinateEnable
= 1 << input_index
;
385 const int slot
= fs_input_map
->varying_to_slot
[attr
];
388 /* This attribute does not exist in the VUE--that means that the
389 * vertex shader did not write to it. It could be that it's a
390 * regular varying read by the fragment shader but not written by
391 * the vertex shader or it's gl_PrimitiveID. In the first case the
392 * value is undefined, in the second it needs to be
395 swiz
.Attribute
[input_index
].ConstantSource
= PRIM_ID
;
396 swiz
.Attribute
[input_index
].ComponentOverrideX
= true;
397 swiz
.Attribute
[input_index
].ComponentOverrideY
= true;
398 swiz
.Attribute
[input_index
].ComponentOverrideZ
= true;
399 swiz
.Attribute
[input_index
].ComponentOverrideW
= true;
403 /* We have to subtract two slots to accout for the URB entry output
404 * read offset in the VS and GS stages.
406 const int source_attr
= slot
- 2 * urb_entry_read_offset
;
407 assert(source_attr
>= 0 && source_attr
< 32);
408 max_source_attr
= MAX2(max_source_attr
, source_attr
);
409 /* The hardware can only do overrides on 16 overrides at a time, and the
410 * other up to 16 have to be lined up so that the input index = the
411 * output index. We'll need to do some tweaking to make sure that's the
414 if (input_index
< 16)
415 swiz
.Attribute
[input_index
].SourceAttribute
= source_attr
;
417 assert(source_attr
== input_index
);
420 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
421 sbe
.VertexURBEntryReadLength
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
423 sbe
.ForceVertexURBEntryReadOffset
= true;
424 sbe
.ForceVertexURBEntryReadLength
= true;
427 uint32_t *dw
= anv_batch_emit_dwords(&pipeline
->base
.batch
,
428 GENX(3DSTATE_SBE_length
));
431 GENX(3DSTATE_SBE_pack
)(&pipeline
->base
.batch
, dw
, &sbe
);
434 dw
= anv_batch_emit_dwords(&pipeline
->base
.batch
, GENX(3DSTATE_SBE_SWIZ_length
));
437 GENX(3DSTATE_SBE_SWIZ_pack
)(&pipeline
->base
.batch
, dw
, &swiz
);
441 static const uint32_t vk_to_gen_cullmode
[] = {
442 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
443 [VK_CULL_MODE_FRONT_BIT
] = CULLMODE_FRONT
,
444 [VK_CULL_MODE_BACK_BIT
] = CULLMODE_BACK
,
445 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
448 static const uint32_t vk_to_gen_fillmode
[] = {
449 [VK_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
450 [VK_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
451 [VK_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
454 static const uint32_t vk_to_gen_front_face
[] = {
455 [VK_FRONT_FACE_COUNTER_CLOCKWISE
] = 1,
456 [VK_FRONT_FACE_CLOCKWISE
] = 0
459 static VkLineRasterizationModeEXT
460 vk_line_rasterization_mode(const VkPipelineRasterizationLineStateCreateInfoEXT
*line_info
,
461 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
463 VkLineRasterizationModeEXT line_mode
=
464 line_info
? line_info
->lineRasterizationMode
:
465 VK_LINE_RASTERIZATION_MODE_DEFAULT_EXT
;
467 if (line_mode
== VK_LINE_RASTERIZATION_MODE_DEFAULT_EXT
) {
468 if (ms_info
&& ms_info
->rasterizationSamples
> 1) {
469 return VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT
;
471 return VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
;
478 /** Returns the final polygon mode for rasterization
480 * This function takes into account polygon mode, primitive topology and the
481 * different shader stages which might generate their own type of primitives.
484 anv_raster_polygon_mode(struct anv_graphics_pipeline
*pipeline
,
485 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
,
486 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
488 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
)) {
489 switch (get_gs_prog_data(pipeline
)->output_topology
) {
490 case _3DPRIM_POINTLIST
:
491 return VK_POLYGON_MODE_POINT
;
493 case _3DPRIM_LINELIST
:
494 case _3DPRIM_LINESTRIP
:
495 case _3DPRIM_LINELOOP
:
496 return VK_POLYGON_MODE_LINE
;
498 case _3DPRIM_TRILIST
:
500 case _3DPRIM_TRISTRIP
:
501 case _3DPRIM_RECTLIST
:
502 case _3DPRIM_QUADLIST
:
503 case _3DPRIM_QUADSTRIP
:
504 case _3DPRIM_POLYGON
:
505 return rs_info
->polygonMode
;
507 unreachable("Unsupported GS output topology");
508 } else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
509 switch (get_tes_prog_data(pipeline
)->output_topology
) {
510 case BRW_TESS_OUTPUT_TOPOLOGY_POINT
:
511 return VK_POLYGON_MODE_POINT
;
513 case BRW_TESS_OUTPUT_TOPOLOGY_LINE
:
514 return VK_POLYGON_MODE_LINE
;
516 case BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
:
517 case BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
:
518 return rs_info
->polygonMode
;
520 unreachable("Unsupported TCS output topology");
522 switch (ia_info
->topology
) {
523 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
524 return VK_POLYGON_MODE_POINT
;
526 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
527 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
528 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
529 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
530 return VK_POLYGON_MODE_LINE
;
532 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
533 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
534 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
535 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
536 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
537 return rs_info
->polygonMode
;
540 unreachable("Unsupported primitive topology");
547 gen7_ms_rast_mode(struct anv_graphics_pipeline
*pipeline
,
548 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
,
549 const VkPipelineRasterizationStateCreateInfo
*rs_info
,
550 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
552 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_info
=
553 vk_find_struct_const(rs_info
->pNext
,
554 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
556 VkPolygonMode raster_mode
=
557 anv_raster_polygon_mode(pipeline
, ia_info
, rs_info
);
558 if (raster_mode
== VK_POLYGON_MODE_LINE
) {
559 switch (vk_line_rasterization_mode(line_info
, ms_info
)) {
560 case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT
:
561 return MSRASTMODE_ON_PATTERN
;
563 case VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
:
564 case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT
:
565 return MSRASTMODE_OFF_PIXEL
;
568 unreachable("Unsupported line rasterization mode");
571 return (ms_info
&& ms_info
->rasterizationSamples
> 1) ?
572 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
578 emit_rs_state(struct anv_graphics_pipeline
*pipeline
,
579 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
,
580 const VkPipelineRasterizationStateCreateInfo
*rs_info
,
581 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
582 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_info
,
583 const uint32_t dynamic_states
,
584 const struct anv_render_pass
*pass
,
585 const struct anv_subpass
*subpass
,
586 enum gen_urb_deref_block_size urb_deref_block_size
)
588 struct GENX(3DSTATE_SF
) sf
= {
589 GENX(3DSTATE_SF_header
),
592 sf
.ViewportTransformEnable
= true;
593 sf
.StatisticsEnable
= true;
594 sf
.TriangleStripListProvokingVertexSelect
= 0;
595 sf
.LineStripListProvokingVertexSelect
= 0;
596 sf
.TriangleFanProvokingVertexSelect
= 1;
597 sf
.VertexSubPixelPrecisionSelect
= _8Bit
;
598 sf
.AALineDistanceMode
= true;
601 sf
.LineStippleEnable
= line_info
&& line_info
->stippledLineEnable
;
605 sf
.DerefBlockSize
= urb_deref_block_size
;
608 const struct brw_vue_prog_data
*last_vue_prog_data
=
609 anv_pipeline_get_last_vue_prog_data(pipeline
);
611 if (last_vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
612 sf
.PointWidthSource
= Vertex
;
614 sf
.PointWidthSource
= State
;
619 struct GENX(3DSTATE_RASTER
) raster
= {
620 GENX(3DSTATE_RASTER_header
),
626 VkPolygonMode raster_mode
=
627 anv_raster_polygon_mode(pipeline
, ia_info
, rs_info
);
628 VkLineRasterizationModeEXT line_mode
=
629 vk_line_rasterization_mode(line_info
, ms_info
);
631 /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
632 * "Multisample Modes State".
635 if (raster_mode
== VK_POLYGON_MODE_LINE
) {
636 /* Unfortunately, configuring our line rasterization hardware on gen8
637 * and later is rather painful. Instead of giving us bits to tell the
638 * hardware what line mode to use like we had on gen7, we now have an
639 * arcane combination of API Mode and MSAA enable bits which do things
640 * in a table which are expected to magically put the hardware into the
641 * right mode for your API. Sadly, Vulkan isn't any of the APIs the
642 * hardware people thought of so nothing works the way you want it to.
644 * Look at the table titled "Multisample Rasterization Modes" in Vol 7
645 * of the Skylake PRM for more details.
648 case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT
:
649 raster
.APIMode
= DX100
;
650 raster
.DXMultisampleRasterizationEnable
= true;
653 case VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
:
654 case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT
:
655 raster
.APIMode
= DX9OGL
;
656 raster
.DXMultisampleRasterizationEnable
= false;
660 unreachable("Unsupported line rasterization mode");
663 raster
.APIMode
= DX100
;
664 raster
.DXMultisampleRasterizationEnable
= true;
667 /* NOTE: 3DSTATE_RASTER::ForcedSampleCount affects the BDW and SKL PMA fix
668 * computations. If we ever set this bit to a different value, they will
669 * need to be updated accordingly.
671 raster
.ForcedSampleCount
= FSC_NUMRASTSAMPLES_0
;
672 raster
.ForceMultisampling
= false;
674 raster
.MultisampleRasterizationMode
=
675 gen7_ms_rast_mode(pipeline
, ia_info
, rs_info
, ms_info
);
678 if (raster_mode
== VK_POLYGON_MODE_LINE
&&
679 line_mode
== VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT
)
680 raster
.AntialiasingEnable
= true;
682 raster
.FrontWinding
=
683 dynamic_states
& ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE
?
684 0 : vk_to_gen_front_face
[rs_info
->frontFace
];
686 dynamic_states
& ANV_CMD_DIRTY_DYNAMIC_CULL_MODE
?
687 0 : vk_to_gen_cullmode
[rs_info
->cullMode
];
689 raster
.FrontFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
690 raster
.BackFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
691 raster
.ScissorRectangleEnable
= true;
694 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
695 raster
.ViewportZFarClipTestEnable
= pipeline
->depth_clip_enable
;
696 raster
.ViewportZNearClipTestEnable
= pipeline
->depth_clip_enable
;
698 raster
.ViewportZClipTestEnable
= pipeline
->depth_clip_enable
;
701 raster
.GlobalDepthOffsetEnableSolid
= rs_info
->depthBiasEnable
;
702 raster
.GlobalDepthOffsetEnableWireframe
= rs_info
->depthBiasEnable
;
703 raster
.GlobalDepthOffsetEnablePoint
= rs_info
->depthBiasEnable
;
706 /* Gen7 requires that we provide the depth format in 3DSTATE_SF so that it
707 * can get the depth offsets correct.
709 if (subpass
->depth_stencil_attachment
) {
711 pass
->attachments
[subpass
->depth_stencil_attachment
->attachment
].format
;
712 assert(vk_format_is_depth_or_stencil(vk_format
));
713 if (vk_format_aspects(vk_format
) & VK_IMAGE_ASPECT_DEPTH_BIT
) {
714 enum isl_format isl_format
=
715 anv_get_isl_format(&pipeline
->base
.device
->info
, vk_format
,
716 VK_IMAGE_ASPECT_DEPTH_BIT
,
717 VK_IMAGE_TILING_OPTIMAL
);
718 sf
.DepthBufferSurfaceFormat
=
719 isl_format_get_depth_format(isl_format
, false);
725 GENX(3DSTATE_SF_pack
)(NULL
, pipeline
->gen8
.sf
, &sf
);
726 GENX(3DSTATE_RASTER_pack
)(NULL
, pipeline
->gen8
.raster
, &raster
);
729 GENX(3DSTATE_SF_pack
)(NULL
, &pipeline
->gen7
.sf
, &sf
);
734 emit_ms_state(struct anv_graphics_pipeline
*pipeline
,
735 const VkPipelineMultisampleStateCreateInfo
*info
)
737 uint32_t samples
= 1;
738 uint32_t log2_samples
= 0;
740 /* From the Vulkan 1.0 spec:
741 * If pSampleMask is NULL, it is treated as if the mask has all bits
742 * enabled, i.e. no coverage is removed from fragments.
744 * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
747 uint32_t sample_mask
= 0xffff;
749 uint32_t sample_mask
= 0xff;
753 samples
= info
->rasterizationSamples
;
754 log2_samples
= __builtin_ffs(samples
) - 1;
757 if (info
&& info
->pSampleMask
)
758 sample_mask
&= info
->pSampleMask
[0];
760 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
761 ms
.NumberofMultisamples
= log2_samples
;
763 ms
.PixelLocation
= CENTER
;
765 /* The PRM says that this bit is valid only for DX9:
767 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
768 * should not have any effect by setting or not setting this bit.
770 ms
.PixelPositionOffsetEnable
= false;
775 GEN_SAMPLE_POS_1X(ms
.Sample
);
778 GEN_SAMPLE_POS_2X(ms
.Sample
);
781 GEN_SAMPLE_POS_4X(ms
.Sample
);
784 GEN_SAMPLE_POS_8X(ms
.Sample
);
792 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
793 sm
.SampleMask
= sample_mask
;
797 static const uint32_t vk_to_gen_logic_op
[] = {
798 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
799 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
800 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
801 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
802 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
803 [VK_LOGIC_OP_NO_OP
] = LOGICOP_NOOP
,
804 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
805 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
806 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
807 [VK_LOGIC_OP_EQUIVALENT
] = LOGICOP_EQUIV
,
808 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
809 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
810 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
811 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
812 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
813 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
816 static const uint32_t vk_to_gen_blend
[] = {
817 [VK_BLEND_FACTOR_ZERO
] = BLENDFACTOR_ZERO
,
818 [VK_BLEND_FACTOR_ONE
] = BLENDFACTOR_ONE
,
819 [VK_BLEND_FACTOR_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
820 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
821 [VK_BLEND_FACTOR_DST_COLOR
] = BLENDFACTOR_DST_COLOR
,
822 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
823 [VK_BLEND_FACTOR_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
824 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
825 [VK_BLEND_FACTOR_DST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
826 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
827 [VK_BLEND_FACTOR_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
828 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
]= BLENDFACTOR_INV_CONST_COLOR
,
829 [VK_BLEND_FACTOR_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
830 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
]= BLENDFACTOR_INV_CONST_ALPHA
,
831 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
832 [VK_BLEND_FACTOR_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
833 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
834 [VK_BLEND_FACTOR_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
835 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
838 static const uint32_t vk_to_gen_blend_op
[] = {
839 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
840 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
841 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
842 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
843 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
846 static const uint32_t vk_to_gen_compare_op
[] = {
847 [VK_COMPARE_OP_NEVER
] = PREFILTEROPNEVER
,
848 [VK_COMPARE_OP_LESS
] = PREFILTEROPLESS
,
849 [VK_COMPARE_OP_EQUAL
] = PREFILTEROPEQUAL
,
850 [VK_COMPARE_OP_LESS_OR_EQUAL
] = PREFILTEROPLEQUAL
,
851 [VK_COMPARE_OP_GREATER
] = PREFILTEROPGREATER
,
852 [VK_COMPARE_OP_NOT_EQUAL
] = PREFILTEROPNOTEQUAL
,
853 [VK_COMPARE_OP_GREATER_OR_EQUAL
] = PREFILTEROPGEQUAL
,
854 [VK_COMPARE_OP_ALWAYS
] = PREFILTEROPALWAYS
,
857 static const uint32_t vk_to_gen_stencil_op
[] = {
858 [VK_STENCIL_OP_KEEP
] = STENCILOP_KEEP
,
859 [VK_STENCIL_OP_ZERO
] = STENCILOP_ZERO
,
860 [VK_STENCIL_OP_REPLACE
] = STENCILOP_REPLACE
,
861 [VK_STENCIL_OP_INCREMENT_AND_CLAMP
] = STENCILOP_INCRSAT
,
862 [VK_STENCIL_OP_DECREMENT_AND_CLAMP
] = STENCILOP_DECRSAT
,
863 [VK_STENCIL_OP_INVERT
] = STENCILOP_INVERT
,
864 [VK_STENCIL_OP_INCREMENT_AND_WRAP
] = STENCILOP_INCR
,
865 [VK_STENCIL_OP_DECREMENT_AND_WRAP
] = STENCILOP_DECR
,
868 /* This function sanitizes the VkStencilOpState by looking at the compare ops
869 * and trying to determine whether or not a given stencil op can ever actually
870 * occur. Stencil ops which can never occur are set to VK_STENCIL_OP_KEEP.
871 * This function returns true if, after sanitation, any of the stencil ops are
872 * set to something other than VK_STENCIL_OP_KEEP.
875 sanitize_stencil_face(VkStencilOpState
*face
,
876 VkCompareOp depthCompareOp
)
878 /* If compareOp is ALWAYS then the stencil test will never fail and failOp
879 * will never happen. Set failOp to KEEP in this case.
881 if (face
->compareOp
== VK_COMPARE_OP_ALWAYS
)
882 face
->failOp
= VK_STENCIL_OP_KEEP
;
884 /* If compareOp is NEVER or depthCompareOp is NEVER then one of the depth
885 * or stencil tests will fail and passOp will never happen.
887 if (face
->compareOp
== VK_COMPARE_OP_NEVER
||
888 depthCompareOp
== VK_COMPARE_OP_NEVER
)
889 face
->passOp
= VK_STENCIL_OP_KEEP
;
891 /* If compareOp is NEVER or depthCompareOp is ALWAYS then either the
892 * stencil test will fail or the depth test will pass. In either case,
893 * depthFailOp will never happen.
895 if (face
->compareOp
== VK_COMPARE_OP_NEVER
||
896 depthCompareOp
== VK_COMPARE_OP_ALWAYS
)
897 face
->depthFailOp
= VK_STENCIL_OP_KEEP
;
899 return face
->failOp
!= VK_STENCIL_OP_KEEP
||
900 face
->depthFailOp
!= VK_STENCIL_OP_KEEP
||
901 face
->passOp
!= VK_STENCIL_OP_KEEP
;
904 /* Intel hardware is fairly sensitive to whether or not depth/stencil writes
905 * are enabled. In the presence of discards, it's fairly easy to get into the
906 * non-promoted case which means a fairly big performance hit. From the Iron
907 * Lake PRM, Vol 2, pt. 1, section 8.4.3.2, "Early Depth Test Cases":
909 * "Non-promoted depth (N) is active whenever the depth test can be done
910 * early but it cannot determine whether or not to write source depth to
911 * the depth buffer, therefore the depth write must be performed post pixel
912 * shader. This includes cases where the pixel shader can kill pixels,
913 * including via sampler chroma key, as well as cases where the alpha test
914 * function is enabled, which kills pixels based on a programmable alpha
915 * test. In this case, even if the depth test fails, the pixel cannot be
916 * killed if a stencil write is indicated. Whether or not the stencil write
917 * happens depends on whether or not the pixel is killed later. In these
918 * cases if stencil test fails and stencil writes are off, the pixels can
919 * also be killed early. If stencil writes are enabled, the pixels must be
920 * treated as Computed depth (described above)."
922 * The same thing as mentioned in the stencil case can happen in the depth
923 * case as well if it thinks it writes depth but, thanks to the depth test
924 * being GL_EQUAL, the write doesn't actually matter. A little extra work
925 * up-front to try and disable depth and stencil writes can make a big
928 * Unfortunately, the way depth and stencil testing is specified, there are
929 * many case where, regardless of depth/stencil writes being enabled, nothing
930 * actually gets written due to some other bit of state being set. This
931 * function attempts to "sanitize" the depth stencil state and disable writes
932 * and sometimes even testing whenever possible.
935 sanitize_ds_state(VkPipelineDepthStencilStateCreateInfo
*state
,
936 bool *stencilWriteEnable
,
937 VkImageAspectFlags ds_aspects
)
939 *stencilWriteEnable
= state
->stencilTestEnable
;
941 /* If the depth test is disabled, we won't be writing anything. Make sure we
942 * treat the test as always passing later on as well.
944 * Also, the Vulkan spec requires that if either depth or stencil is not
945 * present, the pipeline is to act as if the test silently passes. In that
946 * case we won't write either.
948 if (!state
->depthTestEnable
|| !(ds_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
949 state
->depthWriteEnable
= false;
950 state
->depthCompareOp
= VK_COMPARE_OP_ALWAYS
;
953 if (!(ds_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
954 *stencilWriteEnable
= false;
955 state
->front
.compareOp
= VK_COMPARE_OP_ALWAYS
;
956 state
->back
.compareOp
= VK_COMPARE_OP_ALWAYS
;
959 /* If the stencil test is enabled and always fails, then we will never get
960 * to the depth test so we can just disable the depth test entirely.
962 if (state
->stencilTestEnable
&&
963 state
->front
.compareOp
== VK_COMPARE_OP_NEVER
&&
964 state
->back
.compareOp
== VK_COMPARE_OP_NEVER
) {
965 state
->depthTestEnable
= false;
966 state
->depthWriteEnable
= false;
969 /* If depthCompareOp is EQUAL then the value we would be writing to the
970 * depth buffer is the same as the value that's already there so there's no
971 * point in writing it.
973 if (state
->depthCompareOp
== VK_COMPARE_OP_EQUAL
)
974 state
->depthWriteEnable
= false;
976 /* If the stencil ops are such that we don't actually ever modify the
977 * stencil buffer, we should disable writes.
979 if (!sanitize_stencil_face(&state
->front
, state
->depthCompareOp
) &&
980 !sanitize_stencil_face(&state
->back
, state
->depthCompareOp
))
981 *stencilWriteEnable
= false;
983 /* If the depth test always passes and we never write out depth, that's the
984 * same as if the depth test is disabled entirely.
986 if (state
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
&&
987 !state
->depthWriteEnable
)
988 state
->depthTestEnable
= false;
990 /* If the stencil test always passes and we never write out stencil, that's
991 * the same as if the stencil test is disabled entirely.
993 if (state
->front
.compareOp
== VK_COMPARE_OP_ALWAYS
&&
994 state
->back
.compareOp
== VK_COMPARE_OP_ALWAYS
&&
995 !*stencilWriteEnable
)
996 state
->stencilTestEnable
= false;
1000 emit_ds_state(struct anv_graphics_pipeline
*pipeline
,
1001 const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
,
1002 const uint32_t dynamic_states
,
1003 const struct anv_render_pass
*pass
,
1004 const struct anv_subpass
*subpass
)
1007 # define depth_stencil_dw pipeline->gen7.depth_stencil_state
1009 # define depth_stencil_dw pipeline->gen8.wm_depth_stencil
1011 # define depth_stencil_dw pipeline->gen9.wm_depth_stencil
1014 if (pCreateInfo
== NULL
) {
1015 /* We're going to OR this together with the dynamic state. We need
1016 * to make sure it's initialized to something useful.
1018 pipeline
->writes_stencil
= false;
1019 pipeline
->stencil_test_enable
= false;
1020 pipeline
->writes_depth
= false;
1021 pipeline
->depth_test_enable
= false;
1022 pipeline
->depth_bounds_test_enable
= false;
1023 memset(depth_stencil_dw
, 0, sizeof(depth_stencil_dw
));
1027 VkImageAspectFlags ds_aspects
= 0;
1028 if (subpass
->depth_stencil_attachment
) {
1029 VkFormat depth_stencil_format
=
1030 pass
->attachments
[subpass
->depth_stencil_attachment
->attachment
].format
;
1031 ds_aspects
= vk_format_aspects(depth_stencil_format
);
1034 VkPipelineDepthStencilStateCreateInfo info
= *pCreateInfo
;
1035 sanitize_ds_state(&info
, &pipeline
->writes_stencil
, ds_aspects
);
1036 pipeline
->stencil_test_enable
= info
.stencilTestEnable
;
1037 pipeline
->writes_depth
= info
.depthWriteEnable
;
1038 pipeline
->depth_test_enable
= info
.depthTestEnable
;
1039 pipeline
->depth_bounds_test_enable
= info
.depthBoundsTestEnable
;
1041 bool dynamic_stencil_op
=
1042 dynamic_states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP
;
1045 struct GENX(DEPTH_STENCIL_STATE
) depth_stencil
= {
1047 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) depth_stencil
= {
1050 dynamic_states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE
?
1051 0 : info
.depthTestEnable
,
1053 .DepthBufferWriteEnable
=
1054 dynamic_states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE
?
1055 0 : info
.depthWriteEnable
,
1057 .DepthTestFunction
=
1058 dynamic_states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP
?
1059 0 : vk_to_gen_compare_op
[info
.depthCompareOp
],
1061 .DoubleSidedStencilEnable
= true,
1063 .StencilTestEnable
=
1064 dynamic_states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE
?
1065 0 : info
.stencilTestEnable
,
1067 .StencilFailOp
= vk_to_gen_stencil_op
[info
.front
.failOp
],
1068 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
.front
.passOp
],
1069 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
.front
.depthFailOp
],
1070 .StencilTestFunction
= vk_to_gen_compare_op
[info
.front
.compareOp
],
1071 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
.back
.failOp
],
1072 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
.back
.passOp
],
1073 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
.back
.depthFailOp
],
1074 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
.back
.compareOp
],
1077 if (dynamic_stencil_op
) {
1078 depth_stencil
.StencilFailOp
= 0;
1079 depth_stencil
.StencilPassDepthPassOp
= 0;
1080 depth_stencil
.StencilPassDepthFailOp
= 0;
1081 depth_stencil
.StencilTestFunction
= 0;
1082 depth_stencil
.BackfaceStencilFailOp
= 0;
1083 depth_stencil
.BackfaceStencilPassDepthPassOp
= 0;
1084 depth_stencil
.BackfaceStencilPassDepthFailOp
= 0;
1085 depth_stencil
.BackfaceStencilTestFunction
= 0;
1089 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
1091 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
1096 is_dual_src_blend_factor(VkBlendFactor factor
)
1098 return factor
== VK_BLEND_FACTOR_SRC1_COLOR
||
1099 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
||
1100 factor
== VK_BLEND_FACTOR_SRC1_ALPHA
||
1101 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
;
1105 emit_cb_state(struct anv_graphics_pipeline
*pipeline
,
1106 const VkPipelineColorBlendStateCreateInfo
*info
,
1107 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
1109 struct anv_device
*device
= pipeline
->base
.device
;
1110 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1112 struct GENX(BLEND_STATE
) blend_state
= {
1114 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
1115 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
1119 uint32_t surface_count
= 0;
1120 struct anv_pipeline_bind_map
*map
;
1121 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1122 map
= &pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->bind_map
;
1123 surface_count
= map
->surface_count
;
1126 const uint32_t num_dwords
= GENX(BLEND_STATE_length
) +
1127 GENX(BLEND_STATE_ENTRY_length
) * surface_count
;
1128 pipeline
->blend_state
=
1129 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
1131 bool has_writeable_rt
= false;
1132 uint32_t *state_pos
= pipeline
->blend_state
.map
;
1133 state_pos
+= GENX(BLEND_STATE_length
);
1135 struct GENX(BLEND_STATE_ENTRY
) bs0
= { 0 };
1137 for (unsigned i
= 0; i
< surface_count
; i
++) {
1138 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[i
];
1140 /* All color attachments are at the beginning of the binding table */
1141 if (binding
->set
!= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
1144 /* We can have at most 8 attachments */
1147 if (info
== NULL
|| binding
->index
>= info
->attachmentCount
) {
1148 /* Default everything to disabled */
1149 struct GENX(BLEND_STATE_ENTRY
) entry
= {
1150 .WriteDisableAlpha
= true,
1151 .WriteDisableRed
= true,
1152 .WriteDisableGreen
= true,
1153 .WriteDisableBlue
= true,
1155 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, state_pos
, &entry
);
1156 state_pos
+= GENX(BLEND_STATE_ENTRY_length
);
1160 const VkPipelineColorBlendAttachmentState
*a
=
1161 &info
->pAttachments
[binding
->index
];
1163 struct GENX(BLEND_STATE_ENTRY
) entry
= {
1165 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
1166 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
1168 .LogicOpEnable
= info
->logicOpEnable
,
1169 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
1170 .ColorBufferBlendEnable
= a
->blendEnable
,
1171 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
1172 .PreBlendColorClampEnable
= true,
1173 .PostBlendColorClampEnable
= true,
1174 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcColorBlendFactor
],
1175 .DestinationBlendFactor
= vk_to_gen_blend
[a
->dstColorBlendFactor
],
1176 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->colorBlendOp
],
1177 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcAlphaBlendFactor
],
1178 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->dstAlphaBlendFactor
],
1179 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->alphaBlendOp
],
1180 .WriteDisableAlpha
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_A_BIT
),
1181 .WriteDisableRed
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_R_BIT
),
1182 .WriteDisableGreen
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_G_BIT
),
1183 .WriteDisableBlue
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_B_BIT
),
1186 if (a
->srcColorBlendFactor
!= a
->srcAlphaBlendFactor
||
1187 a
->dstColorBlendFactor
!= a
->dstAlphaBlendFactor
||
1188 a
->colorBlendOp
!= a
->alphaBlendOp
) {
1190 blend_state
.IndependentAlphaBlendEnable
= true;
1192 entry
.IndependentAlphaBlendEnable
= true;
1196 /* The Dual Source Blending documentation says:
1198 * "If SRC1 is included in a src/dst blend factor and
1199 * a DualSource RT Write message is not used, results
1200 * are UNDEFINED. (This reflects the same restriction in DX APIs,
1201 * where undefined results are produced if “o1” is not written
1202 * by a PS – there are no default values defined)."
1204 * There is no way to gracefully fix this undefined situation
1205 * so we just disable the blending to prevent possible issues.
1207 if (!wm_prog_data
->dual_src_blend
&&
1208 (is_dual_src_blend_factor(a
->srcColorBlendFactor
) ||
1209 is_dual_src_blend_factor(a
->dstColorBlendFactor
) ||
1210 is_dual_src_blend_factor(a
->srcAlphaBlendFactor
) ||
1211 is_dual_src_blend_factor(a
->dstAlphaBlendFactor
))) {
1212 vk_debug_report(&device
->physical
->instance
->debug_report_callbacks
,
1213 VK_DEBUG_REPORT_WARNING_BIT_EXT
,
1214 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT
,
1215 (uint64_t)(uintptr_t)device
,
1217 "Enabled dual-src blend factors without writing both targets "
1218 "in the shader. Disabling blending to avoid GPU hangs.");
1219 entry
.ColorBufferBlendEnable
= false;
1222 if (a
->colorWriteMask
!= 0)
1223 has_writeable_rt
= true;
1225 /* Our hardware applies the blend factor prior to the blend function
1226 * regardless of what function is used. Technically, this means the
1227 * hardware can do MORE than GL or Vulkan specify. However, it also
1228 * means that, for MIN and MAX, we have to stomp the blend factor to
1229 * ONE to make it a no-op.
1231 if (a
->colorBlendOp
== VK_BLEND_OP_MIN
||
1232 a
->colorBlendOp
== VK_BLEND_OP_MAX
) {
1233 entry
.SourceBlendFactor
= BLENDFACTOR_ONE
;
1234 entry
.DestinationBlendFactor
= BLENDFACTOR_ONE
;
1236 if (a
->alphaBlendOp
== VK_BLEND_OP_MIN
||
1237 a
->alphaBlendOp
== VK_BLEND_OP_MAX
) {
1238 entry
.SourceAlphaBlendFactor
= BLENDFACTOR_ONE
;
1239 entry
.DestinationAlphaBlendFactor
= BLENDFACTOR_ONE
;
1241 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, state_pos
, &entry
);
1242 state_pos
+= GENX(BLEND_STATE_ENTRY_length
);
1250 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PS_BLEND
), blend
) {
1251 blend
.AlphaToCoverageEnable
= blend_state
.AlphaToCoverageEnable
;
1252 blend
.HasWriteableRT
= has_writeable_rt
;
1253 blend
.ColorBufferBlendEnable
= bs0
.ColorBufferBlendEnable
;
1254 blend
.SourceAlphaBlendFactor
= bs0
.SourceAlphaBlendFactor
;
1255 blend
.DestinationAlphaBlendFactor
= bs0
.DestinationAlphaBlendFactor
;
1256 blend
.SourceBlendFactor
= bs0
.SourceBlendFactor
;
1257 blend
.DestinationBlendFactor
= bs0
.DestinationBlendFactor
;
1258 blend
.AlphaTestEnable
= false;
1259 blend
.IndependentAlphaBlendEnable
=
1260 blend_state
.IndependentAlphaBlendEnable
;
1263 (void)has_writeable_rt
;
1266 GENX(BLEND_STATE_pack
)(NULL
, pipeline
->blend_state
.map
, &blend_state
);
1268 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), bsp
) {
1269 bsp
.BlendStatePointer
= pipeline
->blend_state
.offset
;
1271 bsp
.BlendStatePointerValid
= true;
1277 emit_3dstate_clip(struct anv_graphics_pipeline
*pipeline
,
1278 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
,
1279 const VkPipelineViewportStateCreateInfo
*vp_info
,
1280 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
1282 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1283 (void) wm_prog_data
;
1284 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_CLIP
), clip
) {
1285 clip
.ClipEnable
= true;
1286 clip
.StatisticsEnable
= true;
1287 clip
.EarlyCullEnable
= true;
1288 clip
.APIMode
= APIMODE_D3D
;
1289 clip
.GuardbandClipTestEnable
= true;
1291 /* Only enable the XY clip test when the final polygon rasterization
1292 * mode is VK_POLYGON_MODE_FILL. We want to leave it disabled for
1293 * points and lines so we get "pop-free" clipping.
1295 VkPolygonMode raster_mode
=
1296 anv_raster_polygon_mode(pipeline
, ia_info
, rs_info
);
1297 clip
.ViewportXYClipTestEnable
= (raster_mode
== VK_POLYGON_MODE_FILL
);
1300 clip
.VertexSubPixelPrecisionSelect
= _8Bit
;
1303 clip
.ClipMode
= CLIPMODE_NORMAL
;
1305 clip
.TriangleStripListProvokingVertexSelect
= 0;
1306 clip
.LineStripListProvokingVertexSelect
= 0;
1307 clip
.TriangleFanProvokingVertexSelect
= 1;
1309 clip
.MinimumPointWidth
= 0.125;
1310 clip
.MaximumPointWidth
= 255.875;
1312 const struct brw_vue_prog_data
*last
=
1313 anv_pipeline_get_last_vue_prog_data(pipeline
);
1315 /* From the Vulkan 1.0.45 spec:
1317 * "If the last active vertex processing stage shader entry point's
1318 * interface does not include a variable decorated with
1319 * ViewportIndex, then the first viewport is used."
1321 if (vp_info
&& (last
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
)) {
1322 clip
.MaximumVPIndex
= vp_info
->viewportCount
- 1;
1324 clip
.MaximumVPIndex
= 0;
1327 /* From the Vulkan 1.0.45 spec:
1329 * "If the last active vertex processing stage shader entry point's
1330 * interface does not include a variable decorated with Layer, then
1331 * the first layer is used."
1333 clip
.ForceZeroRTAIndexEnable
=
1334 !(last
->vue_map
.slots_valid
& VARYING_BIT_LAYER
);
1337 clip
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
];
1338 clip
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
];
1339 clip
.ViewportZClipTestEnable
= pipeline
->depth_clip_enable
;
1340 clip
.UserClipDistanceClipTestEnableBitmask
= last
->clip_distance_mask
;
1341 clip
.UserClipDistanceCullTestEnableBitmask
= last
->cull_distance_mask
;
1343 clip
.NonPerspectiveBarycentricEnable
= wm_prog_data
?
1344 (wm_prog_data
->barycentric_interp_modes
&
1345 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
) != 0 : 0;
1351 emit_3dstate_streamout(struct anv_graphics_pipeline
*pipeline
,
1352 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
1355 const struct brw_vue_prog_data
*prog_data
=
1356 anv_pipeline_get_last_vue_prog_data(pipeline
);
1357 const struct brw_vue_map
*vue_map
= &prog_data
->vue_map
;
1359 nir_xfb_info
*xfb_info
;
1360 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1361 xfb_info
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->xfb_info
;
1362 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1363 xfb_info
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->xfb_info
;
1365 xfb_info
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->xfb_info
;
1368 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_STREAMOUT
), so
) {
1369 so
.RenderingDisable
= rs_info
->rasterizerDiscardEnable
;
1373 so
.SOFunctionEnable
= true;
1374 so
.SOStatisticsEnable
= true;
1376 const VkPipelineRasterizationStateStreamCreateInfoEXT
*stream_info
=
1377 vk_find_struct_const(rs_info
, PIPELINE_RASTERIZATION_STATE_STREAM_CREATE_INFO_EXT
);
1378 so
.RenderStreamSelect
= stream_info
?
1379 stream_info
->rasterizationStream
: 0;
1381 so
.Buffer0SurfacePitch
= xfb_info
->buffers
[0].stride
;
1382 so
.Buffer1SurfacePitch
= xfb_info
->buffers
[1].stride
;
1383 so
.Buffer2SurfacePitch
= xfb_info
->buffers
[2].stride
;
1384 so
.Buffer3SurfacePitch
= xfb_info
->buffers
[3].stride
;
1386 int urb_entry_read_offset
= 0;
1387 int urb_entry_read_length
=
1388 (prog_data
->vue_map
.num_slots
+ 1) / 2 - urb_entry_read_offset
;
1390 /* We always read the whole vertex. This could be reduced at some
1391 * point by reading less and offsetting the register index in the
1394 so
.Stream0VertexReadOffset
= urb_entry_read_offset
;
1395 so
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
1396 so
.Stream1VertexReadOffset
= urb_entry_read_offset
;
1397 so
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
1398 so
.Stream2VertexReadOffset
= urb_entry_read_offset
;
1399 so
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
1400 so
.Stream3VertexReadOffset
= urb_entry_read_offset
;
1401 so
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
1403 #endif /* GEN_GEN >= 8 */
1408 struct GENX(SO_DECL
) so_decl
[MAX_XFB_STREAMS
][128];
1409 int next_offset
[MAX_XFB_BUFFERS
] = {0, 0, 0, 0};
1410 int decls
[MAX_XFB_STREAMS
] = {0, 0, 0, 0};
1412 memset(so_decl
, 0, sizeof(so_decl
));
1414 for (unsigned i
= 0; i
< xfb_info
->output_count
; i
++) {
1415 const nir_xfb_output_info
*output
= &xfb_info
->outputs
[i
];
1416 unsigned buffer
= output
->buffer
;
1417 unsigned stream
= xfb_info
->buffer_to_stream
[buffer
];
1419 /* Our hardware is unusual in that it requires us to program SO_DECLs
1420 * for fake "hole" components, rather than simply taking the offset
1421 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
1422 * program as many size = 4 holes as we can, then a final hole to
1423 * accommodate the final 1, 2, or 3 remaining.
1425 int hole_dwords
= (output
->offset
- next_offset
[buffer
]) / 4;
1426 while (hole_dwords
> 0) {
1427 so_decl
[stream
][decls
[stream
]++] = (struct GENX(SO_DECL
)) {
1429 .OutputBufferSlot
= buffer
,
1430 .ComponentMask
= (1 << MIN2(hole_dwords
, 4)) - 1,
1435 int varying
= output
->location
;
1436 uint8_t component_mask
= output
->component_mask
;
1437 /* VARYING_SLOT_PSIZ contains three scalar fields packed together:
1438 * - VARYING_SLOT_LAYER in VARYING_SLOT_PSIZ.y
1439 * - VARYING_SLOT_VIEWPORT in VARYING_SLOT_PSIZ.z
1440 * - VARYING_SLOT_PSIZ in VARYING_SLOT_PSIZ.w
1442 if (varying
== VARYING_SLOT_LAYER
) {
1443 varying
= VARYING_SLOT_PSIZ
;
1444 component_mask
= 1 << 1; // SO_DECL_COMPMASK_Y
1445 } else if (varying
== VARYING_SLOT_VIEWPORT
) {
1446 varying
= VARYING_SLOT_PSIZ
;
1447 component_mask
= 1 << 2; // SO_DECL_COMPMASK_Z
1448 } else if (varying
== VARYING_SLOT_PSIZ
) {
1449 component_mask
= 1 << 3; // SO_DECL_COMPMASK_W
1452 next_offset
[buffer
] = output
->offset
+
1453 __builtin_popcount(component_mask
) * 4;
1455 const int slot
= vue_map
->varying_to_slot
[varying
];
1457 /* This can happen if the shader never writes to the varying.
1458 * Insert a hole instead of actual varying data.
1460 so_decl
[stream
][decls
[stream
]++] = (struct GENX(SO_DECL
)) {
1462 .OutputBufferSlot
= buffer
,
1463 .ComponentMask
= component_mask
,
1466 so_decl
[stream
][decls
[stream
]++] = (struct GENX(SO_DECL
)) {
1467 .OutputBufferSlot
= buffer
,
1468 .RegisterIndex
= slot
,
1469 .ComponentMask
= component_mask
,
1475 for (unsigned s
= 0; s
< MAX_XFB_STREAMS
; s
++)
1476 max_decls
= MAX2(max_decls
, decls
[s
]);
1478 uint8_t sbs
[MAX_XFB_STREAMS
] = { };
1479 for (unsigned b
= 0; b
< MAX_XFB_BUFFERS
; b
++) {
1480 if (xfb_info
->buffers_written
& (1 << b
))
1481 sbs
[xfb_info
->buffer_to_stream
[b
]] |= 1 << b
;
1484 uint32_t *dw
= anv_batch_emitn(&pipeline
->base
.batch
, 3 + 2 * max_decls
,
1485 GENX(3DSTATE_SO_DECL_LIST
),
1486 .StreamtoBufferSelects0
= sbs
[0],
1487 .StreamtoBufferSelects1
= sbs
[1],
1488 .StreamtoBufferSelects2
= sbs
[2],
1489 .StreamtoBufferSelects3
= sbs
[3],
1490 .NumEntries0
= decls
[0],
1491 .NumEntries1
= decls
[1],
1492 .NumEntries2
= decls
[2],
1493 .NumEntries3
= decls
[3]);
1495 for (int i
= 0; i
< max_decls
; i
++) {
1496 GENX(SO_DECL_ENTRY_pack
)(NULL
, dw
+ 3 + i
* 2,
1497 &(struct GENX(SO_DECL_ENTRY
)) {
1498 .Stream0Decl
= so_decl
[0][i
],
1499 .Stream1Decl
= so_decl
[1][i
],
1500 .Stream2Decl
= so_decl
[2][i
],
1501 .Stream3Decl
= so_decl
[3][i
],
1505 #endif /* GEN_GEN >= 8 */
1509 get_sampler_count(const struct anv_shader_bin
*bin
)
1511 uint32_t count_by_4
= DIV_ROUND_UP(bin
->bind_map
.sampler_count
, 4);
1513 /* We can potentially have way more than 32 samplers and that's ok.
1514 * However, the 3DSTATE_XS packets only have 3 bits to specify how
1515 * many to pre-fetch and all values above 4 are marked reserved.
1517 return MIN2(count_by_4
, 4);
1521 get_binding_table_entry_count(const struct anv_shader_bin
*bin
)
1523 return DIV_ROUND_UP(bin
->bind_map
.surface_count
, 32);
1526 static struct anv_address
1527 get_scratch_address(struct anv_pipeline
*pipeline
,
1528 gl_shader_stage stage
,
1529 const struct anv_shader_bin
*bin
)
1531 return (struct anv_address
) {
1532 .bo
= anv_scratch_pool_alloc(pipeline
->device
,
1533 &pipeline
->device
->scratch_pool
,
1534 stage
, bin
->prog_data
->total_scratch
),
1540 get_scratch_space(const struct anv_shader_bin
*bin
)
1542 return ffs(bin
->prog_data
->total_scratch
/ 2048);
1546 emit_3dstate_vs(struct anv_graphics_pipeline
*pipeline
)
1548 const struct gen_device_info
*devinfo
= &pipeline
->base
.device
->info
;
1549 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1550 const struct anv_shader_bin
*vs_bin
=
1551 pipeline
->shaders
[MESA_SHADER_VERTEX
];
1553 assert(anv_pipeline_has_stage(pipeline
, MESA_SHADER_VERTEX
));
1555 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_VS
), vs
) {
1557 vs
.StatisticsEnable
= true;
1558 vs
.KernelStartPointer
= vs_bin
->kernel
.offset
;
1560 vs
.SIMD8DispatchEnable
=
1561 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
1564 assert(!vs_prog_data
->base
.base
.use_alt_mode
);
1566 vs
.SingleVertexDispatch
= false;
1568 vs
.VectorMaskEnable
= false;
1570 * Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
1571 * Disable the Sampler state prefetch functionality in the SARB by
1572 * programming 0xB000[30] to '1'.
1574 vs
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(vs_bin
);
1575 vs
.BindingTableEntryCount
= get_binding_table_entry_count(vs_bin
);
1576 vs
.FloatingPointMode
= IEEE754
;
1577 vs
.IllegalOpcodeExceptionEnable
= false;
1578 vs
.SoftwareExceptionEnable
= false;
1579 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1581 if (GEN_GEN
== 9 && devinfo
->gt
== 4 &&
1582 anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
1583 /* On Sky Lake GT4, we have experienced some hangs related to the VS
1584 * cache and tessellation. It is unknown exactly what is happening
1585 * but the Haswell docs for the "VS Reference Count Full Force Miss
1586 * Enable" field of the "Thread Mode" register refer to a HSW bug in
1587 * which the VUE handle reference count would overflow resulting in
1588 * internal reference counting bugs. My (Jason's) best guess is that
1589 * this bug cropped back up on SKL GT4 when we suddenly had more
1590 * threads in play than any previous gen9 hardware.
1592 * What we do know for sure is that setting this bit when
1593 * tessellation shaders are in use fixes a GPU hang in Batman: Arkham
1594 * City when playing with DXVK (https://bugs.freedesktop.org/107280).
1595 * Disabling the vertex cache with tessellation shaders should only
1596 * have a minor performance impact as the tessellation shaders are
1597 * likely generating and processing far more geometry than the vertex
1600 vs
.VertexCacheDisable
= true;
1603 vs
.VertexURBEntryReadLength
= vs_prog_data
->base
.urb_read_length
;
1604 vs
.VertexURBEntryReadOffset
= 0;
1605 vs
.DispatchGRFStartRegisterForURBData
=
1606 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1609 vs
.UserClipDistanceClipTestEnableBitmask
=
1610 vs_prog_data
->base
.clip_distance_mask
;
1611 vs
.UserClipDistanceCullTestEnableBitmask
=
1612 vs_prog_data
->base
.cull_distance_mask
;
1615 vs
.PerThreadScratchSpace
= get_scratch_space(vs_bin
);
1616 vs
.ScratchSpaceBasePointer
=
1617 get_scratch_address(&pipeline
->base
, MESA_SHADER_VERTEX
, vs_bin
);
1622 emit_3dstate_hs_te_ds(struct anv_graphics_pipeline
*pipeline
,
1623 const VkPipelineTessellationStateCreateInfo
*tess_info
)
1625 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
1626 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_HS
), hs
);
1627 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_TE
), te
);
1628 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_DS
), ds
);
1632 const struct gen_device_info
*devinfo
= &pipeline
->base
.device
->info
;
1633 const struct anv_shader_bin
*tcs_bin
=
1634 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1635 const struct anv_shader_bin
*tes_bin
=
1636 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1638 const struct brw_tcs_prog_data
*tcs_prog_data
= get_tcs_prog_data(pipeline
);
1639 const struct brw_tes_prog_data
*tes_prog_data
= get_tes_prog_data(pipeline
);
1641 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_HS
), hs
) {
1643 hs
.StatisticsEnable
= true;
1644 hs
.KernelStartPointer
= tcs_bin
->kernel
.offset
;
1646 hs
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(tcs_bin
);
1647 hs
.BindingTableEntryCount
= get_binding_table_entry_count(tcs_bin
);
1650 /* GEN:BUG:1604578095:
1652 * Hang occurs when the number of max threads is less than 2 times
1653 * the number of instance count. The number of max threads must be
1654 * more than 2 times the number of instance count.
1656 assert((devinfo
->max_tcs_threads
/ 2) > tcs_prog_data
->instances
);
1659 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1660 hs
.IncludeVertexHandles
= true;
1661 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1663 hs
.VertexURBEntryReadLength
= 0;
1664 hs
.VertexURBEntryReadOffset
= 0;
1665 hs
.DispatchGRFStartRegisterForURBData
=
1666 tcs_prog_data
->base
.base
.dispatch_grf_start_reg
& 0x1f;
1668 hs
.DispatchGRFStartRegisterForURBData5
=
1669 tcs_prog_data
->base
.base
.dispatch_grf_start_reg
>> 5;
1673 hs
.PerThreadScratchSpace
= get_scratch_space(tcs_bin
);
1674 hs
.ScratchSpaceBasePointer
=
1675 get_scratch_address(&pipeline
->base
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
1678 /* Patch Count threshold specifies the maximum number of patches that
1679 * will be accumulated before a thread dispatch is forced.
1681 hs
.PatchCountThreshold
= tcs_prog_data
->patch_count_threshold
;
1685 hs
.DispatchMode
= tcs_prog_data
->base
.dispatch_mode
;
1686 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
1690 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
1691 tess_info
? vk_find_struct_const(tess_info
, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
) : NULL
;
1693 VkTessellationDomainOrigin uv_origin
=
1694 domain_origin_state
? domain_origin_state
->domainOrigin
:
1695 VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
;
1697 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_TE
), te
) {
1698 te
.Partitioning
= tes_prog_data
->partitioning
;
1700 if (uv_origin
== VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT
) {
1701 te
.OutputTopology
= tes_prog_data
->output_topology
;
1703 /* When the origin is upper-left, we have to flip the winding order */
1704 if (tes_prog_data
->output_topology
== OUTPUT_TRI_CCW
) {
1705 te
.OutputTopology
= OUTPUT_TRI_CW
;
1706 } else if (tes_prog_data
->output_topology
== OUTPUT_TRI_CW
) {
1707 te
.OutputTopology
= OUTPUT_TRI_CCW
;
1709 te
.OutputTopology
= tes_prog_data
->output_topology
;
1713 te
.TEDomain
= tes_prog_data
->domain
;
1715 te
.MaximumTessellationFactorOdd
= 63.0;
1716 te
.MaximumTessellationFactorNotOdd
= 64.0;
1719 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_DS
), ds
) {
1721 ds
.StatisticsEnable
= true;
1722 ds
.KernelStartPointer
= tes_bin
->kernel
.offset
;
1724 ds
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(tes_bin
);
1725 ds
.BindingTableEntryCount
= get_binding_table_entry_count(tes_bin
);
1726 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
1728 ds
.ComputeWCoordinateEnable
=
1729 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
1731 ds
.PatchURBEntryReadLength
= tes_prog_data
->base
.urb_read_length
;
1732 ds
.PatchURBEntryReadOffset
= 0;
1733 ds
.DispatchGRFStartRegisterForURBData
=
1734 tes_prog_data
->base
.base
.dispatch_grf_start_reg
;
1739 tes_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
?
1740 DISPATCH_MODE_SIMD8_SINGLE_PATCH
:
1741 DISPATCH_MODE_SIMD4X2
;
1743 assert(tes_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
);
1744 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
1747 ds
.UserClipDistanceClipTestEnableBitmask
=
1748 tes_prog_data
->base
.clip_distance_mask
;
1749 ds
.UserClipDistanceCullTestEnableBitmask
=
1750 tes_prog_data
->base
.cull_distance_mask
;
1753 ds
.PerThreadScratchSpace
= get_scratch_space(tes_bin
);
1754 ds
.ScratchSpaceBasePointer
=
1755 get_scratch_address(&pipeline
->base
, MESA_SHADER_TESS_EVAL
, tes_bin
);
1760 emit_3dstate_gs(struct anv_graphics_pipeline
*pipeline
)
1762 const struct gen_device_info
*devinfo
= &pipeline
->base
.device
->info
;
1763 const struct anv_shader_bin
*gs_bin
=
1764 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1766 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
)) {
1767 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_GS
), gs
);
1771 const struct brw_gs_prog_data
*gs_prog_data
= get_gs_prog_data(pipeline
);
1773 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_GS
), gs
) {
1775 gs
.StatisticsEnable
= true;
1776 gs
.KernelStartPointer
= gs_bin
->kernel
.offset
;
1777 gs
.DispatchMode
= gs_prog_data
->base
.dispatch_mode
;
1779 gs
.SingleProgramFlow
= false;
1780 gs
.VectorMaskEnable
= false;
1782 gs
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(gs_bin
);
1783 gs
.BindingTableEntryCount
= get_binding_table_entry_count(gs_bin
);
1784 gs
.IncludeVertexHandles
= gs_prog_data
->base
.include_vue_handles
;
1785 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
1788 /* Broadwell is weird. It needs us to divide by 2. */
1789 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
/ 2 - 1;
1791 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
1794 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
1795 gs
.OutputTopology
= gs_prog_data
->output_topology
;
1796 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1797 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
1798 gs
.ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
;
1799 gs
.InstanceControl
= MAX2(gs_prog_data
->invocations
, 1) - 1;
1800 gs
.ReorderMode
= TRAILING
;
1803 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
1804 gs
.StaticOutput
= gs_prog_data
->static_vertex_count
>= 0;
1805 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
>= 0 ?
1806 gs_prog_data
->static_vertex_count
: 0;
1809 gs
.VertexURBEntryReadOffset
= 0;
1810 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1811 gs
.DispatchGRFStartRegisterForURBData
=
1812 gs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1815 gs
.UserClipDistanceClipTestEnableBitmask
=
1816 gs_prog_data
->base
.clip_distance_mask
;
1817 gs
.UserClipDistanceCullTestEnableBitmask
=
1818 gs_prog_data
->base
.cull_distance_mask
;
1821 gs
.PerThreadScratchSpace
= get_scratch_space(gs_bin
);
1822 gs
.ScratchSpaceBasePointer
=
1823 get_scratch_address(&pipeline
->base
, MESA_SHADER_GEOMETRY
, gs_bin
);
1828 has_color_buffer_write_enabled(const struct anv_graphics_pipeline
*pipeline
,
1829 const VkPipelineColorBlendStateCreateInfo
*blend
)
1831 const struct anv_shader_bin
*shader_bin
=
1832 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1836 const struct anv_pipeline_bind_map
*bind_map
= &shader_bin
->bind_map
;
1837 for (int i
= 0; i
< bind_map
->surface_count
; i
++) {
1838 struct anv_pipeline_binding
*binding
= &bind_map
->surface_to_descriptor
[i
];
1840 if (binding
->set
!= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
1843 if (binding
->index
== UINT32_MAX
)
1846 if (blend
&& blend
->pAttachments
[binding
->index
].colorWriteMask
!= 0)
1854 emit_3dstate_wm(struct anv_graphics_pipeline
*pipeline
, struct anv_subpass
*subpass
,
1855 const VkPipelineInputAssemblyStateCreateInfo
*ia
,
1856 const VkPipelineRasterizationStateCreateInfo
*raster
,
1857 const VkPipelineColorBlendStateCreateInfo
*blend
,
1858 const VkPipelineMultisampleStateCreateInfo
*multisample
,
1859 const VkPipelineRasterizationLineStateCreateInfoEXT
*line
)
1861 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1863 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_WM
), wm
) {
1864 wm
.StatisticsEnable
= true;
1865 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1866 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1867 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1869 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1870 if (wm_prog_data
->early_fragment_tests
) {
1871 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1872 } else if (wm_prog_data
->has_side_effects
) {
1873 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1875 wm
.EarlyDepthStencilControl
= EDSC_NORMAL
;
1879 /* Gen8 hardware tries to compute ThreadDispatchEnable for us but
1880 * doesn't take into account KillPixels when no depth or stencil
1881 * writes are enabled. In order for occlusion queries to work
1882 * correctly with no attachments, we need to force-enable PS thread
1885 * The BDW docs are pretty clear that that this bit isn't validated
1886 * and probably shouldn't be used in production:
1888 * "This must always be set to Normal. This field should not be
1889 * tested for functional validation."
1891 * Unfortunately, however, the other mechanism we have for doing this
1892 * is 3DSTATE_PS_EXTRA::PixelShaderHasUAV which causes hangs on BDW.
1893 * Given two bad options, we choose the one which works.
1895 if ((wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
) &&
1896 !has_color_buffer_write_enabled(pipeline
, blend
))
1897 wm
.ForceThreadDispatchEnable
= ForceON
;
1900 wm
.BarycentricInterpolationMode
=
1901 wm_prog_data
->barycentric_interp_modes
;
1904 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1905 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1906 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1907 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1909 /* If the subpass has a depth or stencil self-dependency, then we
1910 * need to force the hardware to do the depth/stencil write *after*
1911 * fragment shader execution. Otherwise, the writes may hit memory
1912 * before we get around to fetching from the input attachment and we
1913 * may get the depth or stencil value from the current draw rather
1914 * than the previous one.
1916 wm
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
1917 wm_prog_data
->uses_kill
;
1919 if (wm
.PixelShaderComputedDepthMode
!= PSCDEPTH_OFF
||
1920 wm_prog_data
->has_side_effects
||
1921 wm
.PixelShaderKillsPixel
||
1922 has_color_buffer_write_enabled(pipeline
, blend
))
1923 wm
.ThreadDispatchEnable
= true;
1925 if (multisample
&& multisample
->rasterizationSamples
> 1) {
1926 if (wm_prog_data
->persample_dispatch
) {
1927 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1929 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1932 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1934 wm
.MultisampleRasterizationMode
=
1935 gen7_ms_rast_mode(pipeline
, ia
, raster
, multisample
);
1938 wm
.LineStippleEnable
= line
&& line
->stippledLineEnable
;
1944 emit_3dstate_ps(struct anv_graphics_pipeline
*pipeline
,
1945 const VkPipelineColorBlendStateCreateInfo
*blend
,
1946 const VkPipelineMultisampleStateCreateInfo
*multisample
)
1948 UNUSED
const struct gen_device_info
*devinfo
= &pipeline
->base
.device
->info
;
1949 const struct anv_shader_bin
*fs_bin
=
1950 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1952 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1953 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PS
), ps
) {
1955 /* Even if no fragments are ever dispatched, gen7 hardware hangs if
1956 * we don't at least set the maximum number of threads.
1958 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1964 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1967 /* The hardware wedges if you have this bit set but don't turn on any dual
1968 * source blend factors.
1970 bool dual_src_blend
= false;
1971 if (wm_prog_data
->dual_src_blend
&& blend
) {
1972 for (uint32_t i
= 0; i
< blend
->attachmentCount
; i
++) {
1973 const VkPipelineColorBlendAttachmentState
*bstate
=
1974 &blend
->pAttachments
[i
];
1976 if (bstate
->blendEnable
&&
1977 (is_dual_src_blend_factor(bstate
->srcColorBlendFactor
) ||
1978 is_dual_src_blend_factor(bstate
->dstColorBlendFactor
) ||
1979 is_dual_src_blend_factor(bstate
->srcAlphaBlendFactor
) ||
1980 is_dual_src_blend_factor(bstate
->dstAlphaBlendFactor
))) {
1981 dual_src_blend
= true;
1988 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PS
), ps
) {
1989 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1990 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1991 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1993 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
1995 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
1996 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
1998 * Since 16x MSAA is first introduced on SKL, we don't need to apply
1999 * the workaround on any older hardware.
2001 if (GEN_GEN
>= 9 && !wm_prog_data
->persample_dispatch
&&
2002 multisample
&& multisample
->rasterizationSamples
== 16) {
2003 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
2004 ps
._32PixelDispatchEnable
= false;
2007 ps
.KernelStartPointer0
= fs_bin
->kernel
.offset
+
2008 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
2009 ps
.KernelStartPointer1
= fs_bin
->kernel
.offset
+
2010 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
2011 ps
.KernelStartPointer2
= fs_bin
->kernel
.offset
+
2012 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
2014 ps
.SingleProgramFlow
= false;
2015 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
2017 ps
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(fs_bin
);
2018 ps
.BindingTableEntryCount
= get_binding_table_entry_count(fs_bin
);
2019 ps
.PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0 ||
2020 wm_prog_data
->base
.ubo_ranges
[0].length
;
2021 ps
.PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
2022 POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
2024 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
2025 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
2026 ps
.DualSourceBlendEnable
= dual_src_blend
;
2030 /* Haswell requires the sample mask to be set in this packet as well
2031 * as in 3DSTATE_SAMPLE_MASK; the values should match.
2033 ps
.SampleMask
= 0xff;
2037 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
2039 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
2041 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
2044 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
2045 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
2046 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
2047 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
2048 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
2049 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
2051 ps
.PerThreadScratchSpace
= get_scratch_space(fs_bin
);
2052 ps
.ScratchSpaceBasePointer
=
2053 get_scratch_address(&pipeline
->base
, MESA_SHADER_FRAGMENT
, fs_bin
);
2059 emit_3dstate_ps_extra(struct anv_graphics_pipeline
*pipeline
,
2060 struct anv_subpass
*subpass
)
2062 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
2064 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
2065 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PS_EXTRA
), ps
);
2069 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PS_EXTRA
), ps
) {
2070 ps
.PixelShaderValid
= true;
2071 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
2072 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
2073 ps
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
2074 ps
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
2075 ps
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
2076 ps
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
2078 /* If the subpass has a depth or stencil self-dependency, then we need
2079 * to force the hardware to do the depth/stencil write *after* fragment
2080 * shader execution. Otherwise, the writes may hit memory before we get
2081 * around to fetching from the input attachment and we may get the depth
2082 * or stencil value from the current draw rather than the previous one.
2084 ps
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
2085 wm_prog_data
->uses_kill
;
2088 ps
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
2089 ps
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
2091 ps
.InputCoverageMaskState
= ICMS_NONE
;
2092 if (wm_prog_data
->uses_sample_mask
) {
2093 if (wm_prog_data
->post_depth_coverage
)
2094 ps
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
2096 ps
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
2099 ps
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
2105 emit_3dstate_vf_topology(struct anv_graphics_pipeline
*pipeline
)
2107 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_VF_TOPOLOGY
), vft
) {
2108 vft
.PrimitiveTopologyType
= pipeline
->topology
;
2114 emit_3dstate_vf_statistics(struct anv_graphics_pipeline
*pipeline
)
2116 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_VF_STATISTICS
), vfs
) {
2117 vfs
.StatisticsEnable
= true;
2122 compute_kill_pixel(struct anv_graphics_pipeline
*pipeline
,
2123 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
2124 const struct anv_subpass
*subpass
)
2126 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
2127 pipeline
->kill_pixel
= false;
2131 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
2133 /* This computes the KillPixel portion of the computation for whether or
2134 * not we want to enable the PMA fix on gen8 or gen9. It's given by this
2135 * chunk of the giant formula:
2137 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
2138 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
2139 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
2140 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
2141 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
2143 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false and so is
2144 * 3DSTATE_PS_BLEND::AlphaTestEnable since Vulkan doesn't have a concept
2147 pipeline
->kill_pixel
=
2148 subpass
->has_ds_self_dep
|| wm_prog_data
->uses_kill
||
2149 wm_prog_data
->uses_omask
||
2150 (ms_info
&& ms_info
->alphaToCoverageEnable
);
2155 emit_3dstate_primitive_replication(struct anv_graphics_pipeline
*pipeline
)
2157 if (!pipeline
->use_primitive_replication
) {
2158 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PRIMITIVE_REPLICATION
), pr
);
2162 uint32_t view_mask
= pipeline
->subpass
->view_mask
;
2163 int view_count
= util_bitcount(view_mask
);
2164 assert(view_count
> 1 && view_count
<= MAX_VIEWS_FOR_PRIMITIVE_REPLICATION
);
2166 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PRIMITIVE_REPLICATION
), pr
) {
2167 pr
.ReplicaMask
= (1 << view_count
) - 1;
2168 pr
.ReplicationCount
= view_count
- 1;
2170 int i
= 0, view_index
;
2171 for_each_bit(view_index
, view_mask
) {
2172 pr
.RTAIOffset
[i
] = view_index
;
2180 genX(graphics_pipeline_create
)(
2182 struct anv_pipeline_cache
* cache
,
2183 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
2184 const VkAllocationCallbacks
* pAllocator
,
2185 VkPipeline
* pPipeline
)
2187 ANV_FROM_HANDLE(anv_device
, device
, _device
);
2188 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
2189 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
2190 struct anv_graphics_pipeline
*pipeline
;
2193 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
2195 /* Use the default pipeline cache if none is specified */
2196 if (cache
== NULL
&& device
->physical
->instance
->pipeline_cache_enabled
)
2197 cache
= &device
->default_pipeline_cache
;
2199 pipeline
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
2200 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2201 if (pipeline
== NULL
)
2202 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2204 result
= anv_graphics_pipeline_init(pipeline
, device
, cache
,
2205 pCreateInfo
, pAllocator
);
2206 if (result
!= VK_SUCCESS
) {
2207 vk_free2(&device
->vk
.alloc
, pAllocator
, pipeline
);
2208 if (result
== VK_PIPELINE_COMPILE_REQUIRED_EXT
)
2209 *pPipeline
= VK_NULL_HANDLE
;
2213 /* If rasterization is not enabled, various CreateInfo structs must be
2216 const bool raster_enabled
=
2217 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
;
2219 const VkPipelineViewportStateCreateInfo
*vp_info
=
2220 raster_enabled
? pCreateInfo
->pViewportState
: NULL
;
2222 const VkPipelineMultisampleStateCreateInfo
*ms_info
=
2223 raster_enabled
? pCreateInfo
->pMultisampleState
: NULL
;
2225 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
2226 raster_enabled
? pCreateInfo
->pDepthStencilState
: NULL
;
2228 const VkPipelineColorBlendStateCreateInfo
*cb_info
=
2229 raster_enabled
? pCreateInfo
->pColorBlendState
: NULL
;
2231 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_info
=
2232 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
2233 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
2235 /* Information on which states are considered dynamic. */
2236 const VkPipelineDynamicStateCreateInfo
*dyn_info
=
2237 pCreateInfo
->pDynamicState
;
2238 uint32_t dynamic_states
= 0;
2240 for (unsigned i
= 0; i
< dyn_info
->dynamicStateCount
; i
++)
2242 anv_cmd_dirty_bit_for_vk_dynamic_state(dyn_info
->pDynamicStates
[i
]);
2245 enum gen_urb_deref_block_size urb_deref_block_size
;
2246 emit_urb_setup(pipeline
, &urb_deref_block_size
);
2248 assert(pCreateInfo
->pVertexInputState
);
2249 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
);
2250 assert(pCreateInfo
->pRasterizationState
);
2251 emit_rs_state(pipeline
, pCreateInfo
->pInputAssemblyState
,
2252 pCreateInfo
->pRasterizationState
,
2253 ms_info
, line_info
, dynamic_states
, pass
, subpass
,
2254 urb_deref_block_size
);
2255 emit_ms_state(pipeline
, ms_info
);
2256 emit_ds_state(pipeline
, ds_info
, dynamic_states
, pass
, subpass
);
2257 emit_cb_state(pipeline
, cb_info
, ms_info
);
2258 compute_kill_pixel(pipeline
, ms_info
, subpass
);
2260 emit_3dstate_clip(pipeline
,
2261 pCreateInfo
->pInputAssemblyState
,
2263 pCreateInfo
->pRasterizationState
);
2264 emit_3dstate_streamout(pipeline
, pCreateInfo
->pRasterizationState
);
2267 emit_3dstate_primitive_replication(pipeline
);
2271 /* From gen7_vs_state.c */
2274 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2275 * Geometry > Geometry Shader > State:
2277 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2278 * whole fixed function pipeline when the GS enable changes value in
2281 * The hardware architects have clarified that in this context "flush the
2282 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2285 if (!device
->info
.is_haswell
&& !device
->info
.is_baytrail
)
2286 gen7_emit_vs_workaround_flush(brw
);
2289 emit_3dstate_vs(pipeline
);
2290 emit_3dstate_hs_te_ds(pipeline
, pCreateInfo
->pTessellationState
);
2291 emit_3dstate_gs(pipeline
);
2292 emit_3dstate_sbe(pipeline
);
2293 emit_3dstate_wm(pipeline
, subpass
,
2294 pCreateInfo
->pInputAssemblyState
,
2295 pCreateInfo
->pRasterizationState
,
2296 cb_info
, ms_info
, line_info
);
2297 emit_3dstate_ps(pipeline
, cb_info
, ms_info
);
2299 emit_3dstate_ps_extra(pipeline
, subpass
);
2301 if (!(dynamic_states
& ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY
))
2302 emit_3dstate_vf_topology(pipeline
);
2304 emit_3dstate_vf_statistics(pipeline
);
2306 *pPipeline
= anv_pipeline_to_handle(&pipeline
->base
);
2308 return pipeline
->base
.batch
.status
;
2312 emit_media_cs_state(struct anv_compute_pipeline
*pipeline
,
2313 const struct anv_device
*device
)
2315 const struct brw_cs_prog_data
*cs_prog_data
= get_cs_prog_data(pipeline
);
2317 anv_pipeline_setup_l3_config(&pipeline
->base
, cs_prog_data
->base
.total_shared
> 0);
2319 const struct anv_cs_parameters cs_params
= anv_cs_parameters(pipeline
);
2321 pipeline
->cs_right_mask
= brw_cs_right_mask(cs_params
.group_size
, cs_params
.simd_size
);
2323 const uint32_t vfe_curbe_allocation
=
2324 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_params
.threads
+
2325 cs_prog_data
->push
.cross_thread
.regs
, 2);
2327 const uint32_t subslices
= MAX2(device
->physical
->subslice_total
, 1);
2329 const struct anv_shader_bin
*cs_bin
= pipeline
->cs
;
2330 const struct gen_device_info
*devinfo
= &device
->info
;
2332 anv_batch_emit(&pipeline
->base
.batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
2336 vfe
.GPGPUMode
= true;
2338 vfe
.MaximumNumberofThreads
=
2339 devinfo
->max_cs_threads
* subslices
- 1;
2340 vfe
.NumberofURBEntries
= GEN_GEN
<= 7 ? 0 : 2;
2342 vfe
.ResetGatewayTimer
= true;
2345 vfe
.BypassGatewayControl
= true;
2347 vfe
.URBEntryAllocationSize
= GEN_GEN
<= 7 ? 0 : 2;
2348 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
2350 if (cs_bin
->prog_data
->total_scratch
) {
2352 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
2353 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
2355 vfe
.PerThreadScratchSpace
=
2356 ffs(cs_bin
->prog_data
->total_scratch
) - 11;
2357 } else if (GEN_IS_HASWELL
) {
2358 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
2359 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
2361 vfe
.PerThreadScratchSpace
=
2362 ffs(cs_bin
->prog_data
->total_scratch
) - 12;
2364 /* IVB and BYT use the range [0, 11] to mean [1kB, 12kB]
2365 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
2367 vfe
.PerThreadScratchSpace
=
2368 cs_bin
->prog_data
->total_scratch
/ 1024 - 1;
2370 vfe
.ScratchSpaceBasePointer
=
2371 get_scratch_address(&pipeline
->base
, MESA_SHADER_COMPUTE
, cs_bin
);
2375 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2376 .KernelStartPointer
=
2377 cs_bin
->kernel
.offset
+
2378 brw_cs_prog_data_prog_offset(cs_prog_data
, cs_params
.simd_size
),
2381 .SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(cs_bin
),
2382 /* We add 1 because the CS indirect parameters buffer isn't accounted
2383 * for in bind_map.surface_count.
2385 .BindingTableEntryCount
= 1 + MIN2(cs_bin
->bind_map
.surface_count
, 30),
2386 .BarrierEnable
= cs_prog_data
->uses_barrier
,
2387 .SharedLocalMemorySize
=
2388 encode_slm_size(GEN_GEN
, cs_prog_data
->base
.total_shared
),
2391 .ConstantURBEntryReadOffset
= 0,
2393 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
2394 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2395 .CrossThreadConstantDataReadLength
=
2396 cs_prog_data
->push
.cross_thread
.regs
,
2399 /* TODO: Check if we are missing workarounds and enable mid-thread
2402 * We still have issues with mid-thread preemption (it was already
2403 * disabled by the kernel on gen11, due to missing workarounds). It's
2404 * possible that we are just missing some workarounds, and could enable
2405 * it later, but for now let's disable it to fix a GPU in compute in Car
2406 * Chase (and possibly more).
2408 .ThreadPreemptionDisable
= true,
2411 .NumberofThreadsinGPGPUThreadGroup
= cs_params
.threads
,
2413 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
,
2414 pipeline
->interface_descriptor_data
,
2419 compute_pipeline_create(
2421 struct anv_pipeline_cache
* cache
,
2422 const VkComputePipelineCreateInfo
* pCreateInfo
,
2423 const VkAllocationCallbacks
* pAllocator
,
2424 VkPipeline
* pPipeline
)
2426 ANV_FROM_HANDLE(anv_device
, device
, _device
);
2427 struct anv_compute_pipeline
*pipeline
;
2430 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
);
2432 /* Use the default pipeline cache if none is specified */
2433 if (cache
== NULL
&& device
->physical
->instance
->pipeline_cache_enabled
)
2434 cache
= &device
->default_pipeline_cache
;
2436 pipeline
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
2437 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2438 if (pipeline
== NULL
)
2439 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2441 result
= anv_pipeline_init(&pipeline
->base
, device
,
2442 ANV_PIPELINE_COMPUTE
, pCreateInfo
->flags
,
2444 if (result
!= VK_SUCCESS
) {
2445 vk_free2(&device
->vk
.alloc
, pAllocator
, pipeline
);
2449 anv_batch_set_storage(&pipeline
->base
.batch
, ANV_NULL_ADDRESS
,
2450 pipeline
->batch_data
, sizeof(pipeline
->batch_data
));
2452 pipeline
->cs
= NULL
;
2454 assert(pCreateInfo
->stage
.stage
== VK_SHADER_STAGE_COMPUTE_BIT
);
2455 ANV_FROM_HANDLE(anv_shader_module
, module
, pCreateInfo
->stage
.module
);
2456 result
= anv_pipeline_compile_cs(pipeline
, cache
, pCreateInfo
, module
,
2457 pCreateInfo
->stage
.pName
,
2458 pCreateInfo
->stage
.pSpecializationInfo
);
2459 if (result
!= VK_SUCCESS
) {
2460 anv_pipeline_finish(&pipeline
->base
, device
, pAllocator
);
2461 vk_free2(&device
->vk
.alloc
, pAllocator
, pipeline
);
2462 if (result
== VK_PIPELINE_COMPILE_REQUIRED_EXT
)
2463 *pPipeline
= VK_NULL_HANDLE
;
2467 emit_media_cs_state(pipeline
, device
);
2469 *pPipeline
= anv_pipeline_to_handle(&pipeline
->base
);
2471 return pipeline
->base
.batch
.status
;
2474 VkResult
genX(CreateGraphicsPipelines
)(
2476 VkPipelineCache pipelineCache
,
2478 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
2479 const VkAllocationCallbacks
* pAllocator
,
2480 VkPipeline
* pPipelines
)
2482 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
2484 VkResult result
= VK_SUCCESS
;
2487 for (i
= 0; i
< count
; i
++) {
2488 VkResult res
= genX(graphics_pipeline_create
)(_device
,
2491 pAllocator
, &pPipelines
[i
]);
2493 if (res
== VK_SUCCESS
)
2496 /* Bail out on the first error != VK_PIPELINE_COMPILE_REQUIRED_EX as it
2497 * is not obvious what error should be report upon 2 different failures.
2500 if (res
!= VK_PIPELINE_COMPILE_REQUIRED_EXT
)
2503 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
2507 for (; i
< count
; i
++)
2508 pPipelines
[i
] = VK_NULL_HANDLE
;
2513 VkResult
genX(CreateComputePipelines
)(
2515 VkPipelineCache pipelineCache
,
2517 const VkComputePipelineCreateInfo
* pCreateInfos
,
2518 const VkAllocationCallbacks
* pAllocator
,
2519 VkPipeline
* pPipelines
)
2521 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
2523 VkResult result
= VK_SUCCESS
;
2526 for (i
= 0; i
< count
; i
++) {
2527 VkResult res
= compute_pipeline_create(_device
, pipeline_cache
,
2529 pAllocator
, &pPipelines
[i
]);
2531 if (res
== VK_SUCCESS
)
2534 /* Bail out on the first error != VK_PIPELINE_COMPILE_REQUIRED_EX as it
2535 * is not obvious what error should be report upon 2 different failures.
2538 if (res
!= VK_PIPELINE_COMPILE_REQUIRED_EXT
)
2541 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
2545 for (; i
< count
; i
++)
2546 pPipelines
[i
] = VK_NULL_HANDLE
;