2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
26 #include "genxml/gen_macros.h"
27 #include "genxml/genX_pack.h"
29 #include "common/gen_l3_config.h"
30 #include "common/gen_sample_positions.h"
31 #include "nir/nir_xfb_info.h"
33 #include "vk_format_info.h"
36 vertex_element_comp_control(enum isl_format format
, unsigned comp
)
40 case 0: bits
= isl_format_layouts
[format
].channels
.r
.bits
; break;
41 case 1: bits
= isl_format_layouts
[format
].channels
.g
.bits
; break;
42 case 2: bits
= isl_format_layouts
[format
].channels
.b
.bits
; break;
43 case 3: bits
= isl_format_layouts
[format
].channels
.a
.bits
; break;
44 default: unreachable("Invalid component");
48 * Take in account hardware restrictions when dealing with 64-bit floats.
50 * From Broadwell spec, command reference structures, page 586:
51 * "When SourceElementFormat is set to one of the *64*_PASSTHRU formats,
52 * 64-bit components are stored * in the URB without any conversion. In
53 * this case, vertex elements must be written as 128 or 256 bits, with
54 * VFCOMP_STORE_0 being used to pad the output as required. E.g., if
55 * R64_PASSTHRU is used to copy a 64-bit Red component into the URB,
56 * Component 1 must be specified as VFCOMP_STORE_0 (with Components 2,3
57 * set to VFCOMP_NOSTORE) in order to output a 128-bit vertex element, or
58 * Components 1-3 must be specified as VFCOMP_STORE_0 in order to output
59 * a 256-bit vertex element. Likewise, use of R64G64B64_PASSTHRU requires
60 * Component 3 to be specified as VFCOMP_STORE_0 in order to output a
61 * 256-bit vertex element."
64 return VFCOMP_STORE_SRC
;
65 } else if (comp
>= 2 &&
66 !isl_format_layouts
[format
].channels
.b
.bits
&&
67 isl_format_layouts
[format
].channels
.r
.type
== ISL_RAW
) {
68 /* When emitting 64-bit attributes, we need to write either 128 or 256
69 * bit chunks, using VFCOMP_NOSTORE when not writing the chunk, and
70 * VFCOMP_STORE_0 to pad the written chunk */
71 return VFCOMP_NOSTORE
;
72 } else if (comp
< 3 ||
73 isl_format_layouts
[format
].channels
.r
.type
== ISL_RAW
) {
74 /* Note we need to pad with value 0, not 1, due hardware restrictions
75 * (see comment above) */
76 return VFCOMP_STORE_0
;
77 } else if (isl_format_layouts
[format
].channels
.r
.type
== ISL_UINT
||
78 isl_format_layouts
[format
].channels
.r
.type
== ISL_SINT
) {
80 return VFCOMP_STORE_1_INT
;
83 return VFCOMP_STORE_1_FP
;
88 emit_vertex_input(struct anv_graphics_pipeline
*pipeline
,
89 const VkPipelineVertexInputStateCreateInfo
*info
)
91 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
93 /* Pull inputs_read out of the VS prog data */
94 const uint64_t inputs_read
= vs_prog_data
->inputs_read
;
95 const uint64_t double_inputs_read
=
96 vs_prog_data
->double_inputs_read
& inputs_read
;
97 assert((inputs_read
& ((1 << VERT_ATTRIB_GENERIC0
) - 1)) == 0);
98 const uint32_t elements
= inputs_read
>> VERT_ATTRIB_GENERIC0
;
99 const uint32_t elements_double
= double_inputs_read
>> VERT_ATTRIB_GENERIC0
;
100 const bool needs_svgs_elem
= vs_prog_data
->uses_vertexid
||
101 vs_prog_data
->uses_instanceid
||
102 vs_prog_data
->uses_firstvertex
||
103 vs_prog_data
->uses_baseinstance
;
105 uint32_t elem_count
= __builtin_popcount(elements
) -
106 __builtin_popcount(elements_double
) / 2;
108 const uint32_t total_elems
=
109 MAX2(1, elem_count
+ needs_svgs_elem
+ vs_prog_data
->uses_drawid
);
113 const uint32_t num_dwords
= 1 + total_elems
* 2;
114 p
= anv_batch_emitn(&pipeline
->base
.batch
, num_dwords
,
115 GENX(3DSTATE_VERTEX_ELEMENTS
));
119 for (uint32_t i
= 0; i
< total_elems
; i
++) {
120 /* The SKL docs for VERTEX_ELEMENT_STATE say:
122 * "All elements must be valid from Element[0] to the last valid
123 * element. (I.e. if Element[2] is valid then Element[1] and
124 * Element[0] must also be valid)."
126 * The SKL docs for 3D_Vertex_Component_Control say:
128 * "Don't store this component. (Not valid for Component 0, but can
129 * be used for Component 1-3)."
131 * So we can't just leave a vertex element blank and hope for the best.
132 * We have to tell the VF hardware to put something in it; so we just
133 * store a bunch of zero.
135 * TODO: Compact vertex elements so we never end up with holes.
137 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
139 .Component0Control
= VFCOMP_STORE_0
,
140 .Component1Control
= VFCOMP_STORE_0
,
141 .Component2Control
= VFCOMP_STORE_0
,
142 .Component3Control
= VFCOMP_STORE_0
,
144 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + i
* 2], &element
);
147 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
148 const VkVertexInputAttributeDescription
*desc
=
149 &info
->pVertexAttributeDescriptions
[i
];
150 enum isl_format format
= anv_get_isl_format(&pipeline
->base
.device
->info
,
152 VK_IMAGE_ASPECT_COLOR_BIT
,
153 VK_IMAGE_TILING_LINEAR
);
155 assert(desc
->binding
< MAX_VBS
);
157 if ((elements
& (1 << desc
->location
)) == 0)
158 continue; /* Binding unused */
161 __builtin_popcount(elements
& ((1 << desc
->location
) - 1)) -
162 DIV_ROUND_UP(__builtin_popcount(elements_double
&
163 ((1 << desc
->location
) -1)), 2);
165 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
166 .VertexBufferIndex
= desc
->binding
,
168 .SourceElementFormat
= format
,
169 .EdgeFlagEnable
= false,
170 .SourceElementOffset
= desc
->offset
,
171 .Component0Control
= vertex_element_comp_control(format
, 0),
172 .Component1Control
= vertex_element_comp_control(format
, 1),
173 .Component2Control
= vertex_element_comp_control(format
, 2),
174 .Component3Control
= vertex_element_comp_control(format
, 3),
176 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + slot
* 2], &element
);
179 /* On Broadwell and later, we have a separate VF_INSTANCING packet
180 * that controls instancing. On Haswell and prior, that's part of
181 * VERTEX_BUFFER_STATE which we emit later.
183 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
184 vfi
.InstancingEnable
= pipeline
->vb
[desc
->binding
].instanced
;
185 vfi
.VertexElementIndex
= slot
;
186 vfi
.InstanceDataStepRate
=
187 pipeline
->vb
[desc
->binding
].instance_divisor
;
192 const uint32_t id_slot
= elem_count
;
193 if (needs_svgs_elem
) {
194 /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
195 * "Within a VERTEX_ELEMENT_STATE structure, if a Component
196 * Control field is set to something other than VFCOMP_STORE_SRC,
197 * no higher-numbered Component Control fields may be set to
200 * This means, that if we have BaseInstance, we need BaseVertex as
201 * well. Just do all or nothing.
203 uint32_t base_ctrl
= (vs_prog_data
->uses_firstvertex
||
204 vs_prog_data
->uses_baseinstance
) ?
205 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
207 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
208 .VertexBufferIndex
= ANV_SVGS_VB_INDEX
,
210 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
211 .Component0Control
= base_ctrl
,
212 .Component1Control
= base_ctrl
,
214 .Component2Control
= VFCOMP_STORE_0
,
215 .Component3Control
= VFCOMP_STORE_0
,
217 .Component2Control
= VFCOMP_STORE_VID
,
218 .Component3Control
= VFCOMP_STORE_IID
,
221 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + id_slot
* 2], &element
);
225 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
226 sgvs
.VertexIDEnable
= vs_prog_data
->uses_vertexid
;
227 sgvs
.VertexIDComponentNumber
= 2;
228 sgvs
.VertexIDElementOffset
= id_slot
;
229 sgvs
.InstanceIDEnable
= vs_prog_data
->uses_instanceid
;
230 sgvs
.InstanceIDComponentNumber
= 3;
231 sgvs
.InstanceIDElementOffset
= id_slot
;
235 const uint32_t drawid_slot
= elem_count
+ needs_svgs_elem
;
236 if (vs_prog_data
->uses_drawid
) {
237 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
238 .VertexBufferIndex
= ANV_DRAWID_VB_INDEX
,
240 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
241 .Component0Control
= VFCOMP_STORE_SRC
,
242 .Component1Control
= VFCOMP_STORE_0
,
243 .Component2Control
= VFCOMP_STORE_0
,
244 .Component3Control
= VFCOMP_STORE_0
,
246 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
,
247 &p
[1 + drawid_slot
* 2],
251 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
252 vfi
.VertexElementIndex
= drawid_slot
;
259 genX(emit_urb_setup
)(struct anv_device
*device
, struct anv_batch
*batch
,
260 const struct gen_l3_config
*l3_config
,
261 VkShaderStageFlags active_stages
,
262 const unsigned entry_size
[4],
263 enum gen_urb_deref_block_size
*deref_block_size
)
265 const struct gen_device_info
*devinfo
= &device
->info
;
269 gen_get_urb_config(devinfo
, l3_config
,
271 VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
,
272 active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
,
273 entry_size
, entries
, start
, deref_block_size
);
275 #if GEN_GEN == 7 && !GEN_IS_HASWELL
276 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
278 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
279 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
280 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
281 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
282 * needs to be sent before any combination of VS associated 3DSTATE."
284 anv_batch_emit(batch
, GEN7_PIPE_CONTROL
, pc
) {
285 pc
.DepthStallEnable
= true;
286 pc
.PostSyncOperation
= WriteImmediateData
;
287 pc
.Address
= (struct anv_address
) { device
->workaround_bo
, 0 };
291 for (int i
= 0; i
<= MESA_SHADER_GEOMETRY
; i
++) {
292 anv_batch_emit(batch
, GENX(3DSTATE_URB_VS
), urb
) {
293 urb
._3DCommandSubOpcode
+= i
;
294 urb
.VSURBStartingAddress
= start
[i
];
295 urb
.VSURBEntryAllocationSize
= entry_size
[i
] - 1;
296 urb
.VSNumberofURBEntries
= entries
[i
];
302 emit_urb_setup(struct anv_graphics_pipeline
*pipeline
,
303 enum gen_urb_deref_block_size
*deref_block_size
)
305 unsigned entry_size
[4];
306 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
307 const struct brw_vue_prog_data
*prog_data
=
308 !anv_pipeline_has_stage(pipeline
, i
) ? NULL
:
309 (const struct brw_vue_prog_data
*) pipeline
->shaders
[i
]->prog_data
;
311 entry_size
[i
] = prog_data
? prog_data
->urb_entry_size
: 1;
314 genX(emit_urb_setup
)(pipeline
->base
.device
, &pipeline
->base
.batch
,
315 pipeline
->base
.l3_config
,
316 pipeline
->active_stages
, entry_size
,
321 emit_3dstate_sbe(struct anv_graphics_pipeline
*pipeline
)
323 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
325 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
326 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_SBE
), sbe
);
328 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_SBE_SWIZ
), sbe
);
333 const struct brw_vue_map
*fs_input_map
=
334 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
336 struct GENX(3DSTATE_SBE
) sbe
= {
337 GENX(3DSTATE_SBE_header
),
338 .AttributeSwizzleEnable
= true,
339 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
,
340 .NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
,
341 .ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
,
345 for (unsigned i
= 0; i
< 32; i
++)
346 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
350 /* On Broadwell, they broke 3DSTATE_SBE into two packets */
351 struct GENX(3DSTATE_SBE_SWIZ
) swiz
= {
352 GENX(3DSTATE_SBE_SWIZ_header
),
358 int first_slot
= brw_compute_first_urb_slot_required(wm_prog_data
->inputs
,
360 assert(first_slot
% 2 == 0);
361 unsigned urb_entry_read_offset
= first_slot
/ 2;
362 int max_source_attr
= 0;
363 for (uint8_t idx
= 0; idx
< wm_prog_data
->urb_setup_attribs_count
; idx
++) {
364 uint8_t attr
= wm_prog_data
->urb_setup_attribs
[idx
];
365 int input_index
= wm_prog_data
->urb_setup
[attr
];
367 assert(0 <= input_index
);
369 /* gl_Viewport and gl_Layer are stored in the VUE header */
370 if (attr
== VARYING_SLOT_VIEWPORT
|| attr
== VARYING_SLOT_LAYER
) {
374 if (attr
== VARYING_SLOT_PNTC
) {
375 sbe
.PointSpriteTextureCoordinateEnable
= 1 << input_index
;
379 const int slot
= fs_input_map
->varying_to_slot
[attr
];
382 /* This attribute does not exist in the VUE--that means that the
383 * vertex shader did not write to it. It could be that it's a
384 * regular varying read by the fragment shader but not written by
385 * the vertex shader or it's gl_PrimitiveID. In the first case the
386 * value is undefined, in the second it needs to be
389 swiz
.Attribute
[input_index
].ConstantSource
= PRIM_ID
;
390 swiz
.Attribute
[input_index
].ComponentOverrideX
= true;
391 swiz
.Attribute
[input_index
].ComponentOverrideY
= true;
392 swiz
.Attribute
[input_index
].ComponentOverrideZ
= true;
393 swiz
.Attribute
[input_index
].ComponentOverrideW
= true;
397 /* We have to subtract two slots to accout for the URB entry output
398 * read offset in the VS and GS stages.
400 const int source_attr
= slot
- 2 * urb_entry_read_offset
;
401 assert(source_attr
>= 0 && source_attr
< 32);
402 max_source_attr
= MAX2(max_source_attr
, source_attr
);
403 /* The hardware can only do overrides on 16 overrides at a time, and the
404 * other up to 16 have to be lined up so that the input index = the
405 * output index. We'll need to do some tweaking to make sure that's the
408 if (input_index
< 16)
409 swiz
.Attribute
[input_index
].SourceAttribute
= source_attr
;
411 assert(source_attr
== input_index
);
414 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
415 sbe
.VertexURBEntryReadLength
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
417 sbe
.ForceVertexURBEntryReadOffset
= true;
418 sbe
.ForceVertexURBEntryReadLength
= true;
421 uint32_t *dw
= anv_batch_emit_dwords(&pipeline
->base
.batch
,
422 GENX(3DSTATE_SBE_length
));
425 GENX(3DSTATE_SBE_pack
)(&pipeline
->base
.batch
, dw
, &sbe
);
428 dw
= anv_batch_emit_dwords(&pipeline
->base
.batch
, GENX(3DSTATE_SBE_SWIZ_length
));
431 GENX(3DSTATE_SBE_SWIZ_pack
)(&pipeline
->base
.batch
, dw
, &swiz
);
435 static const uint32_t vk_to_gen_cullmode
[] = {
436 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
437 [VK_CULL_MODE_FRONT_BIT
] = CULLMODE_FRONT
,
438 [VK_CULL_MODE_BACK_BIT
] = CULLMODE_BACK
,
439 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
442 static const uint32_t vk_to_gen_fillmode
[] = {
443 [VK_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
444 [VK_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
445 [VK_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
448 static const uint32_t vk_to_gen_front_face
[] = {
449 [VK_FRONT_FACE_COUNTER_CLOCKWISE
] = 1,
450 [VK_FRONT_FACE_CLOCKWISE
] = 0
453 static VkLineRasterizationModeEXT
454 vk_line_rasterization_mode(const VkPipelineRasterizationLineStateCreateInfoEXT
*line_info
,
455 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
457 VkLineRasterizationModeEXT line_mode
=
458 line_info
? line_info
->lineRasterizationMode
:
459 VK_LINE_RASTERIZATION_MODE_DEFAULT_EXT
;
461 if (line_mode
== VK_LINE_RASTERIZATION_MODE_DEFAULT_EXT
) {
462 if (ms_info
&& ms_info
->rasterizationSamples
> 1) {
463 return VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT
;
465 return VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
;
472 /** Returns the final polygon mode for rasterization
474 * This function takes into account polygon mode, primitive topology and the
475 * different shader stages which might generate their own type of primitives.
478 anv_raster_polygon_mode(struct anv_graphics_pipeline
*pipeline
,
479 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
,
480 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
482 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
)) {
483 switch (get_gs_prog_data(pipeline
)->output_topology
) {
484 case _3DPRIM_POINTLIST
:
485 return VK_POLYGON_MODE_POINT
;
487 case _3DPRIM_LINELIST
:
488 case _3DPRIM_LINESTRIP
:
489 case _3DPRIM_LINELOOP
:
490 return VK_POLYGON_MODE_LINE
;
492 case _3DPRIM_TRILIST
:
494 case _3DPRIM_TRISTRIP
:
495 case _3DPRIM_RECTLIST
:
496 case _3DPRIM_QUADLIST
:
497 case _3DPRIM_QUADSTRIP
:
498 case _3DPRIM_POLYGON
:
499 return rs_info
->polygonMode
;
501 unreachable("Unsupported GS output topology");
502 } else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
503 switch (get_tes_prog_data(pipeline
)->output_topology
) {
504 case BRW_TESS_OUTPUT_TOPOLOGY_POINT
:
505 return VK_POLYGON_MODE_POINT
;
507 case BRW_TESS_OUTPUT_TOPOLOGY_LINE
:
508 return VK_POLYGON_MODE_LINE
;
510 case BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
:
511 case BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
:
512 return rs_info
->polygonMode
;
514 unreachable("Unsupported TCS output topology");
516 switch (ia_info
->topology
) {
517 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
518 return VK_POLYGON_MODE_POINT
;
520 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
521 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
522 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
523 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
524 return VK_POLYGON_MODE_LINE
;
526 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
527 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
528 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
529 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
530 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
531 return rs_info
->polygonMode
;
534 unreachable("Unsupported primitive topology");
541 gen7_ms_rast_mode(struct anv_graphics_pipeline
*pipeline
,
542 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
,
543 const VkPipelineRasterizationStateCreateInfo
*rs_info
,
544 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
546 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_info
=
547 vk_find_struct_const(rs_info
->pNext
,
548 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
550 VkPolygonMode raster_mode
=
551 anv_raster_polygon_mode(pipeline
, ia_info
, rs_info
);
552 if (raster_mode
== VK_POLYGON_MODE_LINE
) {
553 switch (vk_line_rasterization_mode(line_info
, ms_info
)) {
554 case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT
:
555 return MSRASTMODE_ON_PATTERN
;
557 case VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
:
558 case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT
:
559 return MSRASTMODE_OFF_PIXEL
;
562 unreachable("Unsupported line rasterization mode");
565 return (ms_info
&& ms_info
->rasterizationSamples
> 1) ?
566 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
572 emit_rs_state(struct anv_graphics_pipeline
*pipeline
,
573 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
,
574 const VkPipelineRasterizationStateCreateInfo
*rs_info
,
575 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
576 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_info
,
577 const struct anv_render_pass
*pass
,
578 const struct anv_subpass
*subpass
,
579 enum gen_urb_deref_block_size urb_deref_block_size
)
581 struct GENX(3DSTATE_SF
) sf
= {
582 GENX(3DSTATE_SF_header
),
585 sf
.ViewportTransformEnable
= true;
586 sf
.StatisticsEnable
= true;
587 sf
.TriangleStripListProvokingVertexSelect
= 0;
588 sf
.LineStripListProvokingVertexSelect
= 0;
589 sf
.TriangleFanProvokingVertexSelect
= 1;
590 sf
.VertexSubPixelPrecisionSelect
= _8Bit
;
591 sf
.AALineDistanceMode
= true;
594 sf
.LineStippleEnable
= line_info
&& line_info
->stippledLineEnable
;
598 sf
.DerefBlockSize
= urb_deref_block_size
;
601 const struct brw_vue_prog_data
*last_vue_prog_data
=
602 anv_pipeline_get_last_vue_prog_data(pipeline
);
604 if (last_vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
605 sf
.PointWidthSource
= Vertex
;
607 sf
.PointWidthSource
= State
;
612 struct GENX(3DSTATE_RASTER
) raster
= {
613 GENX(3DSTATE_RASTER_header
),
619 VkPolygonMode raster_mode
=
620 anv_raster_polygon_mode(pipeline
, ia_info
, rs_info
);
621 VkLineRasterizationModeEXT line_mode
=
622 vk_line_rasterization_mode(line_info
, ms_info
);
624 /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
625 * "Multisample Modes State".
628 if (raster_mode
== VK_POLYGON_MODE_LINE
) {
629 /* Unfortunately, configuring our line rasterization hardware on gen8
630 * and later is rather painful. Instead of giving us bits to tell the
631 * hardware what line mode to use like we had on gen7, we now have an
632 * arcane combination of API Mode and MSAA enable bits which do things
633 * in a table which are expected to magically put the hardware into the
634 * right mode for your API. Sadly, Vulkan isn't any of the APIs the
635 * hardware people thought of so nothing works the way you want it to.
637 * Look at the table titled "Multisample Rasterization Modes" in Vol 7
638 * of the Skylake PRM for more details.
641 case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT
:
642 raster
.APIMode
= DX100
;
643 raster
.DXMultisampleRasterizationEnable
= true;
646 case VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
:
647 case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT
:
648 raster
.APIMode
= DX9OGL
;
649 raster
.DXMultisampleRasterizationEnable
= false;
653 unreachable("Unsupported line rasterization mode");
656 raster
.APIMode
= DX100
;
657 raster
.DXMultisampleRasterizationEnable
= true;
660 /* NOTE: 3DSTATE_RASTER::ForcedSampleCount affects the BDW and SKL PMA fix
661 * computations. If we ever set this bit to a different value, they will
662 * need to be updated accordingly.
664 raster
.ForcedSampleCount
= FSC_NUMRASTSAMPLES_0
;
665 raster
.ForceMultisampling
= false;
667 raster
.MultisampleRasterizationMode
=
668 gen7_ms_rast_mode(pipeline
, ia_info
, rs_info
, ms_info
);
671 if (raster_mode
== VK_POLYGON_MODE_LINE
&&
672 line_mode
== VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT
)
673 raster
.AntialiasingEnable
= true;
675 raster
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
];
676 raster
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
];
677 raster
.FrontFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
678 raster
.BackFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
679 raster
.ScissorRectangleEnable
= true;
682 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
683 raster
.ViewportZFarClipTestEnable
= pipeline
->depth_clip_enable
;
684 raster
.ViewportZNearClipTestEnable
= pipeline
->depth_clip_enable
;
686 raster
.ViewportZClipTestEnable
= pipeline
->depth_clip_enable
;
689 raster
.GlobalDepthOffsetEnableSolid
= rs_info
->depthBiasEnable
;
690 raster
.GlobalDepthOffsetEnableWireframe
= rs_info
->depthBiasEnable
;
691 raster
.GlobalDepthOffsetEnablePoint
= rs_info
->depthBiasEnable
;
694 /* Gen7 requires that we provide the depth format in 3DSTATE_SF so that it
695 * can get the depth offsets correct.
697 if (subpass
->depth_stencil_attachment
) {
699 pass
->attachments
[subpass
->depth_stencil_attachment
->attachment
].format
;
700 assert(vk_format_is_depth_or_stencil(vk_format
));
701 if (vk_format_aspects(vk_format
) & VK_IMAGE_ASPECT_DEPTH_BIT
) {
702 enum isl_format isl_format
=
703 anv_get_isl_format(&pipeline
->base
.device
->info
, vk_format
,
704 VK_IMAGE_ASPECT_DEPTH_BIT
,
705 VK_IMAGE_TILING_OPTIMAL
);
706 sf
.DepthBufferSurfaceFormat
=
707 isl_format_get_depth_format(isl_format
, false);
713 GENX(3DSTATE_SF_pack
)(NULL
, pipeline
->gen8
.sf
, &sf
);
714 GENX(3DSTATE_RASTER_pack
)(NULL
, pipeline
->gen8
.raster
, &raster
);
717 GENX(3DSTATE_SF_pack
)(NULL
, &pipeline
->gen7
.sf
, &sf
);
722 emit_ms_state(struct anv_graphics_pipeline
*pipeline
,
723 const VkPipelineMultisampleStateCreateInfo
*info
)
725 uint32_t samples
= 1;
726 uint32_t log2_samples
= 0;
728 /* From the Vulkan 1.0 spec:
729 * If pSampleMask is NULL, it is treated as if the mask has all bits
730 * enabled, i.e. no coverage is removed from fragments.
732 * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
735 uint32_t sample_mask
= 0xffff;
737 uint32_t sample_mask
= 0xff;
741 samples
= info
->rasterizationSamples
;
742 log2_samples
= __builtin_ffs(samples
) - 1;
745 if (info
&& info
->pSampleMask
)
746 sample_mask
&= info
->pSampleMask
[0];
748 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
749 ms
.NumberofMultisamples
= log2_samples
;
751 ms
.PixelLocation
= CENTER
;
753 /* The PRM says that this bit is valid only for DX9:
755 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
756 * should not have any effect by setting or not setting this bit.
758 ms
.PixelPositionOffsetEnable
= false;
763 GEN_SAMPLE_POS_1X(ms
.Sample
);
766 GEN_SAMPLE_POS_2X(ms
.Sample
);
769 GEN_SAMPLE_POS_4X(ms
.Sample
);
772 GEN_SAMPLE_POS_8X(ms
.Sample
);
780 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
781 sm
.SampleMask
= sample_mask
;
785 static const uint32_t vk_to_gen_logic_op
[] = {
786 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
787 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
788 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
789 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
790 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
791 [VK_LOGIC_OP_NO_OP
] = LOGICOP_NOOP
,
792 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
793 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
794 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
795 [VK_LOGIC_OP_EQUIVALENT
] = LOGICOP_EQUIV
,
796 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
797 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
798 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
799 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
800 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
801 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
804 static const uint32_t vk_to_gen_blend
[] = {
805 [VK_BLEND_FACTOR_ZERO
] = BLENDFACTOR_ZERO
,
806 [VK_BLEND_FACTOR_ONE
] = BLENDFACTOR_ONE
,
807 [VK_BLEND_FACTOR_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
808 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
809 [VK_BLEND_FACTOR_DST_COLOR
] = BLENDFACTOR_DST_COLOR
,
810 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
811 [VK_BLEND_FACTOR_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
812 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
813 [VK_BLEND_FACTOR_DST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
814 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
815 [VK_BLEND_FACTOR_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
816 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
]= BLENDFACTOR_INV_CONST_COLOR
,
817 [VK_BLEND_FACTOR_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
818 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
]= BLENDFACTOR_INV_CONST_ALPHA
,
819 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
820 [VK_BLEND_FACTOR_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
821 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
822 [VK_BLEND_FACTOR_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
823 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
826 static const uint32_t vk_to_gen_blend_op
[] = {
827 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
828 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
829 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
830 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
831 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
834 static const uint32_t vk_to_gen_compare_op
[] = {
835 [VK_COMPARE_OP_NEVER
] = PREFILTEROPNEVER
,
836 [VK_COMPARE_OP_LESS
] = PREFILTEROPLESS
,
837 [VK_COMPARE_OP_EQUAL
] = PREFILTEROPEQUAL
,
838 [VK_COMPARE_OP_LESS_OR_EQUAL
] = PREFILTEROPLEQUAL
,
839 [VK_COMPARE_OP_GREATER
] = PREFILTEROPGREATER
,
840 [VK_COMPARE_OP_NOT_EQUAL
] = PREFILTEROPNOTEQUAL
,
841 [VK_COMPARE_OP_GREATER_OR_EQUAL
] = PREFILTEROPGEQUAL
,
842 [VK_COMPARE_OP_ALWAYS
] = PREFILTEROPALWAYS
,
845 static const uint32_t vk_to_gen_stencil_op
[] = {
846 [VK_STENCIL_OP_KEEP
] = STENCILOP_KEEP
,
847 [VK_STENCIL_OP_ZERO
] = STENCILOP_ZERO
,
848 [VK_STENCIL_OP_REPLACE
] = STENCILOP_REPLACE
,
849 [VK_STENCIL_OP_INCREMENT_AND_CLAMP
] = STENCILOP_INCRSAT
,
850 [VK_STENCIL_OP_DECREMENT_AND_CLAMP
] = STENCILOP_DECRSAT
,
851 [VK_STENCIL_OP_INVERT
] = STENCILOP_INVERT
,
852 [VK_STENCIL_OP_INCREMENT_AND_WRAP
] = STENCILOP_INCR
,
853 [VK_STENCIL_OP_DECREMENT_AND_WRAP
] = STENCILOP_DECR
,
856 /* This function sanitizes the VkStencilOpState by looking at the compare ops
857 * and trying to determine whether or not a given stencil op can ever actually
858 * occur. Stencil ops which can never occur are set to VK_STENCIL_OP_KEEP.
859 * This function returns true if, after sanitation, any of the stencil ops are
860 * set to something other than VK_STENCIL_OP_KEEP.
863 sanitize_stencil_face(VkStencilOpState
*face
,
864 VkCompareOp depthCompareOp
)
866 /* If compareOp is ALWAYS then the stencil test will never fail and failOp
867 * will never happen. Set failOp to KEEP in this case.
869 if (face
->compareOp
== VK_COMPARE_OP_ALWAYS
)
870 face
->failOp
= VK_STENCIL_OP_KEEP
;
872 /* If compareOp is NEVER or depthCompareOp is NEVER then one of the depth
873 * or stencil tests will fail and passOp will never happen.
875 if (face
->compareOp
== VK_COMPARE_OP_NEVER
||
876 depthCompareOp
== VK_COMPARE_OP_NEVER
)
877 face
->passOp
= VK_STENCIL_OP_KEEP
;
879 /* If compareOp is NEVER or depthCompareOp is ALWAYS then either the
880 * stencil test will fail or the depth test will pass. In either case,
881 * depthFailOp will never happen.
883 if (face
->compareOp
== VK_COMPARE_OP_NEVER
||
884 depthCompareOp
== VK_COMPARE_OP_ALWAYS
)
885 face
->depthFailOp
= VK_STENCIL_OP_KEEP
;
887 return face
->failOp
!= VK_STENCIL_OP_KEEP
||
888 face
->depthFailOp
!= VK_STENCIL_OP_KEEP
||
889 face
->passOp
!= VK_STENCIL_OP_KEEP
;
892 /* Intel hardware is fairly sensitive to whether or not depth/stencil writes
893 * are enabled. In the presence of discards, it's fairly easy to get into the
894 * non-promoted case which means a fairly big performance hit. From the Iron
895 * Lake PRM, Vol 2, pt. 1, section 8.4.3.2, "Early Depth Test Cases":
897 * "Non-promoted depth (N) is active whenever the depth test can be done
898 * early but it cannot determine whether or not to write source depth to
899 * the depth buffer, therefore the depth write must be performed post pixel
900 * shader. This includes cases where the pixel shader can kill pixels,
901 * including via sampler chroma key, as well as cases where the alpha test
902 * function is enabled, which kills pixels based on a programmable alpha
903 * test. In this case, even if the depth test fails, the pixel cannot be
904 * killed if a stencil write is indicated. Whether or not the stencil write
905 * happens depends on whether or not the pixel is killed later. In these
906 * cases if stencil test fails and stencil writes are off, the pixels can
907 * also be killed early. If stencil writes are enabled, the pixels must be
908 * treated as Computed depth (described above)."
910 * The same thing as mentioned in the stencil case can happen in the depth
911 * case as well if it thinks it writes depth but, thanks to the depth test
912 * being GL_EQUAL, the write doesn't actually matter. A little extra work
913 * up-front to try and disable depth and stencil writes can make a big
916 * Unfortunately, the way depth and stencil testing is specified, there are
917 * many case where, regardless of depth/stencil writes being enabled, nothing
918 * actually gets written due to some other bit of state being set. This
919 * function attempts to "sanitize" the depth stencil state and disable writes
920 * and sometimes even testing whenever possible.
923 sanitize_ds_state(VkPipelineDepthStencilStateCreateInfo
*state
,
924 bool *stencilWriteEnable
,
925 VkImageAspectFlags ds_aspects
)
927 *stencilWriteEnable
= state
->stencilTestEnable
;
929 /* If the depth test is disabled, we won't be writing anything. Make sure we
930 * treat the test as always passing later on as well.
932 * Also, the Vulkan spec requires that if either depth or stencil is not
933 * present, the pipeline is to act as if the test silently passes. In that
934 * case we won't write either.
936 if (!state
->depthTestEnable
|| !(ds_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
937 state
->depthWriteEnable
= false;
938 state
->depthCompareOp
= VK_COMPARE_OP_ALWAYS
;
941 if (!(ds_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
942 *stencilWriteEnable
= false;
943 state
->front
.compareOp
= VK_COMPARE_OP_ALWAYS
;
944 state
->back
.compareOp
= VK_COMPARE_OP_ALWAYS
;
947 /* If the stencil test is enabled and always fails, then we will never get
948 * to the depth test so we can just disable the depth test entirely.
950 if (state
->stencilTestEnable
&&
951 state
->front
.compareOp
== VK_COMPARE_OP_NEVER
&&
952 state
->back
.compareOp
== VK_COMPARE_OP_NEVER
) {
953 state
->depthTestEnable
= false;
954 state
->depthWriteEnable
= false;
957 /* If depthCompareOp is EQUAL then the value we would be writing to the
958 * depth buffer is the same as the value that's already there so there's no
959 * point in writing it.
961 if (state
->depthCompareOp
== VK_COMPARE_OP_EQUAL
)
962 state
->depthWriteEnable
= false;
964 /* If the stencil ops are such that we don't actually ever modify the
965 * stencil buffer, we should disable writes.
967 if (!sanitize_stencil_face(&state
->front
, state
->depthCompareOp
) &&
968 !sanitize_stencil_face(&state
->back
, state
->depthCompareOp
))
969 *stencilWriteEnable
= false;
971 /* If the depth test always passes and we never write out depth, that's the
972 * same as if the depth test is disabled entirely.
974 if (state
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
&&
975 !state
->depthWriteEnable
)
976 state
->depthTestEnable
= false;
978 /* If the stencil test always passes and we never write out stencil, that's
979 * the same as if the stencil test is disabled entirely.
981 if (state
->front
.compareOp
== VK_COMPARE_OP_ALWAYS
&&
982 state
->back
.compareOp
== VK_COMPARE_OP_ALWAYS
&&
983 !*stencilWriteEnable
)
984 state
->stencilTestEnable
= false;
988 emit_ds_state(struct anv_graphics_pipeline
*pipeline
,
989 const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
,
990 const struct anv_render_pass
*pass
,
991 const struct anv_subpass
*subpass
)
994 # define depth_stencil_dw pipeline->gen7.depth_stencil_state
996 # define depth_stencil_dw pipeline->gen8.wm_depth_stencil
998 # define depth_stencil_dw pipeline->gen9.wm_depth_stencil
1001 if (pCreateInfo
== NULL
) {
1002 /* We're going to OR this together with the dynamic state. We need
1003 * to make sure it's initialized to something useful.
1005 pipeline
->writes_stencil
= false;
1006 pipeline
->stencil_test_enable
= false;
1007 pipeline
->writes_depth
= false;
1008 pipeline
->depth_test_enable
= false;
1009 pipeline
->depth_bounds_test_enable
= false;
1010 memset(depth_stencil_dw
, 0, sizeof(depth_stencil_dw
));
1014 VkImageAspectFlags ds_aspects
= 0;
1015 if (subpass
->depth_stencil_attachment
) {
1016 VkFormat depth_stencil_format
=
1017 pass
->attachments
[subpass
->depth_stencil_attachment
->attachment
].format
;
1018 ds_aspects
= vk_format_aspects(depth_stencil_format
);
1021 VkPipelineDepthStencilStateCreateInfo info
= *pCreateInfo
;
1022 sanitize_ds_state(&info
, &pipeline
->writes_stencil
, ds_aspects
);
1023 pipeline
->stencil_test_enable
= info
.stencilTestEnable
;
1024 pipeline
->writes_depth
= info
.depthWriteEnable
;
1025 pipeline
->depth_test_enable
= info
.depthTestEnable
;
1026 pipeline
->depth_bounds_test_enable
= info
.depthBoundsTestEnable
;
1029 struct GENX(DEPTH_STENCIL_STATE
) depth_stencil
= {
1031 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) depth_stencil
= {
1033 .DepthTestEnable
= info
.depthTestEnable
,
1034 .DepthBufferWriteEnable
= info
.depthWriteEnable
,
1035 .DepthTestFunction
= vk_to_gen_compare_op
[info
.depthCompareOp
],
1036 .DoubleSidedStencilEnable
= true,
1038 .StencilTestEnable
= info
.stencilTestEnable
,
1039 .StencilFailOp
= vk_to_gen_stencil_op
[info
.front
.failOp
],
1040 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
.front
.passOp
],
1041 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
.front
.depthFailOp
],
1042 .StencilTestFunction
= vk_to_gen_compare_op
[info
.front
.compareOp
],
1043 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
.back
.failOp
],
1044 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
.back
.passOp
],
1045 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
.back
.depthFailOp
],
1046 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
.back
.compareOp
],
1050 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
1052 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
1057 is_dual_src_blend_factor(VkBlendFactor factor
)
1059 return factor
== VK_BLEND_FACTOR_SRC1_COLOR
||
1060 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
||
1061 factor
== VK_BLEND_FACTOR_SRC1_ALPHA
||
1062 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
;
1066 emit_cb_state(struct anv_graphics_pipeline
*pipeline
,
1067 const VkPipelineColorBlendStateCreateInfo
*info
,
1068 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
1070 struct anv_device
*device
= pipeline
->base
.device
;
1071 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1073 struct GENX(BLEND_STATE
) blend_state
= {
1075 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
1076 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
1080 uint32_t surface_count
= 0;
1081 struct anv_pipeline_bind_map
*map
;
1082 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1083 map
= &pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->bind_map
;
1084 surface_count
= map
->surface_count
;
1087 const uint32_t num_dwords
= GENX(BLEND_STATE_length
) +
1088 GENX(BLEND_STATE_ENTRY_length
) * surface_count
;
1089 pipeline
->blend_state
=
1090 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
1092 bool has_writeable_rt
= false;
1093 uint32_t *state_pos
= pipeline
->blend_state
.map
;
1094 state_pos
+= GENX(BLEND_STATE_length
);
1096 struct GENX(BLEND_STATE_ENTRY
) bs0
= { 0 };
1098 for (unsigned i
= 0; i
< surface_count
; i
++) {
1099 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[i
];
1101 /* All color attachments are at the beginning of the binding table */
1102 if (binding
->set
!= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
1105 /* We can have at most 8 attachments */
1108 if (info
== NULL
|| binding
->index
>= info
->attachmentCount
) {
1109 /* Default everything to disabled */
1110 struct GENX(BLEND_STATE_ENTRY
) entry
= {
1111 .WriteDisableAlpha
= true,
1112 .WriteDisableRed
= true,
1113 .WriteDisableGreen
= true,
1114 .WriteDisableBlue
= true,
1116 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, state_pos
, &entry
);
1117 state_pos
+= GENX(BLEND_STATE_ENTRY_length
);
1121 const VkPipelineColorBlendAttachmentState
*a
=
1122 &info
->pAttachments
[binding
->index
];
1124 struct GENX(BLEND_STATE_ENTRY
) entry
= {
1126 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
1127 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
1129 .LogicOpEnable
= info
->logicOpEnable
,
1130 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
1131 .ColorBufferBlendEnable
= a
->blendEnable
,
1132 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
1133 .PreBlendColorClampEnable
= true,
1134 .PostBlendColorClampEnable
= true,
1135 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcColorBlendFactor
],
1136 .DestinationBlendFactor
= vk_to_gen_blend
[a
->dstColorBlendFactor
],
1137 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->colorBlendOp
],
1138 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcAlphaBlendFactor
],
1139 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->dstAlphaBlendFactor
],
1140 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->alphaBlendOp
],
1141 .WriteDisableAlpha
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_A_BIT
),
1142 .WriteDisableRed
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_R_BIT
),
1143 .WriteDisableGreen
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_G_BIT
),
1144 .WriteDisableBlue
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_B_BIT
),
1147 if (a
->srcColorBlendFactor
!= a
->srcAlphaBlendFactor
||
1148 a
->dstColorBlendFactor
!= a
->dstAlphaBlendFactor
||
1149 a
->colorBlendOp
!= a
->alphaBlendOp
) {
1151 blend_state
.IndependentAlphaBlendEnable
= true;
1153 entry
.IndependentAlphaBlendEnable
= true;
1157 /* The Dual Source Blending documentation says:
1159 * "If SRC1 is included in a src/dst blend factor and
1160 * a DualSource RT Write message is not used, results
1161 * are UNDEFINED. (This reflects the same restriction in DX APIs,
1162 * where undefined results are produced if “o1” is not written
1163 * by a PS – there are no default values defined)."
1165 * There is no way to gracefully fix this undefined situation
1166 * so we just disable the blending to prevent possible issues.
1168 if (!wm_prog_data
->dual_src_blend
&&
1169 (is_dual_src_blend_factor(a
->srcColorBlendFactor
) ||
1170 is_dual_src_blend_factor(a
->dstColorBlendFactor
) ||
1171 is_dual_src_blend_factor(a
->srcAlphaBlendFactor
) ||
1172 is_dual_src_blend_factor(a
->dstAlphaBlendFactor
))) {
1173 vk_debug_report(&device
->physical
->instance
->debug_report_callbacks
,
1174 VK_DEBUG_REPORT_WARNING_BIT_EXT
,
1175 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT
,
1176 (uint64_t)(uintptr_t)device
,
1178 "Enabled dual-src blend factors without writing both targets "
1179 "in the shader. Disabling blending to avoid GPU hangs.");
1180 entry
.ColorBufferBlendEnable
= false;
1183 if (a
->colorWriteMask
!= 0)
1184 has_writeable_rt
= true;
1186 /* Our hardware applies the blend factor prior to the blend function
1187 * regardless of what function is used. Technically, this means the
1188 * hardware can do MORE than GL or Vulkan specify. However, it also
1189 * means that, for MIN and MAX, we have to stomp the blend factor to
1190 * ONE to make it a no-op.
1192 if (a
->colorBlendOp
== VK_BLEND_OP_MIN
||
1193 a
->colorBlendOp
== VK_BLEND_OP_MAX
) {
1194 entry
.SourceBlendFactor
= BLENDFACTOR_ONE
;
1195 entry
.DestinationBlendFactor
= BLENDFACTOR_ONE
;
1197 if (a
->alphaBlendOp
== VK_BLEND_OP_MIN
||
1198 a
->alphaBlendOp
== VK_BLEND_OP_MAX
) {
1199 entry
.SourceAlphaBlendFactor
= BLENDFACTOR_ONE
;
1200 entry
.DestinationAlphaBlendFactor
= BLENDFACTOR_ONE
;
1202 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, state_pos
, &entry
);
1203 state_pos
+= GENX(BLEND_STATE_ENTRY_length
);
1211 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PS_BLEND
), blend
) {
1212 blend
.AlphaToCoverageEnable
= blend_state
.AlphaToCoverageEnable
;
1213 blend
.HasWriteableRT
= has_writeable_rt
;
1214 blend
.ColorBufferBlendEnable
= bs0
.ColorBufferBlendEnable
;
1215 blend
.SourceAlphaBlendFactor
= bs0
.SourceAlphaBlendFactor
;
1216 blend
.DestinationAlphaBlendFactor
= bs0
.DestinationAlphaBlendFactor
;
1217 blend
.SourceBlendFactor
= bs0
.SourceBlendFactor
;
1218 blend
.DestinationBlendFactor
= bs0
.DestinationBlendFactor
;
1219 blend
.AlphaTestEnable
= false;
1220 blend
.IndependentAlphaBlendEnable
=
1221 blend_state
.IndependentAlphaBlendEnable
;
1224 (void)has_writeable_rt
;
1227 GENX(BLEND_STATE_pack
)(NULL
, pipeline
->blend_state
.map
, &blend_state
);
1229 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), bsp
) {
1230 bsp
.BlendStatePointer
= pipeline
->blend_state
.offset
;
1232 bsp
.BlendStatePointerValid
= true;
1238 emit_3dstate_clip(struct anv_graphics_pipeline
*pipeline
,
1239 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
,
1240 const VkPipelineViewportStateCreateInfo
*vp_info
,
1241 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
1243 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1244 (void) wm_prog_data
;
1245 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_CLIP
), clip
) {
1246 clip
.ClipEnable
= true;
1247 clip
.StatisticsEnable
= true;
1248 clip
.EarlyCullEnable
= true;
1249 clip
.APIMode
= APIMODE_D3D
;
1250 clip
.GuardbandClipTestEnable
= true;
1252 /* Only enable the XY clip test when the final polygon rasterization
1253 * mode is VK_POLYGON_MODE_FILL. We want to leave it disabled for
1254 * points and lines so we get "pop-free" clipping.
1256 VkPolygonMode raster_mode
=
1257 anv_raster_polygon_mode(pipeline
, ia_info
, rs_info
);
1258 clip
.ViewportXYClipTestEnable
= (raster_mode
== VK_POLYGON_MODE_FILL
);
1261 clip
.VertexSubPixelPrecisionSelect
= _8Bit
;
1264 clip
.ClipMode
= CLIPMODE_NORMAL
;
1266 clip
.TriangleStripListProvokingVertexSelect
= 0;
1267 clip
.LineStripListProvokingVertexSelect
= 0;
1268 clip
.TriangleFanProvokingVertexSelect
= 1;
1270 clip
.MinimumPointWidth
= 0.125;
1271 clip
.MaximumPointWidth
= 255.875;
1273 const struct brw_vue_prog_data
*last
=
1274 anv_pipeline_get_last_vue_prog_data(pipeline
);
1276 /* From the Vulkan 1.0.45 spec:
1278 * "If the last active vertex processing stage shader entry point's
1279 * interface does not include a variable decorated with
1280 * ViewportIndex, then the first viewport is used."
1282 if (vp_info
&& (last
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
)) {
1283 clip
.MaximumVPIndex
= vp_info
->viewportCount
- 1;
1285 clip
.MaximumVPIndex
= 0;
1288 /* From the Vulkan 1.0.45 spec:
1290 * "If the last active vertex processing stage shader entry point's
1291 * interface does not include a variable decorated with Layer, then
1292 * the first layer is used."
1294 clip
.ForceZeroRTAIndexEnable
=
1295 !(last
->vue_map
.slots_valid
& VARYING_BIT_LAYER
);
1298 clip
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
];
1299 clip
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
];
1300 clip
.ViewportZClipTestEnable
= pipeline
->depth_clip_enable
;
1301 clip
.UserClipDistanceClipTestEnableBitmask
= last
->clip_distance_mask
;
1302 clip
.UserClipDistanceCullTestEnableBitmask
= last
->cull_distance_mask
;
1304 clip
.NonPerspectiveBarycentricEnable
= wm_prog_data
?
1305 (wm_prog_data
->barycentric_interp_modes
&
1306 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
) != 0 : 0;
1312 emit_3dstate_streamout(struct anv_graphics_pipeline
*pipeline
,
1313 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
1316 const struct brw_vue_prog_data
*prog_data
=
1317 anv_pipeline_get_last_vue_prog_data(pipeline
);
1318 const struct brw_vue_map
*vue_map
= &prog_data
->vue_map
;
1320 nir_xfb_info
*xfb_info
;
1321 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1322 xfb_info
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->xfb_info
;
1323 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1324 xfb_info
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->xfb_info
;
1326 xfb_info
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->xfb_info
;
1329 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_STREAMOUT
), so
) {
1330 so
.RenderingDisable
= rs_info
->rasterizerDiscardEnable
;
1334 so
.SOFunctionEnable
= true;
1335 so
.SOStatisticsEnable
= true;
1337 const VkPipelineRasterizationStateStreamCreateInfoEXT
*stream_info
=
1338 vk_find_struct_const(rs_info
, PIPELINE_RASTERIZATION_STATE_STREAM_CREATE_INFO_EXT
);
1339 so
.RenderStreamSelect
= stream_info
?
1340 stream_info
->rasterizationStream
: 0;
1342 so
.Buffer0SurfacePitch
= xfb_info
->buffers
[0].stride
;
1343 so
.Buffer1SurfacePitch
= xfb_info
->buffers
[1].stride
;
1344 so
.Buffer2SurfacePitch
= xfb_info
->buffers
[2].stride
;
1345 so
.Buffer3SurfacePitch
= xfb_info
->buffers
[3].stride
;
1347 int urb_entry_read_offset
= 0;
1348 int urb_entry_read_length
=
1349 (prog_data
->vue_map
.num_slots
+ 1) / 2 - urb_entry_read_offset
;
1351 /* We always read the whole vertex. This could be reduced at some
1352 * point by reading less and offsetting the register index in the
1355 so
.Stream0VertexReadOffset
= urb_entry_read_offset
;
1356 so
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
1357 so
.Stream1VertexReadOffset
= urb_entry_read_offset
;
1358 so
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
1359 so
.Stream2VertexReadOffset
= urb_entry_read_offset
;
1360 so
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
1361 so
.Stream3VertexReadOffset
= urb_entry_read_offset
;
1362 so
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
1364 #endif /* GEN_GEN >= 8 */
1369 struct GENX(SO_DECL
) so_decl
[MAX_XFB_STREAMS
][128];
1370 int next_offset
[MAX_XFB_BUFFERS
] = {0, 0, 0, 0};
1371 int decls
[MAX_XFB_STREAMS
] = {0, 0, 0, 0};
1373 memset(so_decl
, 0, sizeof(so_decl
));
1375 for (unsigned i
= 0; i
< xfb_info
->output_count
; i
++) {
1376 const nir_xfb_output_info
*output
= &xfb_info
->outputs
[i
];
1377 unsigned buffer
= output
->buffer
;
1378 unsigned stream
= xfb_info
->buffer_to_stream
[buffer
];
1380 /* Our hardware is unusual in that it requires us to program SO_DECLs
1381 * for fake "hole" components, rather than simply taking the offset
1382 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
1383 * program as many size = 4 holes as we can, then a final hole to
1384 * accommodate the final 1, 2, or 3 remaining.
1386 int hole_dwords
= (output
->offset
- next_offset
[buffer
]) / 4;
1387 while (hole_dwords
> 0) {
1388 so_decl
[stream
][decls
[stream
]++] = (struct GENX(SO_DECL
)) {
1390 .OutputBufferSlot
= buffer
,
1391 .ComponentMask
= (1 << MIN2(hole_dwords
, 4)) - 1,
1396 int varying
= output
->location
;
1397 uint8_t component_mask
= output
->component_mask
;
1398 /* VARYING_SLOT_PSIZ contains three scalar fields packed together:
1399 * - VARYING_SLOT_LAYER in VARYING_SLOT_PSIZ.y
1400 * - VARYING_SLOT_VIEWPORT in VARYING_SLOT_PSIZ.z
1401 * - VARYING_SLOT_PSIZ in VARYING_SLOT_PSIZ.w
1403 if (varying
== VARYING_SLOT_LAYER
) {
1404 varying
= VARYING_SLOT_PSIZ
;
1405 component_mask
= 1 << 1; // SO_DECL_COMPMASK_Y
1406 } else if (varying
== VARYING_SLOT_VIEWPORT
) {
1407 varying
= VARYING_SLOT_PSIZ
;
1408 component_mask
= 1 << 2; // SO_DECL_COMPMASK_Z
1409 } else if (varying
== VARYING_SLOT_PSIZ
) {
1410 component_mask
= 1 << 3; // SO_DECL_COMPMASK_W
1413 next_offset
[buffer
] = output
->offset
+
1414 __builtin_popcount(component_mask
) * 4;
1416 const int slot
= vue_map
->varying_to_slot
[varying
];
1418 /* This can happen if the shader never writes to the varying.
1419 * Insert a hole instead of actual varying data.
1421 so_decl
[stream
][decls
[stream
]++] = (struct GENX(SO_DECL
)) {
1423 .OutputBufferSlot
= buffer
,
1424 .ComponentMask
= component_mask
,
1427 so_decl
[stream
][decls
[stream
]++] = (struct GENX(SO_DECL
)) {
1428 .OutputBufferSlot
= buffer
,
1429 .RegisterIndex
= slot
,
1430 .ComponentMask
= component_mask
,
1436 for (unsigned s
= 0; s
< MAX_XFB_STREAMS
; s
++)
1437 max_decls
= MAX2(max_decls
, decls
[s
]);
1439 uint8_t sbs
[MAX_XFB_STREAMS
] = { };
1440 for (unsigned b
= 0; b
< MAX_XFB_BUFFERS
; b
++) {
1441 if (xfb_info
->buffers_written
& (1 << b
))
1442 sbs
[xfb_info
->buffer_to_stream
[b
]] |= 1 << b
;
1445 uint32_t *dw
= anv_batch_emitn(&pipeline
->base
.batch
, 3 + 2 * max_decls
,
1446 GENX(3DSTATE_SO_DECL_LIST
),
1447 .StreamtoBufferSelects0
= sbs
[0],
1448 .StreamtoBufferSelects1
= sbs
[1],
1449 .StreamtoBufferSelects2
= sbs
[2],
1450 .StreamtoBufferSelects3
= sbs
[3],
1451 .NumEntries0
= decls
[0],
1452 .NumEntries1
= decls
[1],
1453 .NumEntries2
= decls
[2],
1454 .NumEntries3
= decls
[3]);
1456 for (int i
= 0; i
< max_decls
; i
++) {
1457 GENX(SO_DECL_ENTRY_pack
)(NULL
, dw
+ 3 + i
* 2,
1458 &(struct GENX(SO_DECL_ENTRY
)) {
1459 .Stream0Decl
= so_decl
[0][i
],
1460 .Stream1Decl
= so_decl
[1][i
],
1461 .Stream2Decl
= so_decl
[2][i
],
1462 .Stream3Decl
= so_decl
[3][i
],
1466 #endif /* GEN_GEN >= 8 */
1470 get_sampler_count(const struct anv_shader_bin
*bin
)
1472 uint32_t count_by_4
= DIV_ROUND_UP(bin
->bind_map
.sampler_count
, 4);
1474 /* We can potentially have way more than 32 samplers and that's ok.
1475 * However, the 3DSTATE_XS packets only have 3 bits to specify how
1476 * many to pre-fetch and all values above 4 are marked reserved.
1478 return MIN2(count_by_4
, 4);
1482 get_binding_table_entry_count(const struct anv_shader_bin
*bin
)
1484 return DIV_ROUND_UP(bin
->bind_map
.surface_count
, 32);
1487 static struct anv_address
1488 get_scratch_address(struct anv_pipeline
*pipeline
,
1489 gl_shader_stage stage
,
1490 const struct anv_shader_bin
*bin
)
1492 return (struct anv_address
) {
1493 .bo
= anv_scratch_pool_alloc(pipeline
->device
,
1494 &pipeline
->device
->scratch_pool
,
1495 stage
, bin
->prog_data
->total_scratch
),
1501 get_scratch_space(const struct anv_shader_bin
*bin
)
1503 return ffs(bin
->prog_data
->total_scratch
/ 2048);
1507 emit_3dstate_vs(struct anv_graphics_pipeline
*pipeline
)
1509 const struct gen_device_info
*devinfo
= &pipeline
->base
.device
->info
;
1510 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1511 const struct anv_shader_bin
*vs_bin
=
1512 pipeline
->shaders
[MESA_SHADER_VERTEX
];
1514 assert(anv_pipeline_has_stage(pipeline
, MESA_SHADER_VERTEX
));
1516 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_VS
), vs
) {
1518 vs
.StatisticsEnable
= true;
1519 vs
.KernelStartPointer
= vs_bin
->kernel
.offset
;
1521 vs
.SIMD8DispatchEnable
=
1522 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
1525 assert(!vs_prog_data
->base
.base
.use_alt_mode
);
1527 vs
.SingleVertexDispatch
= false;
1529 vs
.VectorMaskEnable
= false;
1531 * Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
1532 * Disable the Sampler state prefetch functionality in the SARB by
1533 * programming 0xB000[30] to '1'.
1535 vs
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(vs_bin
);
1536 vs
.BindingTableEntryCount
= get_binding_table_entry_count(vs_bin
);
1537 vs
.FloatingPointMode
= IEEE754
;
1538 vs
.IllegalOpcodeExceptionEnable
= false;
1539 vs
.SoftwareExceptionEnable
= false;
1540 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1542 if (GEN_GEN
== 9 && devinfo
->gt
== 4 &&
1543 anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
1544 /* On Sky Lake GT4, we have experienced some hangs related to the VS
1545 * cache and tessellation. It is unknown exactly what is happening
1546 * but the Haswell docs for the "VS Reference Count Full Force Miss
1547 * Enable" field of the "Thread Mode" register refer to a HSW bug in
1548 * which the VUE handle reference count would overflow resulting in
1549 * internal reference counting bugs. My (Jason's) best guess is that
1550 * this bug cropped back up on SKL GT4 when we suddenly had more
1551 * threads in play than any previous gen9 hardware.
1553 * What we do know for sure is that setting this bit when
1554 * tessellation shaders are in use fixes a GPU hang in Batman: Arkham
1555 * City when playing with DXVK (https://bugs.freedesktop.org/107280).
1556 * Disabling the vertex cache with tessellation shaders should only
1557 * have a minor performance impact as the tessellation shaders are
1558 * likely generating and processing far more geometry than the vertex
1561 vs
.VertexCacheDisable
= true;
1564 vs
.VertexURBEntryReadLength
= vs_prog_data
->base
.urb_read_length
;
1565 vs
.VertexURBEntryReadOffset
= 0;
1566 vs
.DispatchGRFStartRegisterForURBData
=
1567 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1570 vs
.UserClipDistanceClipTestEnableBitmask
=
1571 vs_prog_data
->base
.clip_distance_mask
;
1572 vs
.UserClipDistanceCullTestEnableBitmask
=
1573 vs_prog_data
->base
.cull_distance_mask
;
1576 vs
.PerThreadScratchSpace
= get_scratch_space(vs_bin
);
1577 vs
.ScratchSpaceBasePointer
=
1578 get_scratch_address(&pipeline
->base
, MESA_SHADER_VERTEX
, vs_bin
);
1583 emit_3dstate_hs_te_ds(struct anv_graphics_pipeline
*pipeline
,
1584 const VkPipelineTessellationStateCreateInfo
*tess_info
)
1586 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
1587 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_HS
), hs
);
1588 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_TE
), te
);
1589 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_DS
), ds
);
1593 const struct gen_device_info
*devinfo
= &pipeline
->base
.device
->info
;
1594 const struct anv_shader_bin
*tcs_bin
=
1595 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1596 const struct anv_shader_bin
*tes_bin
=
1597 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1599 const struct brw_tcs_prog_data
*tcs_prog_data
= get_tcs_prog_data(pipeline
);
1600 const struct brw_tes_prog_data
*tes_prog_data
= get_tes_prog_data(pipeline
);
1602 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_HS
), hs
) {
1604 hs
.StatisticsEnable
= true;
1605 hs
.KernelStartPointer
= tcs_bin
->kernel
.offset
;
1607 hs
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(tcs_bin
);
1608 hs
.BindingTableEntryCount
= get_binding_table_entry_count(tcs_bin
);
1611 /* GEN:BUG:1604578095:
1613 * Hang occurs when the number of max threads is less than 2 times
1614 * the number of instance count. The number of max threads must be
1615 * more than 2 times the number of instance count.
1617 assert((devinfo
->max_tcs_threads
/ 2) > tcs_prog_data
->instances
);
1620 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1621 hs
.IncludeVertexHandles
= true;
1622 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1624 hs
.VertexURBEntryReadLength
= 0;
1625 hs
.VertexURBEntryReadOffset
= 0;
1626 hs
.DispatchGRFStartRegisterForURBData
=
1627 tcs_prog_data
->base
.base
.dispatch_grf_start_reg
& 0x1f;
1629 hs
.DispatchGRFStartRegisterForURBData5
=
1630 tcs_prog_data
->base
.base
.dispatch_grf_start_reg
>> 5;
1634 hs
.PerThreadScratchSpace
= get_scratch_space(tcs_bin
);
1635 hs
.ScratchSpaceBasePointer
=
1636 get_scratch_address(&pipeline
->base
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
1639 /* Patch Count threshold specifies the maximum number of patches that
1640 * will be accumulated before a thread dispatch is forced.
1642 hs
.PatchCountThreshold
= tcs_prog_data
->patch_count_threshold
;
1646 hs
.DispatchMode
= tcs_prog_data
->base
.dispatch_mode
;
1647 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
1651 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
1652 tess_info
? vk_find_struct_const(tess_info
, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
) : NULL
;
1654 VkTessellationDomainOrigin uv_origin
=
1655 domain_origin_state
? domain_origin_state
->domainOrigin
:
1656 VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
;
1658 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_TE
), te
) {
1659 te
.Partitioning
= tes_prog_data
->partitioning
;
1661 if (uv_origin
== VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT
) {
1662 te
.OutputTopology
= tes_prog_data
->output_topology
;
1664 /* When the origin is upper-left, we have to flip the winding order */
1665 if (tes_prog_data
->output_topology
== OUTPUT_TRI_CCW
) {
1666 te
.OutputTopology
= OUTPUT_TRI_CW
;
1667 } else if (tes_prog_data
->output_topology
== OUTPUT_TRI_CW
) {
1668 te
.OutputTopology
= OUTPUT_TRI_CCW
;
1670 te
.OutputTopology
= tes_prog_data
->output_topology
;
1674 te
.TEDomain
= tes_prog_data
->domain
;
1676 te
.MaximumTessellationFactorOdd
= 63.0;
1677 te
.MaximumTessellationFactorNotOdd
= 64.0;
1680 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_DS
), ds
) {
1682 ds
.StatisticsEnable
= true;
1683 ds
.KernelStartPointer
= tes_bin
->kernel
.offset
;
1685 ds
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(tes_bin
);
1686 ds
.BindingTableEntryCount
= get_binding_table_entry_count(tes_bin
);
1687 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
1689 ds
.ComputeWCoordinateEnable
=
1690 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
1692 ds
.PatchURBEntryReadLength
= tes_prog_data
->base
.urb_read_length
;
1693 ds
.PatchURBEntryReadOffset
= 0;
1694 ds
.DispatchGRFStartRegisterForURBData
=
1695 tes_prog_data
->base
.base
.dispatch_grf_start_reg
;
1700 tes_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
?
1701 DISPATCH_MODE_SIMD8_SINGLE_PATCH
:
1702 DISPATCH_MODE_SIMD4X2
;
1704 assert(tes_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
);
1705 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
1708 ds
.UserClipDistanceClipTestEnableBitmask
=
1709 tes_prog_data
->base
.clip_distance_mask
;
1710 ds
.UserClipDistanceCullTestEnableBitmask
=
1711 tes_prog_data
->base
.cull_distance_mask
;
1714 ds
.PerThreadScratchSpace
= get_scratch_space(tes_bin
);
1715 ds
.ScratchSpaceBasePointer
=
1716 get_scratch_address(&pipeline
->base
, MESA_SHADER_TESS_EVAL
, tes_bin
);
1721 emit_3dstate_gs(struct anv_graphics_pipeline
*pipeline
)
1723 const struct gen_device_info
*devinfo
= &pipeline
->base
.device
->info
;
1724 const struct anv_shader_bin
*gs_bin
=
1725 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1727 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
)) {
1728 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_GS
), gs
);
1732 const struct brw_gs_prog_data
*gs_prog_data
= get_gs_prog_data(pipeline
);
1734 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_GS
), gs
) {
1736 gs
.StatisticsEnable
= true;
1737 gs
.KernelStartPointer
= gs_bin
->kernel
.offset
;
1738 gs
.DispatchMode
= gs_prog_data
->base
.dispatch_mode
;
1740 gs
.SingleProgramFlow
= false;
1741 gs
.VectorMaskEnable
= false;
1743 gs
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(gs_bin
);
1744 gs
.BindingTableEntryCount
= get_binding_table_entry_count(gs_bin
);
1745 gs
.IncludeVertexHandles
= gs_prog_data
->base
.include_vue_handles
;
1746 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
1749 /* Broadwell is weird. It needs us to divide by 2. */
1750 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
/ 2 - 1;
1752 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
1755 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
1756 gs
.OutputTopology
= gs_prog_data
->output_topology
;
1757 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1758 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
1759 gs
.ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
;
1760 gs
.InstanceControl
= MAX2(gs_prog_data
->invocations
, 1) - 1;
1761 gs
.ReorderMode
= TRAILING
;
1764 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
1765 gs
.StaticOutput
= gs_prog_data
->static_vertex_count
>= 0;
1766 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
>= 0 ?
1767 gs_prog_data
->static_vertex_count
: 0;
1770 gs
.VertexURBEntryReadOffset
= 0;
1771 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1772 gs
.DispatchGRFStartRegisterForURBData
=
1773 gs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1776 gs
.UserClipDistanceClipTestEnableBitmask
=
1777 gs_prog_data
->base
.clip_distance_mask
;
1778 gs
.UserClipDistanceCullTestEnableBitmask
=
1779 gs_prog_data
->base
.cull_distance_mask
;
1782 gs
.PerThreadScratchSpace
= get_scratch_space(gs_bin
);
1783 gs
.ScratchSpaceBasePointer
=
1784 get_scratch_address(&pipeline
->base
, MESA_SHADER_GEOMETRY
, gs_bin
);
1789 has_color_buffer_write_enabled(const struct anv_graphics_pipeline
*pipeline
,
1790 const VkPipelineColorBlendStateCreateInfo
*blend
)
1792 const struct anv_shader_bin
*shader_bin
=
1793 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1797 const struct anv_pipeline_bind_map
*bind_map
= &shader_bin
->bind_map
;
1798 for (int i
= 0; i
< bind_map
->surface_count
; i
++) {
1799 struct anv_pipeline_binding
*binding
= &bind_map
->surface_to_descriptor
[i
];
1801 if (binding
->set
!= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
1804 if (binding
->index
== UINT32_MAX
)
1807 if (blend
&& blend
->pAttachments
[binding
->index
].colorWriteMask
!= 0)
1815 emit_3dstate_wm(struct anv_graphics_pipeline
*pipeline
, struct anv_subpass
*subpass
,
1816 const VkPipelineInputAssemblyStateCreateInfo
*ia
,
1817 const VkPipelineRasterizationStateCreateInfo
*raster
,
1818 const VkPipelineColorBlendStateCreateInfo
*blend
,
1819 const VkPipelineMultisampleStateCreateInfo
*multisample
,
1820 const VkPipelineRasterizationLineStateCreateInfoEXT
*line
)
1822 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1824 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_WM
), wm
) {
1825 wm
.StatisticsEnable
= true;
1826 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1827 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1828 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1830 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1831 if (wm_prog_data
->early_fragment_tests
) {
1832 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1833 } else if (wm_prog_data
->has_side_effects
) {
1834 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1836 wm
.EarlyDepthStencilControl
= EDSC_NORMAL
;
1840 /* Gen8 hardware tries to compute ThreadDispatchEnable for us but
1841 * doesn't take into account KillPixels when no depth or stencil
1842 * writes are enabled. In order for occlusion queries to work
1843 * correctly with no attachments, we need to force-enable PS thread
1846 * The BDW docs are pretty clear that that this bit isn't validated
1847 * and probably shouldn't be used in production:
1849 * "This must always be set to Normal. This field should not be
1850 * tested for functional validation."
1852 * Unfortunately, however, the other mechanism we have for doing this
1853 * is 3DSTATE_PS_EXTRA::PixelShaderHasUAV which causes hangs on BDW.
1854 * Given two bad options, we choose the one which works.
1856 if ((wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
) &&
1857 !has_color_buffer_write_enabled(pipeline
, blend
))
1858 wm
.ForceThreadDispatchEnable
= ForceON
;
1861 wm
.BarycentricInterpolationMode
=
1862 wm_prog_data
->barycentric_interp_modes
;
1865 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1866 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1867 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1868 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1870 /* If the subpass has a depth or stencil self-dependency, then we
1871 * need to force the hardware to do the depth/stencil write *after*
1872 * fragment shader execution. Otherwise, the writes may hit memory
1873 * before we get around to fetching from the input attachment and we
1874 * may get the depth or stencil value from the current draw rather
1875 * than the previous one.
1877 wm
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
1878 wm_prog_data
->uses_kill
;
1880 if (wm
.PixelShaderComputedDepthMode
!= PSCDEPTH_OFF
||
1881 wm_prog_data
->has_side_effects
||
1882 wm
.PixelShaderKillsPixel
||
1883 has_color_buffer_write_enabled(pipeline
, blend
))
1884 wm
.ThreadDispatchEnable
= true;
1886 if (multisample
&& multisample
->rasterizationSamples
> 1) {
1887 if (wm_prog_data
->persample_dispatch
) {
1888 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1890 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1893 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1895 wm
.MultisampleRasterizationMode
=
1896 gen7_ms_rast_mode(pipeline
, ia
, raster
, multisample
);
1899 wm
.LineStippleEnable
= line
&& line
->stippledLineEnable
;
1905 emit_3dstate_ps(struct anv_graphics_pipeline
*pipeline
,
1906 const VkPipelineColorBlendStateCreateInfo
*blend
,
1907 const VkPipelineMultisampleStateCreateInfo
*multisample
)
1909 UNUSED
const struct gen_device_info
*devinfo
= &pipeline
->base
.device
->info
;
1910 const struct anv_shader_bin
*fs_bin
=
1911 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1913 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1914 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PS
), ps
) {
1916 /* Even if no fragments are ever dispatched, gen7 hardware hangs if
1917 * we don't at least set the maximum number of threads.
1919 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1925 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1928 /* The hardware wedges if you have this bit set but don't turn on any dual
1929 * source blend factors.
1931 bool dual_src_blend
= false;
1932 if (wm_prog_data
->dual_src_blend
&& blend
) {
1933 for (uint32_t i
= 0; i
< blend
->attachmentCount
; i
++) {
1934 const VkPipelineColorBlendAttachmentState
*bstate
=
1935 &blend
->pAttachments
[i
];
1937 if (bstate
->blendEnable
&&
1938 (is_dual_src_blend_factor(bstate
->srcColorBlendFactor
) ||
1939 is_dual_src_blend_factor(bstate
->dstColorBlendFactor
) ||
1940 is_dual_src_blend_factor(bstate
->srcAlphaBlendFactor
) ||
1941 is_dual_src_blend_factor(bstate
->dstAlphaBlendFactor
))) {
1942 dual_src_blend
= true;
1949 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PS
), ps
) {
1950 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1951 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1952 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1954 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
1956 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
1957 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
1959 * Since 16x MSAA is first introduced on SKL, we don't need to apply
1960 * the workaround on any older hardware.
1962 if (GEN_GEN
>= 9 && !wm_prog_data
->persample_dispatch
&&
1963 multisample
&& multisample
->rasterizationSamples
== 16) {
1964 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
1965 ps
._32PixelDispatchEnable
= false;
1968 ps
.KernelStartPointer0
= fs_bin
->kernel
.offset
+
1969 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
1970 ps
.KernelStartPointer1
= fs_bin
->kernel
.offset
+
1971 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
1972 ps
.KernelStartPointer2
= fs_bin
->kernel
.offset
+
1973 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
1975 ps
.SingleProgramFlow
= false;
1976 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
1978 ps
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(fs_bin
);
1979 ps
.BindingTableEntryCount
= get_binding_table_entry_count(fs_bin
);
1980 ps
.PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0 ||
1981 wm_prog_data
->base
.ubo_ranges
[0].length
;
1982 ps
.PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
1983 POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
1985 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
1986 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1987 ps
.DualSourceBlendEnable
= dual_src_blend
;
1991 /* Haswell requires the sample mask to be set in this packet as well
1992 * as in 3DSTATE_SAMPLE_MASK; the values should match.
1994 ps
.SampleMask
= 0xff;
1998 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
2000 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
2002 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
2005 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
2006 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
2007 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
2008 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
2009 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
2010 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
2012 ps
.PerThreadScratchSpace
= get_scratch_space(fs_bin
);
2013 ps
.ScratchSpaceBasePointer
=
2014 get_scratch_address(&pipeline
->base
, MESA_SHADER_FRAGMENT
, fs_bin
);
2020 emit_3dstate_ps_extra(struct anv_graphics_pipeline
*pipeline
,
2021 struct anv_subpass
*subpass
)
2023 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
2025 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
2026 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PS_EXTRA
), ps
);
2030 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PS_EXTRA
), ps
) {
2031 ps
.PixelShaderValid
= true;
2032 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
2033 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
2034 ps
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
2035 ps
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
2036 ps
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
2037 ps
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
2039 /* If the subpass has a depth or stencil self-dependency, then we need
2040 * to force the hardware to do the depth/stencil write *after* fragment
2041 * shader execution. Otherwise, the writes may hit memory before we get
2042 * around to fetching from the input attachment and we may get the depth
2043 * or stencil value from the current draw rather than the previous one.
2045 ps
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
2046 wm_prog_data
->uses_kill
;
2049 ps
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
2050 ps
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
2052 ps
.InputCoverageMaskState
= ICMS_NONE
;
2053 if (wm_prog_data
->uses_sample_mask
) {
2054 if (wm_prog_data
->post_depth_coverage
)
2055 ps
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
2057 ps
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
2060 ps
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
2066 emit_3dstate_vf_topology(struct anv_graphics_pipeline
*pipeline
)
2068 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_VF_TOPOLOGY
), vft
) {
2069 vft
.PrimitiveTopologyType
= pipeline
->topology
;
2075 emit_3dstate_vf_statistics(struct anv_graphics_pipeline
*pipeline
)
2077 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_VF_STATISTICS
), vfs
) {
2078 vfs
.StatisticsEnable
= true;
2083 compute_kill_pixel(struct anv_graphics_pipeline
*pipeline
,
2084 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
2085 const struct anv_subpass
*subpass
)
2087 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
2088 pipeline
->kill_pixel
= false;
2092 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
2094 /* This computes the KillPixel portion of the computation for whether or
2095 * not we want to enable the PMA fix on gen8 or gen9. It's given by this
2096 * chunk of the giant formula:
2098 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
2099 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
2100 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
2101 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
2102 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
2104 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false and so is
2105 * 3DSTATE_PS_BLEND::AlphaTestEnable since Vulkan doesn't have a concept
2108 pipeline
->kill_pixel
=
2109 subpass
->has_ds_self_dep
|| wm_prog_data
->uses_kill
||
2110 wm_prog_data
->uses_omask
||
2111 (ms_info
&& ms_info
->alphaToCoverageEnable
);
2116 emit_3dstate_primitive_replication(struct anv_graphics_pipeline
*pipeline
)
2118 if (!pipeline
->use_primitive_replication
) {
2119 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PRIMITIVE_REPLICATION
), pr
);
2123 uint32_t view_mask
= pipeline
->subpass
->view_mask
;
2124 int view_count
= util_bitcount(view_mask
);
2125 assert(view_count
> 1 && view_count
<= MAX_VIEWS_FOR_PRIMITIVE_REPLICATION
);
2127 anv_batch_emit(&pipeline
->base
.batch
, GENX(3DSTATE_PRIMITIVE_REPLICATION
), pr
) {
2128 pr
.ReplicaMask
= (1 << view_count
) - 1;
2129 pr
.ReplicationCount
= view_count
- 1;
2131 int i
= 0, view_index
;
2132 for_each_bit(view_index
, view_mask
) {
2133 pr
.RTAIOffset
[i
] = view_index
;
2141 genX(graphics_pipeline_create
)(
2143 struct anv_pipeline_cache
* cache
,
2144 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
2145 const VkAllocationCallbacks
* pAllocator
,
2146 VkPipeline
* pPipeline
)
2148 ANV_FROM_HANDLE(anv_device
, device
, _device
);
2149 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
2150 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
2151 struct anv_graphics_pipeline
*pipeline
;
2154 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
2156 /* Use the default pipeline cache if none is specified */
2157 if (cache
== NULL
&& device
->physical
->instance
->pipeline_cache_enabled
)
2158 cache
= &device
->default_pipeline_cache
;
2160 pipeline
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
2161 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2162 if (pipeline
== NULL
)
2163 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2165 result
= anv_pipeline_init(pipeline
, device
, cache
,
2166 pCreateInfo
, pAllocator
);
2167 if (result
!= VK_SUCCESS
) {
2168 vk_free2(&device
->vk
.alloc
, pAllocator
, pipeline
);
2172 /* If rasterization is not enabled, various CreateInfo structs must be
2175 const bool raster_enabled
=
2176 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
;
2178 const VkPipelineViewportStateCreateInfo
*vp_info
=
2179 raster_enabled
? pCreateInfo
->pViewportState
: NULL
;
2181 const VkPipelineMultisampleStateCreateInfo
*ms_info
=
2182 raster_enabled
? pCreateInfo
->pMultisampleState
: NULL
;
2184 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
2185 raster_enabled
? pCreateInfo
->pDepthStencilState
: NULL
;
2187 const VkPipelineColorBlendStateCreateInfo
*cb_info
=
2188 raster_enabled
? pCreateInfo
->pColorBlendState
: NULL
;
2190 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_info
=
2191 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
2192 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
2194 enum gen_urb_deref_block_size urb_deref_block_size
;
2195 emit_urb_setup(pipeline
, &urb_deref_block_size
);
2197 assert(pCreateInfo
->pVertexInputState
);
2198 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
);
2199 assert(pCreateInfo
->pRasterizationState
);
2200 emit_rs_state(pipeline
, pCreateInfo
->pInputAssemblyState
,
2201 pCreateInfo
->pRasterizationState
,
2202 ms_info
, line_info
, pass
, subpass
,
2203 urb_deref_block_size
);
2204 emit_ms_state(pipeline
, ms_info
);
2205 emit_ds_state(pipeline
, ds_info
, pass
, subpass
);
2206 emit_cb_state(pipeline
, cb_info
, ms_info
);
2207 compute_kill_pixel(pipeline
, ms_info
, subpass
);
2209 emit_3dstate_clip(pipeline
,
2210 pCreateInfo
->pInputAssemblyState
,
2212 pCreateInfo
->pRasterizationState
);
2213 emit_3dstate_streamout(pipeline
, pCreateInfo
->pRasterizationState
);
2216 emit_3dstate_primitive_replication(pipeline
);
2220 /* From gen7_vs_state.c */
2223 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2224 * Geometry > Geometry Shader > State:
2226 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2227 * whole fixed function pipeline when the GS enable changes value in
2230 * The hardware architects have clarified that in this context "flush the
2231 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2234 if (!device
->info
.is_haswell
&& !device
->info
.is_baytrail
)
2235 gen7_emit_vs_workaround_flush(brw
);
2238 emit_3dstate_vs(pipeline
);
2239 emit_3dstate_hs_te_ds(pipeline
, pCreateInfo
->pTessellationState
);
2240 emit_3dstate_gs(pipeline
);
2241 emit_3dstate_sbe(pipeline
);
2242 emit_3dstate_wm(pipeline
, subpass
,
2243 pCreateInfo
->pInputAssemblyState
,
2244 pCreateInfo
->pRasterizationState
,
2245 cb_info
, ms_info
, line_info
);
2246 emit_3dstate_ps(pipeline
, cb_info
, ms_info
);
2248 emit_3dstate_ps_extra(pipeline
, subpass
);
2249 emit_3dstate_vf_topology(pipeline
);
2251 emit_3dstate_vf_statistics(pipeline
);
2253 *pPipeline
= anv_pipeline_to_handle(&pipeline
->base
);
2255 return pipeline
->base
.batch
.status
;
2259 compute_pipeline_create(
2261 struct anv_pipeline_cache
* cache
,
2262 const VkComputePipelineCreateInfo
* pCreateInfo
,
2263 const VkAllocationCallbacks
* pAllocator
,
2264 VkPipeline
* pPipeline
)
2266 ANV_FROM_HANDLE(anv_device
, device
, _device
);
2267 const struct gen_device_info
*devinfo
= &device
->info
;
2268 struct anv_compute_pipeline
*pipeline
;
2271 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
);
2273 /* Use the default pipeline cache if none is specified */
2274 if (cache
== NULL
&& device
->physical
->instance
->pipeline_cache_enabled
)
2275 cache
= &device
->default_pipeline_cache
;
2277 pipeline
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
2278 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2279 if (pipeline
== NULL
)
2280 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2282 pipeline
->base
.device
= device
;
2283 pipeline
->base
.type
= ANV_PIPELINE_COMPUTE
;
2285 const VkAllocationCallbacks
*alloc
=
2286 pAllocator
? pAllocator
: &device
->vk
.alloc
;
2288 result
= anv_reloc_list_init(&pipeline
->base
.batch_relocs
, alloc
);
2289 if (result
!= VK_SUCCESS
) {
2290 vk_free2(&device
->vk
.alloc
, pAllocator
, pipeline
);
2293 pipeline
->base
.batch
.alloc
= alloc
;
2294 pipeline
->base
.batch
.next
= pipeline
->base
.batch
.start
= pipeline
->batch_data
;
2295 pipeline
->base
.batch
.end
= pipeline
->base
.batch
.start
+ sizeof(pipeline
->batch_data
);
2296 pipeline
->base
.batch
.relocs
= &pipeline
->base
.batch_relocs
;
2297 pipeline
->base
.batch
.status
= VK_SUCCESS
;
2299 pipeline
->base
.mem_ctx
= ralloc_context(NULL
);
2300 pipeline
->base
.flags
= pCreateInfo
->flags
;
2301 pipeline
->cs
= NULL
;
2303 util_dynarray_init(&pipeline
->base
.executables
, pipeline
->base
.mem_ctx
);
2305 assert(pCreateInfo
->stage
.stage
== VK_SHADER_STAGE_COMPUTE_BIT
);
2306 ANV_FROM_HANDLE(anv_shader_module
, module
, pCreateInfo
->stage
.module
);
2307 result
= anv_pipeline_compile_cs(pipeline
, cache
, pCreateInfo
, module
,
2308 pCreateInfo
->stage
.pName
,
2309 pCreateInfo
->stage
.pSpecializationInfo
);
2310 if (result
!= VK_SUCCESS
) {
2311 ralloc_free(pipeline
->base
.mem_ctx
);
2312 vk_free2(&device
->vk
.alloc
, pAllocator
, pipeline
);
2316 const struct brw_cs_prog_data
*cs_prog_data
= get_cs_prog_data(pipeline
);
2318 anv_pipeline_setup_l3_config(&pipeline
->base
, cs_prog_data
->base
.total_shared
> 0);
2320 uint32_t group_size
= cs_prog_data
->local_size
[0] *
2321 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
2322 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
2325 pipeline
->cs_right_mask
= ~0u >> (32 - remainder
);
2327 pipeline
->cs_right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
2329 const uint32_t threads
= anv_cs_threads(pipeline
);
2331 const uint32_t vfe_curbe_allocation
=
2332 ALIGN(cs_prog_data
->push
.per_thread
.regs
* threads
+
2333 cs_prog_data
->push
.cross_thread
.regs
, 2);
2335 const uint32_t subslices
= MAX2(device
->physical
->subslice_total
, 1);
2337 const struct anv_shader_bin
*cs_bin
= pipeline
->cs
;
2339 anv_batch_emit(&pipeline
->base
.batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
2343 vfe
.GPGPUMode
= true;
2345 vfe
.MaximumNumberofThreads
=
2346 devinfo
->max_cs_threads
* subslices
- 1;
2347 vfe
.NumberofURBEntries
= GEN_GEN
<= 7 ? 0 : 2;
2349 vfe
.ResetGatewayTimer
= true;
2352 vfe
.BypassGatewayControl
= true;
2354 vfe
.URBEntryAllocationSize
= GEN_GEN
<= 7 ? 0 : 2;
2355 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
2357 if (cs_bin
->prog_data
->total_scratch
) {
2359 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
2360 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
2362 vfe
.PerThreadScratchSpace
=
2363 ffs(cs_bin
->prog_data
->total_scratch
) - 11;
2364 } else if (GEN_IS_HASWELL
) {
2365 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
2366 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
2368 vfe
.PerThreadScratchSpace
=
2369 ffs(cs_bin
->prog_data
->total_scratch
) - 12;
2371 /* IVB and BYT use the range [0, 11] to mean [1kB, 12kB]
2372 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
2374 vfe
.PerThreadScratchSpace
=
2375 cs_bin
->prog_data
->total_scratch
/ 1024 - 1;
2377 vfe
.ScratchSpaceBasePointer
=
2378 get_scratch_address(&pipeline
->base
, MESA_SHADER_COMPUTE
, cs_bin
);
2382 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2383 .KernelStartPointer
= cs_bin
->kernel
.offset
,
2385 .SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(cs_bin
),
2386 /* We add 1 because the CS indirect parameters buffer isn't accounted
2387 * for in bind_map.surface_count.
2389 .BindingTableEntryCount
= 1 + MIN2(cs_bin
->bind_map
.surface_count
, 30),
2390 .BarrierEnable
= cs_prog_data
->uses_barrier
,
2391 .SharedLocalMemorySize
=
2392 encode_slm_size(GEN_GEN
, cs_prog_data
->base
.total_shared
),
2395 .ConstantURBEntryReadOffset
= 0,
2397 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
2398 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2399 .CrossThreadConstantDataReadLength
=
2400 cs_prog_data
->push
.cross_thread
.regs
,
2403 /* TODO: Check if we are missing workarounds and enable mid-thread
2406 * We still have issues with mid-thread preemption (it was already
2407 * disabled by the kernel on gen11, due to missing workarounds). It's
2408 * possible that we are just missing some workarounds, and could enable
2409 * it later, but for now let's disable it to fix a GPU in compute in Car
2410 * Chase (and possibly more).
2412 .ThreadPreemptionDisable
= true,
2415 .NumberofThreadsinGPGPUThreadGroup
= threads
,
2417 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
,
2418 pipeline
->interface_descriptor_data
,
2421 *pPipeline
= anv_pipeline_to_handle(&pipeline
->base
);
2423 return pipeline
->base
.batch
.status
;
2426 VkResult
genX(CreateGraphicsPipelines
)(
2428 VkPipelineCache pipelineCache
,
2430 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
2431 const VkAllocationCallbacks
* pAllocator
,
2432 VkPipeline
* pPipelines
)
2434 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
2436 VkResult result
= VK_SUCCESS
;
2439 for (i
= 0; i
< count
; i
++) {
2440 result
= genX(graphics_pipeline_create
)(_device
,
2443 pAllocator
, &pPipelines
[i
]);
2445 /* Bail out on the first error as it is not obvious what error should be
2446 * report upon 2 different failures. */
2447 if (result
!= VK_SUCCESS
)
2451 for (; i
< count
; i
++)
2452 pPipelines
[i
] = VK_NULL_HANDLE
;
2457 VkResult
genX(CreateComputePipelines
)(
2459 VkPipelineCache pipelineCache
,
2461 const VkComputePipelineCreateInfo
* pCreateInfos
,
2462 const VkAllocationCallbacks
* pAllocator
,
2463 VkPipeline
* pPipelines
)
2465 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
2467 VkResult result
= VK_SUCCESS
;
2470 for (i
= 0; i
< count
; i
++) {
2471 result
= compute_pipeline_create(_device
, pipeline_cache
,
2473 pAllocator
, &pPipelines
[i
]);
2475 /* Bail out on the first error as it is not obvious what error should be
2476 * report upon 2 different failures. */
2477 if (result
!= VK_SUCCESS
)
2481 for (; i
< count
; i
++)
2482 pPipelines
[i
] = VK_NULL_HANDLE
;