2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
26 #include "genxml/gen_macros.h"
27 #include "genxml/genX_pack.h"
29 #include "common/gen_l3_config.h"
30 #include "common/gen_sample_positions.h"
32 #include "vk_format_info.h"
35 vertex_element_comp_control(enum isl_format format
, unsigned comp
)
39 case 0: bits
= isl_format_layouts
[format
].channels
.r
.bits
; break;
40 case 1: bits
= isl_format_layouts
[format
].channels
.g
.bits
; break;
41 case 2: bits
= isl_format_layouts
[format
].channels
.b
.bits
; break;
42 case 3: bits
= isl_format_layouts
[format
].channels
.a
.bits
; break;
43 default: unreachable("Invalid component");
47 * Take in account hardware restrictions when dealing with 64-bit floats.
49 * From Broadwell spec, command reference structures, page 586:
50 * "When SourceElementFormat is set to one of the *64*_PASSTHRU formats,
51 * 64-bit components are stored * in the URB without any conversion. In
52 * this case, vertex elements must be written as 128 or 256 bits, with
53 * VFCOMP_STORE_0 being used to pad the output as required. E.g., if
54 * R64_PASSTHRU is used to copy a 64-bit Red component into the URB,
55 * Component 1 must be specified as VFCOMP_STORE_0 (with Components 2,3
56 * set to VFCOMP_NOSTORE) in order to output a 128-bit vertex element, or
57 * Components 1-3 must be specified as VFCOMP_STORE_0 in order to output
58 * a 256-bit vertex element. Likewise, use of R64G64B64_PASSTHRU requires
59 * Component 3 to be specified as VFCOMP_STORE_0 in order to output a
60 * 256-bit vertex element."
63 return VFCOMP_STORE_SRC
;
64 } else if (comp
>= 2 &&
65 !isl_format_layouts
[format
].channels
.b
.bits
&&
66 isl_format_layouts
[format
].channels
.r
.type
== ISL_RAW
) {
67 /* When emitting 64-bit attributes, we need to write either 128 or 256
68 * bit chunks, using VFCOMP_NOSTORE when not writing the chunk, and
69 * VFCOMP_STORE_0 to pad the written chunk */
70 return VFCOMP_NOSTORE
;
71 } else if (comp
< 3 ||
72 isl_format_layouts
[format
].channels
.r
.type
== ISL_RAW
) {
73 /* Note we need to pad with value 0, not 1, due hardware restrictions
74 * (see comment above) */
75 return VFCOMP_STORE_0
;
76 } else if (isl_format_layouts
[format
].channels
.r
.type
== ISL_UINT
||
77 isl_format_layouts
[format
].channels
.r
.type
== ISL_SINT
) {
79 return VFCOMP_STORE_1_INT
;
82 return VFCOMP_STORE_1_FP
;
87 emit_vertex_input(struct anv_pipeline
*pipeline
,
88 const VkPipelineVertexInputStateCreateInfo
*info
)
90 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
92 /* Pull inputs_read out of the VS prog data */
93 const uint64_t inputs_read
= vs_prog_data
->inputs_read
;
94 const uint64_t double_inputs_read
=
95 vs_prog_data
->double_inputs_read
& inputs_read
;
96 assert((inputs_read
& ((1 << VERT_ATTRIB_GENERIC0
) - 1)) == 0);
97 const uint32_t elements
= inputs_read
>> VERT_ATTRIB_GENERIC0
;
98 const uint32_t elements_double
= double_inputs_read
>> VERT_ATTRIB_GENERIC0
;
99 const bool needs_svgs_elem
= vs_prog_data
->uses_vertexid
||
100 vs_prog_data
->uses_instanceid
||
101 vs_prog_data
->uses_firstvertex
||
102 vs_prog_data
->uses_baseinstance
;
104 uint32_t elem_count
= __builtin_popcount(elements
) -
105 __builtin_popcount(elements_double
) / 2;
107 const uint32_t total_elems
=
108 elem_count
+ needs_svgs_elem
+ vs_prog_data
->uses_drawid
;
109 if (total_elems
== 0)
114 const uint32_t num_dwords
= 1 + total_elems
* 2;
115 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
116 GENX(3DSTATE_VERTEX_ELEMENTS
));
120 for (uint32_t i
= 0; i
< total_elems
; i
++) {
121 /* The SKL docs for VERTEX_ELEMENT_STATE say:
123 * "All elements must be valid from Element[0] to the last valid
124 * element. (I.e. if Element[2] is valid then Element[1] and
125 * Element[0] must also be valid)."
127 * The SKL docs for 3D_Vertex_Component_Control say:
129 * "Don't store this component. (Not valid for Component 0, but can
130 * be used for Component 1-3)."
132 * So we can't just leave a vertex element blank and hope for the best.
133 * We have to tell the VF hardware to put something in it; so we just
134 * store a bunch of zero.
136 * TODO: Compact vertex elements so we never end up with holes.
138 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
140 .Component0Control
= VFCOMP_STORE_0
,
141 .Component1Control
= VFCOMP_STORE_0
,
142 .Component2Control
= VFCOMP_STORE_0
,
143 .Component3Control
= VFCOMP_STORE_0
,
145 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + i
* 2], &element
);
148 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
149 const VkVertexInputAttributeDescription
*desc
=
150 &info
->pVertexAttributeDescriptions
[i
];
151 enum isl_format format
= anv_get_isl_format(&pipeline
->device
->info
,
153 VK_IMAGE_ASPECT_COLOR_BIT
,
154 VK_IMAGE_TILING_LINEAR
);
156 assert(desc
->binding
< MAX_VBS
);
158 if ((elements
& (1 << desc
->location
)) == 0)
159 continue; /* Binding unused */
162 __builtin_popcount(elements
& ((1 << desc
->location
) - 1)) -
163 DIV_ROUND_UP(__builtin_popcount(elements_double
&
164 ((1 << desc
->location
) -1)), 2);
166 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
167 .VertexBufferIndex
= desc
->binding
,
169 .SourceElementFormat
= format
,
170 .EdgeFlagEnable
= false,
171 .SourceElementOffset
= desc
->offset
,
172 .Component0Control
= vertex_element_comp_control(format
, 0),
173 .Component1Control
= vertex_element_comp_control(format
, 1),
174 .Component2Control
= vertex_element_comp_control(format
, 2),
175 .Component3Control
= vertex_element_comp_control(format
, 3),
177 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + slot
* 2], &element
);
180 /* On Broadwell and later, we have a separate VF_INSTANCING packet
181 * that controls instancing. On Haswell and prior, that's part of
182 * VERTEX_BUFFER_STATE which we emit later.
184 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
185 vfi
.InstancingEnable
= pipeline
->vb
[desc
->binding
].instanced
;
186 vfi
.VertexElementIndex
= slot
;
187 vfi
.InstanceDataStepRate
=
188 pipeline
->vb
[desc
->binding
].instance_divisor
;
193 const uint32_t id_slot
= elem_count
;
194 if (needs_svgs_elem
) {
195 /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
196 * "Within a VERTEX_ELEMENT_STATE structure, if a Component
197 * Control field is set to something other than VFCOMP_STORE_SRC,
198 * no higher-numbered Component Control fields may be set to
201 * This means, that if we have BaseInstance, we need BaseVertex as
202 * well. Just do all or nothing.
204 uint32_t base_ctrl
= (vs_prog_data
->uses_firstvertex
||
205 vs_prog_data
->uses_baseinstance
) ?
206 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
208 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
209 .VertexBufferIndex
= ANV_SVGS_VB_INDEX
,
211 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
212 .Component0Control
= base_ctrl
,
213 .Component1Control
= base_ctrl
,
215 .Component2Control
= VFCOMP_STORE_0
,
216 .Component3Control
= VFCOMP_STORE_0
,
218 .Component2Control
= VFCOMP_STORE_VID
,
219 .Component3Control
= VFCOMP_STORE_IID
,
222 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + id_slot
* 2], &element
);
226 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
227 sgvs
.VertexIDEnable
= vs_prog_data
->uses_vertexid
;
228 sgvs
.VertexIDComponentNumber
= 2;
229 sgvs
.VertexIDElementOffset
= id_slot
;
230 sgvs
.InstanceIDEnable
= vs_prog_data
->uses_instanceid
;
231 sgvs
.InstanceIDComponentNumber
= 3;
232 sgvs
.InstanceIDElementOffset
= id_slot
;
236 const uint32_t drawid_slot
= elem_count
+ needs_svgs_elem
;
237 if (vs_prog_data
->uses_drawid
) {
238 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
239 .VertexBufferIndex
= ANV_DRAWID_VB_INDEX
,
241 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
242 .Component0Control
= VFCOMP_STORE_SRC
,
243 .Component1Control
= VFCOMP_STORE_0
,
244 .Component2Control
= VFCOMP_STORE_0
,
245 .Component3Control
= VFCOMP_STORE_0
,
247 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
,
248 &p
[1 + drawid_slot
* 2],
252 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
253 vfi
.VertexElementIndex
= drawid_slot
;
260 genX(emit_urb_setup
)(struct anv_device
*device
, struct anv_batch
*batch
,
261 const struct gen_l3_config
*l3_config
,
262 VkShaderStageFlags active_stages
,
263 const unsigned entry_size
[4])
265 const struct gen_device_info
*devinfo
= &device
->info
;
267 const unsigned push_constant_kb
= devinfo
->gt
== 3 ? 32 : 16;
269 const unsigned push_constant_kb
= GEN_GEN
>= 8 ? 32 : 16;
272 const unsigned urb_size_kb
= gen_get_l3_config_urb_size(devinfo
, l3_config
);
276 gen_get_urb_config(devinfo
,
277 1024 * push_constant_kb
, 1024 * urb_size_kb
,
279 VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
,
280 active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
,
281 entry_size
, entries
, start
);
283 #if GEN_GEN == 7 && !GEN_IS_HASWELL
284 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
286 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
287 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
288 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
289 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
290 * needs to be sent before any combination of VS associated 3DSTATE."
292 anv_batch_emit(batch
, GEN7_PIPE_CONTROL
, pc
) {
293 pc
.DepthStallEnable
= true;
294 pc
.PostSyncOperation
= WriteImmediateData
;
295 pc
.Address
= (struct anv_address
) { &device
->workaround_bo
, 0 };
299 for (int i
= 0; i
<= MESA_SHADER_GEOMETRY
; i
++) {
300 anv_batch_emit(batch
, GENX(3DSTATE_URB_VS
), urb
) {
301 urb
._3DCommandSubOpcode
+= i
;
302 urb
.VSURBStartingAddress
= start
[i
];
303 urb
.VSURBEntryAllocationSize
= entry_size
[i
] - 1;
304 urb
.VSNumberofURBEntries
= entries
[i
];
310 emit_urb_setup(struct anv_pipeline
*pipeline
)
312 unsigned entry_size
[4];
313 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
314 const struct brw_vue_prog_data
*prog_data
=
315 !anv_pipeline_has_stage(pipeline
, i
) ? NULL
:
316 (const struct brw_vue_prog_data
*) pipeline
->shaders
[i
]->prog_data
;
318 entry_size
[i
] = prog_data
? prog_data
->urb_entry_size
: 1;
321 genX(emit_urb_setup
)(pipeline
->device
, &pipeline
->batch
,
322 pipeline
->urb
.l3_config
,
323 pipeline
->active_stages
, entry_size
);
327 emit_3dstate_sbe(struct anv_pipeline
*pipeline
)
329 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
331 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
332 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SBE
), sbe
);
334 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SBE_SWIZ
), sbe
);
339 const struct brw_vue_map
*fs_input_map
=
340 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
342 struct GENX(3DSTATE_SBE
) sbe
= {
343 GENX(3DSTATE_SBE_header
),
344 .AttributeSwizzleEnable
= true,
345 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
,
346 .NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
,
347 .ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
,
351 for (unsigned i
= 0; i
< 32; i
++)
352 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
356 /* On Broadwell, they broke 3DSTATE_SBE into two packets */
357 struct GENX(3DSTATE_SBE_SWIZ
) swiz
= {
358 GENX(3DSTATE_SBE_SWIZ_header
),
364 /* Skip the VUE header and position slots by default */
365 unsigned urb_entry_read_offset
= 1;
366 int max_source_attr
= 0;
367 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
368 int input_index
= wm_prog_data
->urb_setup
[attr
];
373 /* gl_Layer is stored in the VUE header */
374 if (attr
== VARYING_SLOT_LAYER
) {
375 urb_entry_read_offset
= 0;
379 if (attr
== VARYING_SLOT_PNTC
) {
380 sbe
.PointSpriteTextureCoordinateEnable
= 1 << input_index
;
384 const int slot
= fs_input_map
->varying_to_slot
[attr
];
386 if (input_index
>= 16)
390 /* This attribute does not exist in the VUE--that means that the
391 * vertex shader did not write to it. It could be that it's a
392 * regular varying read by the fragment shader but not written by
393 * the vertex shader or it's gl_PrimitiveID. In the first case the
394 * value is undefined, in the second it needs to be
397 swiz
.Attribute
[input_index
].ConstantSource
= PRIM_ID
;
398 swiz
.Attribute
[input_index
].ComponentOverrideX
= true;
399 swiz
.Attribute
[input_index
].ComponentOverrideY
= true;
400 swiz
.Attribute
[input_index
].ComponentOverrideZ
= true;
401 swiz
.Attribute
[input_index
].ComponentOverrideW
= true;
403 /* We have to subtract two slots to accout for the URB entry output
404 * read offset in the VS and GS stages.
406 const int source_attr
= slot
- 2 * urb_entry_read_offset
;
407 assert(source_attr
>= 0 && source_attr
< 32);
408 max_source_attr
= MAX2(max_source_attr
, source_attr
);
409 swiz
.Attribute
[input_index
].SourceAttribute
= source_attr
;
413 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
414 sbe
.VertexURBEntryReadLength
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
416 sbe
.ForceVertexURBEntryReadOffset
= true;
417 sbe
.ForceVertexURBEntryReadLength
= true;
420 uint32_t *dw
= anv_batch_emit_dwords(&pipeline
->batch
,
421 GENX(3DSTATE_SBE_length
));
424 GENX(3DSTATE_SBE_pack
)(&pipeline
->batch
, dw
, &sbe
);
427 dw
= anv_batch_emit_dwords(&pipeline
->batch
, GENX(3DSTATE_SBE_SWIZ_length
));
430 GENX(3DSTATE_SBE_SWIZ_pack
)(&pipeline
->batch
, dw
, &swiz
);
434 static const uint32_t vk_to_gen_cullmode
[] = {
435 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
436 [VK_CULL_MODE_FRONT_BIT
] = CULLMODE_FRONT
,
437 [VK_CULL_MODE_BACK_BIT
] = CULLMODE_BACK
,
438 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
441 static const uint32_t vk_to_gen_fillmode
[] = {
442 [VK_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
443 [VK_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
444 [VK_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
447 static const uint32_t vk_to_gen_front_face
[] = {
448 [VK_FRONT_FACE_COUNTER_CLOCKWISE
] = 1,
449 [VK_FRONT_FACE_CLOCKWISE
] = 0
453 emit_rs_state(struct anv_pipeline
*pipeline
,
454 const VkPipelineRasterizationStateCreateInfo
*rs_info
,
455 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
456 const struct anv_render_pass
*pass
,
457 const struct anv_subpass
*subpass
)
459 struct GENX(3DSTATE_SF
) sf
= {
460 GENX(3DSTATE_SF_header
),
463 sf
.ViewportTransformEnable
= true;
464 sf
.StatisticsEnable
= true;
465 sf
.TriangleStripListProvokingVertexSelect
= 0;
466 sf
.LineStripListProvokingVertexSelect
= 0;
467 sf
.TriangleFanProvokingVertexSelect
= 1;
469 const struct brw_vue_prog_data
*last_vue_prog_data
=
470 anv_pipeline_get_last_vue_prog_data(pipeline
);
472 if (last_vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
473 sf
.PointWidthSource
= Vertex
;
475 sf
.PointWidthSource
= State
;
480 struct GENX(3DSTATE_RASTER
) raster
= {
481 GENX(3DSTATE_RASTER_header
),
487 /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
488 * "Multisample Modes State".
491 raster
.DXMultisampleRasterizationEnable
= true;
492 /* NOTE: 3DSTATE_RASTER::ForcedSampleCount affects the BDW and SKL PMA fix
493 * computations. If we ever set this bit to a different value, they will
494 * need to be updated accordingly.
496 raster
.ForcedSampleCount
= FSC_NUMRASTSAMPLES_0
;
497 raster
.ForceMultisampling
= false;
499 raster
.MultisampleRasterizationMode
=
500 (ms_info
&& ms_info
->rasterizationSamples
> 1) ?
501 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
504 raster
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
];
505 raster
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
];
506 raster
.FrontFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
507 raster
.BackFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
508 raster
.ScissorRectangleEnable
= true;
511 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
512 raster
.ViewportZFarClipTestEnable
= !pipeline
->depth_clamp_enable
;
513 raster
.ViewportZNearClipTestEnable
= !pipeline
->depth_clamp_enable
;
515 raster
.ViewportZClipTestEnable
= !pipeline
->depth_clamp_enable
;
518 raster
.GlobalDepthOffsetEnableSolid
= rs_info
->depthBiasEnable
;
519 raster
.GlobalDepthOffsetEnableWireframe
= rs_info
->depthBiasEnable
;
520 raster
.GlobalDepthOffsetEnablePoint
= rs_info
->depthBiasEnable
;
523 /* Gen7 requires that we provide the depth format in 3DSTATE_SF so that it
524 * can get the depth offsets correct.
526 if (subpass
->depth_stencil_attachment
) {
528 pass
->attachments
[subpass
->depth_stencil_attachment
->attachment
].format
;
529 assert(vk_format_is_depth_or_stencil(vk_format
));
530 if (vk_format_aspects(vk_format
) & VK_IMAGE_ASPECT_DEPTH_BIT
) {
531 enum isl_format isl_format
=
532 anv_get_isl_format(&pipeline
->device
->info
, vk_format
,
533 VK_IMAGE_ASPECT_DEPTH_BIT
,
534 VK_IMAGE_TILING_OPTIMAL
);
535 sf
.DepthBufferSurfaceFormat
=
536 isl_format_get_depth_format(isl_format
, false);
542 GENX(3DSTATE_SF_pack
)(NULL
, pipeline
->gen8
.sf
, &sf
);
543 GENX(3DSTATE_RASTER_pack
)(NULL
, pipeline
->gen8
.raster
, &raster
);
546 GENX(3DSTATE_SF_pack
)(NULL
, &pipeline
->gen7
.sf
, &sf
);
551 emit_ms_state(struct anv_pipeline
*pipeline
,
552 const VkPipelineMultisampleStateCreateInfo
*info
)
554 uint32_t samples
= 1;
555 uint32_t log2_samples
= 0;
557 /* From the Vulkan 1.0 spec:
558 * If pSampleMask is NULL, it is treated as if the mask has all bits
559 * enabled, i.e. no coverage is removed from fragments.
561 * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
564 uint32_t sample_mask
= 0xffff;
566 uint32_t sample_mask
= 0xff;
570 samples
= info
->rasterizationSamples
;
571 log2_samples
= __builtin_ffs(samples
) - 1;
574 if (info
&& info
->pSampleMask
)
575 sample_mask
&= info
->pSampleMask
[0];
577 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
578 ms
.NumberofMultisamples
= log2_samples
;
580 ms
.PixelLocation
= CENTER
;
582 /* The PRM says that this bit is valid only for DX9:
584 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
585 * should not have any effect by setting or not setting this bit.
587 ms
.PixelPositionOffsetEnable
= false;
592 GEN_SAMPLE_POS_1X(ms
.Sample
);
595 GEN_SAMPLE_POS_2X(ms
.Sample
);
598 GEN_SAMPLE_POS_4X(ms
.Sample
);
601 GEN_SAMPLE_POS_8X(ms
.Sample
);
609 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
610 sm
.SampleMask
= sample_mask
;
614 static const uint32_t vk_to_gen_logic_op
[] = {
615 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
616 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
617 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
618 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
619 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
620 [VK_LOGIC_OP_NO_OP
] = LOGICOP_NOOP
,
621 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
622 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
623 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
624 [VK_LOGIC_OP_EQUIVALENT
] = LOGICOP_EQUIV
,
625 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
626 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
627 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
628 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
629 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
630 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
633 static const uint32_t vk_to_gen_blend
[] = {
634 [VK_BLEND_FACTOR_ZERO
] = BLENDFACTOR_ZERO
,
635 [VK_BLEND_FACTOR_ONE
] = BLENDFACTOR_ONE
,
636 [VK_BLEND_FACTOR_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
637 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
638 [VK_BLEND_FACTOR_DST_COLOR
] = BLENDFACTOR_DST_COLOR
,
639 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
640 [VK_BLEND_FACTOR_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
641 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
642 [VK_BLEND_FACTOR_DST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
643 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
644 [VK_BLEND_FACTOR_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
645 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
]= BLENDFACTOR_INV_CONST_COLOR
,
646 [VK_BLEND_FACTOR_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
647 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
]= BLENDFACTOR_INV_CONST_ALPHA
,
648 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
649 [VK_BLEND_FACTOR_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
650 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
651 [VK_BLEND_FACTOR_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
652 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
655 static const uint32_t vk_to_gen_blend_op
[] = {
656 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
657 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
658 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
659 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
660 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
663 static const uint32_t vk_to_gen_compare_op
[] = {
664 [VK_COMPARE_OP_NEVER
] = PREFILTEROPNEVER
,
665 [VK_COMPARE_OP_LESS
] = PREFILTEROPLESS
,
666 [VK_COMPARE_OP_EQUAL
] = PREFILTEROPEQUAL
,
667 [VK_COMPARE_OP_LESS_OR_EQUAL
] = PREFILTEROPLEQUAL
,
668 [VK_COMPARE_OP_GREATER
] = PREFILTEROPGREATER
,
669 [VK_COMPARE_OP_NOT_EQUAL
] = PREFILTEROPNOTEQUAL
,
670 [VK_COMPARE_OP_GREATER_OR_EQUAL
] = PREFILTEROPGEQUAL
,
671 [VK_COMPARE_OP_ALWAYS
] = PREFILTEROPALWAYS
,
674 static const uint32_t vk_to_gen_stencil_op
[] = {
675 [VK_STENCIL_OP_KEEP
] = STENCILOP_KEEP
,
676 [VK_STENCIL_OP_ZERO
] = STENCILOP_ZERO
,
677 [VK_STENCIL_OP_REPLACE
] = STENCILOP_REPLACE
,
678 [VK_STENCIL_OP_INCREMENT_AND_CLAMP
] = STENCILOP_INCRSAT
,
679 [VK_STENCIL_OP_DECREMENT_AND_CLAMP
] = STENCILOP_DECRSAT
,
680 [VK_STENCIL_OP_INVERT
] = STENCILOP_INVERT
,
681 [VK_STENCIL_OP_INCREMENT_AND_WRAP
] = STENCILOP_INCR
,
682 [VK_STENCIL_OP_DECREMENT_AND_WRAP
] = STENCILOP_DECR
,
685 /* This function sanitizes the VkStencilOpState by looking at the compare ops
686 * and trying to determine whether or not a given stencil op can ever actually
687 * occur. Stencil ops which can never occur are set to VK_STENCIL_OP_KEEP.
688 * This function returns true if, after sanitation, any of the stencil ops are
689 * set to something other than VK_STENCIL_OP_KEEP.
692 sanitize_stencil_face(VkStencilOpState
*face
,
693 VkCompareOp depthCompareOp
)
695 /* If compareOp is ALWAYS then the stencil test will never fail and failOp
696 * will never happen. Set failOp to KEEP in this case.
698 if (face
->compareOp
== VK_COMPARE_OP_ALWAYS
)
699 face
->failOp
= VK_STENCIL_OP_KEEP
;
701 /* If compareOp is NEVER or depthCompareOp is NEVER then one of the depth
702 * or stencil tests will fail and passOp will never happen.
704 if (face
->compareOp
== VK_COMPARE_OP_NEVER
||
705 depthCompareOp
== VK_COMPARE_OP_NEVER
)
706 face
->passOp
= VK_STENCIL_OP_KEEP
;
708 /* If compareOp is NEVER or depthCompareOp is ALWAYS then either the
709 * stencil test will fail or the depth test will pass. In either case,
710 * depthFailOp will never happen.
712 if (face
->compareOp
== VK_COMPARE_OP_NEVER
||
713 depthCompareOp
== VK_COMPARE_OP_ALWAYS
)
714 face
->depthFailOp
= VK_STENCIL_OP_KEEP
;
716 return face
->failOp
!= VK_STENCIL_OP_KEEP
||
717 face
->depthFailOp
!= VK_STENCIL_OP_KEEP
||
718 face
->passOp
!= VK_STENCIL_OP_KEEP
;
721 /* Intel hardware is fairly sensitive to whether or not depth/stencil writes
722 * are enabled. In the presence of discards, it's fairly easy to get into the
723 * non-promoted case which means a fairly big performance hit. From the Iron
724 * Lake PRM, Vol 2, pt. 1, section 8.4.3.2, "Early Depth Test Cases":
726 * "Non-promoted depth (N) is active whenever the depth test can be done
727 * early but it cannot determine whether or not to write source depth to
728 * the depth buffer, therefore the depth write must be performed post pixel
729 * shader. This includes cases where the pixel shader can kill pixels,
730 * including via sampler chroma key, as well as cases where the alpha test
731 * function is enabled, which kills pixels based on a programmable alpha
732 * test. In this case, even if the depth test fails, the pixel cannot be
733 * killed if a stencil write is indicated. Whether or not the stencil write
734 * happens depends on whether or not the pixel is killed later. In these
735 * cases if stencil test fails and stencil writes are off, the pixels can
736 * also be killed early. If stencil writes are enabled, the pixels must be
737 * treated as Computed depth (described above)."
739 * The same thing as mentioned in the stencil case can happen in the depth
740 * case as well if it thinks it writes depth but, thanks to the depth test
741 * being GL_EQUAL, the write doesn't actually matter. A little extra work
742 * up-front to try and disable depth and stencil writes can make a big
745 * Unfortunately, the way depth and stencil testing is specified, there are
746 * many case where, regardless of depth/stencil writes being enabled, nothing
747 * actually gets written due to some other bit of state being set. This
748 * function attempts to "sanitize" the depth stencil state and disable writes
749 * and sometimes even testing whenever possible.
752 sanitize_ds_state(VkPipelineDepthStencilStateCreateInfo
*state
,
753 bool *stencilWriteEnable
,
754 VkImageAspectFlags ds_aspects
)
756 *stencilWriteEnable
= state
->stencilTestEnable
;
758 /* If the depth test is disabled, we won't be writing anything. */
759 if (!state
->depthTestEnable
)
760 state
->depthWriteEnable
= false;
762 /* The Vulkan spec requires that if either depth or stencil is not present,
763 * the pipeline is to act as if the test silently passes.
765 if (!(ds_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
766 state
->depthWriteEnable
= false;
767 state
->depthCompareOp
= VK_COMPARE_OP_ALWAYS
;
770 if (!(ds_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
771 *stencilWriteEnable
= false;
772 state
->front
.compareOp
= VK_COMPARE_OP_ALWAYS
;
773 state
->back
.compareOp
= VK_COMPARE_OP_ALWAYS
;
776 /* If the stencil test is enabled and always fails, then we will never get
777 * to the depth test so we can just disable the depth test entirely.
779 if (state
->stencilTestEnable
&&
780 state
->front
.compareOp
== VK_COMPARE_OP_NEVER
&&
781 state
->back
.compareOp
== VK_COMPARE_OP_NEVER
) {
782 state
->depthTestEnable
= false;
783 state
->depthWriteEnable
= false;
786 /* If depthCompareOp is EQUAL then the value we would be writing to the
787 * depth buffer is the same as the value that's already there so there's no
788 * point in writing it.
790 if (state
->depthCompareOp
== VK_COMPARE_OP_EQUAL
)
791 state
->depthWriteEnable
= false;
793 /* If the stencil ops are such that we don't actually ever modify the
794 * stencil buffer, we should disable writes.
796 if (!sanitize_stencil_face(&state
->front
, state
->depthCompareOp
) &&
797 !sanitize_stencil_face(&state
->back
, state
->depthCompareOp
))
798 *stencilWriteEnable
= false;
800 /* If the depth test always passes and we never write out depth, that's the
801 * same as if the depth test is disabled entirely.
803 if (state
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
&&
804 !state
->depthWriteEnable
)
805 state
->depthTestEnable
= false;
807 /* If the stencil test always passes and we never write out stencil, that's
808 * the same as if the stencil test is disabled entirely.
810 if (state
->front
.compareOp
== VK_COMPARE_OP_ALWAYS
&&
811 state
->back
.compareOp
== VK_COMPARE_OP_ALWAYS
&&
812 !*stencilWriteEnable
)
813 state
->stencilTestEnable
= false;
817 emit_ds_state(struct anv_pipeline
*pipeline
,
818 const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
,
819 const struct anv_render_pass
*pass
,
820 const struct anv_subpass
*subpass
)
823 # define depth_stencil_dw pipeline->gen7.depth_stencil_state
825 # define depth_stencil_dw pipeline->gen8.wm_depth_stencil
827 # define depth_stencil_dw pipeline->gen9.wm_depth_stencil
830 if (pCreateInfo
== NULL
) {
831 /* We're going to OR this together with the dynamic state. We need
832 * to make sure it's initialized to something useful.
834 pipeline
->writes_stencil
= false;
835 pipeline
->stencil_test_enable
= false;
836 pipeline
->writes_depth
= false;
837 pipeline
->depth_test_enable
= false;
838 memset(depth_stencil_dw
, 0, sizeof(depth_stencil_dw
));
842 VkImageAspectFlags ds_aspects
= 0;
843 if (subpass
->depth_stencil_attachment
) {
844 VkFormat depth_stencil_format
=
845 pass
->attachments
[subpass
->depth_stencil_attachment
->attachment
].format
;
846 ds_aspects
= vk_format_aspects(depth_stencil_format
);
849 VkPipelineDepthStencilStateCreateInfo info
= *pCreateInfo
;
850 sanitize_ds_state(&info
, &pipeline
->writes_stencil
, ds_aspects
);
851 pipeline
->stencil_test_enable
= info
.stencilTestEnable
;
852 pipeline
->writes_depth
= info
.depthWriteEnable
;
853 pipeline
->depth_test_enable
= info
.depthTestEnable
;
855 /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
858 struct GENX(DEPTH_STENCIL_STATE
) depth_stencil
= {
860 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) depth_stencil
= {
862 .DepthTestEnable
= info
.depthTestEnable
,
863 .DepthBufferWriteEnable
= info
.depthWriteEnable
,
864 .DepthTestFunction
= vk_to_gen_compare_op
[info
.depthCompareOp
],
865 .DoubleSidedStencilEnable
= true,
867 .StencilTestEnable
= info
.stencilTestEnable
,
868 .StencilFailOp
= vk_to_gen_stencil_op
[info
.front
.failOp
],
869 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
.front
.passOp
],
870 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
.front
.depthFailOp
],
871 .StencilTestFunction
= vk_to_gen_compare_op
[info
.front
.compareOp
],
872 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
.back
.failOp
],
873 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
.back
.passOp
],
874 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
.back
.depthFailOp
],
875 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
.back
.compareOp
],
879 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
881 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
886 emit_cb_state(struct anv_pipeline
*pipeline
,
887 const VkPipelineColorBlendStateCreateInfo
*info
,
888 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
890 struct anv_device
*device
= pipeline
->device
;
893 struct GENX(BLEND_STATE
) blend_state
= {
895 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
896 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
900 uint32_t surface_count
= 0;
901 struct anv_pipeline_bind_map
*map
;
902 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
903 map
= &pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->bind_map
;
904 surface_count
= map
->surface_count
;
907 const uint32_t num_dwords
= GENX(BLEND_STATE_length
) +
908 GENX(BLEND_STATE_ENTRY_length
) * surface_count
;
909 pipeline
->blend_state
=
910 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
912 bool has_writeable_rt
= false;
913 uint32_t *state_pos
= pipeline
->blend_state
.map
;
914 state_pos
+= GENX(BLEND_STATE_length
);
916 struct GENX(BLEND_STATE_ENTRY
) bs0
= { 0 };
918 for (unsigned i
= 0; i
< surface_count
; i
++) {
919 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[i
];
921 /* All color attachments are at the beginning of the binding table */
922 if (binding
->set
!= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
925 /* We can have at most 8 attachments */
928 if (info
== NULL
|| binding
->index
>= info
->attachmentCount
) {
929 /* Default everything to disabled */
930 struct GENX(BLEND_STATE_ENTRY
) entry
= {
931 .WriteDisableAlpha
= true,
932 .WriteDisableRed
= true,
933 .WriteDisableGreen
= true,
934 .WriteDisableBlue
= true,
936 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, state_pos
, &entry
);
937 state_pos
+= GENX(BLEND_STATE_ENTRY_length
);
941 assert(binding
->binding
== 0);
942 const VkPipelineColorBlendAttachmentState
*a
=
943 &info
->pAttachments
[binding
->index
];
945 struct GENX(BLEND_STATE_ENTRY
) entry
= {
947 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
948 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
950 .LogicOpEnable
= info
->logicOpEnable
,
951 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
952 .ColorBufferBlendEnable
= a
->blendEnable
,
953 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
954 .PreBlendColorClampEnable
= true,
955 .PostBlendColorClampEnable
= true,
956 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcColorBlendFactor
],
957 .DestinationBlendFactor
= vk_to_gen_blend
[a
->dstColorBlendFactor
],
958 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->colorBlendOp
],
959 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcAlphaBlendFactor
],
960 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->dstAlphaBlendFactor
],
961 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->alphaBlendOp
],
962 .WriteDisableAlpha
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_A_BIT
),
963 .WriteDisableRed
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_R_BIT
),
964 .WriteDisableGreen
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_G_BIT
),
965 .WriteDisableBlue
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_B_BIT
),
968 if (a
->srcColorBlendFactor
!= a
->srcAlphaBlendFactor
||
969 a
->dstColorBlendFactor
!= a
->dstAlphaBlendFactor
||
970 a
->colorBlendOp
!= a
->alphaBlendOp
) {
972 blend_state
.IndependentAlphaBlendEnable
= true;
974 entry
.IndependentAlphaBlendEnable
= true;
978 if (a
->colorWriteMask
!= 0)
979 has_writeable_rt
= true;
981 /* Our hardware applies the blend factor prior to the blend function
982 * regardless of what function is used. Technically, this means the
983 * hardware can do MORE than GL or Vulkan specify. However, it also
984 * means that, for MIN and MAX, we have to stomp the blend factor to
985 * ONE to make it a no-op.
987 if (a
->colorBlendOp
== VK_BLEND_OP_MIN
||
988 a
->colorBlendOp
== VK_BLEND_OP_MAX
) {
989 entry
.SourceBlendFactor
= BLENDFACTOR_ONE
;
990 entry
.DestinationBlendFactor
= BLENDFACTOR_ONE
;
992 if (a
->alphaBlendOp
== VK_BLEND_OP_MIN
||
993 a
->alphaBlendOp
== VK_BLEND_OP_MAX
) {
994 entry
.SourceAlphaBlendFactor
= BLENDFACTOR_ONE
;
995 entry
.DestinationAlphaBlendFactor
= BLENDFACTOR_ONE
;
997 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, state_pos
, &entry
);
998 state_pos
+= GENX(BLEND_STATE_ENTRY_length
);
1006 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_BLEND
), blend
) {
1007 blend
.AlphaToCoverageEnable
= blend_state
.AlphaToCoverageEnable
;
1008 blend
.HasWriteableRT
= has_writeable_rt
;
1009 blend
.ColorBufferBlendEnable
= bs0
.ColorBufferBlendEnable
;
1010 blend
.SourceAlphaBlendFactor
= bs0
.SourceAlphaBlendFactor
;
1011 blend
.DestinationAlphaBlendFactor
= bs0
.DestinationAlphaBlendFactor
;
1012 blend
.SourceBlendFactor
= bs0
.SourceBlendFactor
;
1013 blend
.DestinationBlendFactor
= bs0
.DestinationBlendFactor
;
1014 blend
.AlphaTestEnable
= false;
1015 blend
.IndependentAlphaBlendEnable
=
1016 blend_state
.IndependentAlphaBlendEnable
;
1019 (void)has_writeable_rt
;
1022 GENX(BLEND_STATE_pack
)(NULL
, pipeline
->blend_state
.map
, &blend_state
);
1023 anv_state_flush(device
, pipeline
->blend_state
);
1025 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), bsp
) {
1026 bsp
.BlendStatePointer
= pipeline
->blend_state
.offset
;
1028 bsp
.BlendStatePointerValid
= true;
1034 emit_3dstate_clip(struct anv_pipeline
*pipeline
,
1035 const VkPipelineViewportStateCreateInfo
*vp_info
,
1036 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
1038 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1039 (void) wm_prog_data
;
1040 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_CLIP
), clip
) {
1041 clip
.ClipEnable
= true;
1042 clip
.StatisticsEnable
= true;
1043 clip
.EarlyCullEnable
= true;
1044 clip
.APIMode
= APIMODE_D3D
,
1045 clip
.ViewportXYClipTestEnable
= true;
1047 clip
.ClipMode
= CLIPMODE_NORMAL
;
1049 clip
.TriangleStripListProvokingVertexSelect
= 0;
1050 clip
.LineStripListProvokingVertexSelect
= 0;
1051 clip
.TriangleFanProvokingVertexSelect
= 1;
1053 clip
.MinimumPointWidth
= 0.125;
1054 clip
.MaximumPointWidth
= 255.875;
1056 const struct brw_vue_prog_data
*last
=
1057 anv_pipeline_get_last_vue_prog_data(pipeline
);
1059 /* From the Vulkan 1.0.45 spec:
1061 * "If the last active vertex processing stage shader entry point's
1062 * interface does not include a variable decorated with
1063 * ViewportIndex, then the first viewport is used."
1065 if (vp_info
&& (last
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
)) {
1066 clip
.MaximumVPIndex
= vp_info
->viewportCount
- 1;
1068 clip
.MaximumVPIndex
= 0;
1071 /* From the Vulkan 1.0.45 spec:
1073 * "If the last active vertex processing stage shader entry point's
1074 * interface does not include a variable decorated with Layer, then
1075 * the first layer is used."
1077 clip
.ForceZeroRTAIndexEnable
=
1078 !(last
->vue_map
.slots_valid
& VARYING_BIT_LAYER
);
1081 clip
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
];
1082 clip
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
];
1083 clip
.ViewportZClipTestEnable
= !pipeline
->depth_clamp_enable
;
1085 clip
.UserClipDistanceClipTestEnableBitmask
= last
->clip_distance_mask
;
1086 clip
.UserClipDistanceCullTestEnableBitmask
= last
->cull_distance_mask
;
1089 clip
.NonPerspectiveBarycentricEnable
= wm_prog_data
?
1090 (wm_prog_data
->barycentric_interp_modes
&
1091 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
) != 0 : 0;
1097 emit_3dstate_streamout(struct anv_pipeline
*pipeline
,
1098 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
1100 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_STREAMOUT
), so
) {
1101 so
.RenderingDisable
= rs_info
->rasterizerDiscardEnable
;
1106 get_sampler_count(const struct anv_shader_bin
*bin
)
1108 uint32_t count_by_4
= DIV_ROUND_UP(bin
->bind_map
.sampler_count
, 4);
1110 /* We can potentially have way more than 32 samplers and that's ok.
1111 * However, the 3DSTATE_XS packets only have 3 bits to specify how
1112 * many to pre-fetch and all values above 4 are marked reserved.
1114 return MIN2(count_by_4
, 4);
1118 get_binding_table_entry_count(const struct anv_shader_bin
*bin
)
1120 return DIV_ROUND_UP(bin
->bind_map
.surface_count
, 32);
1123 static struct anv_address
1124 get_scratch_address(struct anv_pipeline
*pipeline
,
1125 gl_shader_stage stage
,
1126 const struct anv_shader_bin
*bin
)
1128 return (struct anv_address
) {
1129 .bo
= anv_scratch_pool_alloc(pipeline
->device
,
1130 &pipeline
->device
->scratch_pool
,
1131 stage
, bin
->prog_data
->total_scratch
),
1137 get_scratch_space(const struct anv_shader_bin
*bin
)
1139 return ffs(bin
->prog_data
->total_scratch
/ 2048);
1143 emit_3dstate_vs(struct anv_pipeline
*pipeline
)
1145 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1146 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1147 const struct anv_shader_bin
*vs_bin
=
1148 pipeline
->shaders
[MESA_SHADER_VERTEX
];
1150 assert(anv_pipeline_has_stage(pipeline
, MESA_SHADER_VERTEX
));
1152 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
), vs
) {
1154 vs
.StatisticsEnable
= true;
1155 vs
.KernelStartPointer
= vs_bin
->kernel
.offset
;
1157 vs
.SIMD8DispatchEnable
=
1158 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
1161 assert(!vs_prog_data
->base
.base
.use_alt_mode
);
1163 vs
.SingleVertexDispatch
= false;
1165 vs
.VectorMaskEnable
= false;
1166 vs
.SamplerCount
= get_sampler_count(vs_bin
);
1167 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to
1168 * disable prefetching of binding tables on A0 and B0 steppings.
1169 * TODO: Revisit this WA on newer steppings.
1171 vs
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 : get_binding_table_entry_count(vs_bin
);
1172 vs
.FloatingPointMode
= IEEE754
;
1173 vs
.IllegalOpcodeExceptionEnable
= false;
1174 vs
.SoftwareExceptionEnable
= false;
1175 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1177 if (GEN_GEN
== 9 && devinfo
->gt
== 4 &&
1178 anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
1179 /* On Sky Lake GT4, we have experienced some hangs related to the VS
1180 * cache and tessellation. It is unknown exactly what is happening
1181 * but the Haswell docs for the "VS Reference Count Full Force Miss
1182 * Enable" field of the "Thread Mode" register refer to a HSW bug in
1183 * which the VUE handle reference count would overflow resulting in
1184 * internal reference counting bugs. My (Jason's) best guess is that
1185 * this bug cropped back up on SKL GT4 when we suddenly had more
1186 * threads in play than any previous gen9 hardware.
1188 * What we do know for sure is that setting this bit when
1189 * tessellation shaders are in use fixes a GPU hang in Batman: Arkham
1190 * City when playing with DXVK (https://bugs.freedesktop.org/107280).
1191 * Disabling the vertex cache with tessellation shaders should only
1192 * have a minor performance impact as the tessellation shaders are
1193 * likely generating and processing far more geometry than the vertex
1196 vs
.VertexCacheDisable
= true;
1199 vs
.VertexURBEntryReadLength
= vs_prog_data
->base
.urb_read_length
;
1200 vs
.VertexURBEntryReadOffset
= 0;
1201 vs
.DispatchGRFStartRegisterForURBData
=
1202 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1205 vs
.UserClipDistanceClipTestEnableBitmask
=
1206 vs_prog_data
->base
.clip_distance_mask
;
1207 vs
.UserClipDistanceCullTestEnableBitmask
=
1208 vs_prog_data
->base
.cull_distance_mask
;
1211 vs
.PerThreadScratchSpace
= get_scratch_space(vs_bin
);
1212 vs
.ScratchSpaceBasePointer
=
1213 get_scratch_address(pipeline
, MESA_SHADER_VERTEX
, vs_bin
);
1218 emit_3dstate_hs_te_ds(struct anv_pipeline
*pipeline
,
1219 const VkPipelineTessellationStateCreateInfo
*tess_info
)
1221 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
1222 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_HS
), hs
);
1223 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_TE
), te
);
1224 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_DS
), ds
);
1228 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1229 const struct anv_shader_bin
*tcs_bin
=
1230 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1231 const struct anv_shader_bin
*tes_bin
=
1232 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1234 const struct brw_tcs_prog_data
*tcs_prog_data
= get_tcs_prog_data(pipeline
);
1235 const struct brw_tes_prog_data
*tes_prog_data
= get_tes_prog_data(pipeline
);
1237 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_HS
), hs
) {
1239 hs
.StatisticsEnable
= true;
1240 hs
.KernelStartPointer
= tcs_bin
->kernel
.offset
;
1242 hs
.SamplerCount
= get_sampler_count(tcs_bin
);
1243 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
1244 hs
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 : get_binding_table_entry_count(tcs_bin
);
1245 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1246 hs
.IncludeVertexHandles
= true;
1247 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1249 hs
.VertexURBEntryReadLength
= 0;
1250 hs
.VertexURBEntryReadOffset
= 0;
1251 hs
.DispatchGRFStartRegisterForURBData
=
1252 tcs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1254 hs
.PerThreadScratchSpace
= get_scratch_space(tcs_bin
);
1255 hs
.ScratchSpaceBasePointer
=
1256 get_scratch_address(pipeline
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
1259 const VkPipelineTessellationDomainOriginStateCreateInfoKHR
*domain_origin_state
=
1260 tess_info
? vk_find_struct_const(tess_info
, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR
) : NULL
;
1262 VkTessellationDomainOriginKHR uv_origin
=
1263 domain_origin_state
? domain_origin_state
->domainOrigin
:
1264 VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR
;
1266 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_TE
), te
) {
1267 te
.Partitioning
= tes_prog_data
->partitioning
;
1269 if (uv_origin
== VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT_KHR
) {
1270 te
.OutputTopology
= tes_prog_data
->output_topology
;
1272 /* When the origin is upper-left, we have to flip the winding order */
1273 if (tes_prog_data
->output_topology
== OUTPUT_TRI_CCW
) {
1274 te
.OutputTopology
= OUTPUT_TRI_CW
;
1275 } else if (tes_prog_data
->output_topology
== OUTPUT_TRI_CW
) {
1276 te
.OutputTopology
= OUTPUT_TRI_CCW
;
1278 te
.OutputTopology
= tes_prog_data
->output_topology
;
1282 te
.TEDomain
= tes_prog_data
->domain
;
1284 te
.MaximumTessellationFactorOdd
= 63.0;
1285 te
.MaximumTessellationFactorNotOdd
= 64.0;
1288 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_DS
), ds
) {
1290 ds
.StatisticsEnable
= true;
1291 ds
.KernelStartPointer
= tes_bin
->kernel
.offset
;
1293 ds
.SamplerCount
= get_sampler_count(tes_bin
);
1294 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
1295 ds
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 : get_binding_table_entry_count(tes_bin
);
1296 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
1298 ds
.ComputeWCoordinateEnable
=
1299 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
1301 ds
.PatchURBEntryReadLength
= tes_prog_data
->base
.urb_read_length
;
1302 ds
.PatchURBEntryReadOffset
= 0;
1303 ds
.DispatchGRFStartRegisterForURBData
=
1304 tes_prog_data
->base
.base
.dispatch_grf_start_reg
;
1309 tes_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
?
1310 DISPATCH_MODE_SIMD8_SINGLE_PATCH
:
1311 DISPATCH_MODE_SIMD4X2
;
1313 assert(tes_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
);
1314 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
1317 ds
.UserClipDistanceClipTestEnableBitmask
=
1318 tes_prog_data
->base
.clip_distance_mask
;
1319 ds
.UserClipDistanceCullTestEnableBitmask
=
1320 tes_prog_data
->base
.cull_distance_mask
;
1323 ds
.PerThreadScratchSpace
= get_scratch_space(tes_bin
);
1324 ds
.ScratchSpaceBasePointer
=
1325 get_scratch_address(pipeline
, MESA_SHADER_TESS_EVAL
, tes_bin
);
1330 emit_3dstate_gs(struct anv_pipeline
*pipeline
)
1332 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1333 const struct anv_shader_bin
*gs_bin
=
1334 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1336 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
)) {
1337 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), gs
);
1341 const struct brw_gs_prog_data
*gs_prog_data
= get_gs_prog_data(pipeline
);
1343 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), gs
) {
1345 gs
.StatisticsEnable
= true;
1346 gs
.KernelStartPointer
= gs_bin
->kernel
.offset
;
1347 gs
.DispatchMode
= gs_prog_data
->base
.dispatch_mode
;
1349 gs
.SingleProgramFlow
= false;
1350 gs
.VectorMaskEnable
= false;
1351 gs
.SamplerCount
= get_sampler_count(gs_bin
);
1352 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
1353 gs
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 : get_binding_table_entry_count(gs_bin
);
1354 gs
.IncludeVertexHandles
= gs_prog_data
->base
.include_vue_handles
;
1355 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
1358 /* Broadwell is weird. It needs us to divide by 2. */
1359 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
/ 2 - 1;
1361 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
1364 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
1365 gs
.OutputTopology
= gs_prog_data
->output_topology
;
1366 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1367 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
1368 gs
.ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
;
1369 gs
.InstanceControl
= MAX2(gs_prog_data
->invocations
, 1) - 1;
1370 gs
.ReorderMode
= TRAILING
;
1373 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
1374 gs
.StaticOutput
= gs_prog_data
->static_vertex_count
>= 0;
1375 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
>= 0 ?
1376 gs_prog_data
->static_vertex_count
: 0;
1379 gs
.VertexURBEntryReadOffset
= 0;
1380 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1381 gs
.DispatchGRFStartRegisterForURBData
=
1382 gs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1385 gs
.UserClipDistanceClipTestEnableBitmask
=
1386 gs_prog_data
->base
.clip_distance_mask
;
1387 gs
.UserClipDistanceCullTestEnableBitmask
=
1388 gs_prog_data
->base
.cull_distance_mask
;
1391 gs
.PerThreadScratchSpace
= get_scratch_space(gs_bin
);
1392 gs
.ScratchSpaceBasePointer
=
1393 get_scratch_address(pipeline
, MESA_SHADER_GEOMETRY
, gs_bin
);
1398 has_color_buffer_write_enabled(const struct anv_pipeline
*pipeline
,
1399 const VkPipelineColorBlendStateCreateInfo
*blend
)
1401 const struct anv_shader_bin
*shader_bin
=
1402 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1406 const struct anv_pipeline_bind_map
*bind_map
= &shader_bin
->bind_map
;
1407 for (int i
= 0; i
< bind_map
->surface_count
; i
++) {
1408 struct anv_pipeline_binding
*binding
= &bind_map
->surface_to_descriptor
[i
];
1410 if (binding
->set
!= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
1413 if (binding
->index
== UINT32_MAX
)
1416 if (blend
&& blend
->pAttachments
[binding
->index
].colorWriteMask
!= 0)
1424 emit_3dstate_wm(struct anv_pipeline
*pipeline
, struct anv_subpass
*subpass
,
1425 const VkPipelineColorBlendStateCreateInfo
*blend
,
1426 const VkPipelineMultisampleStateCreateInfo
*multisample
)
1428 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1430 MAYBE_UNUSED
uint32_t samples
=
1431 multisample
? multisample
->rasterizationSamples
: 1;
1433 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_WM
), wm
) {
1434 wm
.StatisticsEnable
= true;
1435 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1436 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1437 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1439 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1440 if (wm_prog_data
->early_fragment_tests
) {
1441 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1442 } else if (wm_prog_data
->has_side_effects
) {
1443 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1445 wm
.EarlyDepthStencilControl
= EDSC_NORMAL
;
1449 /* Gen8 and later hardware tries to compute ThreadDispatchEnable for
1450 * us but doesn't take into account KillPixels when no depth or
1451 * stencil writes are enabled. In order for occlusion queries to
1452 * work correctly with no attachments, we need to force-enable PS
1455 * The BDW docs are pretty clear that that this bit isn't validated
1456 * and probably shouldn't be used in production:
1458 * "This must always be set to Normal. This field should not be
1459 * tested for functional validation."
1461 * Unfortunately, however, the other mechanism we have for doing this
1462 * is 3DSTATE_PS_EXTRA::PixelShaderHasUAV which causes hangs on BDW.
1463 * Given two bad options, we choose the one which works. On Skylake
1464 * and later, setting ForceThreadDispatchEnable causes GPU hangs so
1465 * we use the PixelShaderHasUAV mechanism there.
1467 if ((wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
) &&
1468 !has_color_buffer_write_enabled(pipeline
, blend
))
1469 wm
.ForceThreadDispatchEnable
= ForceON
;
1472 wm
.BarycentricInterpolationMode
=
1473 wm_prog_data
->barycentric_interp_modes
;
1476 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1477 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1478 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1479 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1481 /* If the subpass has a depth or stencil self-dependency, then we
1482 * need to force the hardware to do the depth/stencil write *after*
1483 * fragment shader execution. Otherwise, the writes may hit memory
1484 * before we get around to fetching from the input attachment and we
1485 * may get the depth or stencil value from the current draw rather
1486 * than the previous one.
1488 wm
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
1489 wm_prog_data
->uses_kill
;
1491 if (wm
.PixelShaderComputedDepthMode
!= PSCDEPTH_OFF
||
1492 wm_prog_data
->has_side_effects
||
1493 wm
.PixelShaderKillsPixel
||
1494 has_color_buffer_write_enabled(pipeline
, blend
))
1495 wm
.ThreadDispatchEnable
= true;
1498 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1499 if (wm_prog_data
->persample_dispatch
) {
1500 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1502 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1505 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1506 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1514 is_dual_src_blend_factor(VkBlendFactor factor
)
1516 return factor
== VK_BLEND_FACTOR_SRC1_COLOR
||
1517 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
||
1518 factor
== VK_BLEND_FACTOR_SRC1_ALPHA
||
1519 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
;
1523 emit_3dstate_ps(struct anv_pipeline
*pipeline
,
1524 const VkPipelineColorBlendStateCreateInfo
*blend
,
1525 const VkPipelineMultisampleStateCreateInfo
*multisample
)
1527 MAYBE_UNUSED
const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1528 const struct anv_shader_bin
*fs_bin
=
1529 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1531 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1532 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
), ps
) {
1534 /* Even if no fragments are ever dispatched, gen7 hardware hangs if
1535 * we don't at least set the maximum number of threads.
1537 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1543 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1546 /* The hardware wedges if you have this bit set but don't turn on any dual
1547 * source blend factors.
1549 bool dual_src_blend
= false;
1550 if (wm_prog_data
->dual_src_blend
&& blend
) {
1551 for (uint32_t i
= 0; i
< blend
->attachmentCount
; i
++) {
1552 const VkPipelineColorBlendAttachmentState
*bstate
=
1553 &blend
->pAttachments
[i
];
1555 if (bstate
->blendEnable
&&
1556 (is_dual_src_blend_factor(bstate
->srcColorBlendFactor
) ||
1557 is_dual_src_blend_factor(bstate
->dstColorBlendFactor
) ||
1558 is_dual_src_blend_factor(bstate
->srcAlphaBlendFactor
) ||
1559 is_dual_src_blend_factor(bstate
->dstAlphaBlendFactor
))) {
1560 dual_src_blend
= true;
1567 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
), ps
) {
1568 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1569 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1570 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1572 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
1574 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
1575 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
1577 * Since 16x MSAA is first introduced on SKL, we don't need to apply
1578 * the workaround on any older hardware.
1580 if (GEN_GEN
>= 9 && !wm_prog_data
->persample_dispatch
&&
1581 multisample
&& multisample
->rasterizationSamples
== 16) {
1582 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
1583 ps
._32PixelDispatchEnable
= false;
1586 ps
.KernelStartPointer0
= fs_bin
->kernel
.offset
+
1587 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
1588 ps
.KernelStartPointer1
= fs_bin
->kernel
.offset
+
1589 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
1590 ps
.KernelStartPointer2
= fs_bin
->kernel
.offset
+
1591 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
1593 ps
.SingleProgramFlow
= false;
1594 ps
.VectorMaskEnable
= true;
1595 ps
.SamplerCount
= get_sampler_count(fs_bin
);
1596 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
1597 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 : get_binding_table_entry_count(fs_bin
);
1598 ps
.PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0 ||
1599 wm_prog_data
->base
.ubo_ranges
[0].length
;
1600 ps
.PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
1601 POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
1603 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
1604 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1605 ps
.DualSourceBlendEnable
= dual_src_blend
;
1609 /* Haswell requires the sample mask to be set in this packet as well
1610 * as in 3DSTATE_SAMPLE_MASK; the values should match.
1612 ps
.SampleMask
= 0xff;
1616 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
1618 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
1620 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1623 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
1624 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
1625 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
1626 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
1627 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
1628 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
1630 ps
.PerThreadScratchSpace
= get_scratch_space(fs_bin
);
1631 ps
.ScratchSpaceBasePointer
=
1632 get_scratch_address(pipeline
, MESA_SHADER_FRAGMENT
, fs_bin
);
1638 emit_3dstate_ps_extra(struct anv_pipeline
*pipeline
,
1639 struct anv_subpass
*subpass
,
1640 const VkPipelineColorBlendStateCreateInfo
*blend
)
1642 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1644 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1645 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
), ps
);
1649 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
), ps
) {
1650 ps
.PixelShaderValid
= true;
1651 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
1652 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1653 ps
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
1654 ps
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1655 ps
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1656 ps
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1658 /* If the subpass has a depth or stencil self-dependency, then we need
1659 * to force the hardware to do the depth/stencil write *after* fragment
1660 * shader execution. Otherwise, the writes may hit memory before we get
1661 * around to fetching from the input attachment and we may get the depth
1662 * or stencil value from the current draw rather than the previous one.
1664 ps
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
1665 wm_prog_data
->uses_kill
;
1668 /* Gen8 and later hardware tries to compute ThreadDispatchEnable for us
1669 * but doesn't take into account KillPixels when no depth or stencil
1670 * writes are enabled. In order for occlusion queries to work correctly
1671 * with no attachments, we need to force-enable PS thread dispatch.
1673 * The stricter cross-primitive coherency guarantees that the hardware
1674 * gives us with the "Accesses UAV" bit set for at least one shader stage
1675 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command are
1676 * redundant within the current image, atomic counter and SSBO GL and
1677 * Vulkan APIs, which all have very loose ordering and coherency
1678 * requirements and generally rely on the application to insert explicit
1679 * barriers when a shader invocation is expected to see the memory
1680 * writes performed by the invocations of some previous primitive.
1681 * Regardless of the value of "UAV coherency required", the "Accesses
1682 * UAV" bits will implicitly cause an in most cases useless DC flush
1683 * when the lowermost stage with the bit set finishes execution.
1685 * Unfortunately, however, the other mechanism we have for doing this is
1686 * 3DSTATE_WM::ForceThreadDispatchEnable which causes GPU hangs on
1687 * Skylake and later hardware. On Broadwell, however, setting this bit
1688 * causes GPU hangs so we use ForceThreadDispatchEnable there.
1690 if ((wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
) &&
1691 !has_color_buffer_write_enabled(pipeline
, blend
))
1692 ps
.PixelShaderHasUAV
= true;
1694 ps
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
1695 ps
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
1697 ps
.InputCoverageMaskState
= ICMS_NONE
;
1698 if (wm_prog_data
->uses_sample_mask
) {
1699 if (wm_prog_data
->post_depth_coverage
)
1700 ps
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
1702 ps
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
1705 ps
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1711 emit_3dstate_vf_topology(struct anv_pipeline
*pipeline
)
1713 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_TOPOLOGY
), vft
) {
1714 vft
.PrimitiveTopologyType
= pipeline
->topology
;
1720 emit_3dstate_vf_statistics(struct anv_pipeline
*pipeline
)
1722 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_STATISTICS
), vfs
) {
1723 vfs
.StatisticsEnable
= true;
1728 compute_kill_pixel(struct anv_pipeline
*pipeline
,
1729 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
1730 const struct anv_subpass
*subpass
)
1732 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1733 pipeline
->kill_pixel
= false;
1737 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1739 /* This computes the KillPixel portion of the computation for whether or
1740 * not we want to enable the PMA fix on gen8 or gen9. It's given by this
1741 * chunk of the giant formula:
1743 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
1744 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
1745 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
1746 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
1747 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
1749 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false and so is
1750 * 3DSTATE_PS_BLEND::AlphaTestEnable since Vulkan doesn't have a concept
1753 pipeline
->kill_pixel
=
1754 subpass
->has_ds_self_dep
|| wm_prog_data
->uses_kill
||
1755 wm_prog_data
->uses_omask
||
1756 (ms_info
&& ms_info
->alphaToCoverageEnable
);
1760 genX(graphics_pipeline_create
)(
1762 struct anv_pipeline_cache
* cache
,
1763 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
1764 const VkAllocationCallbacks
* pAllocator
,
1765 VkPipeline
* pPipeline
)
1767 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1768 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
1769 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1770 struct anv_pipeline
*pipeline
;
1773 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1775 /* Use the default pipeline cache if none is specified */
1776 if (cache
== NULL
&& device
->instance
->pipeline_cache_enabled
)
1777 cache
= &device
->default_pipeline_cache
;
1779 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1780 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1781 if (pipeline
== NULL
)
1782 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1784 result
= anv_pipeline_init(pipeline
, device
, cache
,
1785 pCreateInfo
, pAllocator
);
1786 if (result
!= VK_SUCCESS
) {
1787 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
1791 assert(pCreateInfo
->pVertexInputState
);
1792 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
);
1793 assert(pCreateInfo
->pRasterizationState
);
1794 emit_rs_state(pipeline
, pCreateInfo
->pRasterizationState
,
1795 pCreateInfo
->pMultisampleState
, pass
, subpass
);
1796 emit_ms_state(pipeline
, pCreateInfo
->pMultisampleState
);
1797 emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
, pass
, subpass
);
1798 emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
,
1799 pCreateInfo
->pMultisampleState
);
1800 compute_kill_pixel(pipeline
, pCreateInfo
->pMultisampleState
, subpass
);
1802 emit_urb_setup(pipeline
);
1804 emit_3dstate_clip(pipeline
, pCreateInfo
->pViewportState
,
1805 pCreateInfo
->pRasterizationState
);
1806 emit_3dstate_streamout(pipeline
, pCreateInfo
->pRasterizationState
);
1809 /* From gen7_vs_state.c */
1812 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
1813 * Geometry > Geometry Shader > State:
1815 * "Note: Because of corruption in IVB:GT2, software needs to flush the
1816 * whole fixed function pipeline when the GS enable changes value in
1819 * The hardware architects have clarified that in this context "flush the
1820 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
1823 if (!device
->info
.is_haswell
&& !device
->info
.is_baytrail
)
1824 gen7_emit_vs_workaround_flush(brw
);
1827 emit_3dstate_vs(pipeline
);
1828 emit_3dstate_hs_te_ds(pipeline
, pCreateInfo
->pTessellationState
);
1829 emit_3dstate_gs(pipeline
);
1830 emit_3dstate_sbe(pipeline
);
1831 emit_3dstate_wm(pipeline
, subpass
, pCreateInfo
->pColorBlendState
,
1832 pCreateInfo
->pMultisampleState
);
1833 emit_3dstate_ps(pipeline
, pCreateInfo
->pColorBlendState
,
1834 pCreateInfo
->pMultisampleState
);
1836 emit_3dstate_ps_extra(pipeline
, subpass
, pCreateInfo
->pColorBlendState
);
1837 emit_3dstate_vf_topology(pipeline
);
1839 emit_3dstate_vf_statistics(pipeline
);
1841 *pPipeline
= anv_pipeline_to_handle(pipeline
);
1843 return pipeline
->batch
.status
;
1847 compute_pipeline_create(
1849 struct anv_pipeline_cache
* cache
,
1850 const VkComputePipelineCreateInfo
* pCreateInfo
,
1851 const VkAllocationCallbacks
* pAllocator
,
1852 VkPipeline
* pPipeline
)
1854 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1855 const struct anv_physical_device
*physical_device
=
1856 &device
->instance
->physicalDevice
;
1857 const struct gen_device_info
*devinfo
= &physical_device
->info
;
1858 struct anv_pipeline
*pipeline
;
1861 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
);
1863 /* Use the default pipeline cache if none is specified */
1864 if (cache
== NULL
&& device
->instance
->pipeline_cache_enabled
)
1865 cache
= &device
->default_pipeline_cache
;
1867 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1868 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1869 if (pipeline
== NULL
)
1870 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1872 pipeline
->device
= device
;
1874 pipeline
->blend_state
.map
= NULL
;
1876 result
= anv_reloc_list_init(&pipeline
->batch_relocs
,
1877 pAllocator
? pAllocator
: &device
->alloc
);
1878 if (result
!= VK_SUCCESS
) {
1879 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
1882 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1883 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1884 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1885 pipeline
->batch
.status
= VK_SUCCESS
;
1887 /* When we free the pipeline, we detect stages based on the NULL status
1888 * of various prog_data pointers. Make them NULL by default.
1890 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1892 pipeline
->needs_data_cache
= false;
1894 assert(pCreateInfo
->stage
.stage
== VK_SHADER_STAGE_COMPUTE_BIT
);
1895 pipeline
->active_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
1896 ANV_FROM_HANDLE(anv_shader_module
, module
, pCreateInfo
->stage
.module
);
1897 result
= anv_pipeline_compile_cs(pipeline
, cache
, pCreateInfo
, module
,
1898 pCreateInfo
->stage
.pName
,
1899 pCreateInfo
->stage
.pSpecializationInfo
);
1900 if (result
!= VK_SUCCESS
) {
1901 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
1905 const struct brw_cs_prog_data
*cs_prog_data
= get_cs_prog_data(pipeline
);
1907 anv_pipeline_setup_l3_config(pipeline
, cs_prog_data
->base
.total_shared
> 0);
1909 uint32_t group_size
= cs_prog_data
->local_size
[0] *
1910 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
1911 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
1914 pipeline
->cs_right_mask
= ~0u >> (32 - remainder
);
1916 pipeline
->cs_right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
1918 const uint32_t vfe_curbe_allocation
=
1919 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
1920 cs_prog_data
->push
.cross_thread
.regs
, 2);
1922 const uint32_t subslices
= MAX2(physical_device
->subslice_total
, 1);
1924 const struct anv_shader_bin
*cs_bin
=
1925 pipeline
->shaders
[MESA_SHADER_COMPUTE
];
1927 anv_batch_emit(&pipeline
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
1931 vfe
.GPGPUMode
= true;
1933 vfe
.MaximumNumberofThreads
=
1934 devinfo
->max_cs_threads
* subslices
- 1;
1935 vfe
.NumberofURBEntries
= GEN_GEN
<= 7 ? 0 : 2;
1937 vfe
.ResetGatewayTimer
= true;
1940 vfe
.BypassGatewayControl
= true;
1942 vfe
.URBEntryAllocationSize
= GEN_GEN
<= 7 ? 0 : 2;
1943 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
1945 vfe
.PerThreadScratchSpace
= get_scratch_space(cs_bin
);
1946 vfe
.ScratchSpaceBasePointer
=
1947 get_scratch_address(pipeline
, MESA_SHADER_COMPUTE
, cs_bin
);
1950 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1951 .KernelStartPointer
= cs_bin
->kernel
.offset
,
1953 .SamplerCount
= get_sampler_count(cs_bin
),
1954 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
1955 .BindingTableEntryCount
= GEN_GEN
== 11 ? 0 : get_binding_table_entry_count(cs_bin
),
1956 .BarrierEnable
= cs_prog_data
->uses_barrier
,
1957 .SharedLocalMemorySize
=
1958 encode_slm_size(GEN_GEN
, cs_prog_data
->base
.total_shared
),
1961 .ConstantURBEntryReadOffset
= 0,
1963 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
1964 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1965 .CrossThreadConstantDataReadLength
=
1966 cs_prog_data
->push
.cross_thread
.regs
,
1969 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
1971 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
,
1972 pipeline
->interface_descriptor_data
,
1975 *pPipeline
= anv_pipeline_to_handle(pipeline
);
1977 return pipeline
->batch
.status
;
1980 VkResult
genX(CreateGraphicsPipelines
)(
1982 VkPipelineCache pipelineCache
,
1984 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
1985 const VkAllocationCallbacks
* pAllocator
,
1986 VkPipeline
* pPipelines
)
1988 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
1990 VkResult result
= VK_SUCCESS
;
1993 for (i
= 0; i
< count
; i
++) {
1994 result
= genX(graphics_pipeline_create
)(_device
,
1997 pAllocator
, &pPipelines
[i
]);
1999 /* Bail out on the first error as it is not obvious what error should be
2000 * report upon 2 different failures. */
2001 if (result
!= VK_SUCCESS
)
2005 for (; i
< count
; i
++)
2006 pPipelines
[i
] = VK_NULL_HANDLE
;
2011 VkResult
genX(CreateComputePipelines
)(
2013 VkPipelineCache pipelineCache
,
2015 const VkComputePipelineCreateInfo
* pCreateInfos
,
2016 const VkAllocationCallbacks
* pAllocator
,
2017 VkPipeline
* pPipelines
)
2019 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
2021 VkResult result
= VK_SUCCESS
;
2024 for (i
= 0; i
< count
; i
++) {
2025 result
= compute_pipeline_create(_device
, pipeline_cache
,
2027 pAllocator
, &pPipelines
[i
]);
2029 /* Bail out on the first error as it is not obvious what error should be
2030 * report upon 2 different failures. */
2031 if (result
!= VK_SUCCESS
)
2035 for (; i
< count
; i
++)
2036 pPipelines
[i
] = VK_NULL_HANDLE
;