2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
26 #include "genxml/gen_macros.h"
27 #include "genxml/genX_pack.h"
29 #include "common/gen_l3_config.h"
30 #include "common/gen_sample_positions.h"
31 #include "nir/nir_xfb_info.h"
33 #include "vk_format_info.h"
36 vertex_element_comp_control(enum isl_format format
, unsigned comp
)
40 case 0: bits
= isl_format_layouts
[format
].channels
.r
.bits
; break;
41 case 1: bits
= isl_format_layouts
[format
].channels
.g
.bits
; break;
42 case 2: bits
= isl_format_layouts
[format
].channels
.b
.bits
; break;
43 case 3: bits
= isl_format_layouts
[format
].channels
.a
.bits
; break;
44 default: unreachable("Invalid component");
48 * Take in account hardware restrictions when dealing with 64-bit floats.
50 * From Broadwell spec, command reference structures, page 586:
51 * "When SourceElementFormat is set to one of the *64*_PASSTHRU formats,
52 * 64-bit components are stored * in the URB without any conversion. In
53 * this case, vertex elements must be written as 128 or 256 bits, with
54 * VFCOMP_STORE_0 being used to pad the output as required. E.g., if
55 * R64_PASSTHRU is used to copy a 64-bit Red component into the URB,
56 * Component 1 must be specified as VFCOMP_STORE_0 (with Components 2,3
57 * set to VFCOMP_NOSTORE) in order to output a 128-bit vertex element, or
58 * Components 1-3 must be specified as VFCOMP_STORE_0 in order to output
59 * a 256-bit vertex element. Likewise, use of R64G64B64_PASSTHRU requires
60 * Component 3 to be specified as VFCOMP_STORE_0 in order to output a
61 * 256-bit vertex element."
64 return VFCOMP_STORE_SRC
;
65 } else if (comp
>= 2 &&
66 !isl_format_layouts
[format
].channels
.b
.bits
&&
67 isl_format_layouts
[format
].channels
.r
.type
== ISL_RAW
) {
68 /* When emitting 64-bit attributes, we need to write either 128 or 256
69 * bit chunks, using VFCOMP_NOSTORE when not writing the chunk, and
70 * VFCOMP_STORE_0 to pad the written chunk */
71 return VFCOMP_NOSTORE
;
72 } else if (comp
< 3 ||
73 isl_format_layouts
[format
].channels
.r
.type
== ISL_RAW
) {
74 /* Note we need to pad with value 0, not 1, due hardware restrictions
75 * (see comment above) */
76 return VFCOMP_STORE_0
;
77 } else if (isl_format_layouts
[format
].channels
.r
.type
== ISL_UINT
||
78 isl_format_layouts
[format
].channels
.r
.type
== ISL_SINT
) {
80 return VFCOMP_STORE_1_INT
;
83 return VFCOMP_STORE_1_FP
;
88 emit_vertex_input(struct anv_pipeline
*pipeline
,
89 const VkPipelineVertexInputStateCreateInfo
*info
)
91 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
93 /* Pull inputs_read out of the VS prog data */
94 const uint64_t inputs_read
= vs_prog_data
->inputs_read
;
95 const uint64_t double_inputs_read
=
96 vs_prog_data
->double_inputs_read
& inputs_read
;
97 assert((inputs_read
& ((1 << VERT_ATTRIB_GENERIC0
) - 1)) == 0);
98 const uint32_t elements
= inputs_read
>> VERT_ATTRIB_GENERIC0
;
99 const uint32_t elements_double
= double_inputs_read
>> VERT_ATTRIB_GENERIC0
;
100 const bool needs_svgs_elem
= vs_prog_data
->uses_vertexid
||
101 vs_prog_data
->uses_instanceid
||
102 vs_prog_data
->uses_firstvertex
||
103 vs_prog_data
->uses_baseinstance
;
105 uint32_t elem_count
= __builtin_popcount(elements
) -
106 __builtin_popcount(elements_double
) / 2;
108 const uint32_t total_elems
=
109 MAX2(1, elem_count
+ needs_svgs_elem
+ vs_prog_data
->uses_drawid
);
113 const uint32_t num_dwords
= 1 + total_elems
* 2;
114 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
115 GENX(3DSTATE_VERTEX_ELEMENTS
));
119 for (uint32_t i
= 0; i
< total_elems
; i
++) {
120 /* The SKL docs for VERTEX_ELEMENT_STATE say:
122 * "All elements must be valid from Element[0] to the last valid
123 * element. (I.e. if Element[2] is valid then Element[1] and
124 * Element[0] must also be valid)."
126 * The SKL docs for 3D_Vertex_Component_Control say:
128 * "Don't store this component. (Not valid for Component 0, but can
129 * be used for Component 1-3)."
131 * So we can't just leave a vertex element blank and hope for the best.
132 * We have to tell the VF hardware to put something in it; so we just
133 * store a bunch of zero.
135 * TODO: Compact vertex elements so we never end up with holes.
137 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
139 .Component0Control
= VFCOMP_STORE_0
,
140 .Component1Control
= VFCOMP_STORE_0
,
141 .Component2Control
= VFCOMP_STORE_0
,
142 .Component3Control
= VFCOMP_STORE_0
,
144 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + i
* 2], &element
);
147 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
148 const VkVertexInputAttributeDescription
*desc
=
149 &info
->pVertexAttributeDescriptions
[i
];
150 enum isl_format format
= anv_get_isl_format(&pipeline
->device
->info
,
152 VK_IMAGE_ASPECT_COLOR_BIT
,
153 VK_IMAGE_TILING_LINEAR
);
155 assert(desc
->binding
< MAX_VBS
);
157 if ((elements
& (1 << desc
->location
)) == 0)
158 continue; /* Binding unused */
161 __builtin_popcount(elements
& ((1 << desc
->location
) - 1)) -
162 DIV_ROUND_UP(__builtin_popcount(elements_double
&
163 ((1 << desc
->location
) -1)), 2);
165 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
166 .VertexBufferIndex
= desc
->binding
,
168 .SourceElementFormat
= format
,
169 .EdgeFlagEnable
= false,
170 .SourceElementOffset
= desc
->offset
,
171 .Component0Control
= vertex_element_comp_control(format
, 0),
172 .Component1Control
= vertex_element_comp_control(format
, 1),
173 .Component2Control
= vertex_element_comp_control(format
, 2),
174 .Component3Control
= vertex_element_comp_control(format
, 3),
176 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + slot
* 2], &element
);
179 /* On Broadwell and later, we have a separate VF_INSTANCING packet
180 * that controls instancing. On Haswell and prior, that's part of
181 * VERTEX_BUFFER_STATE which we emit later.
183 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
184 vfi
.InstancingEnable
= pipeline
->vb
[desc
->binding
].instanced
;
185 vfi
.VertexElementIndex
= slot
;
186 vfi
.InstanceDataStepRate
=
187 pipeline
->vb
[desc
->binding
].instance_divisor
;
192 const uint32_t id_slot
= elem_count
;
193 if (needs_svgs_elem
) {
194 /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
195 * "Within a VERTEX_ELEMENT_STATE structure, if a Component
196 * Control field is set to something other than VFCOMP_STORE_SRC,
197 * no higher-numbered Component Control fields may be set to
200 * This means, that if we have BaseInstance, we need BaseVertex as
201 * well. Just do all or nothing.
203 uint32_t base_ctrl
= (vs_prog_data
->uses_firstvertex
||
204 vs_prog_data
->uses_baseinstance
) ?
205 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
207 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
208 .VertexBufferIndex
= ANV_SVGS_VB_INDEX
,
210 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
211 .Component0Control
= base_ctrl
,
212 .Component1Control
= base_ctrl
,
214 .Component2Control
= VFCOMP_STORE_0
,
215 .Component3Control
= VFCOMP_STORE_0
,
217 .Component2Control
= VFCOMP_STORE_VID
,
218 .Component3Control
= VFCOMP_STORE_IID
,
221 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + id_slot
* 2], &element
);
225 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
226 sgvs
.VertexIDEnable
= vs_prog_data
->uses_vertexid
;
227 sgvs
.VertexIDComponentNumber
= 2;
228 sgvs
.VertexIDElementOffset
= id_slot
;
229 sgvs
.InstanceIDEnable
= vs_prog_data
->uses_instanceid
;
230 sgvs
.InstanceIDComponentNumber
= 3;
231 sgvs
.InstanceIDElementOffset
= id_slot
;
235 const uint32_t drawid_slot
= elem_count
+ needs_svgs_elem
;
236 if (vs_prog_data
->uses_drawid
) {
237 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
238 .VertexBufferIndex
= ANV_DRAWID_VB_INDEX
,
240 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
241 .Component0Control
= VFCOMP_STORE_SRC
,
242 .Component1Control
= VFCOMP_STORE_0
,
243 .Component2Control
= VFCOMP_STORE_0
,
244 .Component3Control
= VFCOMP_STORE_0
,
246 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
,
247 &p
[1 + drawid_slot
* 2],
251 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
252 vfi
.VertexElementIndex
= drawid_slot
;
259 genX(emit_urb_setup
)(struct anv_device
*device
, struct anv_batch
*batch
,
260 const struct gen_l3_config
*l3_config
,
261 VkShaderStageFlags active_stages
,
262 const unsigned entry_size
[4])
264 const struct gen_device_info
*devinfo
= &device
->info
;
266 const unsigned push_constant_kb
= devinfo
->gt
== 3 ? 32 : 16;
268 const unsigned push_constant_kb
= GEN_GEN
>= 8 ? 32 : 16;
271 const unsigned urb_size_kb
= gen_get_l3_config_urb_size(devinfo
, l3_config
);
275 gen_get_urb_config(devinfo
,
276 1024 * push_constant_kb
, 1024 * urb_size_kb
,
278 VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
,
279 active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
,
280 entry_size
, entries
, start
);
282 #if GEN_GEN == 7 && !GEN_IS_HASWELL
283 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
285 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
286 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
287 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
288 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
289 * needs to be sent before any combination of VS associated 3DSTATE."
291 anv_batch_emit(batch
, GEN7_PIPE_CONTROL
, pc
) {
292 pc
.DepthStallEnable
= true;
293 pc
.PostSyncOperation
= WriteImmediateData
;
294 pc
.Address
= (struct anv_address
) { &device
->workaround_bo
, 0 };
298 for (int i
= 0; i
<= MESA_SHADER_GEOMETRY
; i
++) {
299 anv_batch_emit(batch
, GENX(3DSTATE_URB_VS
), urb
) {
300 urb
._3DCommandSubOpcode
+= i
;
301 urb
.VSURBStartingAddress
= start
[i
];
302 urb
.VSURBEntryAllocationSize
= entry_size
[i
] - 1;
303 urb
.VSNumberofURBEntries
= entries
[i
];
309 emit_urb_setup(struct anv_pipeline
*pipeline
)
311 unsigned entry_size
[4];
312 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
313 const struct brw_vue_prog_data
*prog_data
=
314 !anv_pipeline_has_stage(pipeline
, i
) ? NULL
:
315 (const struct brw_vue_prog_data
*) pipeline
->shaders
[i
]->prog_data
;
317 entry_size
[i
] = prog_data
? prog_data
->urb_entry_size
: 1;
320 genX(emit_urb_setup
)(pipeline
->device
, &pipeline
->batch
,
321 pipeline
->urb
.l3_config
,
322 pipeline
->active_stages
, entry_size
);
326 emit_3dstate_sbe(struct anv_pipeline
*pipeline
)
328 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
330 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
331 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SBE
), sbe
);
333 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SBE_SWIZ
), sbe
);
338 const struct brw_vue_map
*fs_input_map
=
339 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
341 struct GENX(3DSTATE_SBE
) sbe
= {
342 GENX(3DSTATE_SBE_header
),
343 .AttributeSwizzleEnable
= true,
344 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
,
345 .NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
,
346 .ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
,
350 for (unsigned i
= 0; i
< 32; i
++)
351 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
355 /* On Broadwell, they broke 3DSTATE_SBE into two packets */
356 struct GENX(3DSTATE_SBE_SWIZ
) swiz
= {
357 GENX(3DSTATE_SBE_SWIZ_header
),
363 /* Skip the VUE header and position slots by default */
364 unsigned urb_entry_read_offset
= 1;
365 int max_source_attr
= 0;
366 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
367 int input_index
= wm_prog_data
->urb_setup
[attr
];
372 /* gl_Layer is stored in the VUE header */
373 if (attr
== VARYING_SLOT_LAYER
) {
374 urb_entry_read_offset
= 0;
378 if (attr
== VARYING_SLOT_PNTC
) {
379 sbe
.PointSpriteTextureCoordinateEnable
= 1 << input_index
;
383 const int slot
= fs_input_map
->varying_to_slot
[attr
];
385 if (input_index
>= 16)
389 /* This attribute does not exist in the VUE--that means that the
390 * vertex shader did not write to it. It could be that it's a
391 * regular varying read by the fragment shader but not written by
392 * the vertex shader or it's gl_PrimitiveID. In the first case the
393 * value is undefined, in the second it needs to be
396 swiz
.Attribute
[input_index
].ConstantSource
= PRIM_ID
;
397 swiz
.Attribute
[input_index
].ComponentOverrideX
= true;
398 swiz
.Attribute
[input_index
].ComponentOverrideY
= true;
399 swiz
.Attribute
[input_index
].ComponentOverrideZ
= true;
400 swiz
.Attribute
[input_index
].ComponentOverrideW
= true;
402 /* We have to subtract two slots to accout for the URB entry output
403 * read offset in the VS and GS stages.
405 const int source_attr
= slot
- 2 * urb_entry_read_offset
;
406 assert(source_attr
>= 0 && source_attr
< 32);
407 max_source_attr
= MAX2(max_source_attr
, source_attr
);
408 swiz
.Attribute
[input_index
].SourceAttribute
= source_attr
;
412 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
413 sbe
.VertexURBEntryReadLength
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
415 sbe
.ForceVertexURBEntryReadOffset
= true;
416 sbe
.ForceVertexURBEntryReadLength
= true;
419 uint32_t *dw
= anv_batch_emit_dwords(&pipeline
->batch
,
420 GENX(3DSTATE_SBE_length
));
423 GENX(3DSTATE_SBE_pack
)(&pipeline
->batch
, dw
, &sbe
);
426 dw
= anv_batch_emit_dwords(&pipeline
->batch
, GENX(3DSTATE_SBE_SWIZ_length
));
429 GENX(3DSTATE_SBE_SWIZ_pack
)(&pipeline
->batch
, dw
, &swiz
);
433 static const uint32_t vk_to_gen_cullmode
[] = {
434 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
435 [VK_CULL_MODE_FRONT_BIT
] = CULLMODE_FRONT
,
436 [VK_CULL_MODE_BACK_BIT
] = CULLMODE_BACK
,
437 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
440 static const uint32_t vk_to_gen_fillmode
[] = {
441 [VK_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
442 [VK_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
443 [VK_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
446 static const uint32_t vk_to_gen_front_face
[] = {
447 [VK_FRONT_FACE_COUNTER_CLOCKWISE
] = 1,
448 [VK_FRONT_FACE_CLOCKWISE
] = 0
452 emit_rs_state(struct anv_pipeline
*pipeline
,
453 const VkPipelineRasterizationStateCreateInfo
*rs_info
,
454 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
455 const struct anv_render_pass
*pass
,
456 const struct anv_subpass
*subpass
)
458 struct GENX(3DSTATE_SF
) sf
= {
459 GENX(3DSTATE_SF_header
),
462 sf
.ViewportTransformEnable
= true;
463 sf
.StatisticsEnable
= true;
464 sf
.TriangleStripListProvokingVertexSelect
= 0;
465 sf
.LineStripListProvokingVertexSelect
= 0;
466 sf
.TriangleFanProvokingVertexSelect
= 1;
468 const struct brw_vue_prog_data
*last_vue_prog_data
=
469 anv_pipeline_get_last_vue_prog_data(pipeline
);
471 if (last_vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
472 sf
.PointWidthSource
= Vertex
;
474 sf
.PointWidthSource
= State
;
479 struct GENX(3DSTATE_RASTER
) raster
= {
480 GENX(3DSTATE_RASTER_header
),
486 /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
487 * "Multisample Modes State".
490 raster
.DXMultisampleRasterizationEnable
= true;
491 /* NOTE: 3DSTATE_RASTER::ForcedSampleCount affects the BDW and SKL PMA fix
492 * computations. If we ever set this bit to a different value, they will
493 * need to be updated accordingly.
495 raster
.ForcedSampleCount
= FSC_NUMRASTSAMPLES_0
;
496 raster
.ForceMultisampling
= false;
498 raster
.MultisampleRasterizationMode
=
499 (ms_info
&& ms_info
->rasterizationSamples
> 1) ?
500 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
503 raster
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
];
504 raster
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
];
505 raster
.FrontFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
506 raster
.BackFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
507 raster
.ScissorRectangleEnable
= true;
510 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
511 raster
.ViewportZFarClipTestEnable
= !pipeline
->depth_clamp_enable
;
512 raster
.ViewportZNearClipTestEnable
= !pipeline
->depth_clamp_enable
;
514 raster
.ViewportZClipTestEnable
= !pipeline
->depth_clamp_enable
;
517 raster
.GlobalDepthOffsetEnableSolid
= rs_info
->depthBiasEnable
;
518 raster
.GlobalDepthOffsetEnableWireframe
= rs_info
->depthBiasEnable
;
519 raster
.GlobalDepthOffsetEnablePoint
= rs_info
->depthBiasEnable
;
522 /* Gen7 requires that we provide the depth format in 3DSTATE_SF so that it
523 * can get the depth offsets correct.
525 if (subpass
->depth_stencil_attachment
) {
527 pass
->attachments
[subpass
->depth_stencil_attachment
->attachment
].format
;
528 assert(vk_format_is_depth_or_stencil(vk_format
));
529 if (vk_format_aspects(vk_format
) & VK_IMAGE_ASPECT_DEPTH_BIT
) {
530 enum isl_format isl_format
=
531 anv_get_isl_format(&pipeline
->device
->info
, vk_format
,
532 VK_IMAGE_ASPECT_DEPTH_BIT
,
533 VK_IMAGE_TILING_OPTIMAL
);
534 sf
.DepthBufferSurfaceFormat
=
535 isl_format_get_depth_format(isl_format
, false);
541 GENX(3DSTATE_SF_pack
)(NULL
, pipeline
->gen8
.sf
, &sf
);
542 GENX(3DSTATE_RASTER_pack
)(NULL
, pipeline
->gen8
.raster
, &raster
);
545 GENX(3DSTATE_SF_pack
)(NULL
, &pipeline
->gen7
.sf
, &sf
);
550 emit_ms_state(struct anv_pipeline
*pipeline
,
551 const VkPipelineMultisampleStateCreateInfo
*info
)
553 uint32_t samples
= 1;
554 uint32_t log2_samples
= 0;
556 /* From the Vulkan 1.0 spec:
557 * If pSampleMask is NULL, it is treated as if the mask has all bits
558 * enabled, i.e. no coverage is removed from fragments.
560 * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
563 uint32_t sample_mask
= 0xffff;
565 uint32_t sample_mask
= 0xff;
569 samples
= info
->rasterizationSamples
;
570 log2_samples
= __builtin_ffs(samples
) - 1;
573 if (info
&& info
->pSampleMask
)
574 sample_mask
&= info
->pSampleMask
[0];
576 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
577 ms
.NumberofMultisamples
= log2_samples
;
579 ms
.PixelLocation
= CENTER
;
581 /* The PRM says that this bit is valid only for DX9:
583 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
584 * should not have any effect by setting or not setting this bit.
586 ms
.PixelPositionOffsetEnable
= false;
591 GEN_SAMPLE_POS_1X(ms
.Sample
);
594 GEN_SAMPLE_POS_2X(ms
.Sample
);
597 GEN_SAMPLE_POS_4X(ms
.Sample
);
600 GEN_SAMPLE_POS_8X(ms
.Sample
);
608 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
609 sm
.SampleMask
= sample_mask
;
613 static const uint32_t vk_to_gen_logic_op
[] = {
614 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
615 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
616 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
617 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
618 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
619 [VK_LOGIC_OP_NO_OP
] = LOGICOP_NOOP
,
620 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
621 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
622 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
623 [VK_LOGIC_OP_EQUIVALENT
] = LOGICOP_EQUIV
,
624 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
625 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
626 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
627 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
628 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
629 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
632 static const uint32_t vk_to_gen_blend
[] = {
633 [VK_BLEND_FACTOR_ZERO
] = BLENDFACTOR_ZERO
,
634 [VK_BLEND_FACTOR_ONE
] = BLENDFACTOR_ONE
,
635 [VK_BLEND_FACTOR_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
636 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
637 [VK_BLEND_FACTOR_DST_COLOR
] = BLENDFACTOR_DST_COLOR
,
638 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
639 [VK_BLEND_FACTOR_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
640 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
641 [VK_BLEND_FACTOR_DST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
642 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
643 [VK_BLEND_FACTOR_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
644 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
]= BLENDFACTOR_INV_CONST_COLOR
,
645 [VK_BLEND_FACTOR_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
646 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
]= BLENDFACTOR_INV_CONST_ALPHA
,
647 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
648 [VK_BLEND_FACTOR_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
649 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
650 [VK_BLEND_FACTOR_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
651 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
654 static const uint32_t vk_to_gen_blend_op
[] = {
655 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
656 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
657 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
658 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
659 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
662 static const uint32_t vk_to_gen_compare_op
[] = {
663 [VK_COMPARE_OP_NEVER
] = PREFILTEROPNEVER
,
664 [VK_COMPARE_OP_LESS
] = PREFILTEROPLESS
,
665 [VK_COMPARE_OP_EQUAL
] = PREFILTEROPEQUAL
,
666 [VK_COMPARE_OP_LESS_OR_EQUAL
] = PREFILTEROPLEQUAL
,
667 [VK_COMPARE_OP_GREATER
] = PREFILTEROPGREATER
,
668 [VK_COMPARE_OP_NOT_EQUAL
] = PREFILTEROPNOTEQUAL
,
669 [VK_COMPARE_OP_GREATER_OR_EQUAL
] = PREFILTEROPGEQUAL
,
670 [VK_COMPARE_OP_ALWAYS
] = PREFILTEROPALWAYS
,
673 static const uint32_t vk_to_gen_stencil_op
[] = {
674 [VK_STENCIL_OP_KEEP
] = STENCILOP_KEEP
,
675 [VK_STENCIL_OP_ZERO
] = STENCILOP_ZERO
,
676 [VK_STENCIL_OP_REPLACE
] = STENCILOP_REPLACE
,
677 [VK_STENCIL_OP_INCREMENT_AND_CLAMP
] = STENCILOP_INCRSAT
,
678 [VK_STENCIL_OP_DECREMENT_AND_CLAMP
] = STENCILOP_DECRSAT
,
679 [VK_STENCIL_OP_INVERT
] = STENCILOP_INVERT
,
680 [VK_STENCIL_OP_INCREMENT_AND_WRAP
] = STENCILOP_INCR
,
681 [VK_STENCIL_OP_DECREMENT_AND_WRAP
] = STENCILOP_DECR
,
684 /* This function sanitizes the VkStencilOpState by looking at the compare ops
685 * and trying to determine whether or not a given stencil op can ever actually
686 * occur. Stencil ops which can never occur are set to VK_STENCIL_OP_KEEP.
687 * This function returns true if, after sanitation, any of the stencil ops are
688 * set to something other than VK_STENCIL_OP_KEEP.
691 sanitize_stencil_face(VkStencilOpState
*face
,
692 VkCompareOp depthCompareOp
)
694 /* If compareOp is ALWAYS then the stencil test will never fail and failOp
695 * will never happen. Set failOp to KEEP in this case.
697 if (face
->compareOp
== VK_COMPARE_OP_ALWAYS
)
698 face
->failOp
= VK_STENCIL_OP_KEEP
;
700 /* If compareOp is NEVER or depthCompareOp is NEVER then one of the depth
701 * or stencil tests will fail and passOp will never happen.
703 if (face
->compareOp
== VK_COMPARE_OP_NEVER
||
704 depthCompareOp
== VK_COMPARE_OP_NEVER
)
705 face
->passOp
= VK_STENCIL_OP_KEEP
;
707 /* If compareOp is NEVER or depthCompareOp is ALWAYS then either the
708 * stencil test will fail or the depth test will pass. In either case,
709 * depthFailOp will never happen.
711 if (face
->compareOp
== VK_COMPARE_OP_NEVER
||
712 depthCompareOp
== VK_COMPARE_OP_ALWAYS
)
713 face
->depthFailOp
= VK_STENCIL_OP_KEEP
;
715 return face
->failOp
!= VK_STENCIL_OP_KEEP
||
716 face
->depthFailOp
!= VK_STENCIL_OP_KEEP
||
717 face
->passOp
!= VK_STENCIL_OP_KEEP
;
720 /* Intel hardware is fairly sensitive to whether or not depth/stencil writes
721 * are enabled. In the presence of discards, it's fairly easy to get into the
722 * non-promoted case which means a fairly big performance hit. From the Iron
723 * Lake PRM, Vol 2, pt. 1, section 8.4.3.2, "Early Depth Test Cases":
725 * "Non-promoted depth (N) is active whenever the depth test can be done
726 * early but it cannot determine whether or not to write source depth to
727 * the depth buffer, therefore the depth write must be performed post pixel
728 * shader. This includes cases where the pixel shader can kill pixels,
729 * including via sampler chroma key, as well as cases where the alpha test
730 * function is enabled, which kills pixels based on a programmable alpha
731 * test. In this case, even if the depth test fails, the pixel cannot be
732 * killed if a stencil write is indicated. Whether or not the stencil write
733 * happens depends on whether or not the pixel is killed later. In these
734 * cases if stencil test fails and stencil writes are off, the pixels can
735 * also be killed early. If stencil writes are enabled, the pixels must be
736 * treated as Computed depth (described above)."
738 * The same thing as mentioned in the stencil case can happen in the depth
739 * case as well if it thinks it writes depth but, thanks to the depth test
740 * being GL_EQUAL, the write doesn't actually matter. A little extra work
741 * up-front to try and disable depth and stencil writes can make a big
744 * Unfortunately, the way depth and stencil testing is specified, there are
745 * many case where, regardless of depth/stencil writes being enabled, nothing
746 * actually gets written due to some other bit of state being set. This
747 * function attempts to "sanitize" the depth stencil state and disable writes
748 * and sometimes even testing whenever possible.
751 sanitize_ds_state(VkPipelineDepthStencilStateCreateInfo
*state
,
752 bool *stencilWriteEnable
,
753 VkImageAspectFlags ds_aspects
)
755 *stencilWriteEnable
= state
->stencilTestEnable
;
757 /* If the depth test is disabled, we won't be writing anything. Make sure we
758 * treat the test as always passing later on as well.
760 * Also, the Vulkan spec requires that if either depth or stencil is not
761 * present, the pipeline is to act as if the test silently passes. In that
762 * case we won't write either.
764 if (!state
->depthTestEnable
|| !(ds_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
765 state
->depthWriteEnable
= false;
766 state
->depthCompareOp
= VK_COMPARE_OP_ALWAYS
;
769 if (!(ds_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
770 *stencilWriteEnable
= false;
771 state
->front
.compareOp
= VK_COMPARE_OP_ALWAYS
;
772 state
->back
.compareOp
= VK_COMPARE_OP_ALWAYS
;
775 /* If the stencil test is enabled and always fails, then we will never get
776 * to the depth test so we can just disable the depth test entirely.
778 if (state
->stencilTestEnable
&&
779 state
->front
.compareOp
== VK_COMPARE_OP_NEVER
&&
780 state
->back
.compareOp
== VK_COMPARE_OP_NEVER
) {
781 state
->depthTestEnable
= false;
782 state
->depthWriteEnable
= false;
785 /* If depthCompareOp is EQUAL then the value we would be writing to the
786 * depth buffer is the same as the value that's already there so there's no
787 * point in writing it.
789 if (state
->depthCompareOp
== VK_COMPARE_OP_EQUAL
)
790 state
->depthWriteEnable
= false;
792 /* If the stencil ops are such that we don't actually ever modify the
793 * stencil buffer, we should disable writes.
795 if (!sanitize_stencil_face(&state
->front
, state
->depthCompareOp
) &&
796 !sanitize_stencil_face(&state
->back
, state
->depthCompareOp
))
797 *stencilWriteEnable
= false;
799 /* If the depth test always passes and we never write out depth, that's the
800 * same as if the depth test is disabled entirely.
802 if (state
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
&&
803 !state
->depthWriteEnable
)
804 state
->depthTestEnable
= false;
806 /* If the stencil test always passes and we never write out stencil, that's
807 * the same as if the stencil test is disabled entirely.
809 if (state
->front
.compareOp
== VK_COMPARE_OP_ALWAYS
&&
810 state
->back
.compareOp
== VK_COMPARE_OP_ALWAYS
&&
811 !*stencilWriteEnable
)
812 state
->stencilTestEnable
= false;
816 emit_ds_state(struct anv_pipeline
*pipeline
,
817 const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
,
818 const struct anv_render_pass
*pass
,
819 const struct anv_subpass
*subpass
)
822 # define depth_stencil_dw pipeline->gen7.depth_stencil_state
824 # define depth_stencil_dw pipeline->gen8.wm_depth_stencil
826 # define depth_stencil_dw pipeline->gen9.wm_depth_stencil
829 if (pCreateInfo
== NULL
) {
830 /* We're going to OR this together with the dynamic state. We need
831 * to make sure it's initialized to something useful.
833 pipeline
->writes_stencil
= false;
834 pipeline
->stencil_test_enable
= false;
835 pipeline
->writes_depth
= false;
836 pipeline
->depth_test_enable
= false;
837 memset(depth_stencil_dw
, 0, sizeof(depth_stencil_dw
));
841 VkImageAspectFlags ds_aspects
= 0;
842 if (subpass
->depth_stencil_attachment
) {
843 VkFormat depth_stencil_format
=
844 pass
->attachments
[subpass
->depth_stencil_attachment
->attachment
].format
;
845 ds_aspects
= vk_format_aspects(depth_stencil_format
);
848 VkPipelineDepthStencilStateCreateInfo info
= *pCreateInfo
;
849 sanitize_ds_state(&info
, &pipeline
->writes_stencil
, ds_aspects
);
850 pipeline
->stencil_test_enable
= info
.stencilTestEnable
;
851 pipeline
->writes_depth
= info
.depthWriteEnable
;
852 pipeline
->depth_test_enable
= info
.depthTestEnable
;
854 /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
857 struct GENX(DEPTH_STENCIL_STATE
) depth_stencil
= {
859 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) depth_stencil
= {
861 .DepthTestEnable
= info
.depthTestEnable
,
862 .DepthBufferWriteEnable
= info
.depthWriteEnable
,
863 .DepthTestFunction
= vk_to_gen_compare_op
[info
.depthCompareOp
],
864 .DoubleSidedStencilEnable
= true,
866 .StencilTestEnable
= info
.stencilTestEnable
,
867 .StencilFailOp
= vk_to_gen_stencil_op
[info
.front
.failOp
],
868 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
.front
.passOp
],
869 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
.front
.depthFailOp
],
870 .StencilTestFunction
= vk_to_gen_compare_op
[info
.front
.compareOp
],
871 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
.back
.failOp
],
872 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
.back
.passOp
],
873 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
.back
.depthFailOp
],
874 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
.back
.compareOp
],
878 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
880 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
884 MAYBE_UNUSED
static bool
885 is_dual_src_blend_factor(VkBlendFactor factor
)
887 return factor
== VK_BLEND_FACTOR_SRC1_COLOR
||
888 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
||
889 factor
== VK_BLEND_FACTOR_SRC1_ALPHA
||
890 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
;
894 emit_cb_state(struct anv_pipeline
*pipeline
,
895 const VkPipelineColorBlendStateCreateInfo
*info
,
896 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
898 struct anv_device
*device
= pipeline
->device
;
899 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
901 struct GENX(BLEND_STATE
) blend_state
= {
903 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
904 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
908 uint32_t surface_count
= 0;
909 struct anv_pipeline_bind_map
*map
;
910 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
911 map
= &pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->bind_map
;
912 surface_count
= map
->surface_count
;
915 const uint32_t num_dwords
= GENX(BLEND_STATE_length
) +
916 GENX(BLEND_STATE_ENTRY_length
) * surface_count
;
917 pipeline
->blend_state
=
918 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
920 bool has_writeable_rt
= false;
921 uint32_t *state_pos
= pipeline
->blend_state
.map
;
922 state_pos
+= GENX(BLEND_STATE_length
);
924 struct GENX(BLEND_STATE_ENTRY
) bs0
= { 0 };
926 for (unsigned i
= 0; i
< surface_count
; i
++) {
927 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[i
];
929 /* All color attachments are at the beginning of the binding table */
930 if (binding
->set
!= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
933 /* We can have at most 8 attachments */
936 if (info
== NULL
|| binding
->index
>= info
->attachmentCount
) {
937 /* Default everything to disabled */
938 struct GENX(BLEND_STATE_ENTRY
) entry
= {
939 .WriteDisableAlpha
= true,
940 .WriteDisableRed
= true,
941 .WriteDisableGreen
= true,
942 .WriteDisableBlue
= true,
944 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, state_pos
, &entry
);
945 state_pos
+= GENX(BLEND_STATE_ENTRY_length
);
949 assert(binding
->binding
== 0);
950 const VkPipelineColorBlendAttachmentState
*a
=
951 &info
->pAttachments
[binding
->index
];
953 struct GENX(BLEND_STATE_ENTRY
) entry
= {
955 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
956 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
958 .LogicOpEnable
= info
->logicOpEnable
,
959 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
960 .ColorBufferBlendEnable
= a
->blendEnable
,
961 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
962 .PreBlendColorClampEnable
= true,
963 .PostBlendColorClampEnable
= true,
964 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcColorBlendFactor
],
965 .DestinationBlendFactor
= vk_to_gen_blend
[a
->dstColorBlendFactor
],
966 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->colorBlendOp
],
967 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcAlphaBlendFactor
],
968 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->dstAlphaBlendFactor
],
969 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->alphaBlendOp
],
970 .WriteDisableAlpha
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_A_BIT
),
971 .WriteDisableRed
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_R_BIT
),
972 .WriteDisableGreen
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_G_BIT
),
973 .WriteDisableBlue
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_B_BIT
),
976 if (a
->srcColorBlendFactor
!= a
->srcAlphaBlendFactor
||
977 a
->dstColorBlendFactor
!= a
->dstAlphaBlendFactor
||
978 a
->colorBlendOp
!= a
->alphaBlendOp
) {
980 blend_state
.IndependentAlphaBlendEnable
= true;
982 entry
.IndependentAlphaBlendEnable
= true;
986 /* The Dual Source Blending documentation says:
988 * "If SRC1 is included in a src/dst blend factor and
989 * a DualSource RT Write message is not used, results
990 * are UNDEFINED. (This reflects the same restriction in DX APIs,
991 * where undefined results are produced if “o1” is not written
992 * by a PS – there are no default values defined)."
994 * There is no way to gracefully fix this undefined situation
995 * so we just disable the blending to prevent possible issues.
997 if (!wm_prog_data
->dual_src_blend
&&
998 (is_dual_src_blend_factor(a
->srcColorBlendFactor
) ||
999 is_dual_src_blend_factor(a
->dstColorBlendFactor
) ||
1000 is_dual_src_blend_factor(a
->srcAlphaBlendFactor
) ||
1001 is_dual_src_blend_factor(a
->dstAlphaBlendFactor
))) {
1002 vk_debug_report(&device
->instance
->debug_report_callbacks
,
1003 VK_DEBUG_REPORT_WARNING_BIT_EXT
,
1004 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT
,
1005 (uint64_t)(uintptr_t)device
,
1007 "Enabled dual-src blend factors without writing both targets "
1008 "in the shader. Disabling blending to avoid GPU hangs.");
1009 entry
.ColorBufferBlendEnable
= false;
1012 if (a
->colorWriteMask
!= 0)
1013 has_writeable_rt
= true;
1015 /* Our hardware applies the blend factor prior to the blend function
1016 * regardless of what function is used. Technically, this means the
1017 * hardware can do MORE than GL or Vulkan specify. However, it also
1018 * means that, for MIN and MAX, we have to stomp the blend factor to
1019 * ONE to make it a no-op.
1021 if (a
->colorBlendOp
== VK_BLEND_OP_MIN
||
1022 a
->colorBlendOp
== VK_BLEND_OP_MAX
) {
1023 entry
.SourceBlendFactor
= BLENDFACTOR_ONE
;
1024 entry
.DestinationBlendFactor
= BLENDFACTOR_ONE
;
1026 if (a
->alphaBlendOp
== VK_BLEND_OP_MIN
||
1027 a
->alphaBlendOp
== VK_BLEND_OP_MAX
) {
1028 entry
.SourceAlphaBlendFactor
= BLENDFACTOR_ONE
;
1029 entry
.DestinationAlphaBlendFactor
= BLENDFACTOR_ONE
;
1031 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, state_pos
, &entry
);
1032 state_pos
+= GENX(BLEND_STATE_ENTRY_length
);
1040 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_BLEND
), blend
) {
1041 blend
.AlphaToCoverageEnable
= blend_state
.AlphaToCoverageEnable
;
1042 blend
.HasWriteableRT
= has_writeable_rt
;
1043 blend
.ColorBufferBlendEnable
= bs0
.ColorBufferBlendEnable
;
1044 blend
.SourceAlphaBlendFactor
= bs0
.SourceAlphaBlendFactor
;
1045 blend
.DestinationAlphaBlendFactor
= bs0
.DestinationAlphaBlendFactor
;
1046 blend
.SourceBlendFactor
= bs0
.SourceBlendFactor
;
1047 blend
.DestinationBlendFactor
= bs0
.DestinationBlendFactor
;
1048 blend
.AlphaTestEnable
= false;
1049 blend
.IndependentAlphaBlendEnable
=
1050 blend_state
.IndependentAlphaBlendEnable
;
1053 (void)has_writeable_rt
;
1056 GENX(BLEND_STATE_pack
)(NULL
, pipeline
->blend_state
.map
, &blend_state
);
1058 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), bsp
) {
1059 bsp
.BlendStatePointer
= pipeline
->blend_state
.offset
;
1061 bsp
.BlendStatePointerValid
= true;
1067 emit_3dstate_clip(struct anv_pipeline
*pipeline
,
1068 const VkPipelineViewportStateCreateInfo
*vp_info
,
1069 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
1071 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1072 (void) wm_prog_data
;
1073 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_CLIP
), clip
) {
1074 clip
.ClipEnable
= true;
1075 clip
.StatisticsEnable
= true;
1076 clip
.EarlyCullEnable
= true;
1077 clip
.APIMode
= APIMODE_D3D
,
1078 clip
.ViewportXYClipTestEnable
= true;
1080 clip
.ClipMode
= CLIPMODE_NORMAL
;
1082 clip
.TriangleStripListProvokingVertexSelect
= 0;
1083 clip
.LineStripListProvokingVertexSelect
= 0;
1084 clip
.TriangleFanProvokingVertexSelect
= 1;
1086 clip
.MinimumPointWidth
= 0.125;
1087 clip
.MaximumPointWidth
= 255.875;
1089 const struct brw_vue_prog_data
*last
=
1090 anv_pipeline_get_last_vue_prog_data(pipeline
);
1092 /* From the Vulkan 1.0.45 spec:
1094 * "If the last active vertex processing stage shader entry point's
1095 * interface does not include a variable decorated with
1096 * ViewportIndex, then the first viewport is used."
1098 if (vp_info
&& (last
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
)) {
1099 clip
.MaximumVPIndex
= vp_info
->viewportCount
- 1;
1101 clip
.MaximumVPIndex
= 0;
1104 /* From the Vulkan 1.0.45 spec:
1106 * "If the last active vertex processing stage shader entry point's
1107 * interface does not include a variable decorated with Layer, then
1108 * the first layer is used."
1110 clip
.ForceZeroRTAIndexEnable
=
1111 !(last
->vue_map
.slots_valid
& VARYING_BIT_LAYER
);
1114 clip
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
];
1115 clip
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
];
1116 clip
.ViewportZClipTestEnable
= !pipeline
->depth_clamp_enable
;
1117 clip
.UserClipDistanceClipTestEnableBitmask
= last
->clip_distance_mask
;
1118 clip
.UserClipDistanceCullTestEnableBitmask
= last
->cull_distance_mask
;
1120 clip
.NonPerspectiveBarycentricEnable
= wm_prog_data
?
1121 (wm_prog_data
->barycentric_interp_modes
&
1122 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
) != 0 : 0;
1128 emit_3dstate_streamout(struct anv_pipeline
*pipeline
,
1129 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
1132 const struct brw_vue_prog_data
*prog_data
=
1133 anv_pipeline_get_last_vue_prog_data(pipeline
);
1134 const struct brw_vue_map
*vue_map
= &prog_data
->vue_map
;
1137 nir_xfb_info
*xfb_info
;
1138 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1139 xfb_info
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->xfb_info
;
1140 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1141 xfb_info
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->xfb_info
;
1143 xfb_info
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->xfb_info
;
1145 pipeline
->xfb_used
= xfb_info
? xfb_info
->buffers_written
: 0;
1147 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_STREAMOUT
), so
) {
1148 so
.RenderingDisable
= rs_info
->rasterizerDiscardEnable
;
1152 so
.SOFunctionEnable
= true;
1153 so
.SOStatisticsEnable
= true;
1155 const VkPipelineRasterizationStateStreamCreateInfoEXT
*stream_info
=
1156 vk_find_struct_const(rs_info
, PIPELINE_RASTERIZATION_STATE_STREAM_CREATE_INFO_EXT
);
1157 so
.RenderStreamSelect
= stream_info
?
1158 stream_info
->rasterizationStream
: 0;
1160 so
.Buffer0SurfacePitch
= xfb_info
->strides
[0];
1161 so
.Buffer1SurfacePitch
= xfb_info
->strides
[1];
1162 so
.Buffer2SurfacePitch
= xfb_info
->strides
[2];
1163 so
.Buffer3SurfacePitch
= xfb_info
->strides
[3];
1165 int urb_entry_read_offset
= 0;
1166 int urb_entry_read_length
=
1167 (prog_data
->vue_map
.num_slots
+ 1) / 2 - urb_entry_read_offset
;
1169 /* We always read the whole vertex. This could be reduced at some
1170 * point by reading less and offsetting the register index in the
1173 so
.Stream0VertexReadOffset
= urb_entry_read_offset
;
1174 so
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
1175 so
.Stream1VertexReadOffset
= urb_entry_read_offset
;
1176 so
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
1177 so
.Stream2VertexReadOffset
= urb_entry_read_offset
;
1178 so
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
1179 so
.Stream3VertexReadOffset
= urb_entry_read_offset
;
1180 so
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
1182 #endif /* GEN_GEN >= 8 */
1187 struct GENX(SO_DECL
) so_decl
[MAX_XFB_STREAMS
][128];
1188 int next_offset
[MAX_XFB_BUFFERS
] = {0, 0, 0, 0};
1189 int decls
[MAX_XFB_STREAMS
] = {0, 0, 0, 0};
1191 memset(so_decl
, 0, sizeof(so_decl
));
1193 for (unsigned i
= 0; i
< xfb_info
->output_count
; i
++) {
1194 const nir_xfb_output_info
*output
= &xfb_info
->outputs
[i
];
1195 unsigned buffer
= output
->buffer
;
1196 unsigned stream
= xfb_info
->buffer_to_stream
[buffer
];
1198 /* Our hardware is unusual in that it requires us to program SO_DECLs
1199 * for fake "hole" components, rather than simply taking the offset
1200 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
1201 * program as many size = 4 holes as we can, then a final hole to
1202 * accommodate the final 1, 2, or 3 remaining.
1204 int hole_dwords
= (output
->offset
- next_offset
[buffer
]) / 4;
1205 while (hole_dwords
> 0) {
1206 so_decl
[stream
][decls
[stream
]++] = (struct GENX(SO_DECL
)) {
1208 .OutputBufferSlot
= buffer
,
1209 .ComponentMask
= (1 << MIN2(hole_dwords
, 4)) - 1,
1214 int varying
= output
->location
;
1215 uint8_t component_mask
= output
->component_mask
;
1216 /* VARYING_SLOT_PSIZ contains three scalar fields packed together:
1217 * - VARYING_SLOT_LAYER in VARYING_SLOT_PSIZ.y
1218 * - VARYING_SLOT_VIEWPORT in VARYING_SLOT_PSIZ.z
1219 * - VARYING_SLOT_PSIZ in VARYING_SLOT_PSIZ.w
1221 if (varying
== VARYING_SLOT_LAYER
) {
1222 varying
= VARYING_SLOT_PSIZ
;
1223 component_mask
= 1 << 1; // SO_DECL_COMPMASK_Y
1224 } else if (varying
== VARYING_SLOT_VIEWPORT
) {
1225 varying
= VARYING_SLOT_PSIZ
;
1226 component_mask
= 1 << 2; // SO_DECL_COMPMASK_Z
1227 } else if (varying
== VARYING_SLOT_PSIZ
) {
1228 component_mask
= 1 << 3; // SO_DECL_COMPMASK_W
1231 next_offset
[buffer
] = output
->offset
+
1232 __builtin_popcount(component_mask
) * 4;
1234 so_decl
[stream
][decls
[stream
]++] = (struct GENX(SO_DECL
)) {
1235 .OutputBufferSlot
= buffer
,
1236 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
1237 .ComponentMask
= component_mask
,
1242 for (unsigned s
= 0; s
< MAX_XFB_STREAMS
; s
++)
1243 max_decls
= MAX2(max_decls
, decls
[s
]);
1245 uint8_t sbs
[MAX_XFB_STREAMS
] = { };
1246 for (unsigned b
= 0; b
< MAX_XFB_BUFFERS
; b
++) {
1247 if (xfb_info
->buffers_written
& (1 << b
))
1248 sbs
[xfb_info
->buffer_to_stream
[b
]] |= 1 << b
;
1251 uint32_t *dw
= anv_batch_emitn(&pipeline
->batch
, 3 + 2 * max_decls
,
1252 GENX(3DSTATE_SO_DECL_LIST
),
1253 .StreamtoBufferSelects0
= sbs
[0],
1254 .StreamtoBufferSelects1
= sbs
[1],
1255 .StreamtoBufferSelects2
= sbs
[2],
1256 .StreamtoBufferSelects3
= sbs
[3],
1257 .NumEntries0
= decls
[0],
1258 .NumEntries1
= decls
[1],
1259 .NumEntries2
= decls
[2],
1260 .NumEntries3
= decls
[3]);
1262 for (int i
= 0; i
< max_decls
; i
++) {
1263 GENX(SO_DECL_ENTRY_pack
)(NULL
, dw
+ 3 + i
* 2,
1264 &(struct GENX(SO_DECL_ENTRY
)) {
1265 .Stream0Decl
= so_decl
[0][i
],
1266 .Stream1Decl
= so_decl
[1][i
],
1267 .Stream2Decl
= so_decl
[2][i
],
1268 .Stream3Decl
= so_decl
[3][i
],
1272 #endif /* GEN_GEN >= 8 */
1276 get_sampler_count(const struct anv_shader_bin
*bin
)
1278 uint32_t count_by_4
= DIV_ROUND_UP(bin
->bind_map
.sampler_count
, 4);
1280 /* We can potentially have way more than 32 samplers and that's ok.
1281 * However, the 3DSTATE_XS packets only have 3 bits to specify how
1282 * many to pre-fetch and all values above 4 are marked reserved.
1284 return MIN2(count_by_4
, 4);
1288 get_binding_table_entry_count(const struct anv_shader_bin
*bin
)
1290 return DIV_ROUND_UP(bin
->bind_map
.surface_count
, 32);
1293 static struct anv_address
1294 get_scratch_address(struct anv_pipeline
*pipeline
,
1295 gl_shader_stage stage
,
1296 const struct anv_shader_bin
*bin
)
1298 return (struct anv_address
) {
1299 .bo
= anv_scratch_pool_alloc(pipeline
->device
,
1300 &pipeline
->device
->scratch_pool
,
1301 stage
, bin
->prog_data
->total_scratch
),
1307 get_scratch_space(const struct anv_shader_bin
*bin
)
1309 return ffs(bin
->prog_data
->total_scratch
/ 2048);
1313 emit_3dstate_vs(struct anv_pipeline
*pipeline
)
1315 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1316 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1317 const struct anv_shader_bin
*vs_bin
=
1318 pipeline
->shaders
[MESA_SHADER_VERTEX
];
1320 assert(anv_pipeline_has_stage(pipeline
, MESA_SHADER_VERTEX
));
1322 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
), vs
) {
1324 vs
.StatisticsEnable
= true;
1325 vs
.KernelStartPointer
= vs_bin
->kernel
.offset
;
1327 vs
.SIMD8DispatchEnable
=
1328 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
1331 assert(!vs_prog_data
->base
.base
.use_alt_mode
);
1333 vs
.SingleVertexDispatch
= false;
1335 vs
.VectorMaskEnable
= false;
1337 * Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
1338 * Disable the Sampler state prefetch functionality in the SARB by
1339 * programming 0xB000[30] to '1'.
1341 vs
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(vs_bin
);
1342 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to
1343 * disable prefetching of binding tables on A0 and B0 steppings.
1344 * TODO: Revisit this WA on newer steppings.
1346 vs
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 : get_binding_table_entry_count(vs_bin
);
1347 vs
.FloatingPointMode
= IEEE754
;
1348 vs
.IllegalOpcodeExceptionEnable
= false;
1349 vs
.SoftwareExceptionEnable
= false;
1350 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1352 if (GEN_GEN
== 9 && devinfo
->gt
== 4 &&
1353 anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
1354 /* On Sky Lake GT4, we have experienced some hangs related to the VS
1355 * cache and tessellation. It is unknown exactly what is happening
1356 * but the Haswell docs for the "VS Reference Count Full Force Miss
1357 * Enable" field of the "Thread Mode" register refer to a HSW bug in
1358 * which the VUE handle reference count would overflow resulting in
1359 * internal reference counting bugs. My (Jason's) best guess is that
1360 * this bug cropped back up on SKL GT4 when we suddenly had more
1361 * threads in play than any previous gen9 hardware.
1363 * What we do know for sure is that setting this bit when
1364 * tessellation shaders are in use fixes a GPU hang in Batman: Arkham
1365 * City when playing with DXVK (https://bugs.freedesktop.org/107280).
1366 * Disabling the vertex cache with tessellation shaders should only
1367 * have a minor performance impact as the tessellation shaders are
1368 * likely generating and processing far more geometry than the vertex
1371 vs
.VertexCacheDisable
= true;
1374 vs
.VertexURBEntryReadLength
= vs_prog_data
->base
.urb_read_length
;
1375 vs
.VertexURBEntryReadOffset
= 0;
1376 vs
.DispatchGRFStartRegisterForURBData
=
1377 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1380 vs
.UserClipDistanceClipTestEnableBitmask
=
1381 vs_prog_data
->base
.clip_distance_mask
;
1382 vs
.UserClipDistanceCullTestEnableBitmask
=
1383 vs_prog_data
->base
.cull_distance_mask
;
1386 vs
.PerThreadScratchSpace
= get_scratch_space(vs_bin
);
1387 vs
.ScratchSpaceBasePointer
=
1388 get_scratch_address(pipeline
, MESA_SHADER_VERTEX
, vs_bin
);
1393 emit_3dstate_hs_te_ds(struct anv_pipeline
*pipeline
,
1394 const VkPipelineTessellationStateCreateInfo
*tess_info
)
1396 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
1397 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_HS
), hs
);
1398 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_TE
), te
);
1399 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_DS
), ds
);
1403 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1404 const struct anv_shader_bin
*tcs_bin
=
1405 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1406 const struct anv_shader_bin
*tes_bin
=
1407 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1409 const struct brw_tcs_prog_data
*tcs_prog_data
= get_tcs_prog_data(pipeline
);
1410 const struct brw_tes_prog_data
*tes_prog_data
= get_tes_prog_data(pipeline
);
1412 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_HS
), hs
) {
1414 hs
.StatisticsEnable
= true;
1415 hs
.KernelStartPointer
= tcs_bin
->kernel
.offset
;
1417 hs
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(tcs_bin
);
1418 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
1419 hs
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 : get_binding_table_entry_count(tcs_bin
);
1420 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1421 hs
.IncludeVertexHandles
= true;
1422 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1424 hs
.VertexURBEntryReadLength
= 0;
1425 hs
.VertexURBEntryReadOffset
= 0;
1426 hs
.DispatchGRFStartRegisterForURBData
=
1427 tcs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1429 hs
.PerThreadScratchSpace
= get_scratch_space(tcs_bin
);
1430 hs
.ScratchSpaceBasePointer
=
1431 get_scratch_address(pipeline
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
1434 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
1435 tess_info
? vk_find_struct_const(tess_info
, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
) : NULL
;
1437 VkTessellationDomainOrigin uv_origin
=
1438 domain_origin_state
? domain_origin_state
->domainOrigin
:
1439 VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
;
1441 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_TE
), te
) {
1442 te
.Partitioning
= tes_prog_data
->partitioning
;
1444 if (uv_origin
== VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT
) {
1445 te
.OutputTopology
= tes_prog_data
->output_topology
;
1447 /* When the origin is upper-left, we have to flip the winding order */
1448 if (tes_prog_data
->output_topology
== OUTPUT_TRI_CCW
) {
1449 te
.OutputTopology
= OUTPUT_TRI_CW
;
1450 } else if (tes_prog_data
->output_topology
== OUTPUT_TRI_CW
) {
1451 te
.OutputTopology
= OUTPUT_TRI_CCW
;
1453 te
.OutputTopology
= tes_prog_data
->output_topology
;
1457 te
.TEDomain
= tes_prog_data
->domain
;
1459 te
.MaximumTessellationFactorOdd
= 63.0;
1460 te
.MaximumTessellationFactorNotOdd
= 64.0;
1463 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_DS
), ds
) {
1465 ds
.StatisticsEnable
= true;
1466 ds
.KernelStartPointer
= tes_bin
->kernel
.offset
;
1468 ds
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(tes_bin
);
1469 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
1470 ds
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 : get_binding_table_entry_count(tes_bin
);
1471 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
1473 ds
.ComputeWCoordinateEnable
=
1474 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
1476 ds
.PatchURBEntryReadLength
= tes_prog_data
->base
.urb_read_length
;
1477 ds
.PatchURBEntryReadOffset
= 0;
1478 ds
.DispatchGRFStartRegisterForURBData
=
1479 tes_prog_data
->base
.base
.dispatch_grf_start_reg
;
1484 tes_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
?
1485 DISPATCH_MODE_SIMD8_SINGLE_PATCH
:
1486 DISPATCH_MODE_SIMD4X2
;
1488 assert(tes_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
);
1489 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
1492 ds
.UserClipDistanceClipTestEnableBitmask
=
1493 tes_prog_data
->base
.clip_distance_mask
;
1494 ds
.UserClipDistanceCullTestEnableBitmask
=
1495 tes_prog_data
->base
.cull_distance_mask
;
1498 ds
.PerThreadScratchSpace
= get_scratch_space(tes_bin
);
1499 ds
.ScratchSpaceBasePointer
=
1500 get_scratch_address(pipeline
, MESA_SHADER_TESS_EVAL
, tes_bin
);
1505 emit_3dstate_gs(struct anv_pipeline
*pipeline
)
1507 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1508 const struct anv_shader_bin
*gs_bin
=
1509 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1511 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
)) {
1512 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), gs
);
1516 const struct brw_gs_prog_data
*gs_prog_data
= get_gs_prog_data(pipeline
);
1518 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), gs
) {
1520 gs
.StatisticsEnable
= true;
1521 gs
.KernelStartPointer
= gs_bin
->kernel
.offset
;
1522 gs
.DispatchMode
= gs_prog_data
->base
.dispatch_mode
;
1524 gs
.SingleProgramFlow
= false;
1525 gs
.VectorMaskEnable
= false;
1527 gs
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(gs_bin
);
1528 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
1529 gs
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 : get_binding_table_entry_count(gs_bin
);
1530 gs
.IncludeVertexHandles
= gs_prog_data
->base
.include_vue_handles
;
1531 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
1534 /* Broadwell is weird. It needs us to divide by 2. */
1535 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
/ 2 - 1;
1537 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
1540 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
1541 gs
.OutputTopology
= gs_prog_data
->output_topology
;
1542 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1543 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
1544 gs
.ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
;
1545 gs
.InstanceControl
= MAX2(gs_prog_data
->invocations
, 1) - 1;
1546 gs
.ReorderMode
= TRAILING
;
1549 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
1550 gs
.StaticOutput
= gs_prog_data
->static_vertex_count
>= 0;
1551 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
>= 0 ?
1552 gs_prog_data
->static_vertex_count
: 0;
1555 gs
.VertexURBEntryReadOffset
= 0;
1556 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1557 gs
.DispatchGRFStartRegisterForURBData
=
1558 gs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1561 gs
.UserClipDistanceClipTestEnableBitmask
=
1562 gs_prog_data
->base
.clip_distance_mask
;
1563 gs
.UserClipDistanceCullTestEnableBitmask
=
1564 gs_prog_data
->base
.cull_distance_mask
;
1567 gs
.PerThreadScratchSpace
= get_scratch_space(gs_bin
);
1568 gs
.ScratchSpaceBasePointer
=
1569 get_scratch_address(pipeline
, MESA_SHADER_GEOMETRY
, gs_bin
);
1574 has_color_buffer_write_enabled(const struct anv_pipeline
*pipeline
,
1575 const VkPipelineColorBlendStateCreateInfo
*blend
)
1577 const struct anv_shader_bin
*shader_bin
=
1578 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1582 const struct anv_pipeline_bind_map
*bind_map
= &shader_bin
->bind_map
;
1583 for (int i
= 0; i
< bind_map
->surface_count
; i
++) {
1584 struct anv_pipeline_binding
*binding
= &bind_map
->surface_to_descriptor
[i
];
1586 if (binding
->set
!= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
1589 if (binding
->index
== UINT32_MAX
)
1592 if (blend
&& blend
->pAttachments
[binding
->index
].colorWriteMask
!= 0)
1600 emit_3dstate_wm(struct anv_pipeline
*pipeline
, struct anv_subpass
*subpass
,
1601 const VkPipelineColorBlendStateCreateInfo
*blend
,
1602 const VkPipelineMultisampleStateCreateInfo
*multisample
)
1604 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1606 MAYBE_UNUSED
uint32_t samples
=
1607 multisample
? multisample
->rasterizationSamples
: 1;
1609 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_WM
), wm
) {
1610 wm
.StatisticsEnable
= true;
1611 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1612 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1613 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1615 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1616 if (wm_prog_data
->early_fragment_tests
) {
1617 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1618 } else if (wm_prog_data
->has_side_effects
) {
1619 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1621 wm
.EarlyDepthStencilControl
= EDSC_NORMAL
;
1625 /* Gen8 hardware tries to compute ThreadDispatchEnable for us but
1626 * doesn't take into account KillPixels when no depth or stencil
1627 * writes are enabled. In order for occlusion queries to work
1628 * correctly with no attachments, we need to force-enable PS thread
1631 * The BDW docs are pretty clear that that this bit isn't validated
1632 * and probably shouldn't be used in production:
1634 * "This must always be set to Normal. This field should not be
1635 * tested for functional validation."
1637 * Unfortunately, however, the other mechanism we have for doing this
1638 * is 3DSTATE_PS_EXTRA::PixelShaderHasUAV which causes hangs on BDW.
1639 * Given two bad options, we choose the one which works.
1641 if ((wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
) &&
1642 !has_color_buffer_write_enabled(pipeline
, blend
))
1643 wm
.ForceThreadDispatchEnable
= ForceON
;
1646 wm
.BarycentricInterpolationMode
=
1647 wm_prog_data
->barycentric_interp_modes
;
1650 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1651 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1652 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1653 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1655 /* If the subpass has a depth or stencil self-dependency, then we
1656 * need to force the hardware to do the depth/stencil write *after*
1657 * fragment shader execution. Otherwise, the writes may hit memory
1658 * before we get around to fetching from the input attachment and we
1659 * may get the depth or stencil value from the current draw rather
1660 * than the previous one.
1662 wm
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
1663 wm_prog_data
->uses_kill
;
1665 if (wm
.PixelShaderComputedDepthMode
!= PSCDEPTH_OFF
||
1666 wm_prog_data
->has_side_effects
||
1667 wm
.PixelShaderKillsPixel
||
1668 has_color_buffer_write_enabled(pipeline
, blend
))
1669 wm
.ThreadDispatchEnable
= true;
1672 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1673 if (wm_prog_data
->persample_dispatch
) {
1674 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1676 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1679 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1680 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1688 emit_3dstate_ps(struct anv_pipeline
*pipeline
,
1689 const VkPipelineColorBlendStateCreateInfo
*blend
,
1690 const VkPipelineMultisampleStateCreateInfo
*multisample
)
1692 MAYBE_UNUSED
const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1693 const struct anv_shader_bin
*fs_bin
=
1694 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1696 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1697 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
), ps
) {
1699 /* Even if no fragments are ever dispatched, gen7 hardware hangs if
1700 * we don't at least set the maximum number of threads.
1702 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1708 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1711 /* The hardware wedges if you have this bit set but don't turn on any dual
1712 * source blend factors.
1714 bool dual_src_blend
= false;
1715 if (wm_prog_data
->dual_src_blend
&& blend
) {
1716 for (uint32_t i
= 0; i
< blend
->attachmentCount
; i
++) {
1717 const VkPipelineColorBlendAttachmentState
*bstate
=
1718 &blend
->pAttachments
[i
];
1720 if (bstate
->blendEnable
&&
1721 (is_dual_src_blend_factor(bstate
->srcColorBlendFactor
) ||
1722 is_dual_src_blend_factor(bstate
->dstColorBlendFactor
) ||
1723 is_dual_src_blend_factor(bstate
->srcAlphaBlendFactor
) ||
1724 is_dual_src_blend_factor(bstate
->dstAlphaBlendFactor
))) {
1725 dual_src_blend
= true;
1732 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
), ps
) {
1733 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1734 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1735 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1737 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
1739 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
1740 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
1742 * Since 16x MSAA is first introduced on SKL, we don't need to apply
1743 * the workaround on any older hardware.
1745 if (GEN_GEN
>= 9 && !wm_prog_data
->persample_dispatch
&&
1746 multisample
&& multisample
->rasterizationSamples
== 16) {
1747 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
1748 ps
._32PixelDispatchEnable
= false;
1751 ps
.KernelStartPointer0
= fs_bin
->kernel
.offset
+
1752 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
1753 ps
.KernelStartPointer1
= fs_bin
->kernel
.offset
+
1754 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
1755 ps
.KernelStartPointer2
= fs_bin
->kernel
.offset
+
1756 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
1758 ps
.SingleProgramFlow
= false;
1759 ps
.VectorMaskEnable
= true;
1761 ps
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(fs_bin
);
1762 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
1763 ps
.BindingTableEntryCount
= GEN_GEN
== 11 ? 0 : get_binding_table_entry_count(fs_bin
);
1764 ps
.PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0 ||
1765 wm_prog_data
->base
.ubo_ranges
[0].length
;
1766 ps
.PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
1767 POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
1769 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
1770 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1771 ps
.DualSourceBlendEnable
= dual_src_blend
;
1775 /* Haswell requires the sample mask to be set in this packet as well
1776 * as in 3DSTATE_SAMPLE_MASK; the values should match.
1778 ps
.SampleMask
= 0xff;
1782 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
1784 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
1786 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1789 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
1790 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
1791 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
1792 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
1793 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
1794 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
1796 ps
.PerThreadScratchSpace
= get_scratch_space(fs_bin
);
1797 ps
.ScratchSpaceBasePointer
=
1798 get_scratch_address(pipeline
, MESA_SHADER_FRAGMENT
, fs_bin
);
1804 emit_3dstate_ps_extra(struct anv_pipeline
*pipeline
,
1805 struct anv_subpass
*subpass
,
1806 const VkPipelineColorBlendStateCreateInfo
*blend
)
1808 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1810 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1811 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
), ps
);
1815 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
), ps
) {
1816 ps
.PixelShaderValid
= true;
1817 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
1818 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1819 ps
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
1820 ps
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1821 ps
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1822 ps
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1824 /* If the subpass has a depth or stencil self-dependency, then we need
1825 * to force the hardware to do the depth/stencil write *after* fragment
1826 * shader execution. Otherwise, the writes may hit memory before we get
1827 * around to fetching from the input attachment and we may get the depth
1828 * or stencil value from the current draw rather than the previous one.
1830 ps
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
1831 wm_prog_data
->uses_kill
;
1834 ps
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
1835 ps
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
1837 ps
.InputCoverageMaskState
= ICMS_NONE
;
1838 if (wm_prog_data
->uses_sample_mask
) {
1839 if (wm_prog_data
->post_depth_coverage
)
1840 ps
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
1842 ps
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
1845 ps
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1851 emit_3dstate_vf_topology(struct anv_pipeline
*pipeline
)
1853 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_TOPOLOGY
), vft
) {
1854 vft
.PrimitiveTopologyType
= pipeline
->topology
;
1860 emit_3dstate_vf_statistics(struct anv_pipeline
*pipeline
)
1862 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_STATISTICS
), vfs
) {
1863 vfs
.StatisticsEnable
= true;
1868 compute_kill_pixel(struct anv_pipeline
*pipeline
,
1869 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
1870 const struct anv_subpass
*subpass
)
1872 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1873 pipeline
->kill_pixel
= false;
1877 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1879 /* This computes the KillPixel portion of the computation for whether or
1880 * not we want to enable the PMA fix on gen8 or gen9. It's given by this
1881 * chunk of the giant formula:
1883 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
1884 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
1885 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
1886 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
1887 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
1889 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false and so is
1890 * 3DSTATE_PS_BLEND::AlphaTestEnable since Vulkan doesn't have a concept
1893 pipeline
->kill_pixel
=
1894 subpass
->has_ds_self_dep
|| wm_prog_data
->uses_kill
||
1895 wm_prog_data
->uses_omask
||
1896 (ms_info
&& ms_info
->alphaToCoverageEnable
);
1900 genX(graphics_pipeline_create
)(
1902 struct anv_pipeline_cache
* cache
,
1903 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
1904 const VkAllocationCallbacks
* pAllocator
,
1905 VkPipeline
* pPipeline
)
1907 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1908 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
1909 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1910 struct anv_pipeline
*pipeline
;
1913 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1915 /* Use the default pipeline cache if none is specified */
1916 if (cache
== NULL
&& device
->instance
->pipeline_cache_enabled
)
1917 cache
= &device
->default_pipeline_cache
;
1919 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
1920 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1921 if (pipeline
== NULL
)
1922 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1924 result
= anv_pipeline_init(pipeline
, device
, cache
,
1925 pCreateInfo
, pAllocator
);
1926 if (result
!= VK_SUCCESS
) {
1927 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
1931 assert(pCreateInfo
->pVertexInputState
);
1932 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
);
1933 assert(pCreateInfo
->pRasterizationState
);
1934 emit_rs_state(pipeline
, pCreateInfo
->pRasterizationState
,
1935 pCreateInfo
->pMultisampleState
, pass
, subpass
);
1936 emit_ms_state(pipeline
, pCreateInfo
->pMultisampleState
);
1937 emit_ds_state(pipeline
, pCreateInfo
->pDepthStencilState
, pass
, subpass
);
1938 emit_cb_state(pipeline
, pCreateInfo
->pColorBlendState
,
1939 pCreateInfo
->pMultisampleState
);
1940 compute_kill_pixel(pipeline
, pCreateInfo
->pMultisampleState
, subpass
);
1942 emit_urb_setup(pipeline
);
1944 emit_3dstate_clip(pipeline
, pCreateInfo
->pViewportState
,
1945 pCreateInfo
->pRasterizationState
);
1946 emit_3dstate_streamout(pipeline
, pCreateInfo
->pRasterizationState
);
1949 /* From gen7_vs_state.c */
1952 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
1953 * Geometry > Geometry Shader > State:
1955 * "Note: Because of corruption in IVB:GT2, software needs to flush the
1956 * whole fixed function pipeline when the GS enable changes value in
1959 * The hardware architects have clarified that in this context "flush the
1960 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
1963 if (!device
->info
.is_haswell
&& !device
->info
.is_baytrail
)
1964 gen7_emit_vs_workaround_flush(brw
);
1967 emit_3dstate_vs(pipeline
);
1968 emit_3dstate_hs_te_ds(pipeline
, pCreateInfo
->pTessellationState
);
1969 emit_3dstate_gs(pipeline
);
1970 emit_3dstate_sbe(pipeline
);
1971 emit_3dstate_wm(pipeline
, subpass
, pCreateInfo
->pColorBlendState
,
1972 pCreateInfo
->pMultisampleState
);
1973 emit_3dstate_ps(pipeline
, pCreateInfo
->pColorBlendState
,
1974 pCreateInfo
->pMultisampleState
);
1976 emit_3dstate_ps_extra(pipeline
, subpass
, pCreateInfo
->pColorBlendState
);
1977 emit_3dstate_vf_topology(pipeline
);
1979 emit_3dstate_vf_statistics(pipeline
);
1981 *pPipeline
= anv_pipeline_to_handle(pipeline
);
1983 return pipeline
->batch
.status
;
1987 compute_pipeline_create(
1989 struct anv_pipeline_cache
* cache
,
1990 const VkComputePipelineCreateInfo
* pCreateInfo
,
1991 const VkAllocationCallbacks
* pAllocator
,
1992 VkPipeline
* pPipeline
)
1994 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1995 const struct anv_physical_device
*physical_device
=
1996 &device
->instance
->physicalDevice
;
1997 const struct gen_device_info
*devinfo
= &physical_device
->info
;
1998 struct anv_pipeline
*pipeline
;
2001 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
);
2003 /* Use the default pipeline cache if none is specified */
2004 if (cache
== NULL
&& device
->instance
->pipeline_cache_enabled
)
2005 cache
= &device
->default_pipeline_cache
;
2007 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
2008 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2009 if (pipeline
== NULL
)
2010 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2012 pipeline
->device
= device
;
2014 pipeline
->blend_state
.map
= NULL
;
2016 result
= anv_reloc_list_init(&pipeline
->batch_relocs
,
2017 pAllocator
? pAllocator
: &device
->alloc
);
2018 if (result
!= VK_SUCCESS
) {
2019 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
2022 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
2023 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
2024 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
2025 pipeline
->batch
.status
= VK_SUCCESS
;
2027 /* When we free the pipeline, we detect stages based on the NULL status
2028 * of various prog_data pointers. Make them NULL by default.
2030 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
2032 pipeline
->needs_data_cache
= false;
2034 assert(pCreateInfo
->stage
.stage
== VK_SHADER_STAGE_COMPUTE_BIT
);
2035 pipeline
->active_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2036 ANV_FROM_HANDLE(anv_shader_module
, module
, pCreateInfo
->stage
.module
);
2037 result
= anv_pipeline_compile_cs(pipeline
, cache
, pCreateInfo
, module
,
2038 pCreateInfo
->stage
.pName
,
2039 pCreateInfo
->stage
.pSpecializationInfo
);
2040 if (result
!= VK_SUCCESS
) {
2041 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
2045 const struct brw_cs_prog_data
*cs_prog_data
= get_cs_prog_data(pipeline
);
2047 anv_pipeline_setup_l3_config(pipeline
, cs_prog_data
->base
.total_shared
> 0);
2049 uint32_t group_size
= cs_prog_data
->local_size
[0] *
2050 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
2051 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
2054 pipeline
->cs_right_mask
= ~0u >> (32 - remainder
);
2056 pipeline
->cs_right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
2058 const uint32_t vfe_curbe_allocation
=
2059 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
2060 cs_prog_data
->push
.cross_thread
.regs
, 2);
2062 const uint32_t subslices
= MAX2(physical_device
->subslice_total
, 1);
2064 const struct anv_shader_bin
*cs_bin
=
2065 pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2067 anv_batch_emit(&pipeline
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
2071 vfe
.GPGPUMode
= true;
2073 vfe
.MaximumNumberofThreads
=
2074 devinfo
->max_cs_threads
* subslices
- 1;
2075 vfe
.NumberofURBEntries
= GEN_GEN
<= 7 ? 0 : 2;
2077 vfe
.ResetGatewayTimer
= true;
2080 vfe
.BypassGatewayControl
= true;
2082 vfe
.URBEntryAllocationSize
= GEN_GEN
<= 7 ? 0 : 2;
2083 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
2085 vfe
.PerThreadScratchSpace
= get_scratch_space(cs_bin
);
2086 vfe
.ScratchSpaceBasePointer
=
2087 get_scratch_address(pipeline
, MESA_SHADER_COMPUTE
, cs_bin
);
2090 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2091 .KernelStartPointer
= cs_bin
->kernel
.offset
,
2093 .SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(cs_bin
),
2094 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable
2096 * We add 1 because the CS indirect parameters buffer isn't accounted
2097 * for in bind_map.surface_count.
2099 .BindingTableEntryCount
= GEN_GEN
== 11 ? 0 : 1 + MIN2(cs_bin
->bind_map
.surface_count
, 30),
2100 .BarrierEnable
= cs_prog_data
->uses_barrier
,
2101 .SharedLocalMemorySize
=
2102 encode_slm_size(GEN_GEN
, cs_prog_data
->base
.total_shared
),
2105 .ConstantURBEntryReadOffset
= 0,
2107 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
2108 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2109 .CrossThreadConstantDataReadLength
=
2110 cs_prog_data
->push
.cross_thread
.regs
,
2113 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
2115 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
,
2116 pipeline
->interface_descriptor_data
,
2119 *pPipeline
= anv_pipeline_to_handle(pipeline
);
2121 return pipeline
->batch
.status
;
2124 VkResult
genX(CreateGraphicsPipelines
)(
2126 VkPipelineCache pipelineCache
,
2128 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
2129 const VkAllocationCallbacks
* pAllocator
,
2130 VkPipeline
* pPipelines
)
2132 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
2134 VkResult result
= VK_SUCCESS
;
2137 for (i
= 0; i
< count
; i
++) {
2138 result
= genX(graphics_pipeline_create
)(_device
,
2141 pAllocator
, &pPipelines
[i
]);
2143 /* Bail out on the first error as it is not obvious what error should be
2144 * report upon 2 different failures. */
2145 if (result
!= VK_SUCCESS
)
2149 for (; i
< count
; i
++)
2150 pPipelines
[i
] = VK_NULL_HANDLE
;
2155 VkResult
genX(CreateComputePipelines
)(
2157 VkPipelineCache pipelineCache
,
2159 const VkComputePipelineCreateInfo
* pCreateInfos
,
2160 const VkAllocationCallbacks
* pAllocator
,
2161 VkPipeline
* pPipelines
)
2163 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
2165 VkResult result
= VK_SUCCESS
;
2168 for (i
= 0; i
< count
; i
++) {
2169 result
= compute_pipeline_create(_device
, pipeline_cache
,
2171 pAllocator
, &pPipelines
[i
]);
2173 /* Bail out on the first error as it is not obvious what error should be
2174 * report upon 2 different failures. */
2175 if (result
!= VK_SUCCESS
)
2179 for (; i
< count
; i
++)
2180 pPipelines
[i
] = VK_NULL_HANDLE
;