2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
26 #include "genxml/gen_macros.h"
27 #include "genxml/genX_pack.h"
29 #include "common/gen_l3_config.h"
30 #include "common/gen_sample_positions.h"
31 #include "nir/nir_xfb_info.h"
33 #include "vk_format_info.h"
36 vertex_element_comp_control(enum isl_format format
, unsigned comp
)
40 case 0: bits
= isl_format_layouts
[format
].channels
.r
.bits
; break;
41 case 1: bits
= isl_format_layouts
[format
].channels
.g
.bits
; break;
42 case 2: bits
= isl_format_layouts
[format
].channels
.b
.bits
; break;
43 case 3: bits
= isl_format_layouts
[format
].channels
.a
.bits
; break;
44 default: unreachable("Invalid component");
48 * Take in account hardware restrictions when dealing with 64-bit floats.
50 * From Broadwell spec, command reference structures, page 586:
51 * "When SourceElementFormat is set to one of the *64*_PASSTHRU formats,
52 * 64-bit components are stored * in the URB without any conversion. In
53 * this case, vertex elements must be written as 128 or 256 bits, with
54 * VFCOMP_STORE_0 being used to pad the output as required. E.g., if
55 * R64_PASSTHRU is used to copy a 64-bit Red component into the URB,
56 * Component 1 must be specified as VFCOMP_STORE_0 (with Components 2,3
57 * set to VFCOMP_NOSTORE) in order to output a 128-bit vertex element, or
58 * Components 1-3 must be specified as VFCOMP_STORE_0 in order to output
59 * a 256-bit vertex element. Likewise, use of R64G64B64_PASSTHRU requires
60 * Component 3 to be specified as VFCOMP_STORE_0 in order to output a
61 * 256-bit vertex element."
64 return VFCOMP_STORE_SRC
;
65 } else if (comp
>= 2 &&
66 !isl_format_layouts
[format
].channels
.b
.bits
&&
67 isl_format_layouts
[format
].channels
.r
.type
== ISL_RAW
) {
68 /* When emitting 64-bit attributes, we need to write either 128 or 256
69 * bit chunks, using VFCOMP_NOSTORE when not writing the chunk, and
70 * VFCOMP_STORE_0 to pad the written chunk */
71 return VFCOMP_NOSTORE
;
72 } else if (comp
< 3 ||
73 isl_format_layouts
[format
].channels
.r
.type
== ISL_RAW
) {
74 /* Note we need to pad with value 0, not 1, due hardware restrictions
75 * (see comment above) */
76 return VFCOMP_STORE_0
;
77 } else if (isl_format_layouts
[format
].channels
.r
.type
== ISL_UINT
||
78 isl_format_layouts
[format
].channels
.r
.type
== ISL_SINT
) {
80 return VFCOMP_STORE_1_INT
;
83 return VFCOMP_STORE_1_FP
;
88 emit_vertex_input(struct anv_pipeline
*pipeline
,
89 const VkPipelineVertexInputStateCreateInfo
*info
)
91 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
93 /* Pull inputs_read out of the VS prog data */
94 const uint64_t inputs_read
= vs_prog_data
->inputs_read
;
95 const uint64_t double_inputs_read
=
96 vs_prog_data
->double_inputs_read
& inputs_read
;
97 assert((inputs_read
& ((1 << VERT_ATTRIB_GENERIC0
) - 1)) == 0);
98 const uint32_t elements
= inputs_read
>> VERT_ATTRIB_GENERIC0
;
99 const uint32_t elements_double
= double_inputs_read
>> VERT_ATTRIB_GENERIC0
;
100 const bool needs_svgs_elem
= vs_prog_data
->uses_vertexid
||
101 vs_prog_data
->uses_instanceid
||
102 vs_prog_data
->uses_firstvertex
||
103 vs_prog_data
->uses_baseinstance
;
105 uint32_t elem_count
= __builtin_popcount(elements
) -
106 __builtin_popcount(elements_double
) / 2;
108 const uint32_t total_elems
=
109 MAX2(1, elem_count
+ needs_svgs_elem
+ vs_prog_data
->uses_drawid
);
113 const uint32_t num_dwords
= 1 + total_elems
* 2;
114 p
= anv_batch_emitn(&pipeline
->batch
, num_dwords
,
115 GENX(3DSTATE_VERTEX_ELEMENTS
));
119 for (uint32_t i
= 0; i
< total_elems
; i
++) {
120 /* The SKL docs for VERTEX_ELEMENT_STATE say:
122 * "All elements must be valid from Element[0] to the last valid
123 * element. (I.e. if Element[2] is valid then Element[1] and
124 * Element[0] must also be valid)."
126 * The SKL docs for 3D_Vertex_Component_Control say:
128 * "Don't store this component. (Not valid for Component 0, but can
129 * be used for Component 1-3)."
131 * So we can't just leave a vertex element blank and hope for the best.
132 * We have to tell the VF hardware to put something in it; so we just
133 * store a bunch of zero.
135 * TODO: Compact vertex elements so we never end up with holes.
137 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
139 .Component0Control
= VFCOMP_STORE_0
,
140 .Component1Control
= VFCOMP_STORE_0
,
141 .Component2Control
= VFCOMP_STORE_0
,
142 .Component3Control
= VFCOMP_STORE_0
,
144 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + i
* 2], &element
);
147 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
148 const VkVertexInputAttributeDescription
*desc
=
149 &info
->pVertexAttributeDescriptions
[i
];
150 enum isl_format format
= anv_get_isl_format(&pipeline
->device
->info
,
152 VK_IMAGE_ASPECT_COLOR_BIT
,
153 VK_IMAGE_TILING_LINEAR
);
155 assert(desc
->binding
< MAX_VBS
);
157 if ((elements
& (1 << desc
->location
)) == 0)
158 continue; /* Binding unused */
161 __builtin_popcount(elements
& ((1 << desc
->location
) - 1)) -
162 DIV_ROUND_UP(__builtin_popcount(elements_double
&
163 ((1 << desc
->location
) -1)), 2);
165 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
166 .VertexBufferIndex
= desc
->binding
,
168 .SourceElementFormat
= format
,
169 .EdgeFlagEnable
= false,
170 .SourceElementOffset
= desc
->offset
,
171 .Component0Control
= vertex_element_comp_control(format
, 0),
172 .Component1Control
= vertex_element_comp_control(format
, 1),
173 .Component2Control
= vertex_element_comp_control(format
, 2),
174 .Component3Control
= vertex_element_comp_control(format
, 3),
176 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + slot
* 2], &element
);
179 /* On Broadwell and later, we have a separate VF_INSTANCING packet
180 * that controls instancing. On Haswell and prior, that's part of
181 * VERTEX_BUFFER_STATE which we emit later.
183 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
184 vfi
.InstancingEnable
= pipeline
->vb
[desc
->binding
].instanced
;
185 vfi
.VertexElementIndex
= slot
;
186 vfi
.InstanceDataStepRate
=
187 pipeline
->vb
[desc
->binding
].instance_divisor
;
192 const uint32_t id_slot
= elem_count
;
193 if (needs_svgs_elem
) {
194 /* From the Broadwell PRM for the 3D_Vertex_Component_Control enum:
195 * "Within a VERTEX_ELEMENT_STATE structure, if a Component
196 * Control field is set to something other than VFCOMP_STORE_SRC,
197 * no higher-numbered Component Control fields may be set to
200 * This means, that if we have BaseInstance, we need BaseVertex as
201 * well. Just do all or nothing.
203 uint32_t base_ctrl
= (vs_prog_data
->uses_firstvertex
||
204 vs_prog_data
->uses_baseinstance
) ?
205 VFCOMP_STORE_SRC
: VFCOMP_STORE_0
;
207 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
208 .VertexBufferIndex
= ANV_SVGS_VB_INDEX
,
210 .SourceElementFormat
= ISL_FORMAT_R32G32_UINT
,
211 .Component0Control
= base_ctrl
,
212 .Component1Control
= base_ctrl
,
214 .Component2Control
= VFCOMP_STORE_0
,
215 .Component3Control
= VFCOMP_STORE_0
,
217 .Component2Control
= VFCOMP_STORE_VID
,
218 .Component3Control
= VFCOMP_STORE_IID
,
221 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
, &p
[1 + id_slot
* 2], &element
);
225 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
226 sgvs
.VertexIDEnable
= vs_prog_data
->uses_vertexid
;
227 sgvs
.VertexIDComponentNumber
= 2;
228 sgvs
.VertexIDElementOffset
= id_slot
;
229 sgvs
.InstanceIDEnable
= vs_prog_data
->uses_instanceid
;
230 sgvs
.InstanceIDComponentNumber
= 3;
231 sgvs
.InstanceIDElementOffset
= id_slot
;
235 const uint32_t drawid_slot
= elem_count
+ needs_svgs_elem
;
236 if (vs_prog_data
->uses_drawid
) {
237 struct GENX(VERTEX_ELEMENT_STATE
) element
= {
238 .VertexBufferIndex
= ANV_DRAWID_VB_INDEX
,
240 .SourceElementFormat
= ISL_FORMAT_R32_UINT
,
241 .Component0Control
= VFCOMP_STORE_SRC
,
242 .Component1Control
= VFCOMP_STORE_0
,
243 .Component2Control
= VFCOMP_STORE_0
,
244 .Component3Control
= VFCOMP_STORE_0
,
246 GENX(VERTEX_ELEMENT_STATE_pack
)(NULL
,
247 &p
[1 + drawid_slot
* 2],
251 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_INSTANCING
), vfi
) {
252 vfi
.VertexElementIndex
= drawid_slot
;
259 genX(emit_urb_setup
)(struct anv_device
*device
, struct anv_batch
*batch
,
260 const struct gen_l3_config
*l3_config
,
261 VkShaderStageFlags active_stages
,
262 const unsigned entry_size
[4])
264 const struct gen_device_info
*devinfo
= &device
->info
;
266 const unsigned push_constant_kb
= devinfo
->gt
== 3 ? 32 : 16;
268 const unsigned push_constant_kb
= GEN_GEN
>= 8 ? 32 : 16;
271 const unsigned urb_size_kb
= gen_get_l3_config_urb_size(devinfo
, l3_config
);
275 gen_get_urb_config(devinfo
,
276 1024 * push_constant_kb
, 1024 * urb_size_kb
,
278 VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
,
279 active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
,
280 entry_size
, entries
, start
);
282 #if GEN_GEN == 7 && !GEN_IS_HASWELL
283 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
285 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
286 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
287 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
288 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
289 * needs to be sent before any combination of VS associated 3DSTATE."
291 anv_batch_emit(batch
, GEN7_PIPE_CONTROL
, pc
) {
292 pc
.DepthStallEnable
= true;
293 pc
.PostSyncOperation
= WriteImmediateData
;
294 pc
.Address
= (struct anv_address
) { device
->workaround_bo
, 0 };
298 for (int i
= 0; i
<= MESA_SHADER_GEOMETRY
; i
++) {
299 anv_batch_emit(batch
, GENX(3DSTATE_URB_VS
), urb
) {
300 urb
._3DCommandSubOpcode
+= i
;
301 urb
.VSURBStartingAddress
= start
[i
];
302 urb
.VSURBEntryAllocationSize
= entry_size
[i
] - 1;
303 urb
.VSNumberofURBEntries
= entries
[i
];
309 emit_urb_setup(struct anv_pipeline
*pipeline
)
311 unsigned entry_size
[4];
312 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
313 const struct brw_vue_prog_data
*prog_data
=
314 !anv_pipeline_has_stage(pipeline
, i
) ? NULL
:
315 (const struct brw_vue_prog_data
*) pipeline
->shaders
[i
]->prog_data
;
317 entry_size
[i
] = prog_data
? prog_data
->urb_entry_size
: 1;
320 genX(emit_urb_setup
)(pipeline
->device
, &pipeline
->batch
,
321 pipeline
->urb
.l3_config
,
322 pipeline
->active_stages
, entry_size
);
326 emit_3dstate_sbe(struct anv_pipeline
*pipeline
)
328 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
330 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
331 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SBE
), sbe
);
333 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SBE_SWIZ
), sbe
);
338 const struct brw_vue_map
*fs_input_map
=
339 &anv_pipeline_get_last_vue_prog_data(pipeline
)->vue_map
;
341 struct GENX(3DSTATE_SBE
) sbe
= {
342 GENX(3DSTATE_SBE_header
),
343 .AttributeSwizzleEnable
= true,
344 .PointSpriteTextureCoordinateOrigin
= UPPERLEFT
,
345 .NumberofSFOutputAttributes
= wm_prog_data
->num_varying_inputs
,
346 .ConstantInterpolationEnable
= wm_prog_data
->flat_inputs
,
350 for (unsigned i
= 0; i
< 32; i
++)
351 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
355 /* On Broadwell, they broke 3DSTATE_SBE into two packets */
356 struct GENX(3DSTATE_SBE_SWIZ
) swiz
= {
357 GENX(3DSTATE_SBE_SWIZ_header
),
363 /* Skip the VUE header and position slots by default */
364 unsigned urb_entry_read_offset
= 1;
365 int max_source_attr
= 0;
366 for (int attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
367 int input_index
= wm_prog_data
->urb_setup
[attr
];
372 /* gl_Viewport and gl_Layer are stored in the VUE header */
373 if (attr
== VARYING_SLOT_VIEWPORT
|| attr
== VARYING_SLOT_LAYER
) {
374 urb_entry_read_offset
= 0;
378 if (attr
== VARYING_SLOT_PNTC
) {
379 sbe
.PointSpriteTextureCoordinateEnable
= 1 << input_index
;
383 const int slot
= fs_input_map
->varying_to_slot
[attr
];
385 if (input_index
>= 16)
389 /* This attribute does not exist in the VUE--that means that the
390 * vertex shader did not write to it. It could be that it's a
391 * regular varying read by the fragment shader but not written by
392 * the vertex shader or it's gl_PrimitiveID. In the first case the
393 * value is undefined, in the second it needs to be
396 swiz
.Attribute
[input_index
].ConstantSource
= PRIM_ID
;
397 swiz
.Attribute
[input_index
].ComponentOverrideX
= true;
398 swiz
.Attribute
[input_index
].ComponentOverrideY
= true;
399 swiz
.Attribute
[input_index
].ComponentOverrideZ
= true;
400 swiz
.Attribute
[input_index
].ComponentOverrideW
= true;
402 /* We have to subtract two slots to accout for the URB entry output
403 * read offset in the VS and GS stages.
405 const int source_attr
= slot
- 2 * urb_entry_read_offset
;
406 assert(source_attr
>= 0 && source_attr
< 32);
407 max_source_attr
= MAX2(max_source_attr
, source_attr
);
408 swiz
.Attribute
[input_index
].SourceAttribute
= source_attr
;
412 sbe
.VertexURBEntryReadOffset
= urb_entry_read_offset
;
413 sbe
.VertexURBEntryReadLength
= DIV_ROUND_UP(max_source_attr
+ 1, 2);
415 sbe
.ForceVertexURBEntryReadOffset
= true;
416 sbe
.ForceVertexURBEntryReadLength
= true;
419 uint32_t *dw
= anv_batch_emit_dwords(&pipeline
->batch
,
420 GENX(3DSTATE_SBE_length
));
423 GENX(3DSTATE_SBE_pack
)(&pipeline
->batch
, dw
, &sbe
);
426 dw
= anv_batch_emit_dwords(&pipeline
->batch
, GENX(3DSTATE_SBE_SWIZ_length
));
429 GENX(3DSTATE_SBE_SWIZ_pack
)(&pipeline
->batch
, dw
, &swiz
);
433 static const uint32_t vk_to_gen_cullmode
[] = {
434 [VK_CULL_MODE_NONE
] = CULLMODE_NONE
,
435 [VK_CULL_MODE_FRONT_BIT
] = CULLMODE_FRONT
,
436 [VK_CULL_MODE_BACK_BIT
] = CULLMODE_BACK
,
437 [VK_CULL_MODE_FRONT_AND_BACK
] = CULLMODE_BOTH
440 static const uint32_t vk_to_gen_fillmode
[] = {
441 [VK_POLYGON_MODE_FILL
] = FILL_MODE_SOLID
,
442 [VK_POLYGON_MODE_LINE
] = FILL_MODE_WIREFRAME
,
443 [VK_POLYGON_MODE_POINT
] = FILL_MODE_POINT
,
446 static const uint32_t vk_to_gen_front_face
[] = {
447 [VK_FRONT_FACE_COUNTER_CLOCKWISE
] = 1,
448 [VK_FRONT_FACE_CLOCKWISE
] = 0
451 static VkLineRasterizationModeEXT
452 vk_line_rasterization_mode(const VkPipelineRasterizationLineStateCreateInfoEXT
*line_info
,
453 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
455 VkLineRasterizationModeEXT line_mode
=
456 line_info
? line_info
->lineRasterizationMode
:
457 VK_LINE_RASTERIZATION_MODE_DEFAULT_EXT
;
459 if (line_mode
== VK_LINE_RASTERIZATION_MODE_DEFAULT_EXT
) {
460 if (ms_info
&& ms_info
->rasterizationSamples
> 1) {
461 return VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT
;
463 return VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
;
470 /** Returns the final polygon mode for rasterization
472 * This function takes into account polygon mode, primitive topology and the
473 * different shader stages which might generate their own type of primitives.
476 anv_raster_polygon_mode(struct anv_pipeline
*pipeline
,
477 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
,
478 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
480 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
)) {
481 switch (get_gs_prog_data(pipeline
)->output_topology
) {
482 case _3DPRIM_POINTLIST
:
483 return VK_POLYGON_MODE_POINT
;
485 case _3DPRIM_LINELIST
:
486 case _3DPRIM_LINESTRIP
:
487 case _3DPRIM_LINELOOP
:
488 return VK_POLYGON_MODE_LINE
;
490 case _3DPRIM_TRILIST
:
492 case _3DPRIM_TRISTRIP
:
493 case _3DPRIM_RECTLIST
:
494 case _3DPRIM_QUADLIST
:
495 case _3DPRIM_QUADSTRIP
:
496 case _3DPRIM_POLYGON
:
497 return rs_info
->polygonMode
;
499 unreachable("Unsupported GS output topology");
500 } else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
501 switch (get_tes_prog_data(pipeline
)->output_topology
) {
502 case BRW_TESS_OUTPUT_TOPOLOGY_POINT
:
503 return VK_POLYGON_MODE_POINT
;
505 case BRW_TESS_OUTPUT_TOPOLOGY_LINE
:
506 return VK_POLYGON_MODE_LINE
;
508 case BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
:
509 case BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
:
510 return rs_info
->polygonMode
;
512 unreachable("Unsupported TCS output topology");
514 switch (ia_info
->topology
) {
515 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
516 return VK_POLYGON_MODE_POINT
;
518 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
519 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
520 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
521 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
522 return VK_POLYGON_MODE_LINE
;
524 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
525 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
526 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
527 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
528 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
529 return rs_info
->polygonMode
;
532 unreachable("Unsupported primitive topology");
539 gen7_ms_rast_mode(struct anv_pipeline
*pipeline
,
540 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
,
541 const VkPipelineRasterizationStateCreateInfo
*rs_info
,
542 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
544 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_info
=
545 vk_find_struct_const(rs_info
->pNext
,
546 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
548 VkPolygonMode raster_mode
=
549 anv_raster_polygon_mode(pipeline
, ia_info
, rs_info
);
550 if (raster_mode
== VK_POLYGON_MODE_LINE
) {
551 switch (vk_line_rasterization_mode(line_info
, ms_info
)) {
552 case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT
:
553 return MSRASTMODE_ON_PATTERN
;
555 case VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
:
556 case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT
:
557 return MSRASTMODE_OFF_PIXEL
;
560 unreachable("Unsupported line rasterization mode");
563 return (ms_info
&& ms_info
->rasterizationSamples
> 1) ?
564 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
570 emit_rs_state(struct anv_pipeline
*pipeline
,
571 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
,
572 const VkPipelineRasterizationStateCreateInfo
*rs_info
,
573 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
574 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_info
,
575 const struct anv_render_pass
*pass
,
576 const struct anv_subpass
*subpass
)
578 struct GENX(3DSTATE_SF
) sf
= {
579 GENX(3DSTATE_SF_header
),
582 sf
.ViewportTransformEnable
= true;
583 sf
.StatisticsEnable
= true;
584 sf
.TriangleStripListProvokingVertexSelect
= 0;
585 sf
.LineStripListProvokingVertexSelect
= 0;
586 sf
.TriangleFanProvokingVertexSelect
= 1;
587 sf
.VertexSubPixelPrecisionSelect
= _8Bit
;
588 sf
.AALineDistanceMode
= true;
591 sf
.LineStippleEnable
= line_info
&& line_info
->stippledLineEnable
;
594 const struct brw_vue_prog_data
*last_vue_prog_data
=
595 anv_pipeline_get_last_vue_prog_data(pipeline
);
597 if (last_vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
598 sf
.PointWidthSource
= Vertex
;
600 sf
.PointWidthSource
= State
;
605 struct GENX(3DSTATE_RASTER
) raster
= {
606 GENX(3DSTATE_RASTER_header
),
612 VkPolygonMode raster_mode
=
613 anv_raster_polygon_mode(pipeline
, ia_info
, rs_info
);
614 VkLineRasterizationModeEXT line_mode
=
615 vk_line_rasterization_mode(line_info
, ms_info
);
617 /* For details on 3DSTATE_RASTER multisample state, see the BSpec table
618 * "Multisample Modes State".
621 if (raster_mode
== VK_POLYGON_MODE_LINE
) {
622 /* Unfortunately, configuring our line rasterization hardware on gen8
623 * and later is rather painful. Instead of giving us bits to tell the
624 * hardware what line mode to use like we had on gen7, we now have an
625 * arcane combination of API Mode and MSAA enable bits which do things
626 * in a table which are expected to magically put the hardware into the
627 * right mode for your API. Sadly, Vulkan isn't any of the APIs the
628 * hardware people thought of so nothing works the way you want it to.
630 * Look at the table titled "Multisample Rasterization Modes" in Vol 7
631 * of the Skylake PRM for more details.
634 case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT
:
635 raster
.APIMode
= DX100
;
636 raster
.DXMultisampleRasterizationEnable
= true;
639 case VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
:
640 case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT
:
641 raster
.APIMode
= DX9OGL
;
642 raster
.DXMultisampleRasterizationEnable
= false;
646 unreachable("Unsupported line rasterization mode");
649 raster
.APIMode
= DX100
;
650 raster
.DXMultisampleRasterizationEnable
= true;
653 /* NOTE: 3DSTATE_RASTER::ForcedSampleCount affects the BDW and SKL PMA fix
654 * computations. If we ever set this bit to a different value, they will
655 * need to be updated accordingly.
657 raster
.ForcedSampleCount
= FSC_NUMRASTSAMPLES_0
;
658 raster
.ForceMultisampling
= false;
660 raster
.MultisampleRasterizationMode
=
661 gen7_ms_rast_mode(pipeline
, ia_info
, rs_info
, ms_info
);
664 if (raster_mode
== VK_POLYGON_MODE_LINE
&&
665 line_mode
== VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT
)
666 raster
.AntialiasingEnable
= true;
668 raster
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
];
669 raster
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
];
670 raster
.FrontFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
671 raster
.BackFaceFillMode
= vk_to_gen_fillmode
[rs_info
->polygonMode
];
672 raster
.ScissorRectangleEnable
= true;
675 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */
676 raster
.ViewportZFarClipTestEnable
= pipeline
->depth_clip_enable
;
677 raster
.ViewportZNearClipTestEnable
= pipeline
->depth_clip_enable
;
679 raster
.ViewportZClipTestEnable
= pipeline
->depth_clip_enable
;
682 raster
.GlobalDepthOffsetEnableSolid
= rs_info
->depthBiasEnable
;
683 raster
.GlobalDepthOffsetEnableWireframe
= rs_info
->depthBiasEnable
;
684 raster
.GlobalDepthOffsetEnablePoint
= rs_info
->depthBiasEnable
;
687 /* Gen7 requires that we provide the depth format in 3DSTATE_SF so that it
688 * can get the depth offsets correct.
690 if (subpass
->depth_stencil_attachment
) {
692 pass
->attachments
[subpass
->depth_stencil_attachment
->attachment
].format
;
693 assert(vk_format_is_depth_or_stencil(vk_format
));
694 if (vk_format_aspects(vk_format
) & VK_IMAGE_ASPECT_DEPTH_BIT
) {
695 enum isl_format isl_format
=
696 anv_get_isl_format(&pipeline
->device
->info
, vk_format
,
697 VK_IMAGE_ASPECT_DEPTH_BIT
,
698 VK_IMAGE_TILING_OPTIMAL
);
699 sf
.DepthBufferSurfaceFormat
=
700 isl_format_get_depth_format(isl_format
, false);
706 GENX(3DSTATE_SF_pack
)(NULL
, pipeline
->gen8
.sf
, &sf
);
707 GENX(3DSTATE_RASTER_pack
)(NULL
, pipeline
->gen8
.raster
, &raster
);
710 GENX(3DSTATE_SF_pack
)(NULL
, &pipeline
->gen7
.sf
, &sf
);
715 emit_ms_state(struct anv_pipeline
*pipeline
,
716 const VkPipelineMultisampleStateCreateInfo
*info
)
718 uint32_t samples
= 1;
719 uint32_t log2_samples
= 0;
721 /* From the Vulkan 1.0 spec:
722 * If pSampleMask is NULL, it is treated as if the mask has all bits
723 * enabled, i.e. no coverage is removed from fragments.
725 * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
728 uint32_t sample_mask
= 0xffff;
730 uint32_t sample_mask
= 0xff;
734 samples
= info
->rasterizationSamples
;
735 log2_samples
= __builtin_ffs(samples
) - 1;
738 if (info
&& info
->pSampleMask
)
739 sample_mask
&= info
->pSampleMask
[0];
741 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
742 ms
.NumberofMultisamples
= log2_samples
;
744 ms
.PixelLocation
= CENTER
;
746 /* The PRM says that this bit is valid only for DX9:
748 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
749 * should not have any effect by setting or not setting this bit.
751 ms
.PixelPositionOffsetEnable
= false;
756 GEN_SAMPLE_POS_1X(ms
.Sample
);
759 GEN_SAMPLE_POS_2X(ms
.Sample
);
762 GEN_SAMPLE_POS_4X(ms
.Sample
);
765 GEN_SAMPLE_POS_8X(ms
.Sample
);
773 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_SAMPLE_MASK
), sm
) {
774 sm
.SampleMask
= sample_mask
;
778 static const uint32_t vk_to_gen_logic_op
[] = {
779 [VK_LOGIC_OP_COPY
] = LOGICOP_COPY
,
780 [VK_LOGIC_OP_CLEAR
] = LOGICOP_CLEAR
,
781 [VK_LOGIC_OP_AND
] = LOGICOP_AND
,
782 [VK_LOGIC_OP_AND_REVERSE
] = LOGICOP_AND_REVERSE
,
783 [VK_LOGIC_OP_AND_INVERTED
] = LOGICOP_AND_INVERTED
,
784 [VK_LOGIC_OP_NO_OP
] = LOGICOP_NOOP
,
785 [VK_LOGIC_OP_XOR
] = LOGICOP_XOR
,
786 [VK_LOGIC_OP_OR
] = LOGICOP_OR
,
787 [VK_LOGIC_OP_NOR
] = LOGICOP_NOR
,
788 [VK_LOGIC_OP_EQUIVALENT
] = LOGICOP_EQUIV
,
789 [VK_LOGIC_OP_INVERT
] = LOGICOP_INVERT
,
790 [VK_LOGIC_OP_OR_REVERSE
] = LOGICOP_OR_REVERSE
,
791 [VK_LOGIC_OP_COPY_INVERTED
] = LOGICOP_COPY_INVERTED
,
792 [VK_LOGIC_OP_OR_INVERTED
] = LOGICOP_OR_INVERTED
,
793 [VK_LOGIC_OP_NAND
] = LOGICOP_NAND
,
794 [VK_LOGIC_OP_SET
] = LOGICOP_SET
,
797 static const uint32_t vk_to_gen_blend
[] = {
798 [VK_BLEND_FACTOR_ZERO
] = BLENDFACTOR_ZERO
,
799 [VK_BLEND_FACTOR_ONE
] = BLENDFACTOR_ONE
,
800 [VK_BLEND_FACTOR_SRC_COLOR
] = BLENDFACTOR_SRC_COLOR
,
801 [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
] = BLENDFACTOR_INV_SRC_COLOR
,
802 [VK_BLEND_FACTOR_DST_COLOR
] = BLENDFACTOR_DST_COLOR
,
803 [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
] = BLENDFACTOR_INV_DST_COLOR
,
804 [VK_BLEND_FACTOR_SRC_ALPHA
] = BLENDFACTOR_SRC_ALPHA
,
805 [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
] = BLENDFACTOR_INV_SRC_ALPHA
,
806 [VK_BLEND_FACTOR_DST_ALPHA
] = BLENDFACTOR_DST_ALPHA
,
807 [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
] = BLENDFACTOR_INV_DST_ALPHA
,
808 [VK_BLEND_FACTOR_CONSTANT_COLOR
] = BLENDFACTOR_CONST_COLOR
,
809 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
]= BLENDFACTOR_INV_CONST_COLOR
,
810 [VK_BLEND_FACTOR_CONSTANT_ALPHA
] = BLENDFACTOR_CONST_ALPHA
,
811 [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
]= BLENDFACTOR_INV_CONST_ALPHA
,
812 [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
] = BLENDFACTOR_SRC_ALPHA_SATURATE
,
813 [VK_BLEND_FACTOR_SRC1_COLOR
] = BLENDFACTOR_SRC1_COLOR
,
814 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
] = BLENDFACTOR_INV_SRC1_COLOR
,
815 [VK_BLEND_FACTOR_SRC1_ALPHA
] = BLENDFACTOR_SRC1_ALPHA
,
816 [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
] = BLENDFACTOR_INV_SRC1_ALPHA
,
819 static const uint32_t vk_to_gen_blend_op
[] = {
820 [VK_BLEND_OP_ADD
] = BLENDFUNCTION_ADD
,
821 [VK_BLEND_OP_SUBTRACT
] = BLENDFUNCTION_SUBTRACT
,
822 [VK_BLEND_OP_REVERSE_SUBTRACT
] = BLENDFUNCTION_REVERSE_SUBTRACT
,
823 [VK_BLEND_OP_MIN
] = BLENDFUNCTION_MIN
,
824 [VK_BLEND_OP_MAX
] = BLENDFUNCTION_MAX
,
827 static const uint32_t vk_to_gen_compare_op
[] = {
828 [VK_COMPARE_OP_NEVER
] = PREFILTEROPNEVER
,
829 [VK_COMPARE_OP_LESS
] = PREFILTEROPLESS
,
830 [VK_COMPARE_OP_EQUAL
] = PREFILTEROPEQUAL
,
831 [VK_COMPARE_OP_LESS_OR_EQUAL
] = PREFILTEROPLEQUAL
,
832 [VK_COMPARE_OP_GREATER
] = PREFILTEROPGREATER
,
833 [VK_COMPARE_OP_NOT_EQUAL
] = PREFILTEROPNOTEQUAL
,
834 [VK_COMPARE_OP_GREATER_OR_EQUAL
] = PREFILTEROPGEQUAL
,
835 [VK_COMPARE_OP_ALWAYS
] = PREFILTEROPALWAYS
,
838 static const uint32_t vk_to_gen_stencil_op
[] = {
839 [VK_STENCIL_OP_KEEP
] = STENCILOP_KEEP
,
840 [VK_STENCIL_OP_ZERO
] = STENCILOP_ZERO
,
841 [VK_STENCIL_OP_REPLACE
] = STENCILOP_REPLACE
,
842 [VK_STENCIL_OP_INCREMENT_AND_CLAMP
] = STENCILOP_INCRSAT
,
843 [VK_STENCIL_OP_DECREMENT_AND_CLAMP
] = STENCILOP_DECRSAT
,
844 [VK_STENCIL_OP_INVERT
] = STENCILOP_INVERT
,
845 [VK_STENCIL_OP_INCREMENT_AND_WRAP
] = STENCILOP_INCR
,
846 [VK_STENCIL_OP_DECREMENT_AND_WRAP
] = STENCILOP_DECR
,
849 /* This function sanitizes the VkStencilOpState by looking at the compare ops
850 * and trying to determine whether or not a given stencil op can ever actually
851 * occur. Stencil ops which can never occur are set to VK_STENCIL_OP_KEEP.
852 * This function returns true if, after sanitation, any of the stencil ops are
853 * set to something other than VK_STENCIL_OP_KEEP.
856 sanitize_stencil_face(VkStencilOpState
*face
,
857 VkCompareOp depthCompareOp
)
859 /* If compareOp is ALWAYS then the stencil test will never fail and failOp
860 * will never happen. Set failOp to KEEP in this case.
862 if (face
->compareOp
== VK_COMPARE_OP_ALWAYS
)
863 face
->failOp
= VK_STENCIL_OP_KEEP
;
865 /* If compareOp is NEVER or depthCompareOp is NEVER then one of the depth
866 * or stencil tests will fail and passOp will never happen.
868 if (face
->compareOp
== VK_COMPARE_OP_NEVER
||
869 depthCompareOp
== VK_COMPARE_OP_NEVER
)
870 face
->passOp
= VK_STENCIL_OP_KEEP
;
872 /* If compareOp is NEVER or depthCompareOp is ALWAYS then either the
873 * stencil test will fail or the depth test will pass. In either case,
874 * depthFailOp will never happen.
876 if (face
->compareOp
== VK_COMPARE_OP_NEVER
||
877 depthCompareOp
== VK_COMPARE_OP_ALWAYS
)
878 face
->depthFailOp
= VK_STENCIL_OP_KEEP
;
880 return face
->failOp
!= VK_STENCIL_OP_KEEP
||
881 face
->depthFailOp
!= VK_STENCIL_OP_KEEP
||
882 face
->passOp
!= VK_STENCIL_OP_KEEP
;
885 /* Intel hardware is fairly sensitive to whether or not depth/stencil writes
886 * are enabled. In the presence of discards, it's fairly easy to get into the
887 * non-promoted case which means a fairly big performance hit. From the Iron
888 * Lake PRM, Vol 2, pt. 1, section 8.4.3.2, "Early Depth Test Cases":
890 * "Non-promoted depth (N) is active whenever the depth test can be done
891 * early but it cannot determine whether or not to write source depth to
892 * the depth buffer, therefore the depth write must be performed post pixel
893 * shader. This includes cases where the pixel shader can kill pixels,
894 * including via sampler chroma key, as well as cases where the alpha test
895 * function is enabled, which kills pixels based on a programmable alpha
896 * test. In this case, even if the depth test fails, the pixel cannot be
897 * killed if a stencil write is indicated. Whether or not the stencil write
898 * happens depends on whether or not the pixel is killed later. In these
899 * cases if stencil test fails and stencil writes are off, the pixels can
900 * also be killed early. If stencil writes are enabled, the pixels must be
901 * treated as Computed depth (described above)."
903 * The same thing as mentioned in the stencil case can happen in the depth
904 * case as well if it thinks it writes depth but, thanks to the depth test
905 * being GL_EQUAL, the write doesn't actually matter. A little extra work
906 * up-front to try and disable depth and stencil writes can make a big
909 * Unfortunately, the way depth and stencil testing is specified, there are
910 * many case where, regardless of depth/stencil writes being enabled, nothing
911 * actually gets written due to some other bit of state being set. This
912 * function attempts to "sanitize" the depth stencil state and disable writes
913 * and sometimes even testing whenever possible.
916 sanitize_ds_state(VkPipelineDepthStencilStateCreateInfo
*state
,
917 bool *stencilWriteEnable
,
918 VkImageAspectFlags ds_aspects
)
920 *stencilWriteEnable
= state
->stencilTestEnable
;
922 /* If the depth test is disabled, we won't be writing anything. Make sure we
923 * treat the test as always passing later on as well.
925 * Also, the Vulkan spec requires that if either depth or stencil is not
926 * present, the pipeline is to act as if the test silently passes. In that
927 * case we won't write either.
929 if (!state
->depthTestEnable
|| !(ds_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
930 state
->depthWriteEnable
= false;
931 state
->depthCompareOp
= VK_COMPARE_OP_ALWAYS
;
934 if (!(ds_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
935 *stencilWriteEnable
= false;
936 state
->front
.compareOp
= VK_COMPARE_OP_ALWAYS
;
937 state
->back
.compareOp
= VK_COMPARE_OP_ALWAYS
;
940 /* If the stencil test is enabled and always fails, then we will never get
941 * to the depth test so we can just disable the depth test entirely.
943 if (state
->stencilTestEnable
&&
944 state
->front
.compareOp
== VK_COMPARE_OP_NEVER
&&
945 state
->back
.compareOp
== VK_COMPARE_OP_NEVER
) {
946 state
->depthTestEnable
= false;
947 state
->depthWriteEnable
= false;
950 /* If depthCompareOp is EQUAL then the value we would be writing to the
951 * depth buffer is the same as the value that's already there so there's no
952 * point in writing it.
954 if (state
->depthCompareOp
== VK_COMPARE_OP_EQUAL
)
955 state
->depthWriteEnable
= false;
957 /* If the stencil ops are such that we don't actually ever modify the
958 * stencil buffer, we should disable writes.
960 if (!sanitize_stencil_face(&state
->front
, state
->depthCompareOp
) &&
961 !sanitize_stencil_face(&state
->back
, state
->depthCompareOp
))
962 *stencilWriteEnable
= false;
964 /* If the depth test always passes and we never write out depth, that's the
965 * same as if the depth test is disabled entirely.
967 if (state
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
&&
968 !state
->depthWriteEnable
)
969 state
->depthTestEnable
= false;
971 /* If the stencil test always passes and we never write out stencil, that's
972 * the same as if the stencil test is disabled entirely.
974 if (state
->front
.compareOp
== VK_COMPARE_OP_ALWAYS
&&
975 state
->back
.compareOp
== VK_COMPARE_OP_ALWAYS
&&
976 !*stencilWriteEnable
)
977 state
->stencilTestEnable
= false;
981 emit_ds_state(struct anv_pipeline
*pipeline
,
982 const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
,
983 const struct anv_render_pass
*pass
,
984 const struct anv_subpass
*subpass
)
987 # define depth_stencil_dw pipeline->gen7.depth_stencil_state
989 # define depth_stencil_dw pipeline->gen8.wm_depth_stencil
991 # define depth_stencil_dw pipeline->gen9.wm_depth_stencil
994 if (pCreateInfo
== NULL
) {
995 /* We're going to OR this together with the dynamic state. We need
996 * to make sure it's initialized to something useful.
998 pipeline
->writes_stencil
= false;
999 pipeline
->stencil_test_enable
= false;
1000 pipeline
->writes_depth
= false;
1001 pipeline
->depth_test_enable
= false;
1002 pipeline
->depth_bounds_test_enable
= false;
1003 memset(depth_stencil_dw
, 0, sizeof(depth_stencil_dw
));
1007 VkImageAspectFlags ds_aspects
= 0;
1008 if (subpass
->depth_stencil_attachment
) {
1009 VkFormat depth_stencil_format
=
1010 pass
->attachments
[subpass
->depth_stencil_attachment
->attachment
].format
;
1011 ds_aspects
= vk_format_aspects(depth_stencil_format
);
1014 VkPipelineDepthStencilStateCreateInfo info
= *pCreateInfo
;
1015 sanitize_ds_state(&info
, &pipeline
->writes_stencil
, ds_aspects
);
1016 pipeline
->stencil_test_enable
= info
.stencilTestEnable
;
1017 pipeline
->writes_depth
= info
.depthWriteEnable
;
1018 pipeline
->depth_test_enable
= info
.depthTestEnable
;
1019 pipeline
->depth_bounds_test_enable
= info
.depthBoundsTestEnable
;
1022 struct GENX(DEPTH_STENCIL_STATE
) depth_stencil
= {
1024 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) depth_stencil
= {
1026 .DepthTestEnable
= info
.depthTestEnable
,
1027 .DepthBufferWriteEnable
= info
.depthWriteEnable
,
1028 .DepthTestFunction
= vk_to_gen_compare_op
[info
.depthCompareOp
],
1029 .DoubleSidedStencilEnable
= true,
1031 .StencilTestEnable
= info
.stencilTestEnable
,
1032 .StencilFailOp
= vk_to_gen_stencil_op
[info
.front
.failOp
],
1033 .StencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
.front
.passOp
],
1034 .StencilPassDepthFailOp
= vk_to_gen_stencil_op
[info
.front
.depthFailOp
],
1035 .StencilTestFunction
= vk_to_gen_compare_op
[info
.front
.compareOp
],
1036 .BackfaceStencilFailOp
= vk_to_gen_stencil_op
[info
.back
.failOp
],
1037 .BackfaceStencilPassDepthPassOp
= vk_to_gen_stencil_op
[info
.back
.passOp
],
1038 .BackfaceStencilPassDepthFailOp
=vk_to_gen_stencil_op
[info
.back
.depthFailOp
],
1039 .BackfaceStencilTestFunction
= vk_to_gen_compare_op
[info
.back
.compareOp
],
1043 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
1045 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, depth_stencil_dw
, &depth_stencil
);
1050 is_dual_src_blend_factor(VkBlendFactor factor
)
1052 return factor
== VK_BLEND_FACTOR_SRC1_COLOR
||
1053 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
||
1054 factor
== VK_BLEND_FACTOR_SRC1_ALPHA
||
1055 factor
== VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
;
1059 emit_cb_state(struct anv_pipeline
*pipeline
,
1060 const VkPipelineColorBlendStateCreateInfo
*info
,
1061 const VkPipelineMultisampleStateCreateInfo
*ms_info
)
1063 struct anv_device
*device
= pipeline
->device
;
1064 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1066 struct GENX(BLEND_STATE
) blend_state
= {
1068 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
1069 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
1073 uint32_t surface_count
= 0;
1074 struct anv_pipeline_bind_map
*map
;
1075 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1076 map
= &pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->bind_map
;
1077 surface_count
= map
->surface_count
;
1080 const uint32_t num_dwords
= GENX(BLEND_STATE_length
) +
1081 GENX(BLEND_STATE_ENTRY_length
) * surface_count
;
1082 pipeline
->blend_state
=
1083 anv_state_pool_alloc(&device
->dynamic_state_pool
, num_dwords
* 4, 64);
1085 bool has_writeable_rt
= false;
1086 uint32_t *state_pos
= pipeline
->blend_state
.map
;
1087 state_pos
+= GENX(BLEND_STATE_length
);
1089 struct GENX(BLEND_STATE_ENTRY
) bs0
= { 0 };
1091 for (unsigned i
= 0; i
< surface_count
; i
++) {
1092 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[i
];
1094 /* All color attachments are at the beginning of the binding table */
1095 if (binding
->set
!= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
1098 /* We can have at most 8 attachments */
1101 if (info
== NULL
|| binding
->index
>= info
->attachmentCount
) {
1102 /* Default everything to disabled */
1103 struct GENX(BLEND_STATE_ENTRY
) entry
= {
1104 .WriteDisableAlpha
= true,
1105 .WriteDisableRed
= true,
1106 .WriteDisableGreen
= true,
1107 .WriteDisableBlue
= true,
1109 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, state_pos
, &entry
);
1110 state_pos
+= GENX(BLEND_STATE_ENTRY_length
);
1114 const VkPipelineColorBlendAttachmentState
*a
=
1115 &info
->pAttachments
[binding
->index
];
1117 struct GENX(BLEND_STATE_ENTRY
) entry
= {
1119 .AlphaToCoverageEnable
= ms_info
&& ms_info
->alphaToCoverageEnable
,
1120 .AlphaToOneEnable
= ms_info
&& ms_info
->alphaToOneEnable
,
1122 .LogicOpEnable
= info
->logicOpEnable
,
1123 .LogicOpFunction
= vk_to_gen_logic_op
[info
->logicOp
],
1124 .ColorBufferBlendEnable
= a
->blendEnable
,
1125 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
1126 .PreBlendColorClampEnable
= true,
1127 .PostBlendColorClampEnable
= true,
1128 .SourceBlendFactor
= vk_to_gen_blend
[a
->srcColorBlendFactor
],
1129 .DestinationBlendFactor
= vk_to_gen_blend
[a
->dstColorBlendFactor
],
1130 .ColorBlendFunction
= vk_to_gen_blend_op
[a
->colorBlendOp
],
1131 .SourceAlphaBlendFactor
= vk_to_gen_blend
[a
->srcAlphaBlendFactor
],
1132 .DestinationAlphaBlendFactor
= vk_to_gen_blend
[a
->dstAlphaBlendFactor
],
1133 .AlphaBlendFunction
= vk_to_gen_blend_op
[a
->alphaBlendOp
],
1134 .WriteDisableAlpha
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_A_BIT
),
1135 .WriteDisableRed
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_R_BIT
),
1136 .WriteDisableGreen
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_G_BIT
),
1137 .WriteDisableBlue
= !(a
->colorWriteMask
& VK_COLOR_COMPONENT_B_BIT
),
1140 if (a
->srcColorBlendFactor
!= a
->srcAlphaBlendFactor
||
1141 a
->dstColorBlendFactor
!= a
->dstAlphaBlendFactor
||
1142 a
->colorBlendOp
!= a
->alphaBlendOp
) {
1144 blend_state
.IndependentAlphaBlendEnable
= true;
1146 entry
.IndependentAlphaBlendEnable
= true;
1150 /* The Dual Source Blending documentation says:
1152 * "If SRC1 is included in a src/dst blend factor and
1153 * a DualSource RT Write message is not used, results
1154 * are UNDEFINED. (This reflects the same restriction in DX APIs,
1155 * where undefined results are produced if “o1” is not written
1156 * by a PS – there are no default values defined)."
1158 * There is no way to gracefully fix this undefined situation
1159 * so we just disable the blending to prevent possible issues.
1161 if (!wm_prog_data
->dual_src_blend
&&
1162 (is_dual_src_blend_factor(a
->srcColorBlendFactor
) ||
1163 is_dual_src_blend_factor(a
->dstColorBlendFactor
) ||
1164 is_dual_src_blend_factor(a
->srcAlphaBlendFactor
) ||
1165 is_dual_src_blend_factor(a
->dstAlphaBlendFactor
))) {
1166 vk_debug_report(&device
->physical
->instance
->debug_report_callbacks
,
1167 VK_DEBUG_REPORT_WARNING_BIT_EXT
,
1168 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT
,
1169 (uint64_t)(uintptr_t)device
,
1171 "Enabled dual-src blend factors without writing both targets "
1172 "in the shader. Disabling blending to avoid GPU hangs.");
1173 entry
.ColorBufferBlendEnable
= false;
1176 if (a
->colorWriteMask
!= 0)
1177 has_writeable_rt
= true;
1179 /* Our hardware applies the blend factor prior to the blend function
1180 * regardless of what function is used. Technically, this means the
1181 * hardware can do MORE than GL or Vulkan specify. However, it also
1182 * means that, for MIN and MAX, we have to stomp the blend factor to
1183 * ONE to make it a no-op.
1185 if (a
->colorBlendOp
== VK_BLEND_OP_MIN
||
1186 a
->colorBlendOp
== VK_BLEND_OP_MAX
) {
1187 entry
.SourceBlendFactor
= BLENDFACTOR_ONE
;
1188 entry
.DestinationBlendFactor
= BLENDFACTOR_ONE
;
1190 if (a
->alphaBlendOp
== VK_BLEND_OP_MIN
||
1191 a
->alphaBlendOp
== VK_BLEND_OP_MAX
) {
1192 entry
.SourceAlphaBlendFactor
= BLENDFACTOR_ONE
;
1193 entry
.DestinationAlphaBlendFactor
= BLENDFACTOR_ONE
;
1195 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, state_pos
, &entry
);
1196 state_pos
+= GENX(BLEND_STATE_ENTRY_length
);
1204 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_BLEND
), blend
) {
1205 blend
.AlphaToCoverageEnable
= blend_state
.AlphaToCoverageEnable
;
1206 blend
.HasWriteableRT
= has_writeable_rt
;
1207 blend
.ColorBufferBlendEnable
= bs0
.ColorBufferBlendEnable
;
1208 blend
.SourceAlphaBlendFactor
= bs0
.SourceAlphaBlendFactor
;
1209 blend
.DestinationAlphaBlendFactor
= bs0
.DestinationAlphaBlendFactor
;
1210 blend
.SourceBlendFactor
= bs0
.SourceBlendFactor
;
1211 blend
.DestinationBlendFactor
= bs0
.DestinationBlendFactor
;
1212 blend
.AlphaTestEnable
= false;
1213 blend
.IndependentAlphaBlendEnable
=
1214 blend_state
.IndependentAlphaBlendEnable
;
1217 (void)has_writeable_rt
;
1220 GENX(BLEND_STATE_pack
)(NULL
, pipeline
->blend_state
.map
, &blend_state
);
1222 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), bsp
) {
1223 bsp
.BlendStatePointer
= pipeline
->blend_state
.offset
;
1225 bsp
.BlendStatePointerValid
= true;
1231 emit_3dstate_clip(struct anv_pipeline
*pipeline
,
1232 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
,
1233 const VkPipelineViewportStateCreateInfo
*vp_info
,
1234 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
1236 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1237 (void) wm_prog_data
;
1238 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_CLIP
), clip
) {
1239 clip
.ClipEnable
= true;
1240 clip
.StatisticsEnable
= true;
1241 clip
.EarlyCullEnable
= true;
1242 clip
.APIMode
= APIMODE_D3D
;
1243 clip
.GuardbandClipTestEnable
= true;
1245 /* Only enable the XY clip test when the final polygon rasterization
1246 * mode is VK_POLYGON_MODE_FILL. We want to leave it disabled for
1247 * points and lines so we get "pop-free" clipping.
1249 VkPolygonMode raster_mode
=
1250 anv_raster_polygon_mode(pipeline
, ia_info
, rs_info
);
1251 clip
.ViewportXYClipTestEnable
= (raster_mode
== VK_POLYGON_MODE_FILL
);
1254 clip
.VertexSubPixelPrecisionSelect
= _8Bit
;
1257 clip
.ClipMode
= CLIPMODE_NORMAL
;
1259 clip
.TriangleStripListProvokingVertexSelect
= 0;
1260 clip
.LineStripListProvokingVertexSelect
= 0;
1261 clip
.TriangleFanProvokingVertexSelect
= 1;
1263 clip
.MinimumPointWidth
= 0.125;
1264 clip
.MaximumPointWidth
= 255.875;
1266 const struct brw_vue_prog_data
*last
=
1267 anv_pipeline_get_last_vue_prog_data(pipeline
);
1269 /* From the Vulkan 1.0.45 spec:
1271 * "If the last active vertex processing stage shader entry point's
1272 * interface does not include a variable decorated with
1273 * ViewportIndex, then the first viewport is used."
1275 if (vp_info
&& (last
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
)) {
1276 clip
.MaximumVPIndex
= vp_info
->viewportCount
- 1;
1278 clip
.MaximumVPIndex
= 0;
1281 /* From the Vulkan 1.0.45 spec:
1283 * "If the last active vertex processing stage shader entry point's
1284 * interface does not include a variable decorated with Layer, then
1285 * the first layer is used."
1287 clip
.ForceZeroRTAIndexEnable
=
1288 !(last
->vue_map
.slots_valid
& VARYING_BIT_LAYER
);
1291 clip
.FrontWinding
= vk_to_gen_front_face
[rs_info
->frontFace
];
1292 clip
.CullMode
= vk_to_gen_cullmode
[rs_info
->cullMode
];
1293 clip
.ViewportZClipTestEnable
= pipeline
->depth_clip_enable
;
1294 clip
.UserClipDistanceClipTestEnableBitmask
= last
->clip_distance_mask
;
1295 clip
.UserClipDistanceCullTestEnableBitmask
= last
->cull_distance_mask
;
1297 clip
.NonPerspectiveBarycentricEnable
= wm_prog_data
?
1298 (wm_prog_data
->barycentric_interp_modes
&
1299 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS
) != 0 : 0;
1305 emit_3dstate_streamout(struct anv_pipeline
*pipeline
,
1306 const VkPipelineRasterizationStateCreateInfo
*rs_info
)
1309 const struct brw_vue_prog_data
*prog_data
=
1310 anv_pipeline_get_last_vue_prog_data(pipeline
);
1311 const struct brw_vue_map
*vue_map
= &prog_data
->vue_map
;
1314 nir_xfb_info
*xfb_info
;
1315 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
1316 xfb_info
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->xfb_info
;
1317 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1318 xfb_info
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->xfb_info
;
1320 xfb_info
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->xfb_info
;
1322 pipeline
->xfb_used
= xfb_info
? xfb_info
->buffers_written
: 0;
1324 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_STREAMOUT
), so
) {
1325 so
.RenderingDisable
= rs_info
->rasterizerDiscardEnable
;
1329 so
.SOFunctionEnable
= true;
1330 so
.SOStatisticsEnable
= true;
1332 const VkPipelineRasterizationStateStreamCreateInfoEXT
*stream_info
=
1333 vk_find_struct_const(rs_info
, PIPELINE_RASTERIZATION_STATE_STREAM_CREATE_INFO_EXT
);
1334 so
.RenderStreamSelect
= stream_info
?
1335 stream_info
->rasterizationStream
: 0;
1337 so
.Buffer0SurfacePitch
= xfb_info
->buffers
[0].stride
;
1338 so
.Buffer1SurfacePitch
= xfb_info
->buffers
[1].stride
;
1339 so
.Buffer2SurfacePitch
= xfb_info
->buffers
[2].stride
;
1340 so
.Buffer3SurfacePitch
= xfb_info
->buffers
[3].stride
;
1342 int urb_entry_read_offset
= 0;
1343 int urb_entry_read_length
=
1344 (prog_data
->vue_map
.num_slots
+ 1) / 2 - urb_entry_read_offset
;
1346 /* We always read the whole vertex. This could be reduced at some
1347 * point by reading less and offsetting the register index in the
1350 so
.Stream0VertexReadOffset
= urb_entry_read_offset
;
1351 so
.Stream0VertexReadLength
= urb_entry_read_length
- 1;
1352 so
.Stream1VertexReadOffset
= urb_entry_read_offset
;
1353 so
.Stream1VertexReadLength
= urb_entry_read_length
- 1;
1354 so
.Stream2VertexReadOffset
= urb_entry_read_offset
;
1355 so
.Stream2VertexReadLength
= urb_entry_read_length
- 1;
1356 so
.Stream3VertexReadOffset
= urb_entry_read_offset
;
1357 so
.Stream3VertexReadLength
= urb_entry_read_length
- 1;
1359 #endif /* GEN_GEN >= 8 */
1364 struct GENX(SO_DECL
) so_decl
[MAX_XFB_STREAMS
][128];
1365 int next_offset
[MAX_XFB_BUFFERS
] = {0, 0, 0, 0};
1366 int decls
[MAX_XFB_STREAMS
] = {0, 0, 0, 0};
1368 memset(so_decl
, 0, sizeof(so_decl
));
1370 for (unsigned i
= 0; i
< xfb_info
->output_count
; i
++) {
1371 const nir_xfb_output_info
*output
= &xfb_info
->outputs
[i
];
1372 unsigned buffer
= output
->buffer
;
1373 unsigned stream
= xfb_info
->buffer_to_stream
[buffer
];
1375 /* Our hardware is unusual in that it requires us to program SO_DECLs
1376 * for fake "hole" components, rather than simply taking the offset
1377 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
1378 * program as many size = 4 holes as we can, then a final hole to
1379 * accommodate the final 1, 2, or 3 remaining.
1381 int hole_dwords
= (output
->offset
- next_offset
[buffer
]) / 4;
1382 while (hole_dwords
> 0) {
1383 so_decl
[stream
][decls
[stream
]++] = (struct GENX(SO_DECL
)) {
1385 .OutputBufferSlot
= buffer
,
1386 .ComponentMask
= (1 << MIN2(hole_dwords
, 4)) - 1,
1391 int varying
= output
->location
;
1392 uint8_t component_mask
= output
->component_mask
;
1393 /* VARYING_SLOT_PSIZ contains three scalar fields packed together:
1394 * - VARYING_SLOT_LAYER in VARYING_SLOT_PSIZ.y
1395 * - VARYING_SLOT_VIEWPORT in VARYING_SLOT_PSIZ.z
1396 * - VARYING_SLOT_PSIZ in VARYING_SLOT_PSIZ.w
1398 if (varying
== VARYING_SLOT_LAYER
) {
1399 varying
= VARYING_SLOT_PSIZ
;
1400 component_mask
= 1 << 1; // SO_DECL_COMPMASK_Y
1401 } else if (varying
== VARYING_SLOT_VIEWPORT
) {
1402 varying
= VARYING_SLOT_PSIZ
;
1403 component_mask
= 1 << 2; // SO_DECL_COMPMASK_Z
1404 } else if (varying
== VARYING_SLOT_PSIZ
) {
1405 component_mask
= 1 << 3; // SO_DECL_COMPMASK_W
1408 next_offset
[buffer
] = output
->offset
+
1409 __builtin_popcount(component_mask
) * 4;
1411 so_decl
[stream
][decls
[stream
]++] = (struct GENX(SO_DECL
)) {
1412 .OutputBufferSlot
= buffer
,
1413 .RegisterIndex
= vue_map
->varying_to_slot
[varying
],
1414 .ComponentMask
= component_mask
,
1419 for (unsigned s
= 0; s
< MAX_XFB_STREAMS
; s
++)
1420 max_decls
= MAX2(max_decls
, decls
[s
]);
1422 uint8_t sbs
[MAX_XFB_STREAMS
] = { };
1423 for (unsigned b
= 0; b
< MAX_XFB_BUFFERS
; b
++) {
1424 if (xfb_info
->buffers_written
& (1 << b
))
1425 sbs
[xfb_info
->buffer_to_stream
[b
]] |= 1 << b
;
1428 uint32_t *dw
= anv_batch_emitn(&pipeline
->batch
, 3 + 2 * max_decls
,
1429 GENX(3DSTATE_SO_DECL_LIST
),
1430 .StreamtoBufferSelects0
= sbs
[0],
1431 .StreamtoBufferSelects1
= sbs
[1],
1432 .StreamtoBufferSelects2
= sbs
[2],
1433 .StreamtoBufferSelects3
= sbs
[3],
1434 .NumEntries0
= decls
[0],
1435 .NumEntries1
= decls
[1],
1436 .NumEntries2
= decls
[2],
1437 .NumEntries3
= decls
[3]);
1439 for (int i
= 0; i
< max_decls
; i
++) {
1440 GENX(SO_DECL_ENTRY_pack
)(NULL
, dw
+ 3 + i
* 2,
1441 &(struct GENX(SO_DECL_ENTRY
)) {
1442 .Stream0Decl
= so_decl
[0][i
],
1443 .Stream1Decl
= so_decl
[1][i
],
1444 .Stream2Decl
= so_decl
[2][i
],
1445 .Stream3Decl
= so_decl
[3][i
],
1449 #endif /* GEN_GEN >= 8 */
1453 get_sampler_count(const struct anv_shader_bin
*bin
)
1455 uint32_t count_by_4
= DIV_ROUND_UP(bin
->bind_map
.sampler_count
, 4);
1457 /* We can potentially have way more than 32 samplers and that's ok.
1458 * However, the 3DSTATE_XS packets only have 3 bits to specify how
1459 * many to pre-fetch and all values above 4 are marked reserved.
1461 return MIN2(count_by_4
, 4);
1465 get_binding_table_entry_count(const struct anv_shader_bin
*bin
)
1467 return DIV_ROUND_UP(bin
->bind_map
.surface_count
, 32);
1470 static struct anv_address
1471 get_scratch_address(struct anv_pipeline
*pipeline
,
1472 gl_shader_stage stage
,
1473 const struct anv_shader_bin
*bin
)
1475 return (struct anv_address
) {
1476 .bo
= anv_scratch_pool_alloc(pipeline
->device
,
1477 &pipeline
->device
->scratch_pool
,
1478 stage
, bin
->prog_data
->total_scratch
),
1484 get_scratch_space(const struct anv_shader_bin
*bin
)
1486 return ffs(bin
->prog_data
->total_scratch
/ 2048);
1490 emit_3dstate_vs(struct anv_pipeline
*pipeline
)
1492 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1493 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1494 const struct anv_shader_bin
*vs_bin
=
1495 pipeline
->shaders
[MESA_SHADER_VERTEX
];
1497 assert(anv_pipeline_has_stage(pipeline
, MESA_SHADER_VERTEX
));
1499 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VS
), vs
) {
1501 vs
.StatisticsEnable
= true;
1502 vs
.KernelStartPointer
= vs_bin
->kernel
.offset
;
1504 vs
.SIMD8DispatchEnable
=
1505 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
1508 assert(!vs_prog_data
->base
.base
.use_alt_mode
);
1510 vs
.SingleVertexDispatch
= false;
1512 vs
.VectorMaskEnable
= false;
1514 * Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
1515 * Disable the Sampler state prefetch functionality in the SARB by
1516 * programming 0xB000[30] to '1'.
1518 vs
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(vs_bin
);
1519 vs
.BindingTableEntryCount
= get_binding_table_entry_count(vs_bin
);
1520 vs
.FloatingPointMode
= IEEE754
;
1521 vs
.IllegalOpcodeExceptionEnable
= false;
1522 vs
.SoftwareExceptionEnable
= false;
1523 vs
.MaximumNumberofThreads
= devinfo
->max_vs_threads
- 1;
1525 if (GEN_GEN
== 9 && devinfo
->gt
== 4 &&
1526 anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
1527 /* On Sky Lake GT4, we have experienced some hangs related to the VS
1528 * cache and tessellation. It is unknown exactly what is happening
1529 * but the Haswell docs for the "VS Reference Count Full Force Miss
1530 * Enable" field of the "Thread Mode" register refer to a HSW bug in
1531 * which the VUE handle reference count would overflow resulting in
1532 * internal reference counting bugs. My (Jason's) best guess is that
1533 * this bug cropped back up on SKL GT4 when we suddenly had more
1534 * threads in play than any previous gen9 hardware.
1536 * What we do know for sure is that setting this bit when
1537 * tessellation shaders are in use fixes a GPU hang in Batman: Arkham
1538 * City when playing with DXVK (https://bugs.freedesktop.org/107280).
1539 * Disabling the vertex cache with tessellation shaders should only
1540 * have a minor performance impact as the tessellation shaders are
1541 * likely generating and processing far more geometry than the vertex
1544 vs
.VertexCacheDisable
= true;
1547 vs
.VertexURBEntryReadLength
= vs_prog_data
->base
.urb_read_length
;
1548 vs
.VertexURBEntryReadOffset
= 0;
1549 vs
.DispatchGRFStartRegisterForURBData
=
1550 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1553 vs
.UserClipDistanceClipTestEnableBitmask
=
1554 vs_prog_data
->base
.clip_distance_mask
;
1555 vs
.UserClipDistanceCullTestEnableBitmask
=
1556 vs_prog_data
->base
.cull_distance_mask
;
1559 vs
.PerThreadScratchSpace
= get_scratch_space(vs_bin
);
1560 vs
.ScratchSpaceBasePointer
=
1561 get_scratch_address(pipeline
, MESA_SHADER_VERTEX
, vs_bin
);
1566 emit_3dstate_hs_te_ds(struct anv_pipeline
*pipeline
,
1567 const VkPipelineTessellationStateCreateInfo
*tess_info
)
1569 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
)) {
1570 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_HS
), hs
);
1571 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_TE
), te
);
1572 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_DS
), ds
);
1576 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1577 const struct anv_shader_bin
*tcs_bin
=
1578 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1579 const struct anv_shader_bin
*tes_bin
=
1580 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1582 const struct brw_tcs_prog_data
*tcs_prog_data
= get_tcs_prog_data(pipeline
);
1583 const struct brw_tes_prog_data
*tes_prog_data
= get_tes_prog_data(pipeline
);
1585 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_HS
), hs
) {
1587 hs
.StatisticsEnable
= true;
1588 hs
.KernelStartPointer
= tcs_bin
->kernel
.offset
;
1590 hs
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(tcs_bin
);
1591 hs
.BindingTableEntryCount
= get_binding_table_entry_count(tcs_bin
);
1592 hs
.MaximumNumberofThreads
= devinfo
->max_tcs_threads
- 1;
1593 hs
.IncludeVertexHandles
= true;
1594 hs
.InstanceCount
= tcs_prog_data
->instances
- 1;
1596 hs
.VertexURBEntryReadLength
= 0;
1597 hs
.VertexURBEntryReadOffset
= 0;
1598 hs
.DispatchGRFStartRegisterForURBData
=
1599 tcs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1601 hs
.PerThreadScratchSpace
= get_scratch_space(tcs_bin
);
1602 hs
.ScratchSpaceBasePointer
=
1603 get_scratch_address(pipeline
, MESA_SHADER_TESS_CTRL
, tcs_bin
);
1606 hs
.DispatchMode
= tcs_prog_data
->base
.dispatch_mode
;
1607 hs
.IncludePrimitiveID
= tcs_prog_data
->include_primitive_id
;
1611 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
1612 tess_info
? vk_find_struct_const(tess_info
, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
) : NULL
;
1614 VkTessellationDomainOrigin uv_origin
=
1615 domain_origin_state
? domain_origin_state
->domainOrigin
:
1616 VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
;
1618 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_TE
), te
) {
1619 te
.Partitioning
= tes_prog_data
->partitioning
;
1621 if (uv_origin
== VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT
) {
1622 te
.OutputTopology
= tes_prog_data
->output_topology
;
1624 /* When the origin is upper-left, we have to flip the winding order */
1625 if (tes_prog_data
->output_topology
== OUTPUT_TRI_CCW
) {
1626 te
.OutputTopology
= OUTPUT_TRI_CW
;
1627 } else if (tes_prog_data
->output_topology
== OUTPUT_TRI_CW
) {
1628 te
.OutputTopology
= OUTPUT_TRI_CCW
;
1630 te
.OutputTopology
= tes_prog_data
->output_topology
;
1634 te
.TEDomain
= tes_prog_data
->domain
;
1636 te
.MaximumTessellationFactorOdd
= 63.0;
1637 te
.MaximumTessellationFactorNotOdd
= 64.0;
1640 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_DS
), ds
) {
1642 ds
.StatisticsEnable
= true;
1643 ds
.KernelStartPointer
= tes_bin
->kernel
.offset
;
1645 ds
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(tes_bin
);
1646 ds
.BindingTableEntryCount
= get_binding_table_entry_count(tes_bin
);
1647 ds
.MaximumNumberofThreads
= devinfo
->max_tes_threads
- 1;
1649 ds
.ComputeWCoordinateEnable
=
1650 tes_prog_data
->domain
== BRW_TESS_DOMAIN_TRI
;
1652 ds
.PatchURBEntryReadLength
= tes_prog_data
->base
.urb_read_length
;
1653 ds
.PatchURBEntryReadOffset
= 0;
1654 ds
.DispatchGRFStartRegisterForURBData
=
1655 tes_prog_data
->base
.base
.dispatch_grf_start_reg
;
1660 tes_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
?
1661 DISPATCH_MODE_SIMD8_SINGLE_PATCH
:
1662 DISPATCH_MODE_SIMD4X2
;
1664 assert(tes_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
);
1665 ds
.DispatchMode
= DISPATCH_MODE_SIMD8_SINGLE_PATCH
;
1668 ds
.UserClipDistanceClipTestEnableBitmask
=
1669 tes_prog_data
->base
.clip_distance_mask
;
1670 ds
.UserClipDistanceCullTestEnableBitmask
=
1671 tes_prog_data
->base
.cull_distance_mask
;
1674 ds
.PerThreadScratchSpace
= get_scratch_space(tes_bin
);
1675 ds
.ScratchSpaceBasePointer
=
1676 get_scratch_address(pipeline
, MESA_SHADER_TESS_EVAL
, tes_bin
);
1681 emit_3dstate_gs(struct anv_pipeline
*pipeline
)
1683 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1684 const struct anv_shader_bin
*gs_bin
=
1685 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1687 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
)) {
1688 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), gs
);
1692 const struct brw_gs_prog_data
*gs_prog_data
= get_gs_prog_data(pipeline
);
1694 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_GS
), gs
) {
1696 gs
.StatisticsEnable
= true;
1697 gs
.KernelStartPointer
= gs_bin
->kernel
.offset
;
1698 gs
.DispatchMode
= gs_prog_data
->base
.dispatch_mode
;
1700 gs
.SingleProgramFlow
= false;
1701 gs
.VectorMaskEnable
= false;
1703 gs
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(gs_bin
);
1704 gs
.BindingTableEntryCount
= get_binding_table_entry_count(gs_bin
);
1705 gs
.IncludeVertexHandles
= gs_prog_data
->base
.include_vue_handles
;
1706 gs
.IncludePrimitiveID
= gs_prog_data
->include_primitive_id
;
1709 /* Broadwell is weird. It needs us to divide by 2. */
1710 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
/ 2 - 1;
1712 gs
.MaximumNumberofThreads
= devinfo
->max_gs_threads
- 1;
1715 gs
.OutputVertexSize
= gs_prog_data
->output_vertex_size_hwords
* 2 - 1;
1716 gs
.OutputTopology
= gs_prog_data
->output_topology
;
1717 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1718 gs
.ControlDataFormat
= gs_prog_data
->control_data_format
;
1719 gs
.ControlDataHeaderSize
= gs_prog_data
->control_data_header_size_hwords
;
1720 gs
.InstanceControl
= MAX2(gs_prog_data
->invocations
, 1) - 1;
1721 gs
.ReorderMode
= TRAILING
;
1724 gs
.ExpectedVertexCount
= gs_prog_data
->vertices_in
;
1725 gs
.StaticOutput
= gs_prog_data
->static_vertex_count
>= 0;
1726 gs
.StaticOutputVertexCount
= gs_prog_data
->static_vertex_count
>= 0 ?
1727 gs_prog_data
->static_vertex_count
: 0;
1730 gs
.VertexURBEntryReadOffset
= 0;
1731 gs
.VertexURBEntryReadLength
= gs_prog_data
->base
.urb_read_length
;
1732 gs
.DispatchGRFStartRegisterForURBData
=
1733 gs_prog_data
->base
.base
.dispatch_grf_start_reg
;
1736 gs
.UserClipDistanceClipTestEnableBitmask
=
1737 gs_prog_data
->base
.clip_distance_mask
;
1738 gs
.UserClipDistanceCullTestEnableBitmask
=
1739 gs_prog_data
->base
.cull_distance_mask
;
1742 gs
.PerThreadScratchSpace
= get_scratch_space(gs_bin
);
1743 gs
.ScratchSpaceBasePointer
=
1744 get_scratch_address(pipeline
, MESA_SHADER_GEOMETRY
, gs_bin
);
1749 has_color_buffer_write_enabled(const struct anv_pipeline
*pipeline
,
1750 const VkPipelineColorBlendStateCreateInfo
*blend
)
1752 const struct anv_shader_bin
*shader_bin
=
1753 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1757 const struct anv_pipeline_bind_map
*bind_map
= &shader_bin
->bind_map
;
1758 for (int i
= 0; i
< bind_map
->surface_count
; i
++) {
1759 struct anv_pipeline_binding
*binding
= &bind_map
->surface_to_descriptor
[i
];
1761 if (binding
->set
!= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
)
1764 if (binding
->index
== UINT32_MAX
)
1767 if (blend
&& blend
->pAttachments
[binding
->index
].colorWriteMask
!= 0)
1775 emit_3dstate_wm(struct anv_pipeline
*pipeline
, struct anv_subpass
*subpass
,
1776 const VkPipelineInputAssemblyStateCreateInfo
*ia
,
1777 const VkPipelineRasterizationStateCreateInfo
*raster
,
1778 const VkPipelineColorBlendStateCreateInfo
*blend
,
1779 const VkPipelineMultisampleStateCreateInfo
*multisample
,
1780 const VkPipelineRasterizationLineStateCreateInfoEXT
*line
)
1782 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1784 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_WM
), wm
) {
1785 wm
.StatisticsEnable
= true;
1786 wm
.LineEndCapAntialiasingRegionWidth
= _05pixels
;
1787 wm
.LineAntialiasingRegionWidth
= _10pixels
;
1788 wm
.PointRasterizationRule
= RASTRULE_UPPER_RIGHT
;
1790 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1791 if (wm_prog_data
->early_fragment_tests
) {
1792 wm
.EarlyDepthStencilControl
= EDSC_PREPS
;
1793 } else if (wm_prog_data
->has_side_effects
) {
1794 wm
.EarlyDepthStencilControl
= EDSC_PSEXEC
;
1796 wm
.EarlyDepthStencilControl
= EDSC_NORMAL
;
1800 /* Gen8 hardware tries to compute ThreadDispatchEnable for us but
1801 * doesn't take into account KillPixels when no depth or stencil
1802 * writes are enabled. In order for occlusion queries to work
1803 * correctly with no attachments, we need to force-enable PS thread
1806 * The BDW docs are pretty clear that that this bit isn't validated
1807 * and probably shouldn't be used in production:
1809 * "This must always be set to Normal. This field should not be
1810 * tested for functional validation."
1812 * Unfortunately, however, the other mechanism we have for doing this
1813 * is 3DSTATE_PS_EXTRA::PixelShaderHasUAV which causes hangs on BDW.
1814 * Given two bad options, we choose the one which works.
1816 if ((wm_prog_data
->has_side_effects
|| wm_prog_data
->uses_kill
) &&
1817 !has_color_buffer_write_enabled(pipeline
, blend
))
1818 wm
.ForceThreadDispatchEnable
= ForceON
;
1821 wm
.BarycentricInterpolationMode
=
1822 wm_prog_data
->barycentric_interp_modes
;
1825 wm
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1826 wm
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1827 wm
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1828 wm
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
1830 /* If the subpass has a depth or stencil self-dependency, then we
1831 * need to force the hardware to do the depth/stencil write *after*
1832 * fragment shader execution. Otherwise, the writes may hit memory
1833 * before we get around to fetching from the input attachment and we
1834 * may get the depth or stencil value from the current draw rather
1835 * than the previous one.
1837 wm
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
1838 wm_prog_data
->uses_kill
;
1840 if (wm
.PixelShaderComputedDepthMode
!= PSCDEPTH_OFF
||
1841 wm_prog_data
->has_side_effects
||
1842 wm
.PixelShaderKillsPixel
||
1843 has_color_buffer_write_enabled(pipeline
, blend
))
1844 wm
.ThreadDispatchEnable
= true;
1846 if (multisample
&& multisample
->rasterizationSamples
> 1) {
1847 if (wm_prog_data
->persample_dispatch
) {
1848 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1850 wm
.MultisampleDispatchMode
= MSDISPMODE_PERPIXEL
;
1853 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1855 wm
.MultisampleRasterizationMode
=
1856 gen7_ms_rast_mode(pipeline
, ia
, raster
, multisample
);
1859 wm
.LineStippleEnable
= line
&& line
->stippledLineEnable
;
1865 emit_3dstate_ps(struct anv_pipeline
*pipeline
,
1866 const VkPipelineColorBlendStateCreateInfo
*blend
,
1867 const VkPipelineMultisampleStateCreateInfo
*multisample
)
1869 UNUSED
const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1870 const struct anv_shader_bin
*fs_bin
=
1871 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1873 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1874 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
), ps
) {
1876 /* Even if no fragments are ever dispatched, gen7 hardware hangs if
1877 * we don't at least set the maximum number of threads.
1879 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1885 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1888 /* The hardware wedges if you have this bit set but don't turn on any dual
1889 * source blend factors.
1891 bool dual_src_blend
= false;
1892 if (wm_prog_data
->dual_src_blend
&& blend
) {
1893 for (uint32_t i
= 0; i
< blend
->attachmentCount
; i
++) {
1894 const VkPipelineColorBlendAttachmentState
*bstate
=
1895 &blend
->pAttachments
[i
];
1897 if (bstate
->blendEnable
&&
1898 (is_dual_src_blend_factor(bstate
->srcColorBlendFactor
) ||
1899 is_dual_src_blend_factor(bstate
->dstColorBlendFactor
) ||
1900 is_dual_src_blend_factor(bstate
->srcAlphaBlendFactor
) ||
1901 is_dual_src_blend_factor(bstate
->dstAlphaBlendFactor
))) {
1902 dual_src_blend
= true;
1909 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS
), ps
) {
1910 ps
._8PixelDispatchEnable
= wm_prog_data
->dispatch_8
;
1911 ps
._16PixelDispatchEnable
= wm_prog_data
->dispatch_16
;
1912 ps
._32PixelDispatchEnable
= wm_prog_data
->dispatch_32
;
1914 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
1916 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
1917 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
1919 * Since 16x MSAA is first introduced on SKL, we don't need to apply
1920 * the workaround on any older hardware.
1922 if (GEN_GEN
>= 9 && !wm_prog_data
->persample_dispatch
&&
1923 multisample
&& multisample
->rasterizationSamples
== 16) {
1924 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
1925 ps
._32PixelDispatchEnable
= false;
1928 ps
.KernelStartPointer0
= fs_bin
->kernel
.offset
+
1929 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 0);
1930 ps
.KernelStartPointer1
= fs_bin
->kernel
.offset
+
1931 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 1);
1932 ps
.KernelStartPointer2
= fs_bin
->kernel
.offset
+
1933 brw_wm_prog_data_prog_offset(wm_prog_data
, ps
, 2);
1935 ps
.SingleProgramFlow
= false;
1936 ps
.VectorMaskEnable
= GEN_GEN
>= 8;
1938 ps
.SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(fs_bin
);
1939 ps
.BindingTableEntryCount
= get_binding_table_entry_count(fs_bin
);
1940 ps
.PushConstantEnable
= wm_prog_data
->base
.nr_params
> 0 ||
1941 wm_prog_data
->base
.ubo_ranges
[0].length
;
1942 ps
.PositionXYOffsetSelect
= wm_prog_data
->uses_pos_offset
?
1943 POSOFFSET_SAMPLE
: POSOFFSET_NONE
;
1945 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
1946 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1947 ps
.DualSourceBlendEnable
= dual_src_blend
;
1951 /* Haswell requires the sample mask to be set in this packet as well
1952 * as in 3DSTATE_SAMPLE_MASK; the values should match.
1954 ps
.SampleMask
= 0xff;
1958 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
1960 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
1962 ps
.MaximumNumberofThreads
= devinfo
->max_wm_threads
- 1;
1965 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
1966 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 0);
1967 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
1968 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 1);
1969 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
1970 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data
, ps
, 2);
1972 ps
.PerThreadScratchSpace
= get_scratch_space(fs_bin
);
1973 ps
.ScratchSpaceBasePointer
=
1974 get_scratch_address(pipeline
, MESA_SHADER_FRAGMENT
, fs_bin
);
1980 emit_3dstate_ps_extra(struct anv_pipeline
*pipeline
,
1981 struct anv_subpass
*subpass
)
1983 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
1985 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
1986 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
), ps
);
1990 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_PS_EXTRA
), ps
) {
1991 ps
.PixelShaderValid
= true;
1992 ps
.AttributeEnable
= wm_prog_data
->num_varying_inputs
> 0;
1993 ps
.oMaskPresenttoRenderTarget
= wm_prog_data
->uses_omask
;
1994 ps
.PixelShaderIsPerSample
= wm_prog_data
->persample_dispatch
;
1995 ps
.PixelShaderComputedDepthMode
= wm_prog_data
->computed_depth_mode
;
1996 ps
.PixelShaderUsesSourceDepth
= wm_prog_data
->uses_src_depth
;
1997 ps
.PixelShaderUsesSourceW
= wm_prog_data
->uses_src_w
;
1999 /* If the subpass has a depth or stencil self-dependency, then we need
2000 * to force the hardware to do the depth/stencil write *after* fragment
2001 * shader execution. Otherwise, the writes may hit memory before we get
2002 * around to fetching from the input attachment and we may get the depth
2003 * or stencil value from the current draw rather than the previous one.
2005 ps
.PixelShaderKillsPixel
= subpass
->has_ds_self_dep
||
2006 wm_prog_data
->uses_kill
;
2009 ps
.PixelShaderComputesStencil
= wm_prog_data
->computed_stencil
;
2010 ps
.PixelShaderPullsBary
= wm_prog_data
->pulls_bary
;
2012 ps
.InputCoverageMaskState
= ICMS_NONE
;
2013 if (wm_prog_data
->uses_sample_mask
) {
2014 if (wm_prog_data
->post_depth_coverage
)
2015 ps
.InputCoverageMaskState
= ICMS_DEPTH_COVERAGE
;
2017 ps
.InputCoverageMaskState
= ICMS_INNER_CONSERVATIVE
;
2020 ps
.PixelShaderUsesInputCoverageMask
= wm_prog_data
->uses_sample_mask
;
2026 emit_3dstate_vf_topology(struct anv_pipeline
*pipeline
)
2028 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_TOPOLOGY
), vft
) {
2029 vft
.PrimitiveTopologyType
= pipeline
->topology
;
2035 emit_3dstate_vf_statistics(struct anv_pipeline
*pipeline
)
2037 anv_batch_emit(&pipeline
->batch
, GENX(3DSTATE_VF_STATISTICS
), vfs
) {
2038 vfs
.StatisticsEnable
= true;
2043 compute_kill_pixel(struct anv_pipeline
*pipeline
,
2044 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
2045 const struct anv_subpass
*subpass
)
2047 if (!anv_pipeline_has_stage(pipeline
, MESA_SHADER_FRAGMENT
)) {
2048 pipeline
->kill_pixel
= false;
2052 const struct brw_wm_prog_data
*wm_prog_data
= get_wm_prog_data(pipeline
);
2054 /* This computes the KillPixel portion of the computation for whether or
2055 * not we want to enable the PMA fix on gen8 or gen9. It's given by this
2056 * chunk of the giant formula:
2058 * (3DSTATE_PS_EXTRA::PixelShaderKillsPixels ||
2059 * 3DSTATE_PS_EXTRA::oMask Present to RenderTarget ||
2060 * 3DSTATE_PS_BLEND::AlphaToCoverageEnable ||
2061 * 3DSTATE_PS_BLEND::AlphaTestEnable ||
2062 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable)
2064 * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false and so is
2065 * 3DSTATE_PS_BLEND::AlphaTestEnable since Vulkan doesn't have a concept
2068 pipeline
->kill_pixel
=
2069 subpass
->has_ds_self_dep
|| wm_prog_data
->uses_kill
||
2070 wm_prog_data
->uses_omask
||
2071 (ms_info
&& ms_info
->alphaToCoverageEnable
);
2075 genX(graphics_pipeline_create
)(
2077 struct anv_pipeline_cache
* cache
,
2078 const VkGraphicsPipelineCreateInfo
* pCreateInfo
,
2079 const VkAllocationCallbacks
* pAllocator
,
2080 VkPipeline
* pPipeline
)
2082 ANV_FROM_HANDLE(anv_device
, device
, _device
);
2083 ANV_FROM_HANDLE(anv_render_pass
, pass
, pCreateInfo
->renderPass
);
2084 struct anv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
2085 struct anv_pipeline
*pipeline
;
2088 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
2090 /* Use the default pipeline cache if none is specified */
2091 if (cache
== NULL
&& device
->physical
->instance
->pipeline_cache_enabled
)
2092 cache
= &device
->default_pipeline_cache
;
2094 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
2095 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2096 if (pipeline
== NULL
)
2097 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2099 result
= anv_pipeline_init(pipeline
, device
, cache
,
2100 pCreateInfo
, pAllocator
);
2101 if (result
!= VK_SUCCESS
) {
2102 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
2106 /* If rasterization is not enabled, various CreateInfo structs must be
2109 const bool raster_enabled
=
2110 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
;
2112 const VkPipelineViewportStateCreateInfo
*vp_info
=
2113 raster_enabled
? pCreateInfo
->pViewportState
: NULL
;
2115 const VkPipelineMultisampleStateCreateInfo
*ms_info
=
2116 raster_enabled
? pCreateInfo
->pMultisampleState
: NULL
;
2118 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
2119 raster_enabled
? pCreateInfo
->pDepthStencilState
: NULL
;
2121 const VkPipelineColorBlendStateCreateInfo
*cb_info
=
2122 raster_enabled
? pCreateInfo
->pColorBlendState
: NULL
;
2124 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_info
=
2125 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
2126 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
2128 assert(pCreateInfo
->pVertexInputState
);
2129 emit_vertex_input(pipeline
, pCreateInfo
->pVertexInputState
);
2130 assert(pCreateInfo
->pRasterizationState
);
2131 emit_rs_state(pipeline
, pCreateInfo
->pInputAssemblyState
,
2132 pCreateInfo
->pRasterizationState
,
2133 ms_info
, line_info
, pass
, subpass
);
2134 emit_ms_state(pipeline
, ms_info
);
2135 emit_ds_state(pipeline
, ds_info
, pass
, subpass
);
2136 emit_cb_state(pipeline
, cb_info
, ms_info
);
2137 compute_kill_pixel(pipeline
, ms_info
, subpass
);
2139 emit_urb_setup(pipeline
);
2141 emit_3dstate_clip(pipeline
,
2142 pCreateInfo
->pInputAssemblyState
,
2144 pCreateInfo
->pRasterizationState
);
2145 emit_3dstate_streamout(pipeline
, pCreateInfo
->pRasterizationState
);
2148 /* From gen7_vs_state.c */
2151 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2152 * Geometry > Geometry Shader > State:
2154 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2155 * whole fixed function pipeline when the GS enable changes value in
2158 * The hardware architects have clarified that in this context "flush the
2159 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2162 if (!device
->info
.is_haswell
&& !device
->info
.is_baytrail
)
2163 gen7_emit_vs_workaround_flush(brw
);
2166 emit_3dstate_vs(pipeline
);
2167 emit_3dstate_hs_te_ds(pipeline
, pCreateInfo
->pTessellationState
);
2168 emit_3dstate_gs(pipeline
);
2169 emit_3dstate_sbe(pipeline
);
2170 emit_3dstate_wm(pipeline
, subpass
,
2171 pCreateInfo
->pInputAssemblyState
,
2172 pCreateInfo
->pRasterizationState
,
2173 cb_info
, ms_info
, line_info
);
2174 emit_3dstate_ps(pipeline
, cb_info
, ms_info
);
2176 emit_3dstate_ps_extra(pipeline
, subpass
);
2177 emit_3dstate_vf_topology(pipeline
);
2179 emit_3dstate_vf_statistics(pipeline
);
2181 *pPipeline
= anv_pipeline_to_handle(pipeline
);
2183 return pipeline
->batch
.status
;
2187 compute_pipeline_create(
2189 struct anv_pipeline_cache
* cache
,
2190 const VkComputePipelineCreateInfo
* pCreateInfo
,
2191 const VkAllocationCallbacks
* pAllocator
,
2192 VkPipeline
* pPipeline
)
2194 ANV_FROM_HANDLE(anv_device
, device
, _device
);
2195 const struct gen_device_info
*devinfo
= &device
->info
;
2196 struct anv_pipeline
*pipeline
;
2199 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
);
2201 /* Use the default pipeline cache if none is specified */
2202 if (cache
== NULL
&& device
->physical
->instance
->pipeline_cache_enabled
)
2203 cache
= &device
->default_pipeline_cache
;
2205 pipeline
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
2206 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2207 if (pipeline
== NULL
)
2208 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2210 pipeline
->device
= device
;
2212 pipeline
->blend_state
.map
= NULL
;
2214 const VkAllocationCallbacks
*alloc
=
2215 pAllocator
? pAllocator
: &device
->alloc
;
2217 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
2218 if (result
!= VK_SUCCESS
) {
2219 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
2222 pipeline
->batch
.alloc
= alloc
;
2223 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
2224 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
2225 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
2226 pipeline
->batch
.status
= VK_SUCCESS
;
2228 pipeline
->mem_ctx
= ralloc_context(NULL
);
2229 pipeline
->flags
= pCreateInfo
->flags
;
2231 /* When we free the pipeline, we detect stages based on the NULL status
2232 * of various prog_data pointers. Make them NULL by default.
2234 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
2235 pipeline
->num_executables
= 0;
2237 pipeline
->needs_data_cache
= false;
2239 assert(pCreateInfo
->stage
.stage
== VK_SHADER_STAGE_COMPUTE_BIT
);
2240 pipeline
->active_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
2241 ANV_FROM_HANDLE(anv_shader_module
, module
, pCreateInfo
->stage
.module
);
2242 result
= anv_pipeline_compile_cs(pipeline
, cache
, pCreateInfo
, module
,
2243 pCreateInfo
->stage
.pName
,
2244 pCreateInfo
->stage
.pSpecializationInfo
);
2245 if (result
!= VK_SUCCESS
) {
2246 ralloc_free(pipeline
->mem_ctx
);
2247 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
2251 const struct brw_cs_prog_data
*cs_prog_data
= get_cs_prog_data(pipeline
);
2253 anv_pipeline_setup_l3_config(pipeline
, cs_prog_data
->base
.total_shared
> 0);
2255 uint32_t group_size
= cs_prog_data
->local_size
[0] *
2256 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
2257 uint32_t remainder
= group_size
& (cs_prog_data
->simd_size
- 1);
2260 pipeline
->cs_right_mask
= ~0u >> (32 - remainder
);
2262 pipeline
->cs_right_mask
= ~0u >> (32 - cs_prog_data
->simd_size
);
2264 const uint32_t vfe_curbe_allocation
=
2265 ALIGN(cs_prog_data
->push
.per_thread
.regs
* cs_prog_data
->threads
+
2266 cs_prog_data
->push
.cross_thread
.regs
, 2);
2268 const uint32_t subslices
= MAX2(device
->physical
->subslice_total
, 1);
2270 const struct anv_shader_bin
*cs_bin
=
2271 pipeline
->shaders
[MESA_SHADER_COMPUTE
];
2273 anv_batch_emit(&pipeline
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
2277 vfe
.GPGPUMode
= true;
2279 vfe
.MaximumNumberofThreads
=
2280 devinfo
->max_cs_threads
* subslices
- 1;
2281 vfe
.NumberofURBEntries
= GEN_GEN
<= 7 ? 0 : 2;
2283 vfe
.ResetGatewayTimer
= true;
2286 vfe
.BypassGatewayControl
= true;
2288 vfe
.URBEntryAllocationSize
= GEN_GEN
<= 7 ? 0 : 2;
2289 vfe
.CURBEAllocationSize
= vfe_curbe_allocation
;
2291 if (cs_bin
->prog_data
->total_scratch
) {
2293 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
2294 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
2296 vfe
.PerThreadScratchSpace
=
2297 ffs(cs_bin
->prog_data
->total_scratch
) - 11;
2298 } else if (GEN_IS_HASWELL
) {
2299 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
2300 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
2302 vfe
.PerThreadScratchSpace
=
2303 ffs(cs_bin
->prog_data
->total_scratch
) - 12;
2305 /* IVB and BYT use the range [0, 11] to mean [1kB, 12kB]
2306 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
2308 vfe
.PerThreadScratchSpace
=
2309 cs_bin
->prog_data
->total_scratch
/ 1024 - 1;
2311 vfe
.ScratchSpaceBasePointer
=
2312 get_scratch_address(pipeline
, MESA_SHADER_COMPUTE
, cs_bin
);
2316 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2317 .KernelStartPointer
= cs_bin
->kernel
.offset
,
2319 .SamplerCount
= GEN_GEN
== 11 ? 0 : get_sampler_count(cs_bin
),
2320 /* We add 1 because the CS indirect parameters buffer isn't accounted
2321 * for in bind_map.surface_count.
2323 .BindingTableEntryCount
= 1 + MIN2(cs_bin
->bind_map
.surface_count
, 30),
2324 .BarrierEnable
= cs_prog_data
->uses_barrier
,
2325 .SharedLocalMemorySize
=
2326 encode_slm_size(GEN_GEN
, cs_prog_data
->base
.total_shared
),
2329 .ConstantURBEntryReadOffset
= 0,
2331 .ConstantURBEntryReadLength
= cs_prog_data
->push
.per_thread
.regs
,
2332 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2333 .CrossThreadConstantDataReadLength
=
2334 cs_prog_data
->push
.cross_thread
.regs
,
2337 .NumberofThreadsinGPGPUThreadGroup
= cs_prog_data
->threads
,
2339 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
,
2340 pipeline
->interface_descriptor_data
,
2343 *pPipeline
= anv_pipeline_to_handle(pipeline
);
2345 return pipeline
->batch
.status
;
2348 VkResult
genX(CreateGraphicsPipelines
)(
2350 VkPipelineCache pipelineCache
,
2352 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
2353 const VkAllocationCallbacks
* pAllocator
,
2354 VkPipeline
* pPipelines
)
2356 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
2358 VkResult result
= VK_SUCCESS
;
2361 for (i
= 0; i
< count
; i
++) {
2362 result
= genX(graphics_pipeline_create
)(_device
,
2365 pAllocator
, &pPipelines
[i
]);
2367 /* Bail out on the first error as it is not obvious what error should be
2368 * report upon 2 different failures. */
2369 if (result
!= VK_SUCCESS
)
2373 for (; i
< count
; i
++)
2374 pPipelines
[i
] = VK_NULL_HANDLE
;
2379 VkResult
genX(CreateComputePipelines
)(
2381 VkPipelineCache pipelineCache
,
2383 const VkComputePipelineCreateInfo
* pCreateInfos
,
2384 const VkAllocationCallbacks
* pAllocator
,
2385 VkPipeline
* pPipelines
)
2387 ANV_FROM_HANDLE(anv_pipeline_cache
, pipeline_cache
, pipelineCache
);
2389 VkResult result
= VK_SUCCESS
;
2392 for (i
= 0; i
< count
; i
++) {
2393 result
= compute_pipeline_create(_device
, pipeline_cache
,
2395 pAllocator
, &pPipelines
[i
]);
2397 /* Bail out on the first error as it is not obvious what error should be
2398 * report upon 2 different failures. */
2399 if (result
!= VK_SUCCESS
)
2403 for (; i
< count
; i
++)
2404 pPipelines
[i
] = VK_NULL_HANDLE
;