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c9735df68bfd361b69c265931f5408afc235d81d
[mesa.git] / src / intel / vulkan / genX_state.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "common/gen_aux_map.h"
33 #include "common/gen_sample_positions.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
36
37 #include "vk_util.h"
38
39 static void
40 genX(emit_slice_hashing_state)(struct anv_device *device,
41 struct anv_batch *batch)
42 {
43 device->slice_hash = (struct anv_state) { 0 };
44
45 #if GEN_GEN == 11
46 const unsigned *ppipe_subslices = device->info.ppipe_subslices;
47 int subslices_delta = ppipe_subslices[0] - ppipe_subslices[1];
48 if (subslices_delta == 0)
49 return;
50
51 unsigned size = GENX(SLICE_HASH_TABLE_length) * 4;
52 device->slice_hash =
53 anv_state_pool_alloc(&device->dynamic_state_pool, size, 64);
54
55 struct GENX(SLICE_HASH_TABLE) table0 = {
56 .Entry = {
57 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
58 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
59 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
60 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
61 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
62 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
63 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
64 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
65 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
66 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
67 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
68 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
69 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
70 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
71 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
72 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }
73 }
74 };
75
76 struct GENX(SLICE_HASH_TABLE) table1 = {
77 .Entry = {
78 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
79 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
80 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
81 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
82 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
83 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
84 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
85 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
86 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
87 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
88 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
89 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
90 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
91 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
92 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
93 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }
94 }
95 };
96
97 const struct GENX(SLICE_HASH_TABLE) *table =
98 subslices_delta < 0 ? &table0 : &table1;
99 GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, table);
100
101 anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
102 ptr.SliceHashStatePointerValid = true;
103 ptr.SliceHashTableStatePointer = device->slice_hash.offset;
104 }
105
106 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {
107 mode.SliceHashingTableEnable = true;
108 }
109 #endif
110 }
111
112 VkResult
113 genX(init_device_state)(struct anv_device *device)
114 {
115 struct anv_batch batch;
116
117 uint32_t cmds[64];
118 batch.start = batch.next = cmds;
119 batch.end = (void *) cmds + sizeof(cmds);
120
121 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
122 #if GEN_GEN >= 9
123 ps.MaskBits = 3;
124 #endif
125 ps.PipelineSelection = _3D;
126 }
127
128 #if GEN_GEN == 9
129 uint32_t cache_mode_1;
130 anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
131 .FloatBlendOptimizationEnable = true,
132 .FloatBlendOptimizationEnableMask = true,
133 .PartialResolveDisableInVC = true,
134 .PartialResolveDisableInVCMask = true);
135
136 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
137 lri.RegisterOffset = GENX(CACHE_MODE_1_num);
138 lri.DataDWord = cache_mode_1;
139 }
140 #endif
141
142 anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
143
144 anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
145 rect.ClippedDrawingRectangleYMin = 0;
146 rect.ClippedDrawingRectangleXMin = 0;
147 rect.ClippedDrawingRectangleYMax = UINT16_MAX;
148 rect.ClippedDrawingRectangleXMax = UINT16_MAX;
149 rect.DrawingRectangleOriginY = 0;
150 rect.DrawingRectangleOriginX = 0;
151 }
152
153 #if GEN_GEN >= 8
154 anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
155
156 /* See the Vulkan 1.0 spec Table 24.1 "Standard sample locations" and
157 * VkPhysicalDeviceFeatures::standardSampleLocations.
158 */
159 anv_batch_emit(&batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
160 GEN_SAMPLE_POS_1X(sp._1xSample);
161 GEN_SAMPLE_POS_2X(sp._2xSample);
162 GEN_SAMPLE_POS_4X(sp._4xSample);
163 GEN_SAMPLE_POS_8X(sp._8xSample);
164 #if GEN_GEN >= 9
165 GEN_SAMPLE_POS_16X(sp._16xSample);
166 #endif
167 }
168
169 /* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the
170 * section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
171 * Clear." It mentions that the packet overrides GPU state for the clear
172 * operation and needs to be reset to 0s to clear the overrides. Depending
173 * on the kernel, we may not get a context with the state for this packet
174 * zeroed. Do it ourselves just in case. We've observed this to prevent a
175 * number of GPU hangs on ICL.
176 */
177 anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);
178 #endif
179
180 #if GEN_GEN == 11
181 /* The default behavior of bit 5 "Headerless Message for Pre-emptable
182 * Contexts" in SAMPLER MODE register is set to 0, which means
183 * headerless sampler messages are not allowed for pre-emptable
184 * contexts. Set the bit 5 to 1 to allow them.
185 */
186 uint32_t sampler_mode;
187 anv_pack_struct(&sampler_mode, GENX(SAMPLER_MODE),
188 .HeaderlessMessageforPreemptableContexts = true,
189 .HeaderlessMessageforPreemptableContextsMask = true);
190
191 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
192 lri.RegisterOffset = GENX(SAMPLER_MODE_num);
193 lri.DataDWord = sampler_mode;
194 }
195
196 /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
197 * HALF_SLICE_CHICKEN7 register.
198 */
199 uint32_t half_slice_chicken7;
200 anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7),
201 .EnabledTexelOffsetPrecisionFix = true,
202 .EnabledTexelOffsetPrecisionFixMask = true);
203
204 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
205 lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num);
206 lri.DataDWord = half_slice_chicken7;
207 }
208
209 uint32_t tccntlreg;
210 anv_pack_struct(&tccntlreg, GENX(TCCNTLREG),
211 .L3DataPartialWriteMergingEnable = true,
212 .ColorZPartialWriteMergingEnable = true,
213 .URBPartialWriteMergingEnable = true,
214 .TCDisable = true);
215
216 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
217 lri.RegisterOffset = GENX(TCCNTLREG_num);
218 lri.DataDWord = tccntlreg;
219 }
220
221 #endif
222 genX(emit_slice_hashing_state)(device, &batch);
223
224 #if GEN_GEN >= 11
225 /* hardware specification recommends disabling repacking for
226 * the compatibility with decompression mechanism in display controller.
227 */
228 if (device->info.disable_ccs_repack) {
229 uint32_t cache_mode_0;
230 anv_pack_struct(&cache_mode_0,
231 GENX(CACHE_MODE_0),
232 .DisableRepackingforCompression = true,
233 .DisableRepackingforCompressionMask = true);
234
235 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
236 lri.RegisterOffset = GENX(CACHE_MODE_0_num);
237 lri.DataDWord = cache_mode_0;
238 }
239 }
240 #endif
241
242 #if GEN_GEN == 12
243 uint64_t aux_base_addr = gen_aux_map_get_base(device->aux_map_ctx);
244 assert(aux_base_addr % (32 * 1024) == 0);
245 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
246 lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num);
247 lri.DataDWord = aux_base_addr & 0xffffffff;
248 }
249 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
250 lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4;
251 lri.DataDWord = aux_base_addr >> 32;
252 }
253 #endif
254
255 /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
256 * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
257 *
258 * This is only safe on kernels with context isolation support.
259 */
260 if (GEN_GEN >= 8 && device->physical->has_context_isolation) {
261 UNUSED uint32_t tmp_reg;
262 #if GEN_GEN >= 9
263 anv_pack_struct(&tmp_reg, GENX(CS_DEBUG_MODE2),
264 .CONSTANT_BUFFERAddressOffsetDisable = true,
265 .CONSTANT_BUFFERAddressOffsetDisableMask = true);
266 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
267 lri.RegisterOffset = GENX(CS_DEBUG_MODE2_num);
268 lri.DataDWord = tmp_reg;
269 }
270 #elif GEN_GEN == 8
271 anv_pack_struct(&tmp_reg, GENX(INSTPM),
272 .CONSTANT_BUFFERAddressOffsetDisable = true,
273 .CONSTANT_BUFFERAddressOffsetDisableMask = true);
274 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
275 lri.RegisterOffset = GENX(INSTPM_num);
276 lri.DataDWord = tmp_reg;
277 }
278 #endif
279 }
280
281 anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
282
283 assert(batch.next <= batch.end);
284
285 return anv_queue_submit_simple_batch(&device->queue, &batch);
286 }
287
288 static uint32_t
289 vk_to_gen_tex_filter(VkFilter filter, bool anisotropyEnable)
290 {
291 switch (filter) {
292 default:
293 assert(!"Invalid filter");
294 case VK_FILTER_NEAREST:
295 return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_NEAREST;
296 case VK_FILTER_LINEAR:
297 return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_LINEAR;
298 }
299 }
300
301 static uint32_t
302 vk_to_gen_max_anisotropy(float ratio)
303 {
304 return (anv_clamp_f(ratio, 2, 16) - 2) / 2;
305 }
306
307 static const uint32_t vk_to_gen_mipmap_mode[] = {
308 [VK_SAMPLER_MIPMAP_MODE_NEAREST] = MIPFILTER_NEAREST,
309 [VK_SAMPLER_MIPMAP_MODE_LINEAR] = MIPFILTER_LINEAR
310 };
311
312 static const uint32_t vk_to_gen_tex_address[] = {
313 [VK_SAMPLER_ADDRESS_MODE_REPEAT] = TCM_WRAP,
314 [VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT] = TCM_MIRROR,
315 [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE] = TCM_CLAMP,
316 [VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
317 [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
318 };
319
320 /* Vulkan specifies the result of shadow comparisons as:
321 * 1 if ref <op> texel,
322 * 0 otherwise.
323 *
324 * The hardware does:
325 * 0 if texel <op> ref,
326 * 1 otherwise.
327 *
328 * So, these look a bit strange because there's both a negation
329 * and swapping of the arguments involved.
330 */
331 static const uint32_t vk_to_gen_shadow_compare_op[] = {
332 [VK_COMPARE_OP_NEVER] = PREFILTEROPALWAYS,
333 [VK_COMPARE_OP_LESS] = PREFILTEROPLEQUAL,
334 [VK_COMPARE_OP_EQUAL] = PREFILTEROPNOTEQUAL,
335 [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLESS,
336 [VK_COMPARE_OP_GREATER] = PREFILTEROPGEQUAL,
337 [VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPEQUAL,
338 [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGREATER,
339 [VK_COMPARE_OP_ALWAYS] = PREFILTEROPNEVER,
340 };
341
342 #if GEN_GEN >= 9
343 static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
344 [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
345 [VK_SAMPLER_REDUCTION_MODE_MIN_EXT] = MINIMUM,
346 [VK_SAMPLER_REDUCTION_MODE_MAX_EXT] = MAXIMUM,
347 };
348 #endif
349
350 VkResult genX(CreateSampler)(
351 VkDevice _device,
352 const VkSamplerCreateInfo* pCreateInfo,
353 const VkAllocationCallbacks* pAllocator,
354 VkSampler* pSampler)
355 {
356 ANV_FROM_HANDLE(anv_device, device, _device);
357 struct anv_sampler *sampler;
358
359 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
360
361 sampler = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*sampler), 8,
362 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
363 if (!sampler)
364 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
365
366 vk_object_base_init(&device->vk, &sampler->base, VK_OBJECT_TYPE_SAMPLER);
367 sampler->n_planes = 1;
368
369 uint32_t border_color_stride = GEN_IS_HASWELL ? 512 : 64;
370 uint32_t border_color_offset;
371 ASSERTED bool has_custom_color = false;
372 if (pCreateInfo->borderColor <= VK_BORDER_COLOR_INT_OPAQUE_WHITE) {
373 border_color_offset = device->border_colors.offset +
374 pCreateInfo->borderColor *
375 border_color_stride;
376 } else {
377 assert(GEN_GEN >= 8);
378 sampler->custom_border_color =
379 anv_state_reserved_pool_alloc(&device->custom_border_colors);
380 border_color_offset = sampler->custom_border_color.offset;
381 }
382
383 #if GEN_GEN >= 9
384 unsigned sampler_reduction_mode = STD_FILTER;
385 bool enable_sampler_reduction = false;
386 #endif
387
388 vk_foreach_struct(ext, pCreateInfo->pNext) {
389 switch (ext->sType) {
390 case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
391 VkSamplerYcbcrConversionInfo *pSamplerConversion =
392 (VkSamplerYcbcrConversionInfo *) ext;
393 ANV_FROM_HANDLE(anv_ycbcr_conversion, conversion,
394 pSamplerConversion->conversion);
395
396 /* Ignore conversion for non-YUV formats. This fulfills a requirement
397 * for clients that want to utilize same code path for images with
398 * external formats (VK_FORMAT_UNDEFINED) and "regular" RGBA images
399 * where format is known.
400 */
401 if (conversion == NULL || !conversion->format->can_ycbcr)
402 break;
403
404 sampler->n_planes = conversion->format->n_planes;
405 sampler->conversion = conversion;
406 break;
407 }
408 #if GEN_GEN >= 9
409 case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO: {
410 VkSamplerReductionModeCreateInfo *sampler_reduction =
411 (VkSamplerReductionModeCreateInfo *) ext;
412 sampler_reduction_mode =
413 vk_to_gen_sampler_reduction_mode[sampler_reduction->reductionMode];
414 enable_sampler_reduction = true;
415 break;
416 }
417 #endif
418 case VK_STRUCTURE_TYPE_SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT: {
419 VkSamplerCustomBorderColorCreateInfoEXT *custom_border_color =
420 (VkSamplerCustomBorderColorCreateInfoEXT *) ext;
421 if (sampler->custom_border_color.map == NULL)
422 break;
423 struct gen8_border_color *cbc = sampler->custom_border_color.map;
424 if (custom_border_color->format == VK_FORMAT_B4G4R4A4_UNORM_PACK16) {
425 /* B4G4R4A4_UNORM_PACK16 is treated as R4G4B4A4_UNORM_PACK16 with
426 * a swizzle, but this does not carry over to the sampler for
427 * border colors, so we need to do the swizzle ourselves here.
428 */
429 cbc->uint32[0] = custom_border_color->customBorderColor.uint32[2];
430 cbc->uint32[1] = custom_border_color->customBorderColor.uint32[1];
431 cbc->uint32[2] = custom_border_color->customBorderColor.uint32[0];
432 cbc->uint32[3] = custom_border_color->customBorderColor.uint32[3];
433 } else {
434 /* Both structs share the same layout, so just copy them over. */
435 memcpy(cbc, &custom_border_color->customBorderColor,
436 sizeof(VkClearColorValue));
437 }
438 has_custom_color = true;
439 break;
440 }
441 default:
442 anv_debug_ignored_stype(ext->sType);
443 break;
444 }
445 }
446
447 assert((sampler->custom_border_color.map == NULL) || has_custom_color);
448
449 if (device->physical->has_bindless_samplers) {
450 /* If we have bindless, allocate enough samplers. We allocate 32 bytes
451 * for each sampler instead of 16 bytes because we want all bindless
452 * samplers to be 32-byte aligned so we don't have to use indirect
453 * sampler messages on them.
454 */
455 sampler->bindless_state =
456 anv_state_pool_alloc(&device->dynamic_state_pool,
457 sampler->n_planes * 32, 32);
458 }
459
460 for (unsigned p = 0; p < sampler->n_planes; p++) {
461 const bool plane_has_chroma =
462 sampler->conversion && sampler->conversion->format->planes[p].has_chroma;
463 const VkFilter min_filter =
464 plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->minFilter;
465 const VkFilter mag_filter =
466 plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->magFilter;
467 const bool enable_min_filter_addr_rounding = min_filter != VK_FILTER_NEAREST;
468 const bool enable_mag_filter_addr_rounding = mag_filter != VK_FILTER_NEAREST;
469 /* From Broadwell PRM, SAMPLER_STATE:
470 * "Mip Mode Filter must be set to MIPFILTER_NONE for Planar YUV surfaces."
471 */
472 const uint32_t mip_filter_mode =
473 (sampler->conversion &&
474 isl_format_is_yuv(sampler->conversion->format->planes[0].isl_format)) ?
475 MIPFILTER_NONE : vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode];
476
477 struct GENX(SAMPLER_STATE) sampler_state = {
478 .SamplerDisable = false,
479 .TextureBorderColorMode = DX10OGL,
480
481 #if GEN_GEN >= 8
482 .LODPreClampMode = CLAMP_MODE_OGL,
483 #else
484 .LODPreClampEnable = CLAMP_ENABLE_OGL,
485 #endif
486
487 #if GEN_GEN == 8
488 .BaseMipLevel = 0.0,
489 #endif
490 .MipModeFilter = mip_filter_mode,
491 .MagModeFilter = vk_to_gen_tex_filter(mag_filter, pCreateInfo->anisotropyEnable),
492 .MinModeFilter = vk_to_gen_tex_filter(min_filter, pCreateInfo->anisotropyEnable),
493 .TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996),
494 .AnisotropicAlgorithm =
495 pCreateInfo->anisotropyEnable ? EWAApproximation : LEGACY,
496 .MinLOD = anv_clamp_f(pCreateInfo->minLod, 0, 14),
497 .MaxLOD = anv_clamp_f(pCreateInfo->maxLod, 0, 14),
498 .ChromaKeyEnable = 0,
499 .ChromaKeyIndex = 0,
500 .ChromaKeyMode = 0,
501 .ShadowFunction =
502 vk_to_gen_shadow_compare_op[pCreateInfo->compareEnable ?
503 pCreateInfo->compareOp : VK_COMPARE_OP_NEVER],
504 .CubeSurfaceControlMode = OVERRIDE,
505
506 .BorderColorPointer = border_color_offset,
507
508 #if GEN_GEN >= 8
509 .LODClampMagnificationMode = MIPNONE,
510 #endif
511
512 .MaximumAnisotropy = vk_to_gen_max_anisotropy(pCreateInfo->maxAnisotropy),
513 .RAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
514 .RAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
515 .VAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
516 .VAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
517 .UAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
518 .UAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
519 .TrilinearFilterQuality = 0,
520 .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
521 .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU],
522 .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV],
523 .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
524
525 #if GEN_GEN >= 9
526 .ReductionType = sampler_reduction_mode,
527 .ReductionTypeEnable = enable_sampler_reduction,
528 #endif
529 };
530
531 GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);
532
533 if (sampler->bindless_state.map) {
534 memcpy(sampler->bindless_state.map + p * 32,
535 sampler->state[p], GENX(SAMPLER_STATE_length) * 4);
536 }
537 }
538
539 *pSampler = anv_sampler_to_handle(sampler);
540
541 return VK_SUCCESS;
542 }