projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Added few more stubs so that control reaches to DestroyDevice().
[mesa.git] / src / intel / vulkan / genX_state.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "common/gen_aux_map.h"
33 #include "common/gen_sample_positions.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
36
37 #include "vk_util.h"
38
39 static void
40 genX(emit_slice_hashing_state)(struct anv_device *device,
41 struct anv_batch *batch)
42 {
43 device->slice_hash = (struct anv_state) { 0 };
44
45 #if GEN_GEN == 11
46 const unsigned *ppipe_subslices = device->info.ppipe_subslices;
47 int subslices_delta = ppipe_subslices[0] - ppipe_subslices[1];
48 if (subslices_delta == 0)
49 return;
50
51 unsigned size = GENX(SLICE_HASH_TABLE_length) * 4;
52 device->slice_hash =
53 anv_state_pool_alloc(&device->dynamic_state_pool, size, 64);
54
55 struct GENX(SLICE_HASH_TABLE) table0 = {
56 .Entry = {
57 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
58 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
59 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
60 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
61 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
62 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
63 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
64 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
65 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
66 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
67 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
68 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
69 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 },
70 { 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 },
71 { 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 },
72 { 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 }
73 }
74 };
75
76 struct GENX(SLICE_HASH_TABLE) table1 = {
77 .Entry = {
78 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
79 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
80 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
81 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
82 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
83 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
84 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
85 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
86 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
87 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
88 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
89 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
90 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 },
91 { 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 },
92 { 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1 },
93 { 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0 }
94 }
95 };
96
97 const struct GENX(SLICE_HASH_TABLE) *table =
98 subslices_delta < 0 ? &table0 : &table1;
99 GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, table);
100
101 anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
102 ptr.SliceHashStatePointerValid = true;
103 ptr.SliceHashTableStatePointer = device->slice_hash.offset;
104 }
105
106 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {
107 mode.SliceHashingTableEnable = true;
108 }
109 #endif
110 }
111
112 VkResult
113 genX(init_device_state)(struct anv_device *device)
114 {
115 struct anv_batch batch;
116
117 uint32_t cmds[64];
118 batch.start = batch.next = cmds;
119 batch.end = (void *) cmds + sizeof(cmds);
120
121 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
122 #if GEN_GEN >= 9
123 ps.MaskBits = 3;
124 #endif
125 ps.PipelineSelection = _3D;
126 }
127
128 #if GEN_GEN == 9
129 uint32_t cache_mode_1;
130 anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
131 .FloatBlendOptimizationEnable = true,
132 .FloatBlendOptimizationEnableMask = true,
133 .PartialResolveDisableInVC = true,
134 .PartialResolveDisableInVCMask = true);
135
136 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
137 lri.RegisterOffset = GENX(CACHE_MODE_1_num);
138 lri.DataDWord = cache_mode_1;
139 }
140 #endif
141
142 anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
143
144 anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
145 rect.ClippedDrawingRectangleYMin = 0;
146 rect.ClippedDrawingRectangleXMin = 0;
147 rect.ClippedDrawingRectangleYMax = UINT16_MAX;
148 rect.ClippedDrawingRectangleXMax = UINT16_MAX;
149 rect.DrawingRectangleOriginY = 0;
150 rect.DrawingRectangleOriginX = 0;
151 }
152
153 #if GEN_GEN >= 8
154 anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck);
155
156 /* See the Vulkan 1.0 spec Table 24.1 "Standard sample locations" and
157 * VkPhysicalDeviceFeatures::standardSampleLocations.
158 */
159 anv_batch_emit(&batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
160 GEN_SAMPLE_POS_1X(sp._1xSample);
161 GEN_SAMPLE_POS_2X(sp._2xSample);
162 GEN_SAMPLE_POS_4X(sp._4xSample);
163 GEN_SAMPLE_POS_8X(sp._8xSample);
164 #if GEN_GEN >= 9
165 GEN_SAMPLE_POS_16X(sp._16xSample);
166 #endif
167 }
168
169 /* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the
170 * section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
171 * Clear." It mentions that the packet overrides GPU state for the clear
172 * operation and needs to be reset to 0s to clear the overrides. Depending
173 * on the kernel, we may not get a context with the state for this packet
174 * zeroed. Do it ourselves just in case. We've observed this to prevent a
175 * number of GPU hangs on ICL.
176 */
177 anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp);
178 #endif
179
180 #if GEN_GEN == 11
181 /* The default behavior of bit 5 "Headerless Message for Pre-emptable
182 * Contexts" in SAMPLER MODE register is set to 0, which means
183 * headerless sampler messages are not allowed for pre-emptable
184 * contexts. Set the bit 5 to 1 to allow them.
185 */
186 uint32_t sampler_mode;
187 anv_pack_struct(&sampler_mode, GENX(SAMPLER_MODE),
188 .HeaderlessMessageforPreemptableContexts = true,
189 .HeaderlessMessageforPreemptableContextsMask = true);
190
191 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
192 lri.RegisterOffset = GENX(SAMPLER_MODE_num);
193 lri.DataDWord = sampler_mode;
194 }
195
196 /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
197 * HALF_SLICE_CHICKEN7 register.
198 */
199 uint32_t half_slice_chicken7;
200 anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7),
201 .EnabledTexelOffsetPrecisionFix = true,
202 .EnabledTexelOffsetPrecisionFixMask = true);
203
204 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
205 lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num);
206 lri.DataDWord = half_slice_chicken7;
207 }
208
209 uint32_t tccntlreg;
210 anv_pack_struct(&tccntlreg, GENX(TCCNTLREG),
211 .L3DataPartialWriteMergingEnable = true,
212 .ColorZPartialWriteMergingEnable = true,
213 .URBPartialWriteMergingEnable = true,
214 .TCDisable = true);
215
216 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
217 lri.RegisterOffset = GENX(TCCNTLREG_num);
218 lri.DataDWord = tccntlreg;
219 }
220
221 #endif
222 genX(emit_slice_hashing_state)(device, &batch);
223
224 #if GEN_GEN >= 11
225 /* hardware specification recommends disabling repacking for
226 * the compatibility with decompression mechanism in display controller.
227 */
228 if (device->info.disable_ccs_repack) {
229 uint32_t cache_mode_0;
230 anv_pack_struct(&cache_mode_0,
231 GENX(CACHE_MODE_0),
232 .DisableRepackingforCompression = true,
233 .DisableRepackingforCompressionMask = true);
234
235 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
236 lri.RegisterOffset = GENX(CACHE_MODE_0_num);
237 lri.DataDWord = cache_mode_0;
238 }
239 }
240
241 /* an unknown issue is causing vs push constants to become
242 * corrupted during object-level preemption. For now, restrict
243 * to command buffer level preemption to avoid rendering
244 * corruption.
245 */
246 uint32_t cs_chicken1;
247 anv_pack_struct(&cs_chicken1,
248 GENX(CS_CHICKEN1),
249 .ReplayMode = MidcmdbufferPreemption,
250 .ReplayModeMask = true);
251
252 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
253 lri.RegisterOffset = GENX(CS_CHICKEN1_num);
254 lri.DataDWord = cs_chicken1;
255 }
256 #endif
257
258 #if GEN_GEN == 12
259 if (device->info.has_aux_map) {
260 uint64_t aux_base_addr = gen_aux_map_get_base(device->aux_map_ctx);
261 assert(aux_base_addr % (32 * 1024) == 0);
262 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
263 lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num);
264 lri.DataDWord = aux_base_addr & 0xffffffff;
265 }
266 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
267 lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4;
268 lri.DataDWord = aux_base_addr >> 32;
269 }
270 }
271 #endif
272
273 /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
274 * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
275 *
276 * This is only safe on kernels with context isolation support.
277 */
278 if (GEN_GEN >= 8 && device->physical->has_context_isolation) {
279 UNUSED uint32_t tmp_reg;
280 #if GEN_GEN >= 9
281 anv_pack_struct(&tmp_reg, GENX(CS_DEBUG_MODE2),
282 .CONSTANT_BUFFERAddressOffsetDisable = true,
283 .CONSTANT_BUFFERAddressOffsetDisableMask = true);
284 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
285 lri.RegisterOffset = GENX(CS_DEBUG_MODE2_num);
286 lri.DataDWord = tmp_reg;
287 }
288 #elif GEN_GEN == 8
289 anv_pack_struct(&tmp_reg, GENX(INSTPM),
290 .CONSTANT_BUFFERAddressOffsetDisable = true,
291 .CONSTANT_BUFFERAddressOffsetDisableMask = true);
292 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
293 lri.RegisterOffset = GENX(INSTPM_num);
294 lri.DataDWord = tmp_reg;
295 }
296 #endif
297 }
298
299 #if GEN_GEN >= 12
300 const struct gen_l3_config *cfg = gen_get_default_l3_config(&device->info);
301 if (!cfg) {
302 /* Platforms with no configs just setup full-way allocation. */
303 uint32_t l3cr;
304 anv_pack_struct(&l3cr, GENX(L3ALLOC),
305 .L3FullWayAllocationEnable = true);
306 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
307 lri.RegisterOffset = GENX(L3ALLOC_num);
308 lri.DataDWord = l3cr;
309 }
310 }
311 #endif
312
313 anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
314
315 assert(batch.next <= batch.end);
316
317 return anv_queue_submit_simple_batch(&device->queue, &batch);
318 }
319
320 static uint32_t
321 vk_to_gen_tex_filter(VkFilter filter, bool anisotropyEnable)
322 {
323 switch (filter) {
324 default:
325 assert(!"Invalid filter");
326 case VK_FILTER_NEAREST:
327 return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_NEAREST;
328 case VK_FILTER_LINEAR:
329 return anisotropyEnable ? MAPFILTER_ANISOTROPIC : MAPFILTER_LINEAR;
330 }
331 }
332
333 static uint32_t
334 vk_to_gen_max_anisotropy(float ratio)
335 {
336 return (anv_clamp_f(ratio, 2, 16) - 2) / 2;
337 }
338
339 static const uint32_t vk_to_gen_mipmap_mode[] = {
340 [VK_SAMPLER_MIPMAP_MODE_NEAREST] = MIPFILTER_NEAREST,
341 [VK_SAMPLER_MIPMAP_MODE_LINEAR] = MIPFILTER_LINEAR
342 };
343
344 static const uint32_t vk_to_gen_tex_address[] = {
345 [VK_SAMPLER_ADDRESS_MODE_REPEAT] = TCM_WRAP,
346 [VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT] = TCM_MIRROR,
347 [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE] = TCM_CLAMP,
348 [VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE] = TCM_MIRROR_ONCE,
349 [VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER] = TCM_CLAMP_BORDER,
350 };
351
352 /* Vulkan specifies the result of shadow comparisons as:
353 * 1 if ref <op> texel,
354 * 0 otherwise.
355 *
356 * The hardware does:
357 * 0 if texel <op> ref,
358 * 1 otherwise.
359 *
360 * So, these look a bit strange because there's both a negation
361 * and swapping of the arguments involved.
362 */
363 static const uint32_t vk_to_gen_shadow_compare_op[] = {
364 [VK_COMPARE_OP_NEVER] = PREFILTEROPALWAYS,
365 [VK_COMPARE_OP_LESS] = PREFILTEROPLEQUAL,
366 [VK_COMPARE_OP_EQUAL] = PREFILTEROPNOTEQUAL,
367 [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLESS,
368 [VK_COMPARE_OP_GREATER] = PREFILTEROPGEQUAL,
369 [VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPEQUAL,
370 [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGREATER,
371 [VK_COMPARE_OP_ALWAYS] = PREFILTEROPNEVER,
372 };
373
374 #if GEN_GEN >= 9
375 static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
376 [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
377 [VK_SAMPLER_REDUCTION_MODE_MIN_EXT] = MINIMUM,
378 [VK_SAMPLER_REDUCTION_MODE_MAX_EXT] = MAXIMUM,
379 };
380 #endif
381
382 VkResult genX(CreateSampler)(
383 VkDevice _device,
384 const VkSamplerCreateInfo* pCreateInfo,
385 const VkAllocationCallbacks* pAllocator,
386 VkSampler* pSampler)
387 {
388 ANV_FROM_HANDLE(anv_device, device, _device);
389 struct anv_sampler *sampler;
390
391 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
392
393 sampler = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*sampler), 8,
394 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
395 if (!sampler)
396 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
397
398 vk_object_base_init(&device->vk, &sampler->base, VK_OBJECT_TYPE_SAMPLER);
399 sampler->n_planes = 1;
400
401 uint32_t border_color_stride = GEN_IS_HASWELL ? 512 : 64;
402 uint32_t border_color_offset;
403 ASSERTED bool has_custom_color = false;
404 if (pCreateInfo->borderColor <= VK_BORDER_COLOR_INT_OPAQUE_WHITE) {
405 border_color_offset = device->border_colors.offset +
406 pCreateInfo->borderColor *
407 border_color_stride;
408 } else {
409 assert(GEN_GEN >= 8);
410 sampler->custom_border_color =
411 anv_state_reserved_pool_alloc(&device->custom_border_colors);
412 border_color_offset = sampler->custom_border_color.offset;
413 }
414
415 #if GEN_GEN >= 9
416 unsigned sampler_reduction_mode = STD_FILTER;
417 bool enable_sampler_reduction = false;
418 #endif
419
420 vk_foreach_struct(ext, pCreateInfo->pNext) {
421 switch (ext->sType) {
422 case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
423 VkSamplerYcbcrConversionInfo *pSamplerConversion =
424 (VkSamplerYcbcrConversionInfo *) ext;
425 ANV_FROM_HANDLE(anv_ycbcr_conversion, conversion,
426 pSamplerConversion->conversion);
427
428 /* Ignore conversion for non-YUV formats. This fulfills a requirement
429 * for clients that want to utilize same code path for images with
430 * external formats (VK_FORMAT_UNDEFINED) and "regular" RGBA images
431 * where format is known.
432 */
433 if (conversion == NULL || !conversion->format->can_ycbcr)
434 break;
435
436 sampler->n_planes = conversion->format->n_planes;
437 sampler->conversion = conversion;
438 break;
439 }
440 #if GEN_GEN >= 9
441 case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO: {
442 VkSamplerReductionModeCreateInfo *sampler_reduction =
443 (VkSamplerReductionModeCreateInfo *) ext;
444 sampler_reduction_mode =
445 vk_to_gen_sampler_reduction_mode[sampler_reduction->reductionMode];
446 enable_sampler_reduction = true;
447 break;
448 }
449 #endif
450 case VK_STRUCTURE_TYPE_SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT: {
451 VkSamplerCustomBorderColorCreateInfoEXT *custom_border_color =
452 (VkSamplerCustomBorderColorCreateInfoEXT *) ext;
453 if (sampler->custom_border_color.map == NULL)
454 break;
455 struct gen8_border_color *cbc = sampler->custom_border_color.map;
456 if (custom_border_color->format == VK_FORMAT_B4G4R4A4_UNORM_PACK16) {
457 /* B4G4R4A4_UNORM_PACK16 is treated as R4G4B4A4_UNORM_PACK16 with
458 * a swizzle, but this does not carry over to the sampler for
459 * border colors, so we need to do the swizzle ourselves here.
460 */
461 cbc->uint32[0] = custom_border_color->customBorderColor.uint32[2];
462 cbc->uint32[1] = custom_border_color->customBorderColor.uint32[1];
463 cbc->uint32[2] = custom_border_color->customBorderColor.uint32[0];
464 cbc->uint32[3] = custom_border_color->customBorderColor.uint32[3];
465 } else {
466 /* Both structs share the same layout, so just copy them over. */
467 memcpy(cbc, &custom_border_color->customBorderColor,
468 sizeof(VkClearColorValue));
469 }
470 has_custom_color = true;
471 break;
472 }
473 default:
474 anv_debug_ignored_stype(ext->sType);
475 break;
476 }
477 }
478
479 assert((sampler->custom_border_color.map == NULL) || has_custom_color);
480
481 if (device->physical->has_bindless_samplers) {
482 /* If we have bindless, allocate enough samplers. We allocate 32 bytes
483 * for each sampler instead of 16 bytes because we want all bindless
484 * samplers to be 32-byte aligned so we don't have to use indirect
485 * sampler messages on them.
486 */
487 sampler->bindless_state =
488 anv_state_pool_alloc(&device->dynamic_state_pool,
489 sampler->n_planes * 32, 32);
490 }
491
492 for (unsigned p = 0; p < sampler->n_planes; p++) {
493 const bool plane_has_chroma =
494 sampler->conversion && sampler->conversion->format->planes[p].has_chroma;
495 const VkFilter min_filter =
496 plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->minFilter;
497 const VkFilter mag_filter =
498 plane_has_chroma ? sampler->conversion->chroma_filter : pCreateInfo->magFilter;
499 const bool enable_min_filter_addr_rounding = min_filter != VK_FILTER_NEAREST;
500 const bool enable_mag_filter_addr_rounding = mag_filter != VK_FILTER_NEAREST;
501 /* From Broadwell PRM, SAMPLER_STATE:
502 * "Mip Mode Filter must be set to MIPFILTER_NONE for Planar YUV surfaces."
503 */
504 const uint32_t mip_filter_mode =
505 (sampler->conversion &&
506 isl_format_is_yuv(sampler->conversion->format->planes[0].isl_format)) ?
507 MIPFILTER_NONE : vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode];
508
509 struct GENX(SAMPLER_STATE) sampler_state = {
510 .SamplerDisable = false,
511 .TextureBorderColorMode = DX10OGL,
512
513 #if GEN_GEN >= 8
514 .LODPreClampMode = CLAMP_MODE_OGL,
515 #else
516 .LODPreClampEnable = CLAMP_ENABLE_OGL,
517 #endif
518
519 #if GEN_GEN == 8
520 .BaseMipLevel = 0.0,
521 #endif
522 .MipModeFilter = mip_filter_mode,
523 .MagModeFilter = vk_to_gen_tex_filter(mag_filter, pCreateInfo->anisotropyEnable),
524 .MinModeFilter = vk_to_gen_tex_filter(min_filter, pCreateInfo->anisotropyEnable),
525 .TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996),
526 .AnisotropicAlgorithm =
527 pCreateInfo->anisotropyEnable ? EWAApproximation : LEGACY,
528 .MinLOD = anv_clamp_f(pCreateInfo->minLod, 0, 14),
529 .MaxLOD = anv_clamp_f(pCreateInfo->maxLod, 0, 14),
530 .ChromaKeyEnable = 0,
531 .ChromaKeyIndex = 0,
532 .ChromaKeyMode = 0,
533 .ShadowFunction =
534 vk_to_gen_shadow_compare_op[pCreateInfo->compareEnable ?
535 pCreateInfo->compareOp : VK_COMPARE_OP_NEVER],
536 .CubeSurfaceControlMode = OVERRIDE,
537
538 .BorderColorPointer = border_color_offset,
539
540 #if GEN_GEN >= 8
541 .LODClampMagnificationMode = MIPNONE,
542 #endif
543
544 .MaximumAnisotropy = vk_to_gen_max_anisotropy(pCreateInfo->maxAnisotropy),
545 .RAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
546 .RAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
547 .VAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
548 .VAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
549 .UAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
550 .UAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
551 .TrilinearFilterQuality = 0,
552 .NonnormalizedCoordinateEnable = pCreateInfo->unnormalizedCoordinates,
553 .TCXAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeU],
554 .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV],
555 .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW],
556
557 #if GEN_GEN >= 9
558 .ReductionType = sampler_reduction_mode,
559 .ReductionTypeEnable = enable_sampler_reduction,
560 #endif
561 };
562
563 GENX(SAMPLER_STATE_pack)(NULL, sampler->state[p], &sampler_state);
564
565 if (sampler->bindless_state.map) {
566 memcpy(sampler->bindless_state.map + p * 32,
567 sampler->state[p], GENX(SAMPLER_STATE_length) * 4);
568 }
569 }
570
571 *pSampler = anv_sampler_to_handle(sampler);
572
573 return VK_SUCCESS;
574 }