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[mesa.git] / src / mesa / drivers / dri / i915 / i830_vtbl.c
1 /**************************************************************************
2 *
3 * Copyright 2003 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "i830_context.h"
29 #include "i830_reg.h"
30 #include "intel_batchbuffer.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_regions.h"
33 #include "intel_tris.h"
34 #include "intel_fbo.h"
35 #include "intel_buffers.h"
36 #include "tnl/tnl.h"
37 #include "tnl/t_context.h"
38 #include "tnl/t_vertex.h"
39 #include "swrast_setup/swrast_setup.h"
40 #include "main/renderbuffer.h"
41 #include "main/framebuffer.h"
42 #include "main/fbobject.h"
43
44 #define FILE_DEBUG_FLAG DEBUG_STATE
45
46 static bool i830_check_vertex_size(struct intel_context *intel,
47 GLuint expected);
48
49 #define SZ_TO_HW(sz) ((sz-2)&0x3)
50 #define EMIT_SZ(sz) (EMIT_1F + (sz) - 1)
51 #define EMIT_ATTR( ATTR, STYLE, V0 ) \
52 do { \
53 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
54 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \
55 intel->vertex_attr_count++; \
56 v0 |= V0; \
57 } while (0)
58
59 #define EMIT_PAD( N ) \
60 do { \
61 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \
62 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \
63 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \
64 intel->vertex_attr_count++; \
65 } while (0)
66
67
68 #define VRTX_TEX_SET_FMT(n, x) ((x)<<((n)*2))
69 #define TEXBIND_SET(n, x) ((x)<<((n)*4))
70
71 static void
72 i830_render_prevalidate(struct intel_context *intel)
73 {
74 }
75
76 static void
77 i830_render_start(struct intel_context *intel)
78 {
79 struct gl_context *ctx = &intel->ctx;
80 struct i830_context *i830 = i830_context(ctx);
81 TNLcontext *tnl = TNL_CONTEXT(ctx);
82 struct vertex_buffer *VB = &tnl->vb;
83 GLbitfield64 index_bitset = tnl->render_inputs_bitset;
84 GLuint v0 = _3DSTATE_VFT0_CMD;
85 GLuint v2 = _3DSTATE_VFT1_CMD;
86 GLuint mcsb1 = 0;
87
88 /* Important:
89 */
90 VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
91 intel->vertex_attr_count = 0;
92
93 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
94 * build up a hardware vertex.
95 */
96 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
97 EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VFT0_XYZW);
98 intel->coloroffset = 4;
99 }
100 else {
101 EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, VFT0_XYZ);
102 intel->coloroffset = 3;
103 }
104
105 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_POINTSIZE)) {
106 EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, VFT0_POINT_WIDTH);
107 }
108
109 EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VFT0_DIFFUSE);
110
111 intel->specoffset = 0;
112 if (index_bitset & (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) |
113 BITFIELD64_BIT(_TNL_ATTRIB_FOG))) {
114 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
115 intel->specoffset = intel->coloroffset + 1;
116 EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC);
117 }
118 else
119 EMIT_PAD(3);
120
121 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG))
122 EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC);
123 else
124 EMIT_PAD(1);
125 }
126
127 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
128 int i, count = 0;
129
130 for (i = 0; i < I830_TEX_UNITS; i++) {
131 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
132 GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
133 GLuint emit;
134 GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] &
135 ~TEXCOORDTYPE_MASK);
136
137 switch (sz) {
138 case 1:
139 case 2:
140 emit = EMIT_2F;
141 sz = 2;
142 mcs |= TEXCOORDTYPE_CARTESIAN;
143 break;
144 case 3:
145 emit = EMIT_3F;
146 sz = 3;
147 mcs |= TEXCOORDTYPE_VECTOR;
148 break;
149 case 4:
150 emit = EMIT_3F_XYW;
151 sz = 3;
152 mcs |= TEXCOORDTYPE_HOMOGENEOUS;
153 break;
154 default:
155 continue;
156 };
157
158
159 EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0);
160 v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz));
161 mcsb1 |= (count + 8) << (i * 4);
162
163 if (mcs != i830->state.Tex[i][I830_TEXREG_MCS]) {
164 I830_STATECHANGE(i830, I830_UPLOAD_TEX(i));
165 i830->state.Tex[i][I830_TEXREG_MCS] = mcs;
166 }
167
168 count++;
169 }
170 }
171
172 v0 |= VFT0_TEX_COUNT(count);
173 }
174
175 /* Only need to change the vertex emit code if there has been a
176 * statechange to a new hardware vertex format:
177 */
178 if (v0 != i830->state.Ctx[I830_CTXREG_VF] ||
179 v2 != i830->state.Ctx[I830_CTXREG_VF2] ||
180 mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] ||
181 index_bitset != i830->last_index_bitset) {
182 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
183
184 /* Must do this *after* statechange, so as not to affect
185 * buffered vertices reliant on the old state:
186 */
187 intel->vertex_size =
188 _tnl_install_attrs(ctx,
189 intel->vertex_attrs,
190 intel->vertex_attr_count,
191 intel->ViewportMatrix.m, 0);
192
193 intel->vertex_size >>= 2;
194
195 i830->state.Ctx[I830_CTXREG_VF] = v0;
196 i830->state.Ctx[I830_CTXREG_VF2] = v2;
197 i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1;
198 i830->last_index_bitset = index_bitset;
199
200 assert(i830_check_vertex_size(intel, intel->vertex_size));
201 }
202 }
203
204 static void
205 i830_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
206 {
207 struct i830_context *i830 = i830_context(&intel->ctx);
208 GLuint st1 = i830->state.Stipple[I830_STPREG_ST1];
209
210 st1 &= ~ST1_ENABLE;
211
212 switch (rprim) {
213 case GL_TRIANGLES:
214 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
215 st1 |= ST1_ENABLE;
216 break;
217 case GL_LINES:
218 case GL_POINTS:
219 default:
220 break;
221 }
222
223 i830->intel.reduced_primitive = rprim;
224
225 if (st1 != i830->state.Stipple[I830_STPREG_ST1]) {
226 INTEL_FIREVERTICES(intel);
227
228 I830_STATECHANGE(i830, I830_UPLOAD_STIPPLE);
229 i830->state.Stipple[I830_STPREG_ST1] = st1;
230 }
231 }
232
233 /* Pull apart the vertex format registers and figure out how large a
234 * vertex is supposed to be.
235 */
236 static bool
237 i830_check_vertex_size(struct intel_context *intel, GLuint expected)
238 {
239 struct i830_context *i830 = i830_context(&intel->ctx);
240 int vft0 = i830->state.Ctx[I830_CTXREG_VF];
241 int vft1 = i830->state.Ctx[I830_CTXREG_VF2];
242 int nrtex = (vft0 & VFT0_TEX_COUNT_MASK) >> VFT0_TEX_COUNT_SHIFT;
243 int i, sz = 0;
244
245 switch (vft0 & VFT0_XYZW_MASK) {
246 case VFT0_XY:
247 sz = 2;
248 break;
249 case VFT0_XYZ:
250 sz = 3;
251 break;
252 case VFT0_XYW:
253 sz = 3;
254 break;
255 case VFT0_XYZW:
256 sz = 4;
257 break;
258 default:
259 fprintf(stderr, "no xyzw specified\n");
260 return 0;
261 }
262
263 if (vft0 & VFT0_SPEC)
264 sz++;
265 if (vft0 & VFT0_DIFFUSE)
266 sz++;
267 if (vft0 & VFT0_DEPTH_OFFSET)
268 sz++;
269 if (vft0 & VFT0_POINT_WIDTH)
270 sz++;
271
272 for (i = 0; i < nrtex; i++) {
273 switch (vft1 & VFT1_TEX0_MASK) {
274 case TEXCOORDFMT_2D:
275 sz += 2;
276 break;
277 case TEXCOORDFMT_3D:
278 sz += 3;
279 break;
280 case TEXCOORDFMT_4D:
281 sz += 4;
282 break;
283 case TEXCOORDFMT_1D:
284 sz += 1;
285 break;
286 }
287 vft1 >>= VFT1_TEX1_SHIFT;
288 }
289
290 if (sz != expected)
291 fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
292
293 return sz == expected;
294 }
295
296 static void
297 i830_emit_invarient_state(struct intel_context *intel)
298 {
299 BATCH_LOCALS;
300
301 BEGIN_BATCH(29);
302
303 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
304 OUT_BATCH(0);
305
306 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
307 OUT_BATCH(0);
308
309 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
310 OUT_BATCH(0);
311
312 OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
313 OUT_BATCH(FOGFUNC_ENABLE |
314 FOG_LINEAR_CONST | FOGSRC_INDEX_Z | ENABLE_FOG_DENSITY);
315 OUT_BATCH(0);
316 OUT_BATCH(0);
317
318
319 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
320 MAP_UNIT(0) |
321 DISABLE_TEX_STREAM_BUMP |
322 ENABLE_TEX_STREAM_COORD_SET |
323 TEX_STREAM_COORD_SET(0) |
324 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0));
325 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
326 MAP_UNIT(1) |
327 DISABLE_TEX_STREAM_BUMP |
328 ENABLE_TEX_STREAM_COORD_SET |
329 TEX_STREAM_COORD_SET(1) |
330 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1));
331 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
332 MAP_UNIT(2) |
333 DISABLE_TEX_STREAM_BUMP |
334 ENABLE_TEX_STREAM_COORD_SET |
335 TEX_STREAM_COORD_SET(2) |
336 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2));
337 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
338 MAP_UNIT(3) |
339 DISABLE_TEX_STREAM_BUMP |
340 ENABLE_TEX_STREAM_COORD_SET |
341 TEX_STREAM_COORD_SET(3) |
342 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3));
343
344 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
345 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
346 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
347 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
348 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
349 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
350 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
351 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
352
353 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
354 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
355
356 OUT_BATCH(_3DSTATE_W_STATE_CMD);
357 OUT_BATCH(MAGIC_W_STATE_DWORD1);
358 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
359
360
361 OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD);
362 OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
363
364 ADVANCE_BATCH();
365 }
366
367
368 #define emit( intel, state, size ) \
369 intel_batchbuffer_data(intel, state, size)
370
371 static GLuint
372 get_dirty(struct i830_hw_state *state)
373 {
374 return state->active & ~state->emitted;
375 }
376
377 static GLuint
378 get_state_size(struct i830_hw_state *state)
379 {
380 GLuint dirty = get_dirty(state);
381 GLuint sz = 0;
382 GLuint i;
383
384 if (dirty & I830_UPLOAD_INVARIENT)
385 sz += 40 * sizeof(int);
386
387 if (dirty & I830_UPLOAD_RASTER_RULES)
388 sz += sizeof(state->RasterRules);
389
390 if (dirty & I830_UPLOAD_CTX)
391 sz += sizeof(state->Ctx);
392
393 if (dirty & I830_UPLOAD_BUFFERS)
394 sz += sizeof(state->Buffer);
395
396 if (dirty & I830_UPLOAD_STIPPLE)
397 sz += sizeof(state->Stipple);
398
399 for (i = 0; i < I830_TEX_UNITS; i++) {
400 if ((dirty & I830_UPLOAD_TEX(i)))
401 sz += sizeof(state->Tex[i]);
402
403 if (dirty & I830_UPLOAD_TEXBLEND(i))
404 sz += state->TexBlendWordsUsed[i] * 4;
405 }
406
407 return sz;
408 }
409
410
411 /* Push the state into the sarea and/or texture memory.
412 */
413 static void
414 i830_emit_state(struct intel_context *intel)
415 {
416 struct i830_context *i830 = i830_context(&intel->ctx);
417 struct i830_hw_state *state = &i830->state;
418 int i, count;
419 GLuint dirty;
420 drm_intel_bo *aper_array[3 + I830_TEX_UNITS];
421 int aper_count;
422 GET_CURRENT_CONTEXT(ctx);
423 BATCH_LOCALS;
424
425 /* We don't hold the lock at this point, so want to make sure that
426 * there won't be a buffer wrap between the state emits and the primitive
427 * emit header.
428 *
429 * It might be better to talk about explicit places where
430 * scheduling is allowed, rather than assume that it is whenever a
431 * batchbuffer fills up.
432 */
433 intel_batchbuffer_require_space(intel,
434 get_state_size(state) +
435 INTEL_PRIM_EMIT_SIZE);
436 count = 0;
437 again:
438 aper_count = 0;
439 dirty = get_dirty(state);
440
441 aper_array[aper_count++] = intel->batch.bo;
442 if (dirty & I830_UPLOAD_BUFFERS) {
443 aper_array[aper_count++] = state->draw_region->bo;
444 if (state->depth_region)
445 aper_array[aper_count++] = state->depth_region->bo;
446 }
447
448 for (i = 0; i < I830_TEX_UNITS; i++)
449 if (dirty & I830_UPLOAD_TEX(i)) {
450 if (state->tex_buffer[i]) {
451 aper_array[aper_count++] = state->tex_buffer[i];
452 }
453 }
454
455 if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
456 if (count == 0) {
457 count++;
458 intel_batchbuffer_flush(intel);
459 goto again;
460 } else {
461 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i830 emit state");
462 assert(0);
463 }
464 }
465
466
467 /* Do this here as we may have flushed the batchbuffer above,
468 * causing more state to be dirty!
469 */
470 dirty = get_dirty(state);
471 state->emitted |= dirty;
472 assert(get_dirty(state) == 0);
473
474 if (dirty & I830_UPLOAD_INVARIENT) {
475 DBG("I830_UPLOAD_INVARIENT:\n");
476 i830_emit_invarient_state(intel);
477 }
478
479 if (dirty & I830_UPLOAD_RASTER_RULES) {
480 DBG("I830_UPLOAD_RASTER_RULES:\n");
481 emit(intel, state->RasterRules, sizeof(state->RasterRules));
482 }
483
484 if (dirty & I830_UPLOAD_CTX) {
485 DBG("I830_UPLOAD_CTX:\n");
486 emit(intel, state->Ctx, sizeof(state->Ctx));
487
488 }
489
490 if (dirty & I830_UPLOAD_BUFFERS) {
491 GLuint count = 15;
492
493 DBG("I830_UPLOAD_BUFFERS:\n");
494
495 if (state->depth_region)
496 count += 3;
497
498 BEGIN_BATCH(count);
499 OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
500 OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
501 OUT_RELOC(state->draw_region->bo,
502 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
503
504 if (state->depth_region) {
505 OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
506 OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
507 OUT_RELOC(state->depth_region->bo,
508 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
509 }
510
511 OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
512 OUT_BATCH(state->Buffer[I830_DESTREG_DV1]);
513 OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]);
514 OUT_BATCH(state->Buffer[I830_DESTREG_SR0]);
515 OUT_BATCH(state->Buffer[I830_DESTREG_SR1]);
516 OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
517
518 assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
519 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);
520 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]);
521 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]);
522 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]);
523 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]);
524 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]);
525 ADVANCE_BATCH();
526 }
527
528 if (dirty & I830_UPLOAD_STIPPLE) {
529 DBG("I830_UPLOAD_STIPPLE:\n");
530 emit(intel, state->Stipple, sizeof(state->Stipple));
531 }
532
533 for (i = 0; i < I830_TEX_UNITS; i++) {
534 if ((dirty & I830_UPLOAD_TEX(i))) {
535 DBG("I830_UPLOAD_TEX(%d):\n", i);
536
537 BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1);
538 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]);
539
540 OUT_RELOC(state->tex_buffer[i],
541 I915_GEM_DOMAIN_SAMPLER, 0,
542 state->tex_offset[i]);
543
544 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]);
545 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]);
546 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S3]);
547 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S4]);
548 OUT_BATCH(state->Tex[i][I830_TEXREG_MCS]);
549 OUT_BATCH(state->Tex[i][I830_TEXREG_CUBE]);
550
551 ADVANCE_BATCH();
552 }
553
554 if (dirty & I830_UPLOAD_TEXBLEND(i)) {
555 DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i,
556 state->TexBlendWordsUsed[i]);
557 emit(intel, state->TexBlend[i], state->TexBlendWordsUsed[i] * 4);
558 }
559 }
560
561 assert(get_dirty(state) == 0);
562 }
563
564 static void
565 i830_destroy_context(struct intel_context *intel)
566 {
567 GLuint i;
568 struct i830_context *i830 = i830_context(&intel->ctx);
569
570 intel_region_release(&i830->state.draw_region);
571 intel_region_release(&i830->state.depth_region);
572
573 for (i = 0; i < I830_TEX_UNITS; i++) {
574 if (i830->state.tex_buffer[i] != NULL) {
575 drm_intel_bo_unreference(i830->state.tex_buffer[i]);
576 i830->state.tex_buffer[i] = NULL;
577 }
578 }
579
580 _tnl_free_vertices(&intel->ctx);
581 }
582
583 static uint32_t i830_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
584 {
585 [MESA_FORMAT_ARGB8888] = DV_PF_8888,
586 [MESA_FORMAT_XRGB8888] = DV_PF_8888,
587 [MESA_FORMAT_RGB565] = DV_PF_565,
588 [MESA_FORMAT_ARGB1555] = DV_PF_1555,
589 [MESA_FORMAT_ARGB4444] = DV_PF_4444,
590 };
591
592 static bool
593 i830_render_target_supported(struct intel_context *intel,
594 struct gl_renderbuffer *rb)
595 {
596 gl_format format = rb->Format;
597
598 if (format == MESA_FORMAT_S8_Z24 ||
599 format == MESA_FORMAT_X8_Z24 ||
600 format == MESA_FORMAT_Z16) {
601 return true;
602 }
603
604 return i830_render_target_format_for_mesa_format[format] != 0;
605 }
606
607 static void
608 i830_set_draw_region(struct intel_context *intel,
609 struct intel_region *color_regions[],
610 struct intel_region *depth_region,
611 GLuint num_regions)
612 {
613 struct i830_context *i830 = i830_context(&intel->ctx);
614 struct gl_context *ctx = &intel->ctx;
615 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
616 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
617 struct gl_renderbuffer *drb;
618 struct intel_renderbuffer *idrb = NULL;
619 GLuint value;
620 struct i830_hw_state *state = &i830->state;
621 uint32_t draw_x, draw_y;
622
623 if (state->draw_region != color_regions[0]) {
624 intel_region_reference(&state->draw_region, color_regions[0]);
625 }
626 if (state->depth_region != depth_region) {
627 intel_region_reference(&state->depth_region, depth_region);
628 }
629
630 /*
631 * Set stride/cpp values
632 */
633 i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_CBUFADDR0],
634 color_regions[0], BUF_3D_ID_COLOR_BACK);
635
636 i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_DBUFADDR0],
637 depth_region, BUF_3D_ID_DEPTH);
638
639 /*
640 * Compute/set I830_DESTREG_DV1 value
641 */
642 value = (DSTORG_HORT_BIAS(0x8) | /* .5 */
643 DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */
644
645 if (irb != NULL) {
646 value |= i830_render_target_format_for_mesa_format[intel_rb_format(irb)];
647 }
648
649 if (depth_region && depth_region->cpp == 4) {
650 value |= DEPTH_FRMT_24_FIXED_8_OTHER;
651 }
652 else {
653 value |= DEPTH_FRMT_16_FIXED;
654 }
655 state->Buffer[I830_DESTREG_DV1] = value;
656
657 drb = ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
658 if (!drb)
659 drb = ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
660
661 if (drb)
662 idrb = intel_renderbuffer(drb);
663
664 /* We set up the drawing rectangle to be offset into the color
665 * region's location in the miptree. If it doesn't match with
666 * depth's offsets, we can't render to it.
667 *
668 * (Well, not actually true -- the hw grew a bit to let depth's
669 * offset get forced to 0,0. We may want to use that if people are
670 * hitting that case. Also, some configurations may be supportable
671 * by tweaking the start offset of the buffers around, which we
672 * can't do in general due to tiling)
673 */
674 FALLBACK(intel, I830_FALLBACK_DRAW_OFFSET,
675 idrb && irb && (idrb->draw_x != irb->draw_x ||
676 idrb->draw_y != irb->draw_y));
677
678 if (irb) {
679 draw_x = irb->draw_x;
680 draw_y = irb->draw_y;
681 } else if (idrb) {
682 draw_x = idrb->draw_x;
683 draw_y = idrb->draw_y;
684 } else {
685 draw_x = 0;
686 draw_y = 0;
687 }
688
689 state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
690 state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
691 state->Buffer[I830_DESTREG_DRAWRECT2] = (draw_y << 16) | draw_x;
692 state->Buffer[I830_DESTREG_DRAWRECT3] =
693 ((ctx->DrawBuffer->Width + draw_x - 1) & 0xffff) |
694 ((ctx->DrawBuffer->Height + draw_y - 1) << 16);
695 state->Buffer[I830_DESTREG_DRAWRECT4] = (draw_y << 16) | draw_x;
696 state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP;
697
698 I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
699 }
700
701 /**
702 * Update the hardware state for drawing into a window or framebuffer object.
703 *
704 * Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other
705 * places within the driver.
706 *
707 * Basically, this needs to be called any time the current framebuffer
708 * changes, the renderbuffers change, or we need to draw into different
709 * color buffers.
710 */
711 static void
712 i830_update_draw_buffer(struct intel_context *intel)
713 {
714 struct gl_context *ctx = &intel->ctx;
715 struct gl_framebuffer *fb = ctx->DrawBuffer;
716 struct intel_region *colorRegions[MAX_DRAW_BUFFERS], *depthRegion = NULL;
717 struct intel_renderbuffer *irbDepth = NULL, *irbStencil = NULL;
718
719 if (!fb) {
720 /* this can happen during the initial context initialization */
721 return;
722 }
723
724 irbDepth = intel_get_renderbuffer(fb, BUFFER_DEPTH);
725 irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL);
726
727 /* Do this here, not core Mesa, since this function is called from
728 * many places within the driver.
729 */
730 if (ctx->NewState & _NEW_BUFFERS) {
731 /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
732 _mesa_update_framebuffer(ctx);
733 /* this updates the DrawBuffer's Width/Height if it's a FBO */
734 _mesa_update_draw_buffer_bounds(ctx);
735 }
736
737 if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
738 /* this may occur when we're called by glBindFrameBuffer() during
739 * the process of someone setting up renderbuffers, etc.
740 */
741 /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
742 return;
743 }
744
745 /* How many color buffers are we drawing into?
746 *
747 * If there are zero buffers or the buffer is too big, don't configure any
748 * regions for hardware drawing. We'll fallback to software below. Not
749 * having regions set makes some of the software fallback paths faster.
750 */
751 if ((fb->Width > ctx->Const.MaxRenderbufferSize)
752 || (fb->Height > ctx->Const.MaxRenderbufferSize)
753 || (fb->_NumColorDrawBuffers == 0)) {
754 /* writing to 0 */
755 colorRegions[0] = NULL;
756 }
757 else if (fb->_NumColorDrawBuffers > 1) {
758 int i;
759 struct intel_renderbuffer *irb;
760
761 for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
762 irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]);
763 colorRegions[i] = (irb && irb->mt) ? irb->mt->region : NULL;
764 }
765 }
766 else {
767 /* Get the intel_renderbuffer for the single colorbuffer we're drawing
768 * into.
769 */
770 if (_mesa_is_winsys_fbo(fb)) {
771 /* drawing to window system buffer */
772 if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT)
773 colorRegions[0] = intel_get_rb_region(fb, BUFFER_FRONT_LEFT);
774 else
775 colorRegions[0] = intel_get_rb_region(fb, BUFFER_BACK_LEFT);
776 }
777 else {
778 /* drawing to user-created FBO */
779 struct intel_renderbuffer *irb;
780 irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]);
781 colorRegions[0] = (irb && irb->mt->region) ? irb->mt->region : NULL;
782 }
783 }
784
785 if (!colorRegions[0]) {
786 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
787 }
788 else {
789 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, false);
790 }
791
792 /* Check for depth fallback. */
793 if (irbDepth && irbDepth->mt) {
794 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
795 depthRegion = irbDepth->mt->region;
796 } else if (irbDepth && !irbDepth->mt) {
797 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, true);
798 depthRegion = NULL;
799 } else { /* !irbDepth */
800 /* No fallback is needed because there is no depth buffer. */
801 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
802 depthRegion = NULL;
803 }
804
805 /* Check for stencil fallback. */
806 if (irbStencil && irbStencil->mt) {
807 assert(intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24);
808 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
809 } else if (irbStencil && !irbStencil->mt) {
810 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true);
811 } else { /* !irbStencil */
812 /* No fallback is needed because there is no stencil buffer. */
813 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
814 }
815
816 /* If we have a (packed) stencil buffer attached but no depth buffer,
817 * we still need to set up the shared depth/stencil state so we can use it.
818 */
819 if (depthRegion == NULL && irbStencil && irbStencil->mt
820 && intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24) {
821 depthRegion = irbStencil->mt->region;
822 }
823
824 /*
825 * Update depth and stencil test state
826 */
827 ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
828 ctx->Driver.Enable(ctx, GL_STENCIL_TEST,
829 (ctx->Stencil.Enabled && fb->Visual.stencilBits > 0));
830
831 intel->vtbl.set_draw_region(intel, colorRegions, depthRegion,
832 fb->_NumColorDrawBuffers);
833 intel->NewGLState |= _NEW_BUFFERS;
834
835 /* Set state we know depends on drawable parameters:
836 */
837 intelCalcViewport(ctx);
838 ctx->Driver.Scissor(ctx);
839
840 /* Update culling direction which changes depending on the
841 * orientation of the buffer:
842 */
843 ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace);
844 }
845
846 /* This isn't really handled at the moment.
847 */
848 static void
849 i830_new_batch(struct intel_context *intel)
850 {
851 struct i830_context *i830 = i830_context(&intel->ctx);
852 i830->state.emitted = 0;
853 }
854
855 static void
856 i830_assert_not_dirty( struct intel_context *intel )
857 {
858 struct i830_context *i830 = i830_context(&intel->ctx);
859 assert(!get_dirty(&i830->state));
860 (void) i830;
861 }
862
863 static void
864 i830_invalidate_state(struct intel_context *intel, GLuint new_state)
865 {
866 struct gl_context *ctx = &intel->ctx;
867
868 _swsetup_InvalidateState(ctx, new_state);
869 _tnl_InvalidateState(ctx, new_state);
870 _tnl_invalidate_vertex_state(ctx, new_state);
871
872 if (new_state & _NEW_LIGHT)
873 i830_update_provoking_vertex(&intel->ctx);
874 }
875
876 void
877 i830InitVtbl(struct i830_context *i830)
878 {
879 i830->intel.vtbl.check_vertex_size = i830_check_vertex_size;
880 i830->intel.vtbl.destroy = i830_destroy_context;
881 i830->intel.vtbl.emit_state = i830_emit_state;
882 i830->intel.vtbl.new_batch = i830_new_batch;
883 i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state;
884 i830->intel.vtbl.set_draw_region = i830_set_draw_region;
885 i830->intel.vtbl.update_draw_buffer = i830_update_draw_buffer;
886 i830->intel.vtbl.update_texture_state = i830UpdateTextureState;
887 i830->intel.vtbl.render_start = i830_render_start;
888 i830->intel.vtbl.render_prevalidate = i830_render_prevalidate;
889 i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty;
890 i830->intel.vtbl.finish_batch = intel_finish_vb;
891 i830->intel.vtbl.invalidate_state = i830_invalidate_state;
892 i830->intel.vtbl.render_target_supported = i830_render_target_supported;
893 }