src/mesa/drivers/dri/i915/i915_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 #include "main/glheader.h"
  31 #include "main/mtypes.h"
  32 #include "main/macros.h"
  33 #include "main/renderbuffer.h"
  34 #include "main/framebuffer.h"
  35
  36 #include "tnl/tnl.h"
  37 #include "tnl/t_context.h"
  38 #include "tnl/t_vertex.h"
  39 #include "swrast_setup/swrast_setup.h"
  40
  41 #include "intel_batchbuffer.h"
  42 #include "intel_mipmap_tree.h"
  43 #include "intel_regions.h"
  44 #include "intel_tris.h"
  45 #include "intel_fbo.h"
  46 #include "intel_buffers.h"
  47
  48 #include "i915_reg.h"
  49 #include "i915_context.h"
  50
  51 static void
  52 i915_render_prevalidate(struct intel_context *intel)
  53 {
  54    struct i915_context *i915 = i915_context(&intel->ctx);
  55
  56    i915ValidateFragmentProgram(i915);
  57 }
  58
  59 static void
  60 i915_render_start(struct intel_context *intel)
  61 {
  62    intel_prepare_render(intel);
  63 }
  64
  65
  66 static void
  67 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
  68 {
  69    struct i915_context *i915 = i915_context(&intel->ctx);
  70    GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
  71
  72    st1 &= ~ST1_ENABLE;
  73
  74    switch (rprim) {
  75    case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
  76    case GL_TRIANGLES:
  77       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
  78          st1 |= ST1_ENABLE;
  79       break;
  80    case GL_LINES:
  81    case GL_POINTS:
  82    default:
  83       break;
  84    }
  85
  86    i915->intel.reduced_primitive = rprim;
  87
  88    if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
  89       INTEL_FIREVERTICES(intel);
  90
  91       I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
  92       i915->state.Stipple[I915_STPREG_ST1] = st1;
  93    }
  94 }
  95
  96
  97 /* Pull apart the vertex format registers and figure out how large a
  98  * vertex is supposed to be.
  99  */
 100 static bool
 101 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
 102 {
 103    struct i915_context *i915 = i915_context(&intel->ctx);
 104    int lis2 = i915->state.Ctx[I915_CTXREG_LIS2];
 105    int lis4 = i915->state.Ctx[I915_CTXREG_LIS4];
 106    int i, sz = 0;
 107
 108    switch (lis4 & S4_VFMT_XYZW_MASK) {
 109    case S4_VFMT_XY:
 110       sz = 2;
 111       break;
 112    case S4_VFMT_XYZ:
 113       sz = 3;
 114       break;
 115    case S4_VFMT_XYW:
 116       sz = 3;
 117       break;
 118    case S4_VFMT_XYZW:
 119       sz = 4;
 120       break;
 121    default:
 122       fprintf(stderr, "no xyzw specified\n");
 123       return 0;
 124    }
 125
 126    if (lis4 & S4_VFMT_SPEC_FOG)
 127       sz++;
 128    if (lis4 & S4_VFMT_COLOR)
 129       sz++;
 130    if (lis4 & S4_VFMT_DEPTH_OFFSET)
 131       sz++;
 132    if (lis4 & S4_VFMT_POINT_WIDTH)
 133       sz++;
 134    if (lis4 & S4_VFMT_FOG_PARAM)
 135       sz++;
 136
 137    for (i = 0; i < 8; i++) {
 138       switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
 139       case TEXCOORDFMT_2D:
 140          sz += 2;
 141          break;
 142       case TEXCOORDFMT_3D:
 143          sz += 3;
 144          break;
 145       case TEXCOORDFMT_4D:
 146          sz += 4;
 147          break;
 148       case TEXCOORDFMT_1D:
 149          sz += 1;
 150          break;
 151       case TEXCOORDFMT_2D_16:
 152          sz += 1;
 153          break;
 154       case TEXCOORDFMT_4D_16:
 155          sz += 2;
 156          break;
 157       case TEXCOORDFMT_NOT_PRESENT:
 158          break;
 159       default:
 160          fprintf(stderr, "bad texcoord fmt %d\n", i);
 161          return false;
 162       }
 163       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
 164    }
 165
 166    if (sz != expected)
 167       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 168
 169    return sz == expected;
 170 }
 171
 172
 173 static void
 174 i915_emit_invarient_state(struct intel_context *intel)
 175 {
 176    BATCH_LOCALS;
 177
 178    BEGIN_BATCH(15);
 179
 180    OUT_BATCH(_3DSTATE_AA_CMD |
 181              AA_LINE_ECAAR_WIDTH_ENABLE |
 182              AA_LINE_ECAAR_WIDTH_1_0 |
 183              AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
 184
 185    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 186    OUT_BATCH(0);
 187
 188    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 189    OUT_BATCH(0);
 190
 191    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 192    OUT_BATCH(0);
 193
 194    /* Don't support texture crossbar yet */
 195    OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
 196              CSB_TCB(0, 0) |
 197              CSB_TCB(1, 1) |
 198              CSB_TCB(2, 2) |
 199              CSB_TCB(3, 3) |
 200              CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
 201
 202    OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
 203    OUT_BATCH(0);
 204    OUT_BATCH(0);
 205
 206    /* XXX: Use this */
 207    OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
 208
 209    OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 210
 211    OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);       /* disable indirect state */
 212    OUT_BATCH(0);
 213
 214    ADVANCE_BATCH();
 215 }
 216
 217
 218 #define emit(intel, state, size )                    \
 219    intel_batchbuffer_data(intel, state, size)
 220
 221 static GLuint
 222 get_dirty(struct i915_hw_state *state)
 223 {
 224    GLuint dirty;
 225
 226    /* Workaround the multitex hang - if one texture unit state is
 227     * modified, emit all texture units.
 228     */
 229    dirty = state->active & ~state->emitted;
 230    if (dirty & I915_UPLOAD_TEX_ALL)
 231       state->emitted &= ~I915_UPLOAD_TEX_ALL;
 232    dirty = state->active & ~state->emitted;
 233    return dirty;
 234 }
 235
 236
 237 static GLuint
 238 get_state_size(struct i915_hw_state *state)
 239 {
 240    GLuint dirty = get_dirty(state);
 241    GLuint i;
 242    GLuint sz = 0;
 243
 244    if (dirty & I915_UPLOAD_INVARIENT)
 245       sz += 30 * 4;
 246
 247    if (dirty & I915_UPLOAD_RASTER_RULES)
 248       sz += sizeof(state->RasterRules);
 249
 250    if (dirty & I915_UPLOAD_CTX)
 251       sz += sizeof(state->Ctx);
 252
 253    if (dirty & I915_UPLOAD_BLEND)
 254       sz += sizeof(state->Blend);
 255
 256    if (dirty & I915_UPLOAD_BUFFERS)
 257       sz += sizeof(state->Buffer);
 258
 259    if (dirty & I915_UPLOAD_STIPPLE)
 260       sz += sizeof(state->Stipple);
 261
 262    if (dirty & I915_UPLOAD_TEX_ALL) {
 263       int nr = 0;
 264       for (i = 0; i < I915_TEX_UNITS; i++)
 265          if (dirty & I915_UPLOAD_TEX(i))
 266             nr++;
 267
 268       sz += (2 + nr * 3) * sizeof(GLuint) * 2;
 269    }
 270
 271    if (dirty & I915_UPLOAD_CONSTANTS)
 272       sz += state->ConstantSize * sizeof(GLuint);
 273
 274    if (dirty & I915_UPLOAD_PROGRAM)
 275       sz += state->ProgramSize * sizeof(GLuint);
 276
 277    return sz;
 278 }
 279
 280 /* Push the state into the sarea and/or texture memory.
 281  */
 282 static void
 283 i915_emit_state(struct intel_context *intel)
 284 {
 285    struct i915_context *i915 = i915_context(&intel->ctx);
 286    struct i915_hw_state *state = &i915->state;
 287    int i, count, aper_count;
 288    GLuint dirty;
 289    drm_intel_bo *aper_array[3 + I915_TEX_UNITS];
 290    GET_CURRENT_CONTEXT(ctx);
 291    BATCH_LOCALS;
 292
 293    /* We don't hold the lock at this point, so want to make sure that
 294     * there won't be a buffer wrap between the state emits and the primitive
 295     * emit header.
 296     *
 297     * It might be better to talk about explicit places where
 298     * scheduling is allowed, rather than assume that it is whenever a
 299     * batchbuffer fills up.
 300     */
 301    intel_batchbuffer_require_space(intel,
 302                                    get_state_size(state) +
 303                                    INTEL_PRIM_EMIT_SIZE);
 304    count = 0;
 305  again:
 306    if (intel->batch.bo == NULL) {
 307       _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
 308       assert(0);
 309    }
 310    aper_count = 0;
 311    dirty = get_dirty(state);
 312
 313    aper_array[aper_count++] = intel->batch.bo;
 314    if (dirty & I915_UPLOAD_BUFFERS) {
 315       if (state->draw_region)
 316          aper_array[aper_count++] = state->draw_region->bo;
 317       if (state->depth_region)
 318          aper_array[aper_count++] = state->depth_region->bo;
 319    }
 320
 321    if (dirty & I915_UPLOAD_TEX_ALL) {
 322       for (i = 0; i < I915_TEX_UNITS; i++) {
 323          if (dirty & I915_UPLOAD_TEX(i)) {
 324             if (state->tex_buffer[i]) {
 325                aper_array[aper_count++] = state->tex_buffer[i];
 326             }
 327          }
 328       }
 329    }
 330
 331    if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
 332        if (count == 0) {
 333            count++;
 334            intel_batchbuffer_flush(intel);
 335            goto again;
 336        } else {
 337            _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
 338            assert(0);
 339        }
 340    }
 341
 342    /* work out list of buffers to emit */
 343
 344    /* Do this here as we may have flushed the batchbuffer above,
 345     * causing more state to be dirty!
 346     */
 347    dirty = get_dirty(state);
 348    state->emitted |= dirty;
 349    assert(get_dirty(state) == 0);
 350
 351    if (INTEL_DEBUG & DEBUG_STATE)
 352       fprintf(stderr, "%s dirty: %x\n", __func__, dirty);
 353
 354    if (dirty & I915_UPLOAD_INVARIENT) {
 355       if (INTEL_DEBUG & DEBUG_STATE)
 356          fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
 357       i915_emit_invarient_state(intel);
 358    }
 359
 360    if (dirty & I915_UPLOAD_RASTER_RULES) {
 361       if (INTEL_DEBUG & DEBUG_STATE)
 362          fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
 363       emit(intel, state->RasterRules, sizeof(state->RasterRules));
 364    }
 365
 366    if (dirty & I915_UPLOAD_CTX) {
 367       if (INTEL_DEBUG & DEBUG_STATE)
 368          fprintf(stderr, "I915_UPLOAD_CTX:\n");
 369
 370       emit(intel, state->Ctx, sizeof(state->Ctx));
 371    }
 372
 373    if (dirty & I915_UPLOAD_BLEND) {
 374       if (INTEL_DEBUG & DEBUG_STATE)
 375          fprintf(stderr, "I915_UPLOAD_BLEND:\n");
 376
 377       emit(intel, state->Blend, sizeof(state->Blend));
 378    }
 379
 380    if (dirty & I915_UPLOAD_BUFFERS) {
 381       GLuint count;
 382
 383       if (INTEL_DEBUG & DEBUG_STATE)
 384          fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
 385
 386       count = 17;
 387       if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
 388          count++;
 389
 390       BEGIN_BATCH(count);
 391       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
 392       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
 393       if (state->draw_region) {
 394          OUT_RELOC(state->draw_region->bo,
 395                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 396       } else {
 397          OUT_BATCH(0);
 398       }
 399
 400       OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
 401       OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
 402       if (state->depth_region) {
 403          OUT_RELOC(state->depth_region->bo,
 404                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 405       } else {
 406          OUT_BATCH(0);
 407       }
 408
 409       OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
 410       OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
 411       OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
 412       OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
 413       OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
 414       OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
 415
 416       if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
 417          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
 418       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
 419       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
 420       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
 421       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
 422       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
 423
 424       ADVANCE_BATCH();
 425    }
 426
 427    if (dirty & I915_UPLOAD_STIPPLE) {
 428       if (INTEL_DEBUG & DEBUG_STATE)
 429          fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
 430       emit(intel, state->Stipple, sizeof(state->Stipple));
 431    }
 432
 433    /* Combine all the dirty texture state into a single command to
 434     * avoid lockups on I915 hardware.
 435     */
 436    if (dirty & I915_UPLOAD_TEX_ALL) {
 437       int nr = 0;
 438       GLuint unwind;
 439
 440       for (i = 0; i < I915_TEX_UNITS; i++)
 441          if (dirty & I915_UPLOAD_TEX(i))
 442             nr++;
 443
 444       BEGIN_BATCH(2 + nr * 3);
 445       OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
 446       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 447       for (i = 0; i < I915_TEX_UNITS; i++)
 448          if (dirty & I915_UPLOAD_TEX(i)) {
 449             OUT_RELOC(state->tex_buffer[i],
 450                       I915_GEM_DOMAIN_SAMPLER, 0,
 451                       state->tex_offset[i]);
 452
 453             OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
 454             OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
 455          }
 456       ADVANCE_BATCH();
 457
 458       unwind = intel->batch.used;
 459       BEGIN_BATCH(2 + nr * 3);
 460       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
 461       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 462       for (i = 0; i < I915_TEX_UNITS; i++)
 463          if (dirty & I915_UPLOAD_TEX(i)) {
 464             OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
 465             OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
 466             OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
 467          }
 468       ADVANCE_BATCH();
 469       if (i915->last_sampler &&
 470           memcmp(intel->batch.map + i915->last_sampler,
 471                  intel->batch.map + unwind,
 472                  (2 + nr*3)*sizeof(int)) == 0)
 473           intel->batch.used = unwind;
 474       else
 475           i915->last_sampler = unwind;
 476    }
 477
 478    if (dirty & I915_UPLOAD_CONSTANTS) {
 479       if (INTEL_DEBUG & DEBUG_STATE)
 480          fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
 481       emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
 482    }
 483
 484    if (dirty & I915_UPLOAD_PROGRAM) {
 485       if (state->ProgramSize) {
 486          if (INTEL_DEBUG & DEBUG_STATE)
 487             fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
 488
 489          assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
 490
 491          emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
 492          if (INTEL_DEBUG & DEBUG_STATE)
 493             i915_disassemble_program(state->Program, state->ProgramSize);
 494       }
 495    }
 496
 497    assert(get_dirty(state) == 0);
 498 }
 499
 500 static void
 501 i915_destroy_context(struct intel_context *intel)
 502 {
 503    GLuint i;
 504    struct i915_context *i915 = i915_context(&intel->ctx);
 505
 506    intel_region_release(&i915->state.draw_region);
 507    intel_region_release(&i915->state.depth_region);
 508
 509    for (i = 0; i < I915_TEX_UNITS; i++) {
 510       if (i915->state.tex_buffer[i] != NULL) {
 511          drm_intel_bo_unreference(i915->state.tex_buffer[i]);
 512          i915->state.tex_buffer[i] = NULL;
 513       }
 514    }
 515
 516    _tnl_free_vertices(&intel->ctx);
 517 }
 518
 519 void
 520 i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
 521                              uint32_t buffer_id)
 522 {
 523    state[0] = _3DSTATE_BUF_INFO_CMD;
 524    state[1] = buffer_id;
 525
 526    if (region != NULL) {
 527       state[1] |= BUF_3D_PITCH(region->pitch);
 528
 529       if (region->tiling != I915_TILING_NONE) {
 530          state[1] |= BUF_3D_TILED_SURFACE;
 531          if (region->tiling == I915_TILING_Y)
 532             state[1] |= BUF_3D_TILE_WALK_Y;
 533       }
 534    } else {
 535       /* Fill in a default pitch, since 0 is invalid.  We'll be
 536        * setting the buffer offset to 0 and not referencing the
 537        * buffer, so the pitch could really be any valid value.
 538        */
 539       state[1] |= BUF_3D_PITCH(4096);
 540    }
 541 }
 542
 543 static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
 544 {
 545    [MESA_FORMAT_B8G8R8A8_UNORM] = DV_PF_8888,
 546    [MESA_FORMAT_B8G8R8X8_UNORM] = DV_PF_8888,
 547    [MESA_FORMAT_B5G6R5_UNORM] = DV_PF_565 | DITHER_FULL_ALWAYS,
 548    [MESA_FORMAT_B5G5R5A1_UNORM] = DV_PF_1555 | DITHER_FULL_ALWAYS,
 549    [MESA_FORMAT_B4G4R4A4_UNORM] = DV_PF_4444 | DITHER_FULL_ALWAYS,
 550 };
 551
 552 static bool
 553 i915_render_target_supported(struct intel_context *intel,
 554                              struct gl_renderbuffer *rb)
 555 {
 556    mesa_format format = rb->Format;
 557
 558    if (format == MESA_FORMAT_Z24_UNORM_S8_UINT ||
 559        format == MESA_FORMAT_Z24_UNORM_X8_UINT ||
 560        format == MESA_FORMAT_Z_UNORM16) {
 561       return true;
 562    }
 563
 564    return i915_render_target_format_for_mesa_format[format] != 0;
 565 }
 566
 567 static void
 568 i915_set_draw_region(struct intel_context *intel,
 569                      struct intel_region *color_regions[],
 570                      struct intel_region *depth_region,
 571                      GLuint num_regions)
 572 {
 573    struct i915_context *i915 = i915_context(&intel->ctx);
 574    struct gl_context *ctx = &intel->ctx;
 575    struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
 576    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 577    struct gl_renderbuffer *drb;
 578    struct intel_renderbuffer *idrb = NULL;
 579    GLuint value;
 580    struct i915_hw_state *state = &i915->state;
 581    uint32_t draw_x, draw_y, draw_offset;
 582
 583    if (state->draw_region != color_regions[0]) {
 584       intel_region_reference(&state->draw_region, color_regions[0]);
 585    }
 586    if (state->depth_region != depth_region) {
 587       intel_region_reference(&state->depth_region, depth_region);
 588    }
 589
 590    /*
 591     * Set stride/cpp values
 592     */
 593    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
 594                                 color_regions[0], BUF_3D_ID_COLOR_BACK);
 595
 596    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
 597                                 depth_region, BUF_3D_ID_DEPTH);
 598
 599    /*
 600     * Compute/set I915_DESTREG_DV1 value
 601     */
 602    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
 603             DSTORG_VERT_BIAS(0x8) |     /* .5 */
 604             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
 605    if (irb != NULL) {
 606       value |= i915_render_target_format_for_mesa_format[intel_rb_format(irb)];
 607    } else {
 608       value |= DV_PF_8888;
 609    }
 610
 611    if (depth_region && depth_region->cpp == 4) {
 612       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
 613    }
 614    else {
 615       value |= DEPTH_FRMT_16_FIXED;
 616    }
 617    state->Buffer[I915_DESTREG_DV1] = value;
 618
 619    drb = ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
 620    if (!drb)
 621       drb = ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
 622
 623    if (drb)
 624       idrb = intel_renderbuffer(drb);
 625
 626    /* We set up the drawing rectangle to be offset into the color
 627     * region's location in the miptree.  If it doesn't match with
 628     * depth's offsets, we can't render to it.
 629     *
 630     * (Well, not actually true -- the hw grew a bit to let depth's
 631     * offset get forced to 0,0.  We may want to use that if people are
 632     * hitting that case.  Also, some configurations may be supportable
 633     * by tweaking the start offset of the buffers around, which we
 634     * can't do in general due to tiling)
 635     */
 636    FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
 637             idrb && irb && (idrb->draw_x != irb->draw_x ||
 638                             idrb->draw_y != irb->draw_y));
 639
 640    if (irb) {
 641       draw_x = irb->draw_x;
 642       draw_y = irb->draw_y;
 643    } else if (idrb) {
 644       draw_x = idrb->draw_x;
 645       draw_y = idrb->draw_y;
 646    } else {
 647       draw_x = 0;
 648       draw_y = 0;
 649    }
 650
 651    draw_offset = (draw_y << 16) | draw_x;
 652
 653    FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
 654             (ctx->DrawBuffer->Width + draw_x > 2048) ||
 655             (ctx->DrawBuffer->Height + draw_y > 2048));
 656    /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
 657    if (draw_offset != i915->last_draw_offset) {
 658       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE;
 659       i915->last_draw_offset = draw_offset;
 660    } else
 661       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
 662
 663    state->Buffer[I915_DESTREG_DRAWRECT1] = _3DSTATE_DRAWRECT_INFO;
 664    state->Buffer[I915_DESTREG_DRAWRECT2] = 0;
 665    state->Buffer[I915_DESTREG_DRAWRECT3] = draw_offset;
 666    state->Buffer[I915_DESTREG_DRAWRECT4] =
 667       ((ctx->DrawBuffer->Width + draw_x - 1) & 0xffff) |
 668       ((ctx->DrawBuffer->Height + draw_y - 1) << 16);
 669    state->Buffer[I915_DESTREG_DRAWRECT5] = draw_offset;
 670
 671    I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
 672 }
 673
 674 static void
 675 i915_update_color_write_enable(struct i915_context *i915, bool enable)
 676 {
 677    uint32_t dw = i915->state.Ctx[I915_CTXREG_LIS6];
 678    if (enable)
 679       dw |= S6_COLOR_WRITE_ENABLE;
 680    else
 681       dw &= ~S6_COLOR_WRITE_ENABLE;
 682    if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
 683       I915_STATECHANGE(i915, I915_UPLOAD_CTX);
 684       i915->state.Ctx[I915_CTXREG_LIS6] = dw;
 685    }
 686 }
 687
 688 /**
 689  * Update the hardware state for drawing into a window or framebuffer object.
 690  *
 691  * Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other
 692  * places within the driver.
 693  *
 694  * Basically, this needs to be called any time the current framebuffer
 695  * changes, the renderbuffers change, or we need to draw into different
 696  * color buffers.
 697  */
 698 static void
 699 i915_update_draw_buffer(struct intel_context *intel)
 700 {
 701    struct i915_context *i915 = (struct i915_context *)intel;
 702    struct gl_context *ctx = &intel->ctx;
 703    struct gl_framebuffer *fb = ctx->DrawBuffer;
 704    struct intel_region *colorRegion = NULL, *depthRegion = NULL;
 705    struct intel_renderbuffer *irbDepth = NULL, *irbStencil = NULL;
 706
 707    if (!fb) {
 708       /* this can happen during the initial context initialization */
 709       return;
 710    }
 711
 712    irbDepth = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 713    irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 714
 715    /* Do this here, not core Mesa, since this function is called from
 716     * many places within the driver.
 717     */
 718    if (ctx->NewState & _NEW_BUFFERS) {
 719       /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
 720       _mesa_update_framebuffer(ctx, ctx->ReadBuffer, ctx->DrawBuffer);
 721       /* this updates the DrawBuffer's Width/Height if it's a FBO */
 722       _mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer);
 723    }
 724
 725    if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
 726       /* this may occur when we're called by glBindFrameBuffer() during
 727        * the process of someone setting up renderbuffers, etc.
 728        */
 729       /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
 730       return;
 731    }
 732
 733    /* How many color buffers are we drawing into?
 734     *
 735     * If there is more than one drawbuffer (GL_FRONT_AND_BACK), or the
 736     * drawbuffers are too big, we have to fallback to software.
 737     */
 738    if ((fb->Width > ctx->Const.MaxRenderbufferSize)
 739        || (fb->Height > ctx->Const.MaxRenderbufferSize)) {
 740       FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
 741    } else if (fb->_NumColorDrawBuffers > 1) {
 742       FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
 743    } else {
 744       struct intel_renderbuffer *irb;
 745       irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]);
 746       colorRegion = (irb && irb->mt) ? irb->mt->region : NULL;
 747       FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, false);
 748    }
 749
 750    /* Check for depth fallback. */
 751    if (irbDepth && irbDepth->mt) {
 752       FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
 753       depthRegion = irbDepth->mt->region;
 754    } else if (irbDepth && !irbDepth->mt) {
 755       FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, true);
 756       depthRegion = NULL;
 757    } else { /* !irbDepth */
 758       /* No fallback is needed because there is no depth buffer. */
 759       FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
 760       depthRegion = NULL;
 761    }
 762
 763    /* Check for stencil fallback. */
 764    if (irbStencil && irbStencil->mt) {
 765       assert(intel_rb_format(irbStencil) == MESA_FORMAT_Z24_UNORM_S8_UINT);
 766       FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
 767    } else if (irbStencil && !irbStencil->mt) {
 768       FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true);
 769    } else { /* !irbStencil */
 770       /* No fallback is needed because there is no stencil buffer. */
 771       FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
 772    }
 773
 774    /* If we have a (packed) stencil buffer attached but no depth buffer,
 775     * we still need to set up the shared depth/stencil state so we can use it.
 776     */
 777    if (depthRegion == NULL && irbStencil && irbStencil->mt
 778        && intel_rb_format(irbStencil) == MESA_FORMAT_Z24_UNORM_S8_UINT) {
 779       depthRegion = irbStencil->mt->region;
 780    }
 781
 782    /*
 783     * Update depth and stencil test state
 784     */
 785    ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
 786    ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled);
 787
 788    i915_update_color_write_enable(i915, colorRegion != NULL);
 789
 790    intel->vtbl.set_draw_region(intel, &colorRegion, depthRegion,
 791                                fb->_NumColorDrawBuffers);
 792    intel->NewGLState |= _NEW_BUFFERS;
 793
 794    /* Set state we know depends on drawable parameters:
 795     */
 796    intelCalcViewport(ctx);
 797    ctx->Driver.Scissor(ctx);
 798
 799    /* Update culling direction which changes depending on the
 800     * orientation of the buffer:
 801     */
 802    ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace);
 803 }
 804
 805 static void
 806 i915_new_batch(struct intel_context *intel)
 807 {
 808    struct i915_context *i915 = i915_context(&intel->ctx);
 809
 810    /* Mark all state as needing to be emitted when starting a new batchbuffer.
 811     * Using hardware contexts would be an alternative, but they have some
 812     * difficulties associated with them (physical address requirements).
 813     */
 814    i915->state.emitted = 0;
 815    i915->last_draw_offset = 0;
 816    i915->last_sampler = 0;
 817
 818    i915->current_vb_bo = NULL;
 819    i915->current_vertex_size = 0;
 820 }
 821
 822 static void
 823 i915_assert_not_dirty( struct intel_context *intel )
 824 {
 825    struct i915_context *i915 = i915_context(&intel->ctx);
 826    GLuint dirty = get_dirty(&i915->state);
 827    assert(!dirty);
 828    (void) dirty;
 829 }
 830
 831 static void
 832 i915_invalidate_state(struct intel_context *intel, GLuint new_state)
 833 {
 834    struct gl_context *ctx = &intel->ctx;
 835
 836    _swsetup_InvalidateState(ctx, new_state);
 837    _tnl_InvalidateState(ctx, new_state);
 838    _tnl_invalidate_vertex_state(ctx, new_state);
 839 }
 840
 841 void
 842 i915InitVtbl(struct i915_context *i915)
 843 {
 844    i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
 845    i915->intel.vtbl.destroy = i915_destroy_context;
 846    i915->intel.vtbl.emit_state = i915_emit_state;
 847    i915->intel.vtbl.new_batch = i915_new_batch;
 848    i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
 849    i915->intel.vtbl.render_start = i915_render_start;
 850    i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
 851    i915->intel.vtbl.set_draw_region = i915_set_draw_region;
 852    i915->intel.vtbl.update_draw_buffer = i915_update_draw_buffer;
 853    i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
 854    i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
 855    i915->intel.vtbl.finish_batch = intel_finish_vb;
 856    i915->intel.vtbl.invalidate_state = i915_invalidate_state;
 857    i915->intel.vtbl.render_target_supported = i915_render_target_supported;
 858 }