2 * Copyright © 2015-2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_compiler.h"
25 #include "brw_context.h"
26 #include "compiler/nir/nir.h"
27 #include "main/errors.h"
28 #include "util/debug.h"
31 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
33 struct brw_context
*brw
= (struct brw_context
*)data
;
38 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
39 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
40 MESA_DEBUG_TYPE_OTHER
,
41 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
46 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
48 struct brw_context
*brw
= (struct brw_context
*)data
;
53 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
55 va_copy(args_copy
, args
);
56 vfprintf(stderr
, fmt
, args_copy
);
60 if (brw
->perf_debug
) {
62 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
63 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
64 MESA_DEBUG_TYPE_PERFORMANCE
,
65 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
70 #define COMMON_OPTIONS \
71 /* In order to help allow for better CSE at the NIR level we tell NIR to \
72 * split all ffma instructions during opt_algebraic and we then re-combine \
73 * them as a later step. \
80 .lower_bitfield_extract = true, \
81 .lower_bitfield_insert = true, \
82 .lower_uadd_carry = true, \
83 .lower_usub_borrow = true, \
85 .native_integers = true, \
86 .vertex_id_zero_based = true
88 static const struct nir_shader_compiler_options scalar_nir_options
= {
90 .lower_pack_half_2x16
= true,
91 .lower_pack_snorm_2x16
= true,
92 .lower_pack_snorm_4x8
= true,
93 .lower_pack_unorm_2x16
= true,
94 .lower_pack_unorm_4x8
= true,
95 .lower_unpack_half_2x16
= true,
96 .lower_unpack_snorm_2x16
= true,
97 .lower_unpack_snorm_4x8
= true,
98 .lower_unpack_unorm_2x16
= true,
99 .lower_unpack_unorm_4x8
= true,
102 static const struct nir_shader_compiler_options vector_nir_options
= {
105 /* In the vec4 backend, our dpN instruction replicates its result to all the
106 * components of a vec4. We would like NIR to give us replicated fdot
107 * instructions because it can optimize better for us.
109 .fdot_replicates
= true,
111 .lower_pack_snorm_2x16
= true,
112 .lower_pack_unorm_2x16
= true,
113 .lower_unpack_snorm_2x16
= true,
114 .lower_unpack_unorm_2x16
= true,
115 .lower_extract_byte
= true,
116 .lower_extract_word
= true,
119 struct brw_compiler
*
120 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
)
122 struct brw_compiler
*compiler
= rzalloc(mem_ctx
, struct brw_compiler
);
124 compiler
->devinfo
= devinfo
;
125 compiler
->shader_debug_log
= shader_debug_log_mesa
;
126 compiler
->shader_perf_log
= shader_perf_log_mesa
;
128 brw_fs_alloc_reg_sets(compiler
);
129 brw_vec4_alloc_reg_set(compiler
);
131 compiler
->scalar_stage
[MESA_SHADER_VERTEX
] =
132 devinfo
->gen
>= 8 && !(INTEL_DEBUG
& DEBUG_VEC4VS
);
133 compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
] = false;
134 compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
] =
135 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
136 compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
] =
137 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
138 compiler
->scalar_stage
[MESA_SHADER_FRAGMENT
] = true;
139 compiler
->scalar_stage
[MESA_SHADER_COMPUTE
] = true;
141 /* We want the GLSL compiler to emit code that uses condition codes */
142 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
143 compiler
->glsl_compiler_options
[i
].MaxUnrollIterations
= 32;
144 compiler
->glsl_compiler_options
[i
].MaxIfDepth
=
145 devinfo
->gen
< 6 ? 16 : UINT_MAX
;
147 compiler
->glsl_compiler_options
[i
].EmitCondCodes
= true;
148 compiler
->glsl_compiler_options
[i
].EmitNoNoise
= true;
149 compiler
->glsl_compiler_options
[i
].EmitNoMainReturn
= true;
150 compiler
->glsl_compiler_options
[i
].EmitNoIndirectInput
= true;
151 compiler
->glsl_compiler_options
[i
].EmitNoIndirectUniform
= false;
152 compiler
->glsl_compiler_options
[i
].LowerClipDistance
= true;
154 bool is_scalar
= compiler
->scalar_stage
[i
];
156 compiler
->glsl_compiler_options
[i
].EmitNoIndirectOutput
= is_scalar
;
157 compiler
->glsl_compiler_options
[i
].EmitNoIndirectTemp
= is_scalar
;
158 compiler
->glsl_compiler_options
[i
].OptimizeForAOS
= !is_scalar
;
160 /* !ARB_gpu_shader5 */
161 if (devinfo
->gen
< 7)
162 compiler
->glsl_compiler_options
[i
].EmitNoIndirectSampler
= true;
164 compiler
->glsl_compiler_options
[i
].NirOptions
=
165 is_scalar
? &scalar_nir_options
: &vector_nir_options
;
167 compiler
->glsl_compiler_options
[i
].LowerBufferInterfaceBlocks
= true;
170 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].EmitNoIndirectInput
= false;
171 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_EVAL
].EmitNoIndirectInput
= false;
173 if (compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
])
174 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].EmitNoIndirectInput
= false;
176 compiler
->glsl_compiler_options
[MESA_SHADER_COMPUTE
]
177 .LowerShaderSharedVariables
= true;