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27 #include "brw_device_info.h"
28 #include "main/mtypes.h"
36 struct brw_geometry_program
;
37 union gl_constant_value
;
40 const struct brw_device_info
*devinfo
;
46 * Array of the ra classes for the unaligned contiguous register
52 * Mapping for register-allocated objects in *regs to the first
53 * GRF for that object.
55 uint8_t *ra_reg_to_grf
;
62 * Array of the ra classes for the unaligned contiguous register
63 * block sizes used, indexed by register size.
68 * Mapping from classes to ra_reg ranges. Each of the per-size
69 * classes corresponds to a range of ra_reg nodes. This array stores
70 * those ranges in the form of first ra_reg in each class and the
71 * total number of ra_reg elements in the last array element. This
72 * way the range of the i'th class is given by:
73 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
75 int class_to_ra_reg_range
[17];
78 * Mapping for register-allocated objects in *regs to the first
79 * GRF for that object.
81 uint8_t *ra_reg_to_grf
;
84 * ra class for the aligned pairs we use for PLN, which doesn't
87 int aligned_pairs_class
;
90 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
91 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 bool scalar_stage
[MESA_SHADER_STAGES
];
94 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
98 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
);
102 * Program key structures.
104 * When drawing, we look for the currently bound shaders in the program
105 * cache. This is essentially a hash table lookup, and these are the keys.
107 * Sometimes OpenGL features specified as state need to be simulated via
108 * shader code, due to a mismatch between the API and the hardware. This
109 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
110 * in the program key so it's considered when searching for a program. If
111 * we haven't seen a particular combination before, we have to recompile a
112 * new specialized version.
114 * Shader compilation should not look up state in gl_context directly, but
115 * instead use the copy in the program key. This guarantees recompiles will
121 enum PACKED gen6_gather_sampler_wa
{
122 WA_SIGN
= 1, /* whether we need to sign extend */
123 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
124 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
128 * Sampler information needed by VS, WM, and GS program cache keys.
130 struct brw_sampler_prog_key_data
{
132 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
134 uint16_t swizzles
[MAX_SAMPLERS
];
136 uint32_t gl_clamp_mask
[3];
139 * For RG32F, gather4's channel select is broken.
141 uint32_t gather_channel_quirk_mask
;
144 * Whether this sampler uses the compressed multisample surface layout.
146 uint32_t compressed_multisample_layout_mask
;
149 * Whether this sampler is using 16x multisampling. If so fetching from
150 * this sampler will be handled with a different instruction, ld2dms_w
156 * For Sandybridge, which shader w/a we need for gather quirks.
158 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
162 /** The program key for Vertex Shaders. */
163 struct brw_vs_prog_key
{
164 unsigned program_string_id
;
167 * Per-attribute workaround flags
169 uint8_t gl_attrib_wa_flags
[VERT_ATTRIB_MAX
];
171 bool copy_edgeflag
:1;
173 bool clamp_vertex_color
:1;
176 * How many user clipping planes are being uploaded to the vertex shader as
179 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
182 unsigned nr_userclip_plane_consts
:4;
185 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
186 * are going to be replaced with point coordinates (as a consequence of a
187 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
188 * our SF thread requires exact matching between VS outputs and FS inputs,
189 * these texture coordinates will need to be unconditionally included in
190 * the VUE, even if they aren't written by the vertex shader.
192 uint8_t point_coord_replace
;
194 struct brw_sampler_prog_key_data tex
;
197 /** The program key for Geometry Shaders. */
198 struct brw_gs_prog_key
200 unsigned program_string_id
;
202 struct brw_sampler_prog_key_data tex
;
205 /** The program key for Fragment/Pixel Shaders. */
206 struct brw_wm_prog_key
{
210 bool persample_shading
:1;
212 unsigned nr_color_regions
:5;
213 bool replicate_alpha
:1;
214 bool render_to_fbo
:1;
215 bool clamp_fragment_color
:1;
216 bool compute_pos_offset
:1;
217 bool compute_sample_id
:1;
219 bool high_quality_derivatives
:1;
221 uint16_t drawable_height
;
222 uint64_t input_slots_valid
;
223 unsigned program_string_id
;
224 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
225 float alpha_test_ref
;
227 struct brw_sampler_prog_key_data tex
;
230 struct brw_cs_prog_key
{
231 uint32_t program_string_id
;
232 struct brw_sampler_prog_key_data tex
;
236 * Image metadata structure as laid out in the shader parameter
237 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
238 * able to use them. That's okay because the padding and any unused
239 * entries [most of them except when we're doing untyped surface
240 * access] will be removed by the uniform packing pass.
242 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
243 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
244 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
245 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
246 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
247 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
248 #define BRW_IMAGE_PARAM_SIZE 24
250 struct brw_image_param
{
251 /** Surface binding table index. */
252 uint32_t surface_idx
;
254 /** Offset applied to the X and Y surface coordinates. */
257 /** Surface X, Y and Z dimensions. */
260 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
261 * pixels, vertical slice stride in pixels.
265 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
269 * Right shift to apply for bit 6 address swizzling. Two different
270 * swizzles can be specified and will be applied one after the other. The
271 * resulting address will be:
273 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
274 * (addr >> swizzling[1])))
276 * Use \c 0xff if any of the swizzles is not required.
278 uint32_t swizzling
[2];
281 struct brw_stage_prog_data
{
283 /** size of our binding table. */
287 * surface indices for the various groups of surfaces
289 uint32_t pull_constants_start
;
290 uint32_t texture_start
;
291 uint32_t gather_texture_start
;
295 uint32_t image_start
;
296 uint32_t shader_time_start
;
300 GLuint nr_params
; /**< number of float params/constants */
301 GLuint nr_pull_params
;
302 unsigned nr_image_params
;
304 unsigned curb_read_length
;
305 unsigned total_scratch
;
306 unsigned total_shared
;
309 * Register where the thread expects to find input data from the URB
310 * (typically uniforms, followed by vertex or fragment attributes).
312 unsigned dispatch_grf_start_reg
;
314 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
316 /* Pointers to tracked values (only valid once
317 * _mesa_load_state_parameters has been called at runtime).
319 const union gl_constant_value
**param
;
320 const union gl_constant_value
**pull_param
;
322 /** Image metadata passed to the shader as uniforms. */
323 struct brw_image_param
*image_param
;
326 /* Data about a particular attempt to compile a program. Note that
327 * there can be many of these, each in a different GL state
328 * corresponding to a different brw_wm_prog_key struct, with different
331 struct brw_wm_prog_data
{
332 struct brw_stage_prog_data base
;
334 GLuint num_varying_inputs
;
336 GLuint dispatch_grf_start_reg_16
;
338 GLuint reg_blocks_16
;
342 * surface indices the WM-specific surfaces
344 uint32_t render_target_start
;
348 uint8_t computed_depth_mode
;
349 bool computed_stencil
;
351 bool early_fragment_tests
;
354 bool uses_pos_offset
;
358 uint32_t prog_offset_16
;
361 * Mask of which interpolation modes are required by the fragment shader.
362 * Used in hardware setup on gen6+.
364 uint32_t barycentric_interp_modes
;
367 * Map from gl_varying_slot to the position within the FS setup data
368 * payload where the varying's attribute vertex deltas should be delivered.
369 * For varying slots that are not used by the FS, the value is -1.
371 int urb_setup
[VARYING_SLOT_MAX
];
374 struct brw_cs_prog_data
{
375 struct brw_stage_prog_data base
;
377 GLuint dispatch_grf_start_reg_16
;
378 unsigned local_size
[3];
381 bool uses_num_work_groups
;
382 unsigned local_invocation_id_regs
;
386 * surface indices the CS-specific surfaces
388 uint32_t work_groups_start
;
394 * Enum representing the i965-specific vertex results that don't correspond
395 * exactly to any element of gl_varying_slot. The values of this enum are
396 * assigned such that they don't conflict with gl_varying_slot.
400 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
401 BRW_VARYING_SLOT_PAD
,
403 * Technically this is not a varying but just a placeholder that
404 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
405 * builtin variable to be compiled correctly. see compile_sf_prog() for
408 BRW_VARYING_SLOT_PNTC
,
409 BRW_VARYING_SLOT_COUNT
413 * Data structure recording the relationship between the gl_varying_slot enum
414 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
415 * single octaword within the VUE (128 bits).
417 * Note that each BRW register contains 256 bits (2 octawords), so when
418 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
419 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
420 * in a vertex shader), each register corresponds to a single VUE slot, since
421 * it contains data for two separate vertices.
425 * Bitfield representing all varying slots that are (a) stored in this VUE
426 * map, and (b) actually written by the shader. Does not include any of
427 * the additional varying slots defined in brw_varying_slot.
429 GLbitfield64 slots_valid
;
432 * Is this VUE map for a separate shader pipeline?
434 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
435 * without the linker having a chance to dead code eliminate unused varyings.
437 * This means that we have to use a fixed slot layout, based on the output's
438 * location field, rather than assigning slots in a compact contiguous block.
443 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
444 * not stored in a slot (because they are not written, or because
445 * additional processing is applied before storing them in the VUE), the
448 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
451 * Map from VUE slot to gl_varying_slot value. For slots that do not
452 * directly correspond to a gl_varying_slot, the value comes from
455 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
457 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
460 * Total number of VUE slots in use
465 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
468 * Convert a VUE slot number into a byte offset within the VUE.
470 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
476 * Convert a vertex output (brw_varying_slot) into a byte offset within the
480 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
482 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
485 void brw_compute_vue_map(const struct brw_device_info
*devinfo
,
486 struct brw_vue_map
*vue_map
,
487 GLbitfield64 slots_valid
,
488 bool separate_shader
);
490 enum shader_dispatch_mode
{
491 DISPATCH_MODE_4X1_SINGLE
= 0,
492 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
493 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
494 DISPATCH_MODE_SIMD8
= 3,
498 * @defgroup Tessellator parameter enumerations.
500 * These correspond to the hardware values in 3DSTATE_TE, and are provided
501 * as part of the tessellation evaluation shader.
505 enum brw_tess_partitioning
{
506 BRW_TESS_PARTITIONING_INTEGER
= 0,
507 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
508 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
511 enum brw_tess_output_topology
{
512 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
513 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
514 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
515 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
518 enum brw_tess_domain
{
519 BRW_TESS_DOMAIN_QUAD
= 0,
520 BRW_TESS_DOMAIN_TRI
= 1,
521 BRW_TESS_DOMAIN_ISOLINE
= 2,
525 struct brw_vue_prog_data
{
526 struct brw_stage_prog_data base
;
527 struct brw_vue_map vue_map
;
529 /** Should the hardware deliver input VUE handles for URB pull loads? */
530 bool include_vue_handles
;
532 GLuint urb_read_length
;
535 /* Used for calculating urb partitions. In the VS, this is the size of the
536 * URB entry used for both input and output to the thread. In the GS, this
537 * is the size of the URB entry used for output.
539 GLuint urb_entry_size
;
541 enum shader_dispatch_mode dispatch_mode
;
544 struct brw_vs_prog_data
{
545 struct brw_vue_prog_data base
;
547 GLbitfield64 inputs_read
;
549 unsigned nr_attributes
;
552 bool uses_instanceid
;
555 struct brw_tcs_prog_data
557 struct brw_vue_prog_data base
;
559 /** Number vertices in output patch */
564 struct brw_tes_prog_data
566 struct brw_vue_prog_data base
;
568 enum brw_tess_partitioning partitioning
;
569 enum brw_tess_output_topology output_topology
;
570 enum brw_tess_domain domain
;
573 struct brw_gs_prog_data
575 struct brw_vue_prog_data base
;
578 * Size of an output vertex, measured in HWORDS (32 bytes).
580 unsigned output_vertex_size_hwords
;
582 unsigned output_topology
;
585 * Size of the control data (cut bits or StreamID bits), in hwords (32
586 * bytes). 0 if there is no control data.
588 unsigned control_data_header_size_hwords
;
591 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
592 * if the control data is StreamID bits, or
593 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
594 * Ignored if control_data_header_size is 0.
596 unsigned control_data_format
;
598 bool include_primitive_id
;
601 * The number of vertices emitted, if constant - otherwise -1.
603 int static_vertex_count
;
608 * Gen6 transform feedback enabled flag.
610 bool gen6_xfb_enabled
;
613 * Gen6: Provoking vertex convention for odd-numbered triangles
619 * Gen6: Number of varyings that are output to transform feedback.
621 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
624 * Gen6: Map from the index of a transform feedback binding table entry to the
625 * gl_varying_slot that should be streamed out through that binding table
628 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
631 * Gen6: Map from the index of a transform feedback binding table entry to the
632 * swizzles that should be used when streaming out data through that
633 * binding table entry.
635 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
642 * Compile a vertex shader.
644 * Returns the final assembly and the program's size.
647 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
649 const struct brw_vs_prog_key
*key
,
650 struct brw_vs_prog_data
*prog_data
,
651 const struct nir_shader
*shader
,
652 gl_clip_plane
*clip_planes
,
653 bool use_legacy_snorm_formula
,
654 int shader_time_index
,
655 unsigned *final_assembly_size
,
659 * Compile a vertex shader.
661 * Returns the final assembly and the program's size.
664 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
666 const struct brw_gs_prog_key
*key
,
667 struct brw_gs_prog_data
*prog_data
,
668 const struct nir_shader
*shader
,
669 struct gl_shader_program
*shader_prog
,
670 int shader_time_index
,
671 unsigned *final_assembly_size
,
675 * Compile a fragment shader.
677 * Returns the final assembly and the program's size.
680 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
682 const struct brw_wm_prog_key
*key
,
683 struct brw_wm_prog_data
*prog_data
,
684 const struct nir_shader
*shader
,
685 struct gl_program
*prog
,
686 int shader_time_index8
,
687 int shader_time_index16
,
689 unsigned *final_assembly_size
,
693 * Compile a compute shader.
695 * Returns the final assembly and the program's size.
698 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
700 const struct brw_cs_prog_key
*key
,
701 struct brw_cs_prog_data
*prog_data
,
702 const struct nir_shader
*shader
,
703 int shader_time_index
,
704 unsigned *final_assembly_size
,
708 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*cs_prog_data
,
709 void *buffer
, uint32_t threads
, uint32_t stride
);