2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "main/errors.h"
40 #include "brw_structs.h"
41 #include "brw_pipe_control.h"
42 #include "compiler/brw_compiler.h"
45 #include "blorp/blorp.h"
47 #include <brw_bufmgr.h>
49 #include "dev/gen_debug.h"
50 #include "common/gen_decoder.h"
51 #include "intel_screen.h"
52 #include "intel_tex_obj.h"
59 * URB - uniform resource buffer. A mid-sized buffer which is
60 * partitioned between the fixed function units and used for passing
61 * values (vertices, primitives, constants) between them.
63 * CURBE - constant URB entry. An urb region (entry) used to hold
64 * constant values which the fixed function units can be instructed to
65 * preload into the GRF when spawning a thread.
67 * VUE - vertex URB entry. An urb entry holding a vertex and usually
68 * a vertex header. The header contains control information and
69 * things like primitive type, Begin/end flags and clip codes.
71 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
72 * unit holding rasterization and interpolation parameters.
74 * GRF - general register file. One of several register files
75 * addressable by programmed threads. The inputs (r0, payload, curbe,
76 * urb) of the thread are preloaded to this area before the thread is
77 * spawned. The registers are individually 8 dwords wide and suitable
78 * for general usage. Registers holding thread input values are not
79 * special and may be overwritten.
81 * MRF - message register file. Threads communicate (and terminate)
82 * by sending messages. Message parameters are placed in contiguous
83 * MRF registers. All program output is via these messages. URB
84 * entries are populated by sending a message to the shared URB
85 * function containing the new data, together with a control word,
86 * often an unmodified copy of R0.
88 * R0 - GRF register 0. Typically holds control information used when
89 * sending messages to other threads.
91 * EU or GEN4 EU: The name of the programmable subsystem of the
92 * i965 hardware. Threads are executed by the EU, the registers
93 * described above are part of the EU architecture.
95 * Fixed function units:
97 * CS - Command streamer. Notional first unit, little software
98 * interaction. Holds the URB entries used for constant data, ie the
101 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
102 * this unit is responsible for pulling vertices out of vertex buffers
103 * in vram and injecting them into the processing pipe as VUEs. If
104 * enabled, it first passes them to a VS thread which is a good place
105 * for the driver to implement any active vertex shader.
107 * HS - Hull Shader (Tessellation Control Shader)
109 * TE - Tessellation Engine (Tessellation Primitive Generation)
111 * DS - Domain Shader (Tessellation Evaluation Shader)
113 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
114 * enabled, incoming strips etc are passed to GS threads in individual
115 * line/triangle/point units. The GS thread may perform arbitary
116 * computation and emit whatever primtives with whatever vertices it
117 * chooses. This makes GS an excellent place to implement GL's
118 * unfilled polygon modes, though of course it is capable of much
119 * more. Additionally, GS is used to translate away primitives not
120 * handled by latter units, including Quads and Lineloops.
122 * CS - Clipper. Mesa's clipping algorithms are imported to run on
123 * this unit. The fixed function part performs cliptesting against
124 * the 6 fixed clipplanes and makes descisions on whether or not the
125 * incoming primitive needs to be passed to a thread for clipping.
126 * User clip planes are handled via cooperation with the VS thread.
128 * SF - Strips Fans or Setup: Triangles are prepared for
129 * rasterization. Interpolation coefficients are calculated.
130 * Flatshading and two-side lighting usually performed here.
132 * WM - Windower. Interpolation of vertex attributes performed here.
133 * Fragment shader implemented here. SIMD aspects of EU taken full
134 * advantage of, as pixels are processed in blocks of 16.
136 * CC - Color Calculator. No EU threads associated with this unit.
137 * Handles blending and (presumably) depth and stencil testing.
142 struct brw_vs_prog_key
;
143 struct brw_vue_prog_key
;
144 struct brw_wm_prog_key
;
145 struct brw_wm_prog_data
;
146 struct brw_cs_prog_key
;
147 struct brw_cs_prog_data
;
151 BRW_COMPUTE_PIPELINE
,
158 BRW_CACHE_BLORP_PROG
,
161 BRW_CACHE_FF_GS_PROG
,
171 enum gen9_astc5x5_wa_tex_type
{
172 GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
= 1 << 0,
173 GEN9_ASTC5X5_WA_TEX_TYPE_AUX
= 1 << 1,
177 /* brw_cache_ids must come first - see brw_program_cache.c */
178 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
179 BRW_STATE_FRAGMENT_PROGRAM
,
180 BRW_STATE_GEOMETRY_PROGRAM
,
181 BRW_STATE_TESS_PROGRAMS
,
182 BRW_STATE_VERTEX_PROGRAM
,
183 BRW_STATE_REDUCED_PRIMITIVE
,
184 BRW_STATE_PATCH_PRIMITIVE
,
189 BRW_STATE_BINDING_TABLE_POINTERS
,
192 BRW_STATE_DEFAULT_TESS_LEVELS
,
194 BRW_STATE_INDEX_BUFFER
,
195 BRW_STATE_VS_CONSTBUF
,
196 BRW_STATE_TCS_CONSTBUF
,
197 BRW_STATE_TES_CONSTBUF
,
198 BRW_STATE_GS_CONSTBUF
,
199 BRW_STATE_PROGRAM_CACHE
,
200 BRW_STATE_STATE_BASE_ADDRESS
,
201 BRW_STATE_VUE_MAP_GEOM_OUT
,
202 BRW_STATE_TRANSFORM_FEEDBACK
,
203 BRW_STATE_RASTERIZER_DISCARD
,
205 BRW_STATE_UNIFORM_BUFFER
,
206 BRW_STATE_IMAGE_UNITS
,
207 BRW_STATE_META_IN_PROGRESS
,
208 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
209 BRW_STATE_NUM_SAMPLES
,
210 BRW_STATE_TEXTURE_BUFFER
,
211 BRW_STATE_GEN4_UNIT_STATE
,
215 BRW_STATE_SAMPLER_STATE_TABLE
,
216 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
217 BRW_STATE_COMPUTE_PROGRAM
,
218 BRW_STATE_CS_WORK_GROUPS
,
222 BRW_STATE_VIEWPORT_COUNT
,
223 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
230 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
232 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
233 * When the currently bound shader program differs from the previous draw
234 * call, these will be flagged. They cover brw->{stage}_program and
235 * ctx->{Stage}Program->_Current.
237 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
238 * driver perspective. Even if the same shader is bound at the API level,
239 * we may need to switch between multiple versions of that shader to handle
240 * changes in non-orthagonal state.
242 * Additionally, multiple shader programs may have identical vertex shaders
243 * (for example), or compile down to the same code in the backend. We combine
244 * those into a single program cache entry.
246 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
247 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
249 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
250 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
251 * use the normal state upload paths), but the cache is still used. To avoid
252 * polluting the brw_program_cache code with special cases, we retain the
253 * dirty bit for now. It should eventually be removed.
255 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
256 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
257 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
258 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
259 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
260 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
261 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
262 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
263 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
264 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
265 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
266 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
267 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
268 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
269 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
270 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
271 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
272 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
273 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
274 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
275 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
276 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
277 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
278 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
280 * Used for any batch entry with a relocated pointer that will be used
281 * by any 3D rendering.
283 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
284 /** \see brw.state.depth_region */
285 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
286 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
287 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
288 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
289 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
290 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
291 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
292 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
293 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
294 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
295 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
296 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
297 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
298 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
299 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
300 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
301 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
302 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
303 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
304 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
305 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
306 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
307 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
308 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
309 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
310 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
311 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
312 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
313 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
314 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
315 #define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL)
316 #define BRW_NEW_AUX_STATE (1ull << BRW_STATE_AUX)
318 struct brw_state_flags
{
319 /** State update flags signalled by mesa internals */
322 * State update flags signalled as the result of brw_tracked_state updates
328 /** Subclass of Mesa program */
330 struct gl_program program
;
337 struct brw_ff_gs_prog_data
{
338 GLuint urb_read_length
;
342 * Gen6 transform feedback: Amount by which the streaming vertex buffer
343 * indices should be incremented each time the GS is invoked.
345 unsigned svbi_postincrement_value
;
348 /** Number of texture sampler units */
349 #define BRW_MAX_TEX_UNIT 32
351 /** Max number of UBOs in a shader */
352 #define BRW_MAX_UBO 14
354 /** Max number of SSBOs in a shader */
355 #define BRW_MAX_SSBO 12
357 /** Max number of atomic counter buffer objects in a shader */
358 #define BRW_MAX_ABO 16
360 /** Max number of image uniforms in a shader */
361 #define BRW_MAX_IMAGES 32
363 /** Maximum number of actual buffers used for stream output */
364 #define BRW_MAX_SOL_BUFFERS 4
366 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
367 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
372 2 + /* shader time, pull constants */ \
373 1 /* cs num work groups */)
376 struct brw_context
*brw
;
378 struct brw_cache_item
**items
;
381 GLuint size
, n_items
;
383 uint32_t next_offset
;
386 #define perf_debug(...) do { \
387 static GLuint msg_id = 0; \
388 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \
389 dbg_printf(__VA_ARGS__); \
390 if (brw->perf_debug) \
391 _mesa_gl_debugf(&brw->ctx, &msg_id, \
392 MESA_DEBUG_SOURCE_API, \
393 MESA_DEBUG_TYPE_PERFORMANCE, \
394 MESA_DEBUG_SEVERITY_MEDIUM, \
398 #define WARN_ONCE(cond, fmt...) do { \
399 if (unlikely(cond)) { \
400 static bool _warned = false; \
401 static GLuint msg_id = 0; \
403 fprintf(stderr, "WARNING: "); \
404 fprintf(stderr, fmt); \
407 _mesa_gl_debugf(ctx, &msg_id, \
408 MESA_DEBUG_SOURCE_API, \
409 MESA_DEBUG_TYPE_OTHER, \
410 MESA_DEBUG_SEVERITY_HIGH, fmt); \
415 /* Considered adding a member to this struct to document which flags
416 * an update might raise so that ordering of the state atoms can be
417 * checked or derived at runtime. Dropped the idea in favor of having
418 * a debug mode where the state is monitored for flags which are
419 * raised that have already been tested against.
421 struct brw_tracked_state
{
422 struct brw_state_flags dirty
;
423 void (*emit
)( struct brw_context
*brw
);
426 enum shader_time_shader_type
{
438 struct brw_vertex_buffer
{
439 /** Buffer object containing the uploaded vertex data */
443 /** Byte stride between elements in the uploaded array */
447 struct brw_vertex_element
{
448 const struct gl_array_attributes
*glattrib
;
449 const struct gl_vertex_buffer_binding
*glbinding
;
453 /** Offset of the first element within the buffer object */
457 struct brw_query_object
{
458 struct gl_query_object Base
;
460 /** Last query BO associated with this query. */
463 /** Last index in bo with query data for this object. */
466 /** True if we know the batch has been flushed since we ended the query. */
470 struct brw_reloc_list
{
471 struct drm_i915_gem_relocation_entry
*relocs
;
473 int reloc_array_size
;
476 struct brw_growing_bo
{
479 struct brw_bo
*partial_bo
;
480 uint32_t *partial_bo_map
;
481 unsigned partial_bytes
;
482 enum brw_memory_zone memzone
;
485 struct intel_batchbuffer
{
486 /** Current batchbuffer being queued up. */
487 struct brw_growing_bo batch
;
488 /** Current statebuffer being queued up. */
489 struct brw_growing_bo state
;
491 /** Last batchbuffer submitted to the hardware. Used for glFinish(). */
492 struct brw_bo
*last_bo
;
495 uint16_t emit
, total
;
500 bool use_shadow_copy
;
501 bool use_batch_first
;
502 bool needs_sol_reset
;
503 bool state_base_address_emitted
;
506 struct brw_reloc_list batch_relocs
;
507 struct brw_reloc_list state_relocs
;
508 unsigned int valid_reloc_flags
;
510 /** The validation list */
511 struct drm_i915_gem_exec_object2
*validation_list
;
512 struct brw_bo
**exec_bos
;
516 /** The amount of aperture space (in bytes) used by all exec_bos */
517 uint64_t aperture_space
;
521 int batch_reloc_count
;
522 int state_reloc_count
;
526 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
527 struct hash_table
*state_batch_sizes
;
529 struct gen_batch_decode_ctx decoder
;
532 #define BRW_MAX_XFB_STREAMS 4
534 struct brw_transform_feedback_counter
{
536 * Index of the first entry of this counter within the primitive count BO.
537 * An entry is considered to be an N-tuple of 64bit values, where N is the
538 * number of vertex streams supported by the platform.
543 * Index one past the last entry of this counter within the primitive
549 * Primitive count values accumulated while this counter was active,
550 * excluding any entries buffered between \c bo_start and \c bo_end, which
551 * haven't been accounted for yet.
553 uint64_t accum
[BRW_MAX_XFB_STREAMS
];
557 brw_reset_transform_feedback_counter(
558 struct brw_transform_feedback_counter
*counter
)
560 counter
->bo_start
= counter
->bo_end
;
561 memset(&counter
->accum
, 0, sizeof(counter
->accum
));
564 struct brw_transform_feedback_object
{
565 struct gl_transform_feedback_object base
;
567 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
568 struct brw_bo
*offset_bo
;
570 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
573 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
574 GLenum primitive_mode
;
577 * The maximum number of vertices that we can write without overflowing
578 * any of the buffers currently being used for transform feedback.
582 struct brw_bo
*prim_count_bo
;
585 * Count of primitives generated during this transform feedback operation.
587 struct brw_transform_feedback_counter counter
;
590 * Count of primitives generated during the previous transform feedback
591 * operation. Used to implement DrawTransformFeedback().
593 struct brw_transform_feedback_counter previous_counter
;
596 * Number of vertices written between last Begin/EndTransformFeedback().
598 * Used to implement DrawTransformFeedback().
600 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
601 bool vertices_written_valid
;
605 * Data shared between each programmable stage in the pipeline (vs, gs, and
608 struct brw_stage_state
610 gl_shader_stage stage
;
611 struct brw_stage_prog_data
*prog_data
;
614 * Optional scratch buffer used to store spilled register values and
615 * variably-indexed GRF arrays.
617 * The contents of this buffer are short-lived so the same memory can be
618 * re-used at will for multiple shader programs (executed by the same fixed
619 * function). However reusing a scratch BO for which shader invocations
620 * are still in flight with a per-thread scratch slot size other than the
621 * original can cause threads with different scratch slot size and FFTID
622 * (which may be executed in parallel depending on the shader stage and
623 * hardware generation) to map to an overlapping region of the scratch
624 * space, which can potentially lead to mutual scratch space corruption.
625 * For that reason if you borrow this scratch buffer you should only be
626 * using the slot size given by the \c per_thread_scratch member below,
627 * unless you're taking additional measures to synchronize thread execution
628 * across slot size changes.
630 struct brw_bo
*scratch_bo
;
633 * Scratch slot size allocated for each thread in the buffer object given
636 uint32_t per_thread_scratch
;
638 /** Offset in the program cache to the program */
639 uint32_t prog_offset
;
641 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
642 uint32_t state_offset
;
644 struct brw_bo
*push_const_bo
; /* NULL if using the batchbuffer */
645 uint32_t push_const_offset
; /* Offset in the push constant BO or batch */
646 int push_const_size
; /* in 256-bit register increments */
648 /* Binding table: pointers to SURFACE_STATE entries. */
649 uint32_t bind_bo_offset
;
650 uint32_t surf_offset
[BRW_MAX_SURFACES
];
652 /** SAMPLER_STATE count and table offset */
653 uint32_t sampler_count
;
654 uint32_t sampler_offset
;
656 struct brw_image_param image_param
[BRW_MAX_IMAGES
];
658 /** Need to re-emit 3DSTATE_CONSTANT_XS? */
659 bool push_constants_dirty
;
662 enum brw_predicate_state
{
663 /* The first two states are used if we can determine whether to draw
664 * without having to look at the values in the query object buffer. This
665 * will happen if there is no conditional render in progress, if the query
666 * object is already completed or if something else has already added
667 * samples to the preliminary result such as via a BLT command.
669 BRW_PREDICATE_STATE_RENDER
,
670 BRW_PREDICATE_STATE_DONT_RENDER
,
671 /* In this case whether to draw or not depends on the result of an
672 * MI_PREDICATE command so the predicate enable bit needs to be checked.
674 BRW_PREDICATE_STATE_USE_BIT
,
675 /* In this case, either MI_PREDICATE doesn't exist or we lack the
676 * necessary kernel features to use it. Stall for the query result.
678 BRW_PREDICATE_STATE_STALL_FOR_QUERY
,
683 struct gen_l3_config
;
686 struct brw_uploader
{
687 struct brw_bufmgr
*bufmgr
;
690 uint32_t next_offset
;
691 unsigned default_size
;
695 * brw_context is derived from gl_context.
699 struct gl_context ctx
; /**< base class, must be first field */
704 * Emit an MI_REPORT_PERF_COUNT command packet.
706 * This asks the GPU to write a report of the current OA counter values
707 * into @bo at the given offset and containing the given @report_id
708 * which we can cross-reference when parsing the report (gen7+ only).
710 void (*emit_mi_report_perf_count
)(struct brw_context
*brw
,
712 uint32_t offset_in_bytes
,
715 void (*emit_compute_walker
)(struct brw_context
*brw
);
716 void (*emit_raw_pipe_control
)(struct brw_context
*brw
, uint32_t flags
,
717 struct brw_bo
*bo
, uint32_t offset
,
721 struct brw_bufmgr
*bufmgr
;
725 /** BO for post-sync nonzero writes for gen6 workaround. */
726 struct brw_bo
*workaround_bo
;
727 uint8_t pipe_controls_since_last_cs_stall
;
730 * Set of struct brw_bo * that have been rendered to within this batchbuffer
731 * and would need flushing before being used from another cache domain that
732 * isn't coherent with it (i.e. the sampler).
734 struct hash_table
*render_cache
;
737 * Set of struct brw_bo * that have been used as a depth buffer within this
738 * batchbuffer and would need flushing before being used from another cache
739 * domain that isn't coherent with it (i.e. the sampler).
741 struct set
*depth_cache
;
744 * Number of resets observed in the system at context creation.
746 * This is tracked in the context so that we can determine that another
747 * reset has occurred.
749 uint32_t reset_count
;
751 struct intel_batchbuffer batch
;
753 struct brw_uploader upload
;
756 * Set if rendering has occurred to the drawable's front buffer.
758 * This is used in the DRI2 case to detect that glFlush should also copy
759 * the contents of the fake front buffer to the real front buffer.
761 bool front_buffer_dirty
;
764 * True if the __DRIdrawable's current __DRIimageBufferMask is
765 * __DRI_IMAGE_BUFFER_SHARED.
767 bool is_shared_buffer_bound
;
770 * True if a shared buffer is bound and it has received any rendering since
771 * the previous __DRImutableRenderBufferLoaderExtension::displaySharedBuffer().
773 bool is_shared_buffer_dirty
;
775 /** Framerate throttling: @{ */
776 struct brw_bo
*throttle_batch
[2];
778 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
779 * frame of rendering to complete. This gives a very precise cap to the
780 * latency between input and output such that rendering never gets more
781 * than a frame behind the user. (With the caveat that we technically are
782 * not using the SwapBuffers itself as a barrier but the first batch
783 * submitted afterwards, which may be immediately prior to the next
786 bool need_swap_throttle
;
788 /** General throttling, not caught by throttling between SwapBuffers */
789 bool need_flush_throttle
;
798 bool always_flush_batch
;
799 bool always_flush_cache
;
800 bool disable_throttling
;
802 bool dual_color_blend_by_location
;
804 driOptionCache optionCache
;
807 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
809 bool object_preemption
; /**< Object level preemption enabled. */
811 GLenum reduced_primitive
;
814 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
815 * variable is set, this is the flag indicating to do expensive work that
816 * might lead to a perf_debug() call.
820 uint64_t max_gtt_map_object_size
;
823 bool has_separate_stencil
;
826 /** Derived stencil states. */
827 bool stencil_enabled
;
828 bool stencil_two_sided
;
829 bool stencil_write_enabled
;
830 /** Derived polygon state. */
831 bool polygon_front_bit
; /**< 0=GL_CCW, 1=GL_CW */
833 struct isl_device isl_dev
;
835 struct blorp_context blorp
;
839 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
842 enum brw_pipeline last_pipeline
;
844 struct brw_cache cache
;
846 /* Whether a meta-operation is in progress. */
847 bool meta_in_progress
;
849 /* Whether the last depth/stencil packets were both NULL. */
850 bool no_depth_or_stencil
;
852 /* The last PMA stall bits programmed. */
853 uint32_t pma_stall_bits
;
858 * Either the value of gl_BaseVertex for indexed draw calls or the
859 * value of the argument <first> for non-indexed draw calls for the
860 * current _mesa_prim.
864 /** The value of gl_BaseInstance for the current _mesa_prim. */
869 * Buffer and offset used for GL_ARB_shader_draw_parameters which will
870 * point to the indirect buffer for indirect draw calls.
872 struct brw_bo
*draw_params_bo
;
873 uint32_t draw_params_offset
;
877 * The value of gl_DrawID for the current _mesa_prim. This always comes
878 * in from it's own vertex buffer since it's not part of the indirect
884 * Stores if the current _mesa_prim is an indexed or non-indexed draw
885 * (~0/0). Useful to calculate gl_BaseVertex as an AND of firstvertex
886 * and is_indexed_draw.
892 * Buffer and offset used for GL_ARB_shader_draw_parameters which contains
893 * parameters that are not present in the indirect buffer. They will go in
894 * their own vertex element.
896 struct brw_bo
*derived_draw_params_bo
;
897 uint32_t derived_draw_params_offset
;
900 * Pointer to the the buffer storing the indirect draw parameters. It
901 * currently only stores the number of requested draw calls but more
902 * parameters could potentially be added.
904 struct brw_bo
*draw_params_count_bo
;
905 uint32_t draw_params_count_offset
;
910 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
911 * an indirect call, and num_work_groups_offset is valid. Otherwise,
912 * num_work_groups is set based on glDispatchCompute.
914 struct brw_bo
*num_work_groups_bo
;
915 GLintptr num_work_groups_offset
;
916 const GLuint
*num_work_groups
;
920 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
921 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
923 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
927 /* Summary of size and varying of active arrays, so we can check
928 * for changes to this state:
930 bool index_bounds_valid
;
931 unsigned int min_index
, max_index
;
933 /* Offset from start of vertex buffer so we can avoid redefining
934 * the same VB packed over and over again.
936 unsigned int start_vertex_bias
;
939 * Certain vertex attribute formats aren't natively handled by the
940 * hardware and require special VS code to fix up their values.
942 * These bitfields indicate which workarounds are needed.
944 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
946 /* High bits of the last seen vertex buffer address (for workarounds). */
947 uint16_t last_bo_high_bits
[33];
952 * Index buffer for this draw_prims call.
954 * Updates are signaled by BRW_NEW_INDICES.
956 const struct _mesa_index_buffer
*ib
;
958 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
963 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
964 * avoid re-uploading the IB packet over and over if we're actually
965 * referencing the same index buffer.
967 unsigned int start_vertex_offset
;
969 /* High bits of the last seen index buffer address (for workarounds). */
970 uint16_t last_bo_high_bits
;
972 /* Used to understand is GPU state of primitive restart is up to date */
973 bool enable_cut_index
;
976 /* Active vertex program:
978 struct gl_program
*programs
[MESA_SHADER_STAGES
];
981 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
982 * that we don't have to reemit that state every time we change FBOs.
984 unsigned int num_samples
;
986 /* BRW_NEW_URB_ALLOCATIONS:
989 GLuint vsize
; /* vertex size plus header in urb registers */
990 GLuint gsize
; /* GS output size in urb registers */
991 GLuint hsize
; /* Tessellation control output size in urb registers */
992 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
993 GLuint csize
; /* constant buffer size in urb registers */
994 GLuint sfsize
; /* setup data size in urb registers */
998 GLuint nr_vs_entries
;
999 GLuint nr_hs_entries
;
1000 GLuint nr_ds_entries
;
1001 GLuint nr_gs_entries
;
1002 GLuint nr_clip_entries
;
1003 GLuint nr_sf_entries
;
1004 GLuint nr_cs_entries
;
1014 * URB size in the current configuration. The units this is expressed
1015 * in are somewhat inconsistent, see gen_device_info::urb::size.
1017 * FINISHME: Represent the URB size consistently in KB on all platforms.
1021 /* True if the most recently sent _3DSTATE_URB message allocated
1022 * URB space for the GS.
1026 /* True if the most recently sent _3DSTATE_URB message allocated
1027 * URB space for the HS and DS.
1033 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1035 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1036 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1044 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1045 * for upload to the CURBE.
1047 struct brw_bo
*curbe_bo
;
1048 /** Offset within curbe_bo of space for current curbe entry */
1049 GLuint curbe_offset
;
1053 * Layout of vertex data exiting the geometry portion of the pipleine.
1054 * This comes from the last enabled shader stage (GS, DS, or VS).
1056 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1058 struct brw_vue_map vue_map_geom_out
;
1061 struct brw_stage_state base
;
1065 struct brw_stage_state base
;
1069 struct brw_stage_state base
;
1073 struct brw_stage_state base
;
1076 * True if the 3DSTATE_GS command most recently emitted to the 3D
1077 * pipeline enabled the GS; false otherwise.
1083 struct brw_ff_gs_prog_data
*prog_data
;
1086 /** Offset in the program cache to the CLIP program pre-gen6 */
1087 uint32_t prog_offset
;
1088 uint32_t state_offset
;
1090 uint32_t bind_bo_offset
;
1092 * Surface offsets for the binding table. We only need surfaces to
1093 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1094 * need in this case.
1096 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1100 struct brw_clip_prog_data
*prog_data
;
1102 /** Offset in the program cache to the CLIP program pre-gen6 */
1103 uint32_t prog_offset
;
1105 /* Offset in the batch to the CLIP state on pre-gen6. */
1106 uint32_t state_offset
;
1108 /* As of gen6, this is the offset in the batch to the CLIP VP,
1114 * The number of viewports to use. If gl_ViewportIndex is written,
1115 * we can have up to ctx->Const.MaxViewports viewports. If not,
1116 * the viewport index is always 0, so we can only emit one.
1118 uint8_t viewport_count
;
1123 struct brw_sf_prog_data
*prog_data
;
1125 /** Offset in the program cache to the CLIP program pre-gen6 */
1126 uint32_t prog_offset
;
1127 uint32_t state_offset
;
1132 struct brw_stage_state base
;
1135 * Buffer object used in place of multisampled null render targets on
1136 * Gen6. See brw_emit_null_surface_state().
1138 struct brw_bo
*multisampled_null_render_target_bo
;
1144 struct brw_stage_state base
;
1148 uint32_t state_offset
;
1149 uint32_t blend_state_offset
;
1150 uint32_t depth_stencil_state_offset
;
1155 struct brw_query_object
*obj
;
1160 enum brw_predicate_state state
;
1165 struct gen_perf
*perf
;
1167 /* The i915 perf stream we open to setup + enable the OA counters */
1170 /* An i915 perf stream fd gives exclusive access to the OA unit that will
1171 * report counter snapshots for a specific counter set/profile in a
1172 * specific layout/format so we can only start OA queries that are
1173 * compatible with the currently open fd...
1175 int current_oa_metrics_set_id
;
1176 int current_oa_format
;
1178 /* List of buffers containing OA reports */
1179 struct exec_list sample_buffers
;
1181 /* Cached list of empty sample buffers */
1182 struct exec_list free_sample_buffers
;
1184 int n_active_oa_queries
;
1185 int n_active_pipeline_stats_queries
;
1187 /* The number of queries depending on running OA counters which
1188 * extends beyond brw_end_perf_query() since we need to wait until
1189 * the last MI_RPC command has parsed by the GPU.
1191 * Accurate accounting is important here as emitting an
1192 * MI_REPORT_PERF_COUNT command while the OA unit is disabled will
1193 * effectively hang the gpu.
1197 /* To help catch an spurious problem with the hardware or perf
1198 * forwarding samples, we emit each MI_REPORT_PERF_COUNT command
1199 * with a unique ID that we can explicitly check for...
1201 int next_query_start_report_id
;
1204 * An array of queries whose results haven't yet been assembled
1205 * based on the data in buffer objects.
1207 * These may be active, or have already ended. However, the
1208 * results have not been requested.
1210 struct brw_perf_query_object
**unaccumulated
;
1211 int unaccumulated_elements
;
1212 int unaccumulated_array_size
;
1214 /* The total number of query objects so we can relinquish
1215 * our exclusive access to perf if the application deletes
1216 * all of its objects. (NB: We only disable perf while
1217 * there are no active queries)
1219 int n_query_instances
;
1222 int num_atoms
[BRW_NUM_PIPELINES
];
1223 const struct brw_tracked_state render_atoms
[76];
1224 const struct brw_tracked_state compute_atoms
[11];
1226 const enum isl_format
*mesa_to_isl_render_format
;
1227 const bool *mesa_format_supports_render
;
1229 /* PrimitiveRestart */
1232 bool enable_cut_index
;
1235 /** Computed depth/stencil/hiz state from the current attached
1236 * renderbuffers, valid only during the drawing state upload loop after
1237 * brw_workaround_depthstencil_alignment().
1240 /* Inter-tile (page-aligned) byte offsets. */
1241 uint32_t depth_offset
;
1242 /* Intra-tile x,y offsets for drawing to combined depth-stencil. Only
1245 uint32_t tile_x
, tile_y
;
1248 uint32_t num_instances
;
1253 const struct gen_l3_config
*config
;
1260 enum shader_time_shader_type
*types
;
1261 struct shader_times
*cumulative
;
1267 struct brw_fast_clear_state
*fast_clear_state
;
1269 /* Array of aux usages to use for drawing. Aux usage for render targets is
1270 * a bit more complex than simply calling a single function so we need some
1271 * way of passing it form brw_draw.c to surface state setup.
1273 enum isl_aux_usage draw_aux_usage
[MAX_DRAW_BUFFERS
];
1275 enum gen9_astc5x5_wa_tex_type gen9_astc5x5_wa_tex_mask
;
1277 __DRIcontext
*driContext
;
1278 struct intel_screen
*screen
;
1282 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1284 /*======================================================================
1287 extern const char *const brw_vendor_string
;
1290 brw_get_renderer_string(const struct intel_screen
*screen
);
1293 DRI_CONF_BO_REUSE_DISABLED
,
1294 DRI_CONF_BO_REUSE_ALL
1297 void intel_update_renderbuffers(__DRIcontext
*context
,
1298 __DRIdrawable
*drawable
);
1299 void intel_prepare_render(struct brw_context
*brw
);
1301 void gen9_apply_single_tex_astc5x5_wa(struct brw_context
*brw
,
1303 enum isl_aux_usage aux_usage
);
1305 void brw_predraw_resolve_inputs(struct brw_context
*brw
, bool rendering
,
1306 bool *draw_aux_buffer_disabled
);
1308 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1309 __DRIdrawable
*drawable
);
1311 GLboolean
brwCreateContext(gl_api api
,
1312 const struct gl_config
*mesaVis
,
1313 __DRIcontext
*driContextPriv
,
1314 const struct __DriverContextConfig
*ctx_config
,
1316 void *sharedContextPrivate
);
1318 /*======================================================================
1321 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1322 GLbitfield clear_mask
);
1324 /* brw_object_purgeable.c */
1325 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1327 /*======================================================================
1330 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1331 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1332 void brw_emit_query_begin(struct brw_context
*brw
);
1333 void brw_emit_query_end(struct brw_context
*brw
);
1334 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1335 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1336 uint64_t brw_timebase_scale(struct brw_context
*brw
, uint64_t gpu_timestamp
);
1337 uint64_t brw_raw_timestamp_delta(struct brw_context
*brw
,
1338 uint64_t time0
, uint64_t time1
);
1340 /** gen6_queryobj.c */
1341 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1342 void brw_write_timestamp(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1343 void brw_write_depth_count(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1345 /** hsw_queryobj.c */
1346 void hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
1347 struct brw_query_object
*query
,
1349 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1351 /** brw_conditional_render.c */
1352 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1353 bool brw_check_conditional_render(struct brw_context
*brw
);
1355 /** intel_batchbuffer.c */
1356 void brw_load_register_mem(struct brw_context
*brw
,
1360 void brw_load_register_mem64(struct brw_context
*brw
,
1364 void brw_store_register_mem32(struct brw_context
*brw
,
1365 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1366 void brw_store_register_mem64(struct brw_context
*brw
,
1367 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1368 void brw_load_register_imm32(struct brw_context
*brw
,
1369 uint32_t reg
, uint32_t imm
);
1370 void brw_load_register_imm64(struct brw_context
*brw
,
1371 uint32_t reg
, uint64_t imm
);
1372 void brw_load_register_reg(struct brw_context
*brw
, uint32_t dst
,
1374 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t dst
,
1376 void brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1377 uint32_t offset
, uint32_t imm
);
1378 void brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1379 uint32_t offset
, uint64_t imm
);
1381 /*======================================================================
1382 * intel_tex_validate.c
1384 void brw_validate_textures( struct brw_context
*brw
);
1387 /*======================================================================
1390 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1392 void brw_get_scratch_bo(struct brw_context
*brw
,
1393 struct brw_bo
**scratch_bo
, int size
);
1394 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1395 struct brw_stage_state
*stage_state
,
1396 unsigned per_thread_size
);
1397 void brw_init_shader_time(struct brw_context
*brw
);
1398 int brw_get_shader_time_index(struct brw_context
*brw
,
1399 struct gl_program
*prog
,
1400 enum shader_time_shader_type type
,
1402 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1403 void brw_destroy_shader_time(struct brw_context
*brw
);
1407 void brw_calculate_urb_fence(struct brw_context
*brw
, unsigned csize
,
1408 unsigned vsize
, unsigned sfsize
);
1409 void brw_upload_urb_fence(struct brw_context
*brw
);
1413 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1416 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1418 /* brw_draw_upload.c */
1419 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1420 const struct gl_vertex_format
*glformat
);
1422 static inline unsigned
1423 brw_get_index_type(unsigned index_size
)
1425 /* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint,
1428 return index_size
>> 1;
1431 void brw_prepare_vertices(struct brw_context
*brw
);
1433 /* brw_wm_surface_state.c */
1434 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1436 uint32_t *surf_offset
);
1438 brw_update_sol_surface(struct brw_context
*brw
,
1439 struct gl_buffer_object
*buffer_obj
,
1440 uint32_t *out_offset
, unsigned num_vector_components
,
1441 unsigned stride_dwords
, unsigned offset_dwords
);
1442 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1443 struct brw_stage_state
*stage_state
,
1444 struct brw_stage_prog_data
*prog_data
);
1445 void brw_upload_image_surfaces(struct brw_context
*brw
,
1446 const struct gl_program
*prog
,
1447 struct brw_stage_state
*stage_state
,
1448 struct brw_stage_prog_data
*prog_data
);
1450 /* brw_surface_formats.c */
1451 void intel_screen_init_surface_formats(struct intel_screen
*screen
);
1452 void brw_init_surface_formats(struct brw_context
*brw
);
1453 bool brw_render_target_supported(struct brw_context
*brw
,
1454 struct gl_renderbuffer
*rb
);
1455 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1457 /* brw_performance_query.c */
1458 void brw_init_performance_queries(struct brw_context
*brw
);
1460 /* intel_extensions.c */
1461 extern void intelInitExtensions(struct gl_context
*ctx
);
1464 extern int intel_translate_shadow_compare_func(GLenum func
);
1465 extern int intel_translate_compare_func(GLenum func
);
1466 extern int intel_translate_stencil_op(GLenum op
);
1469 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1472 struct gl_transform_feedback_object
*
1473 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1475 brw_delete_transform_feedback(struct gl_context
*ctx
,
1476 struct gl_transform_feedback_object
*obj
);
1478 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1479 struct gl_transform_feedback_object
*obj
);
1481 brw_end_transform_feedback(struct gl_context
*ctx
,
1482 struct gl_transform_feedback_object
*obj
);
1484 brw_pause_transform_feedback(struct gl_context
*ctx
,
1485 struct gl_transform_feedback_object
*obj
);
1487 brw_resume_transform_feedback(struct gl_context
*ctx
,
1488 struct gl_transform_feedback_object
*obj
);
1490 brw_save_primitives_written_counters(struct brw_context
*brw
,
1491 struct brw_transform_feedback_object
*obj
);
1493 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1494 struct gl_transform_feedback_object
*obj
,
1497 /* gen7_sol_state.c */
1499 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1500 struct gl_transform_feedback_object
*obj
);
1502 gen7_end_transform_feedback(struct gl_context
*ctx
,
1503 struct gl_transform_feedback_object
*obj
);
1505 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1506 struct gl_transform_feedback_object
*obj
);
1508 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1509 struct gl_transform_feedback_object
*obj
);
1513 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1514 struct gl_transform_feedback_object
*obj
);
1516 hsw_end_transform_feedback(struct gl_context
*ctx
,
1517 struct gl_transform_feedback_object
*obj
);
1519 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1520 struct gl_transform_feedback_object
*obj
);
1522 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1523 struct gl_transform_feedback_object
*obj
);
1525 /* brw_blorp_blit.cpp */
1527 brw_blorp_framebuffer(struct brw_context
*brw
,
1528 struct gl_framebuffer
*readFb
,
1529 struct gl_framebuffer
*drawFb
,
1530 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1531 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1532 GLbitfield mask
, GLenum filter
);
1535 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1536 struct gl_renderbuffer
*src_rb
,
1537 struct gl_texture_image
*dst_image
,
1539 int srcX0
, int srcY0
,
1540 int dstX0
, int dstY0
,
1541 int width
, int height
);
1543 /* brw_generate_mipmap.c */
1544 void brw_generate_mipmap(struct gl_context
*ctx
, GLenum target
,
1545 struct gl_texture_object
*tex_obj
);
1548 gen6_get_sample_position(struct gl_context
*ctx
,
1549 struct gl_framebuffer
*fb
,
1553 gen6_set_sample_maps(struct gl_context
*ctx
);
1555 /* gen8_multisample_state.c */
1556 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1560 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1561 unsigned hs_size
, unsigned ds_size
,
1562 unsigned gs_size
, unsigned fs_size
);
1565 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1566 bool gs_present
, unsigned gs_size
);
1568 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1569 bool gs_present
, bool tess_present
);
1573 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1575 brw_check_for_reset(struct brw_context
*brw
);
1579 brw_init_compute_functions(struct dd_function_table
*functions
);
1581 /* brw_program_binary.c */
1583 brw_program_binary_init(unsigned device_id
);
1585 brw_get_program_binary_driver_sha1(struct gl_context
*ctx
, uint8_t *sha1
);
1586 void brw_serialize_program_binary(struct gl_context
*ctx
,
1587 struct gl_shader_program
*sh_prog
,
1588 struct gl_program
*prog
);
1590 brw_deserialize_program_binary(struct gl_context
*ctx
,
1591 struct gl_shader_program
*shProg
,
1592 struct gl_program
*prog
);
1594 brw_program_serialize_nir(struct gl_context
*ctx
, struct gl_program
*prog
);
1596 brw_program_deserialize_driver_blob(struct gl_context
*ctx
,
1597 struct gl_program
*prog
,
1598 gl_shader_stage stage
);
1600 /*======================================================================
1601 * Inline conversion functions. These are better-typed than the
1602 * macros used previously:
1604 static inline struct brw_context
*
1605 brw_context( struct gl_context
*ctx
)
1607 return (struct brw_context
*)ctx
;
1610 static inline struct brw_program
*
1611 brw_program(struct gl_program
*p
)
1613 return (struct brw_program
*) p
;
1616 static inline const struct brw_program
*
1617 brw_program_const(const struct gl_program
*p
)
1619 return (const struct brw_program
*) p
;
1623 brw_depth_writes_enabled(const struct brw_context
*brw
)
1625 const struct gl_context
*ctx
= &brw
->ctx
;
1627 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1628 * because it would just overwrite the existing depth value with itself.
1630 * These bonus depth writes not only use bandwidth, but they also can
1631 * prevent early depth processing. For example, if the pixel shader
1632 * discards, the hardware must invoke the to determine whether or not
1633 * to do the depth write. If writes are disabled, we may still be able
1634 * to do the depth test before the shader, and skip the shader execution.
1636 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1637 * a programming note saying to disable depth writes for EQUAL.
1639 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1643 brw_emit_depthbuffer(struct brw_context
*brw
);
1645 uint32_t get_hw_prim_for_gl_prim(int mode
);
1648 gen6_upload_push_constants(struct brw_context
*brw
,
1649 const struct gl_program
*prog
,
1650 const struct brw_stage_prog_data
*prog_data
,
1651 struct brw_stage_state
*stage_state
);
1654 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1655 const struct intel_mipmap_tree
*mt
);
1657 /* brw_queryformat.c */
1658 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1659 GLenum internalFormat
, GLenum pname
,