2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
40 #include "brw_structs.h"
41 #include "brw_pipe_control.h"
42 #include "compiler/brw_compiler.h"
45 #include "blorp/blorp.h"
47 #include <brw_bufmgr.h>
49 #include "common/gen_debug.h"
50 #include "intel_screen.h"
51 #include "intel_tex_obj.h"
58 * URB - uniform resource buffer. A mid-sized buffer which is
59 * partitioned between the fixed function units and used for passing
60 * values (vertices, primitives, constants) between them.
62 * CURBE - constant URB entry. An urb region (entry) used to hold
63 * constant values which the fixed function units can be instructed to
64 * preload into the GRF when spawning a thread.
66 * VUE - vertex URB entry. An urb entry holding a vertex and usually
67 * a vertex header. The header contains control information and
68 * things like primitive type, Begin/end flags and clip codes.
70 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
71 * unit holding rasterization and interpolation parameters.
73 * GRF - general register file. One of several register files
74 * addressable by programmed threads. The inputs (r0, payload, curbe,
75 * urb) of the thread are preloaded to this area before the thread is
76 * spawned. The registers are individually 8 dwords wide and suitable
77 * for general usage. Registers holding thread input values are not
78 * special and may be overwritten.
80 * MRF - message register file. Threads communicate (and terminate)
81 * by sending messages. Message parameters are placed in contiguous
82 * MRF registers. All program output is via these messages. URB
83 * entries are populated by sending a message to the shared URB
84 * function containing the new data, together with a control word,
85 * often an unmodified copy of R0.
87 * R0 - GRF register 0. Typically holds control information used when
88 * sending messages to other threads.
90 * EU or GEN4 EU: The name of the programmable subsystem of the
91 * i965 hardware. Threads are executed by the EU, the registers
92 * described above are part of the EU architecture.
94 * Fixed function units:
96 * CS - Command streamer. Notional first unit, little software
97 * interaction. Holds the URB entries used for constant data, ie the
100 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
101 * this unit is responsible for pulling vertices out of vertex buffers
102 * in vram and injecting them into the processing pipe as VUEs. If
103 * enabled, it first passes them to a VS thread which is a good place
104 * for the driver to implement any active vertex shader.
106 * HS - Hull Shader (Tessellation Control Shader)
108 * TE - Tessellation Engine (Tessellation Primitive Generation)
110 * DS - Domain Shader (Tessellation Evaluation Shader)
112 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
113 * enabled, incoming strips etc are passed to GS threads in individual
114 * line/triangle/point units. The GS thread may perform arbitary
115 * computation and emit whatever primtives with whatever vertices it
116 * chooses. This makes GS an excellent place to implement GL's
117 * unfilled polygon modes, though of course it is capable of much
118 * more. Additionally, GS is used to translate away primitives not
119 * handled by latter units, including Quads and Lineloops.
121 * CS - Clipper. Mesa's clipping algorithms are imported to run on
122 * this unit. The fixed function part performs cliptesting against
123 * the 6 fixed clipplanes and makes descisions on whether or not the
124 * incoming primitive needs to be passed to a thread for clipping.
125 * User clip planes are handled via cooperation with the VS thread.
127 * SF - Strips Fans or Setup: Triangles are prepared for
128 * rasterization. Interpolation coefficients are calculated.
129 * Flatshading and two-side lighting usually performed here.
131 * WM - Windower. Interpolation of vertex attributes performed here.
132 * Fragment shader implemented here. SIMD aspects of EU taken full
133 * advantage of, as pixels are processed in blocks of 16.
135 * CC - Color Calculator. No EU threads associated with this unit.
136 * Handles blending and (presumably) depth and stencil testing.
141 struct brw_vs_prog_key
;
142 struct brw_vue_prog_key
;
143 struct brw_wm_prog_key
;
144 struct brw_wm_prog_data
;
145 struct brw_cs_prog_key
;
146 struct brw_cs_prog_data
;
150 BRW_COMPUTE_PIPELINE
,
157 BRW_CACHE_BLORP_PROG
,
160 BRW_CACHE_FF_GS_PROG
,
171 /* brw_cache_ids must come first - see brw_program_cache.c */
172 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
173 BRW_STATE_FRAGMENT_PROGRAM
,
174 BRW_STATE_GEOMETRY_PROGRAM
,
175 BRW_STATE_TESS_PROGRAMS
,
176 BRW_STATE_VERTEX_PROGRAM
,
177 BRW_STATE_REDUCED_PRIMITIVE
,
178 BRW_STATE_PATCH_PRIMITIVE
,
183 BRW_STATE_BINDING_TABLE_POINTERS
,
186 BRW_STATE_DEFAULT_TESS_LEVELS
,
188 BRW_STATE_INDEX_BUFFER
,
189 BRW_STATE_VS_CONSTBUF
,
190 BRW_STATE_TCS_CONSTBUF
,
191 BRW_STATE_TES_CONSTBUF
,
192 BRW_STATE_GS_CONSTBUF
,
193 BRW_STATE_PROGRAM_CACHE
,
194 BRW_STATE_STATE_BASE_ADDRESS
,
195 BRW_STATE_VUE_MAP_GEOM_OUT
,
196 BRW_STATE_TRANSFORM_FEEDBACK
,
197 BRW_STATE_RASTERIZER_DISCARD
,
199 BRW_STATE_UNIFORM_BUFFER
,
200 BRW_STATE_IMAGE_UNITS
,
201 BRW_STATE_META_IN_PROGRESS
,
202 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
203 BRW_STATE_NUM_SAMPLES
,
204 BRW_STATE_TEXTURE_BUFFER
,
205 BRW_STATE_GEN4_UNIT_STATE
,
209 BRW_STATE_SAMPLER_STATE_TABLE
,
210 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
211 BRW_STATE_COMPUTE_PROGRAM
,
212 BRW_STATE_CS_WORK_GROUPS
,
216 BRW_STATE_VIEWPORT_COUNT
,
217 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
224 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
226 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
227 * When the currently bound shader program differs from the previous draw
228 * call, these will be flagged. They cover brw->{stage}_program and
229 * ctx->{Stage}Program->_Current.
231 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
232 * driver perspective. Even if the same shader is bound at the API level,
233 * we may need to switch between multiple versions of that shader to handle
234 * changes in non-orthagonal state.
236 * Additionally, multiple shader programs may have identical vertex shaders
237 * (for example), or compile down to the same code in the backend. We combine
238 * those into a single program cache entry.
240 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
241 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
243 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
244 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
245 * use the normal state upload paths), but the cache is still used. To avoid
246 * polluting the brw_program_cache code with special cases, we retain the
247 * dirty bit for now. It should eventually be removed.
249 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
250 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
251 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
252 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
253 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
254 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
255 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
256 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
257 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
258 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
259 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
260 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
261 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
262 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
263 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
264 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
265 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
266 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
267 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
268 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
269 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
270 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
271 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
272 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
274 * Used for any batch entry with a relocated pointer that will be used
275 * by any 3D rendering.
277 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
278 /** \see brw.state.depth_region */
279 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
280 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
281 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
282 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
283 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
284 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
285 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
286 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
287 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
288 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
289 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
290 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
291 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
292 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
293 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
294 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
295 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
296 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
297 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
298 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
299 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
300 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
301 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
302 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
303 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
304 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
305 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
306 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
307 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
308 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
309 #define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL)
310 #define BRW_NEW_AUX_STATE (1ull << BRW_STATE_AUX)
312 struct brw_state_flags
{
313 /** State update flags signalled by mesa internals */
316 * State update flags signalled as the result of brw_tracked_state updates
322 /** Subclass of Mesa program */
324 struct gl_program program
;
331 struct brw_ff_gs_prog_data
{
332 GLuint urb_read_length
;
336 * Gen6 transform feedback: Amount by which the streaming vertex buffer
337 * indices should be incremented each time the GS is invoked.
339 unsigned svbi_postincrement_value
;
342 /** Number of texture sampler units */
343 #define BRW_MAX_TEX_UNIT 32
345 /** Max number of UBOs in a shader */
346 #define BRW_MAX_UBO 14
348 /** Max number of SSBOs in a shader */
349 #define BRW_MAX_SSBO 12
351 /** Max number of atomic counter buffer objects in a shader */
352 #define BRW_MAX_ABO 16
354 /** Max number of image uniforms in a shader */
355 #define BRW_MAX_IMAGES 32
357 /** Maximum number of actual buffers used for stream output */
358 #define BRW_MAX_SOL_BUFFERS 4
360 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
361 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
366 2 + /* shader time, pull constants */ \
367 1 /* cs num work groups */)
370 struct brw_context
*brw
;
372 struct brw_cache_item
**items
;
375 GLuint size
, n_items
;
377 uint32_t next_offset
;
380 #define perf_debug(...) do { \
381 static GLuint msg_id = 0; \
382 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \
383 dbg_printf(__VA_ARGS__); \
384 if (brw->perf_debug) \
385 _mesa_gl_debug(&brw->ctx, &msg_id, \
386 MESA_DEBUG_SOURCE_API, \
387 MESA_DEBUG_TYPE_PERFORMANCE, \
388 MESA_DEBUG_SEVERITY_MEDIUM, \
392 #define WARN_ONCE(cond, fmt...) do { \
393 if (unlikely(cond)) { \
394 static bool _warned = false; \
395 static GLuint msg_id = 0; \
397 fprintf(stderr, "WARNING: "); \
398 fprintf(stderr, fmt); \
401 _mesa_gl_debug(ctx, &msg_id, \
402 MESA_DEBUG_SOURCE_API, \
403 MESA_DEBUG_TYPE_OTHER, \
404 MESA_DEBUG_SEVERITY_HIGH, fmt); \
409 /* Considered adding a member to this struct to document which flags
410 * an update might raise so that ordering of the state atoms can be
411 * checked or derived at runtime. Dropped the idea in favor of having
412 * a debug mode where the state is monitored for flags which are
413 * raised that have already been tested against.
415 struct brw_tracked_state
{
416 struct brw_state_flags dirty
;
417 void (*emit
)( struct brw_context
*brw
);
420 enum shader_time_shader_type
{
431 struct brw_vertex_buffer
{
432 /** Buffer object containing the uploaded vertex data */
436 /** Byte stride between elements in the uploaded array */
440 struct brw_vertex_element
{
441 const struct gl_vertex_array
*glarray
;
445 /** Offset of the first element within the buffer object */
449 struct brw_query_object
{
450 struct gl_query_object Base
;
452 /** Last query BO associated with this query. */
455 /** Last index in bo with query data for this object. */
458 /** True if we know the batch has been flushed since we ended the query. */
468 struct brw_reloc_list
{
469 struct drm_i915_gem_relocation_entry
*relocs
;
471 int reloc_array_size
;
474 struct brw_growing_bo
{
477 struct brw_bo
*partial_bo
;
478 uint32_t *partial_bo_map
;
479 unsigned partial_bytes
;
482 struct intel_batchbuffer
{
483 /** Current batchbuffer being queued up. */
484 struct brw_growing_bo batch
;
485 /** Current statebuffer being queued up. */
486 struct brw_growing_bo state
;
488 /** Last batchbuffer submitted to the hardware. Used for glFinish(). */
489 struct brw_bo
*last_bo
;
492 uint16_t emit
, total
;
497 enum brw_gpu_ring ring
;
498 bool use_shadow_copy
;
499 bool use_batch_first
;
500 bool needs_sol_reset
;
501 bool state_base_address_emitted
;
504 struct brw_reloc_list batch_relocs
;
505 struct brw_reloc_list state_relocs
;
506 unsigned int valid_reloc_flags
;
508 /** The validation list */
509 struct drm_i915_gem_exec_object2
*validation_list
;
510 struct brw_bo
**exec_bos
;
514 /** The amount of aperture space (in bytes) used by all exec_bos */
519 int batch_reloc_count
;
520 int state_reloc_count
;
524 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
525 struct hash_table
*state_batch_sizes
;
528 #define BRW_MAX_XFB_STREAMS 4
530 struct brw_transform_feedback_counter
{
532 * Index of the first entry of this counter within the primitive count BO.
533 * An entry is considered to be an N-tuple of 64bit values, where N is the
534 * number of vertex streams supported by the platform.
539 * Index one past the last entry of this counter within the primitive
545 * Primitive count values accumulated while this counter was active,
546 * excluding any entries buffered between \c bo_start and \c bo_end, which
547 * haven't been accounted for yet.
549 uint64_t accum
[BRW_MAX_XFB_STREAMS
];
553 brw_reset_transform_feedback_counter(
554 struct brw_transform_feedback_counter
*counter
)
556 counter
->bo_start
= counter
->bo_end
;
557 memset(&counter
->accum
, 0, sizeof(counter
->accum
));
560 struct brw_transform_feedback_object
{
561 struct gl_transform_feedback_object base
;
563 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
564 struct brw_bo
*offset_bo
;
566 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
569 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
570 GLenum primitive_mode
;
573 * The maximum number of vertices that we can write without overflowing
574 * any of the buffers currently being used for transform feedback.
578 struct brw_bo
*prim_count_bo
;
581 * Count of primitives generated during this transform feedback operation.
583 struct brw_transform_feedback_counter counter
;
586 * Count of primitives generated during the previous transform feedback
587 * operation. Used to implement DrawTransformFeedback().
589 struct brw_transform_feedback_counter previous_counter
;
592 * Number of vertices written between last Begin/EndTransformFeedback().
594 * Used to implement DrawTransformFeedback().
596 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
597 bool vertices_written_valid
;
601 * Data shared between each programmable stage in the pipeline (vs, gs, and
604 struct brw_stage_state
606 gl_shader_stage stage
;
607 struct brw_stage_prog_data
*prog_data
;
610 * Optional scratch buffer used to store spilled register values and
611 * variably-indexed GRF arrays.
613 * The contents of this buffer are short-lived so the same memory can be
614 * re-used at will for multiple shader programs (executed by the same fixed
615 * function). However reusing a scratch BO for which shader invocations
616 * are still in flight with a per-thread scratch slot size other than the
617 * original can cause threads with different scratch slot size and FFTID
618 * (which may be executed in parallel depending on the shader stage and
619 * hardware generation) to map to an overlapping region of the scratch
620 * space, which can potentially lead to mutual scratch space corruption.
621 * For that reason if you borrow this scratch buffer you should only be
622 * using the slot size given by the \c per_thread_scratch member below,
623 * unless you're taking additional measures to synchronize thread execution
624 * across slot size changes.
626 struct brw_bo
*scratch_bo
;
629 * Scratch slot size allocated for each thread in the buffer object given
632 uint32_t per_thread_scratch
;
634 /** Offset in the program cache to the program */
635 uint32_t prog_offset
;
637 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
638 uint32_t state_offset
;
640 struct brw_bo
*push_const_bo
; /* NULL if using the batchbuffer */
641 uint32_t push_const_offset
; /* Offset in the push constant BO or batch */
642 int push_const_size
; /* in 256-bit register increments */
644 /* Binding table: pointers to SURFACE_STATE entries. */
645 uint32_t bind_bo_offset
;
646 uint32_t surf_offset
[BRW_MAX_SURFACES
];
648 /** SAMPLER_STATE count and table offset */
649 uint32_t sampler_count
;
650 uint32_t sampler_offset
;
652 struct brw_image_param image_param
[BRW_MAX_IMAGES
];
654 /** Need to re-emit 3DSTATE_CONSTANT_XS? */
655 bool push_constants_dirty
;
658 enum brw_predicate_state
{
659 /* The first two states are used if we can determine whether to draw
660 * without having to look at the values in the query object buffer. This
661 * will happen if there is no conditional render in progress, if the query
662 * object is already completed or if something else has already added
663 * samples to the preliminary result such as via a BLT command.
665 BRW_PREDICATE_STATE_RENDER
,
666 BRW_PREDICATE_STATE_DONT_RENDER
,
667 /* In this case whether to draw or not depends on the result of an
668 * MI_PREDICATE command so the predicate enable bit needs to be checked.
670 BRW_PREDICATE_STATE_USE_BIT
,
671 /* In this case, either MI_PREDICATE doesn't exist or we lack the
672 * necessary kernel features to use it. Stall for the query result.
674 BRW_PREDICATE_STATE_STALL_FOR_QUERY
,
679 struct gen_l3_config
;
681 enum brw_query_kind
{
686 struct brw_perf_query_register_prog
{
691 struct brw_perf_query_info
693 enum brw_query_kind kind
;
696 struct brw_perf_query_counter
*counters
;
701 uint64_t oa_metrics_set_id
;
704 /* For indexing into the accumulator[] ... */
706 int gpu_clock_offset
;
711 /* Register programming for a given query */
712 struct brw_perf_query_register_prog
*flex_regs
;
713 uint32_t n_flex_regs
;
715 struct brw_perf_query_register_prog
*mux_regs
;
718 struct brw_perf_query_register_prog
*b_counter_regs
;
719 uint32_t n_b_counter_regs
;
722 struct brw_uploader
{
723 struct brw_bufmgr
*bufmgr
;
726 uint32_t next_offset
;
727 unsigned default_size
;
731 * brw_context is derived from gl_context.
735 struct gl_context ctx
; /**< base class, must be first field */
740 * Send the appropriate state packets to configure depth, stencil, and
741 * HiZ buffers (i965+ only)
743 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
744 struct intel_mipmap_tree
*depth_mt
,
745 uint32_t depth_offset
,
746 uint32_t depthbuffer_format
,
747 uint32_t depth_surface_type
,
748 struct intel_mipmap_tree
*stencil_mt
,
749 bool hiz
, bool separate_stencil
,
750 uint32_t width
, uint32_t height
,
751 uint32_t tile_x
, uint32_t tile_y
);
754 * Emit an MI_REPORT_PERF_COUNT command packet.
756 * This asks the GPU to write a report of the current OA counter values
757 * into @bo at the given offset and containing the given @report_id
758 * which we can cross-reference when parsing the report (gen7+ only).
760 void (*emit_mi_report_perf_count
)(struct brw_context
*brw
,
762 uint32_t offset_in_bytes
,
766 struct brw_bufmgr
*bufmgr
;
770 /** BO for post-sync nonzero writes for gen6 workaround. */
771 struct brw_bo
*workaround_bo
;
772 uint8_t pipe_controls_since_last_cs_stall
;
775 * Set of struct brw_bo * that have been rendered to within this batchbuffer
776 * and would need flushing before being used from another cache domain that
777 * isn't coherent with it (i.e. the sampler).
779 struct hash_table
*render_cache
;
782 * Set of struct brw_bo * that have been used as a depth buffer within this
783 * batchbuffer and would need flushing before being used from another cache
784 * domain that isn't coherent with it (i.e. the sampler).
786 struct set
*depth_cache
;
789 * Number of resets observed in the system at context creation.
791 * This is tracked in the context so that we can determine that another
792 * reset has occurred.
794 uint32_t reset_count
;
796 struct intel_batchbuffer batch
;
798 struct brw_uploader upload
;
801 * Set if rendering has occurred to the drawable's front buffer.
803 * This is used in the DRI2 case to detect that glFlush should also copy
804 * the contents of the fake front buffer to the real front buffer.
806 bool front_buffer_dirty
;
808 /** Framerate throttling: @{ */
809 struct brw_bo
*throttle_batch
[2];
811 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
812 * frame of rendering to complete. This gives a very precise cap to the
813 * latency between input and output such that rendering never gets more
814 * than a frame behind the user. (With the caveat that we technically are
815 * not using the SwapBuffers itself as a barrier but the first batch
816 * submitted afterwards, which may be immediately prior to the next
819 bool need_swap_throttle
;
821 /** General throttling, not caught by throttling between SwapBuffers */
822 bool need_flush_throttle
;
832 bool always_flush_batch
;
833 bool always_flush_cache
;
834 bool disable_throttling
;
836 bool dual_color_blend_by_location
;
838 driOptionCache optionCache
;
841 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
843 GLenum reduced_primitive
;
846 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
847 * variable is set, this is the flag indicating to do expensive work that
848 * might lead to a perf_debug() call.
852 uint64_t max_gtt_map_object_size
;
855 bool has_separate_stencil
;
858 /** Derived stencil states. */
859 bool stencil_enabled
;
860 bool stencil_two_sided
;
861 bool stencil_write_enabled
;
862 /** Derived polygon state. */
863 bool polygon_front_bit
; /**< 0=GL_CCW, 1=GL_CW */
865 struct isl_device isl_dev
;
867 struct blorp_context blorp
;
871 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
874 enum brw_pipeline last_pipeline
;
876 struct brw_cache cache
;
878 /* Whether a meta-operation is in progress. */
879 bool meta_in_progress
;
881 /* Whether the last depth/stencil packets were both NULL. */
882 bool no_depth_or_stencil
;
884 /* The last PMA stall bits programmed. */
885 uint32_t pma_stall_bits
;
889 /** The value of gl_BaseVertex for the current _mesa_prim. */
892 /** The value of gl_BaseInstance for the current _mesa_prim. */
897 * Buffer and offset used for GL_ARB_shader_draw_parameters
898 * (for now, only gl_BaseVertex).
900 struct brw_bo
*draw_params_bo
;
901 uint32_t draw_params_offset
;
904 * The value of gl_DrawID for the current _mesa_prim. This always comes
905 * in from it's own vertex buffer since it's not part of the indirect
909 struct brw_bo
*draw_id_bo
;
910 uint32_t draw_id_offset
;
913 * Pointer to the the buffer storing the indirect draw parameters. It
914 * currently only stores the number of requested draw calls but more
915 * parameters could potentially be added.
917 struct brw_bo
*draw_params_count_bo
;
918 uint32_t draw_params_count_offset
;
923 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
924 * an indirect call, and num_work_groups_offset is valid. Otherwise,
925 * num_work_groups is set based on glDispatchCompute.
927 struct brw_bo
*num_work_groups_bo
;
928 GLintptr num_work_groups_offset
;
929 const GLuint
*num_work_groups
;
933 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
934 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
936 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
940 /* Summary of size and varying of active arrays, so we can check
941 * for changes to this state:
943 bool index_bounds_valid
;
944 unsigned int min_index
, max_index
;
946 /* Offset from start of vertex buffer so we can avoid redefining
947 * the same VB packed over and over again.
949 unsigned int start_vertex_bias
;
952 * Certain vertex attribute formats aren't natively handled by the
953 * hardware and require special VS code to fix up their values.
955 * These bitfields indicate which workarounds are needed.
957 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
959 /* For the initial pushdown, keep the list of vbo inputs. */
960 struct vbo_inputs draw_arrays
;
965 * Index buffer for this draw_prims call.
967 * Updates are signaled by BRW_NEW_INDICES.
969 const struct _mesa_index_buffer
*ib
;
971 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
976 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
977 * avoid re-uploading the IB packet over and over if we're actually
978 * referencing the same index buffer.
980 unsigned int start_vertex_offset
;
983 /* Active vertex program:
985 struct gl_program
*programs
[MESA_SHADER_STAGES
];
988 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
989 * that we don't have to reemit that state every time we change FBOs.
991 unsigned int num_samples
;
993 /* BRW_NEW_URB_ALLOCATIONS:
996 GLuint vsize
; /* vertex size plus header in urb registers */
997 GLuint gsize
; /* GS output size in urb registers */
998 GLuint hsize
; /* Tessellation control output size in urb registers */
999 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
1000 GLuint csize
; /* constant buffer size in urb registers */
1001 GLuint sfsize
; /* setup data size in urb registers */
1005 GLuint nr_vs_entries
;
1006 GLuint nr_hs_entries
;
1007 GLuint nr_ds_entries
;
1008 GLuint nr_gs_entries
;
1009 GLuint nr_clip_entries
;
1010 GLuint nr_sf_entries
;
1011 GLuint nr_cs_entries
;
1021 * URB size in the current configuration. The units this is expressed
1022 * in are somewhat inconsistent, see gen_device_info::urb::size.
1024 * FINISHME: Represent the URB size consistently in KB on all platforms.
1028 /* True if the most recently sent _3DSTATE_URB message allocated
1029 * URB space for the GS.
1033 /* True if the most recently sent _3DSTATE_URB message allocated
1034 * URB space for the HS and DS.
1040 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1042 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1043 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1051 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1052 * for upload to the CURBE.
1054 struct brw_bo
*curbe_bo
;
1055 /** Offset within curbe_bo of space for current curbe entry */
1056 GLuint curbe_offset
;
1060 * Layout of vertex data exiting the geometry portion of the pipleine.
1061 * This comes from the last enabled shader stage (GS, DS, or VS).
1063 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1065 struct brw_vue_map vue_map_geom_out
;
1068 struct brw_stage_state base
;
1072 struct brw_stage_state base
;
1076 struct brw_stage_state base
;
1080 struct brw_stage_state base
;
1083 * True if the 3DSTATE_GS command most recently emitted to the 3D
1084 * pipeline enabled the GS; false otherwise.
1090 struct brw_ff_gs_prog_data
*prog_data
;
1093 /** Offset in the program cache to the CLIP program pre-gen6 */
1094 uint32_t prog_offset
;
1095 uint32_t state_offset
;
1097 uint32_t bind_bo_offset
;
1099 * Surface offsets for the binding table. We only need surfaces to
1100 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1101 * need in this case.
1103 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1107 struct brw_clip_prog_data
*prog_data
;
1109 /** Offset in the program cache to the CLIP program pre-gen6 */
1110 uint32_t prog_offset
;
1112 /* Offset in the batch to the CLIP state on pre-gen6. */
1113 uint32_t state_offset
;
1115 /* As of gen6, this is the offset in the batch to the CLIP VP,
1121 * The number of viewports to use. If gl_ViewportIndex is written,
1122 * we can have up to ctx->Const.MaxViewports viewports. If not,
1123 * the viewport index is always 0, so we can only emit one.
1125 uint8_t viewport_count
;
1130 struct brw_sf_prog_data
*prog_data
;
1132 /** Offset in the program cache to the CLIP program pre-gen6 */
1133 uint32_t prog_offset
;
1134 uint32_t state_offset
;
1139 struct brw_stage_state base
;
1142 * Buffer object used in place of multisampled null render targets on
1143 * Gen6. See brw_emit_null_surface_state().
1145 struct brw_bo
*multisampled_null_render_target_bo
;
1151 struct brw_stage_state base
;
1155 uint32_t state_offset
;
1156 uint32_t blend_state_offset
;
1157 uint32_t depth_stencil_state_offset
;
1162 struct brw_query_object
*obj
;
1167 enum brw_predicate_state state
;
1172 /* Variables referenced in the XML meta data for OA performance
1173 * counters, e.g in the normalization equations.
1175 * All uint64_t for consistent operand types in generated code
1178 uint64_t timestamp_frequency
; /** $GpuTimestampFrequency */
1179 uint64_t n_eus
; /** $EuCoresTotalCount */
1180 uint64_t n_eu_slices
; /** $EuSlicesTotalCount */
1181 uint64_t n_eu_sub_slices
; /** $EuSubslicesTotalCount */
1182 uint64_t eu_threads_count
; /** $EuThreadsCount */
1183 uint64_t slice_mask
; /** $SliceMask */
1184 uint64_t subslice_mask
; /** $SubsliceMask */
1185 uint64_t gt_min_freq
; /** $GpuMinFrequency */
1186 uint64_t gt_max_freq
; /** $GpuMaxFrequency */
1187 uint64_t revision
; /** $SkuRevisionId */
1190 /* OA metric sets, indexed by GUID, as know by Mesa at build time,
1191 * to cross-reference with the GUIDs of configs advertised by the
1194 struct hash_table
*oa_metrics_table
;
1196 /* Location of the device's sysfs entry. */
1197 char sysfs_dev_dir
[256];
1199 struct brw_perf_query_info
*queries
;
1202 /* The i915 perf stream we open to setup + enable the OA counters */
1205 /* An i915 perf stream fd gives exclusive access to the OA unit that will
1206 * report counter snapshots for a specific counter set/profile in a
1207 * specific layout/format so we can only start OA queries that are
1208 * compatible with the currently open fd...
1210 int current_oa_metrics_set_id
;
1211 int current_oa_format
;
1213 /* List of buffers containing OA reports */
1214 struct exec_list sample_buffers
;
1216 /* Cached list of empty sample buffers */
1217 struct exec_list free_sample_buffers
;
1219 int n_active_oa_queries
;
1220 int n_active_pipeline_stats_queries
;
1222 /* The number of queries depending on running OA counters which
1223 * extends beyond brw_end_perf_query() since we need to wait until
1224 * the last MI_RPC command has parsed by the GPU.
1226 * Accurate accounting is important here as emitting an
1227 * MI_REPORT_PERF_COUNT command while the OA unit is disabled will
1228 * effectively hang the gpu.
1232 /* To help catch an spurious problem with the hardware or perf
1233 * forwarding samples, we emit each MI_REPORT_PERF_COUNT command
1234 * with a unique ID that we can explicitly check for...
1236 int next_query_start_report_id
;
1239 * An array of queries whose results haven't yet been assembled
1240 * based on the data in buffer objects.
1242 * These may be active, or have already ended. However, the
1243 * results have not been requested.
1245 struct brw_perf_query_object
**unaccumulated
;
1246 int unaccumulated_elements
;
1247 int unaccumulated_array_size
;
1249 /* The total number of query objects so we can relinquish
1250 * our exclusive access to perf if the application deletes
1251 * all of its objects. (NB: We only disable perf while
1252 * there are no active queries)
1254 int n_query_instances
;
1257 int num_atoms
[BRW_NUM_PIPELINES
];
1258 const struct brw_tracked_state render_atoms
[76];
1259 const struct brw_tracked_state compute_atoms
[11];
1261 const enum isl_format
*mesa_to_isl_render_format
;
1262 const bool *mesa_format_supports_render
;
1264 /* PrimitiveRestart */
1267 bool enable_cut_index
;
1270 /** Computed depth/stencil/hiz state from the current attached
1271 * renderbuffers, valid only during the drawing state upload loop after
1272 * brw_workaround_depthstencil_alignment().
1275 /* Inter-tile (page-aligned) byte offsets. */
1276 uint32_t depth_offset
;
1277 /* Intra-tile x,y offsets for drawing to combined depth-stencil. Only
1280 uint32_t tile_x
, tile_y
;
1283 uint32_t num_instances
;
1288 const struct gen_l3_config
*config
;
1295 enum shader_time_shader_type
*types
;
1296 struct shader_times
*cumulative
;
1302 struct brw_fast_clear_state
*fast_clear_state
;
1304 /* Array of aux usages to use for drawing. Aux usage for render targets is
1305 * a bit more complex than simply calling a single function so we need some
1306 * way of passing it form brw_draw.c to surface state setup.
1308 enum isl_aux_usage draw_aux_usage
[MAX_DRAW_BUFFERS
];
1310 __DRIcontext
*driContext
;
1311 struct intel_screen
*screen
;
1315 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1317 /*======================================================================
1320 extern const char *const brw_vendor_string
;
1323 brw_get_renderer_string(const struct intel_screen
*screen
);
1326 DRI_CONF_BO_REUSE_DISABLED
,
1327 DRI_CONF_BO_REUSE_ALL
1330 void intel_update_renderbuffers(__DRIcontext
*context
,
1331 __DRIdrawable
*drawable
);
1332 void intel_prepare_render(struct brw_context
*brw
);
1334 void brw_predraw_resolve_inputs(struct brw_context
*brw
, bool rendering
,
1335 bool *draw_aux_buffer_disabled
);
1337 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1338 __DRIdrawable
*drawable
);
1340 GLboolean
brwCreateContext(gl_api api
,
1341 const struct gl_config
*mesaVis
,
1342 __DRIcontext
*driContextPriv
,
1343 const struct __DriverContextConfig
*ctx_config
,
1345 void *sharedContextPrivate
);
1347 /*======================================================================
1351 brw_meta_resolve_color(struct brw_context
*brw
,
1352 struct intel_mipmap_tree
*mt
);
1354 /*======================================================================
1357 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1358 GLbitfield clear_mask
);
1360 /* brw_object_purgeable.c */
1361 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1363 /*======================================================================
1366 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1367 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1368 void brw_emit_query_begin(struct brw_context
*brw
);
1369 void brw_emit_query_end(struct brw_context
*brw
);
1370 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1371 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1372 uint64_t brw_timebase_scale(struct brw_context
*brw
, uint64_t gpu_timestamp
);
1373 uint64_t brw_raw_timestamp_delta(struct brw_context
*brw
,
1374 uint64_t time0
, uint64_t time1
);
1376 /** gen6_queryobj.c */
1377 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1378 void brw_write_timestamp(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1379 void brw_write_depth_count(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1381 /** hsw_queryobj.c */
1382 void hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
1383 struct brw_query_object
*query
,
1385 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1387 /** brw_conditional_render.c */
1388 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1389 bool brw_check_conditional_render(struct brw_context
*brw
);
1391 /** intel_batchbuffer.c */
1392 void brw_load_register_mem(struct brw_context
*brw
,
1396 void brw_load_register_mem64(struct brw_context
*brw
,
1400 void brw_store_register_mem32(struct brw_context
*brw
,
1401 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1402 void brw_store_register_mem64(struct brw_context
*brw
,
1403 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1404 void brw_load_register_imm32(struct brw_context
*brw
,
1405 uint32_t reg
, uint32_t imm
);
1406 void brw_load_register_imm64(struct brw_context
*brw
,
1407 uint32_t reg
, uint64_t imm
);
1408 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1410 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1412 void brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1413 uint32_t offset
, uint32_t imm
);
1414 void brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1415 uint32_t offset
, uint64_t imm
);
1417 /*======================================================================
1418 * intel_tex_validate.c
1420 void brw_validate_textures( struct brw_context
*brw
);
1423 /*======================================================================
1427 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1430 perf_debug(" %s %d->%d\n", name
, a
, b
);
1436 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1438 void brw_get_scratch_bo(struct brw_context
*brw
,
1439 struct brw_bo
**scratch_bo
, int size
);
1440 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1441 struct brw_stage_state
*stage_state
,
1442 unsigned per_thread_size
);
1443 void brw_init_shader_time(struct brw_context
*brw
);
1444 int brw_get_shader_time_index(struct brw_context
*brw
,
1445 struct gl_program
*prog
,
1446 enum shader_time_shader_type type
,
1448 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1449 void brw_destroy_shader_time(struct brw_context
*brw
);
1453 void brw_calculate_urb_fence(struct brw_context
*brw
, unsigned csize
,
1454 unsigned vsize
, unsigned sfsize
);
1455 void brw_upload_urb_fence(struct brw_context
*brw
);
1459 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1462 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1464 /* brw_draw_upload.c */
1465 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1466 const struct gl_array_attributes
*glattr
);
1468 static inline unsigned
1469 brw_get_index_type(unsigned index_size
)
1471 /* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint,
1474 return index_size
>> 1;
1477 void brw_prepare_vertices(struct brw_context
*brw
);
1479 /* brw_wm_surface_state.c */
1480 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1482 uint32_t *surf_offset
);
1484 brw_update_sol_surface(struct brw_context
*brw
,
1485 struct gl_buffer_object
*buffer_obj
,
1486 uint32_t *out_offset
, unsigned num_vector_components
,
1487 unsigned stride_dwords
, unsigned offset_dwords
);
1488 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1489 struct brw_stage_state
*stage_state
,
1490 struct brw_stage_prog_data
*prog_data
);
1491 void brw_upload_image_surfaces(struct brw_context
*brw
,
1492 const struct gl_program
*prog
,
1493 struct brw_stage_state
*stage_state
,
1494 struct brw_stage_prog_data
*prog_data
);
1496 /* brw_surface_formats.c */
1497 void intel_screen_init_surface_formats(struct intel_screen
*screen
);
1498 void brw_init_surface_formats(struct brw_context
*brw
);
1499 bool brw_render_target_supported(struct brw_context
*brw
,
1500 struct gl_renderbuffer
*rb
);
1501 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1503 /* brw_performance_query.c */
1504 void brw_init_performance_queries(struct brw_context
*brw
);
1506 /* intel_extensions.c */
1507 extern void intelInitExtensions(struct gl_context
*ctx
);
1510 extern int intel_translate_shadow_compare_func(GLenum func
);
1511 extern int intel_translate_compare_func(GLenum func
);
1512 extern int intel_translate_stencil_op(GLenum op
);
1515 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1518 struct gl_transform_feedback_object
*
1519 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1521 brw_delete_transform_feedback(struct gl_context
*ctx
,
1522 struct gl_transform_feedback_object
*obj
);
1524 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1525 struct gl_transform_feedback_object
*obj
);
1527 brw_end_transform_feedback(struct gl_context
*ctx
,
1528 struct gl_transform_feedback_object
*obj
);
1530 brw_pause_transform_feedback(struct gl_context
*ctx
,
1531 struct gl_transform_feedback_object
*obj
);
1533 brw_resume_transform_feedback(struct gl_context
*ctx
,
1534 struct gl_transform_feedback_object
*obj
);
1536 brw_save_primitives_written_counters(struct brw_context
*brw
,
1537 struct brw_transform_feedback_object
*obj
);
1539 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1540 struct gl_transform_feedback_object
*obj
,
1543 /* gen7_sol_state.c */
1545 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1546 struct gl_transform_feedback_object
*obj
);
1548 gen7_end_transform_feedback(struct gl_context
*ctx
,
1549 struct gl_transform_feedback_object
*obj
);
1551 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1552 struct gl_transform_feedback_object
*obj
);
1554 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1555 struct gl_transform_feedback_object
*obj
);
1559 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1560 struct gl_transform_feedback_object
*obj
);
1562 hsw_end_transform_feedback(struct gl_context
*ctx
,
1563 struct gl_transform_feedback_object
*obj
);
1565 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1566 struct gl_transform_feedback_object
*obj
);
1568 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1569 struct gl_transform_feedback_object
*obj
);
1571 /* brw_blorp_blit.cpp */
1573 brw_blorp_framebuffer(struct brw_context
*brw
,
1574 struct gl_framebuffer
*readFb
,
1575 struct gl_framebuffer
*drawFb
,
1576 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1577 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1578 GLbitfield mask
, GLenum filter
);
1581 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1582 struct gl_renderbuffer
*src_rb
,
1583 struct gl_texture_image
*dst_image
,
1585 int srcX0
, int srcY0
,
1586 int dstX0
, int dstY0
,
1587 int width
, int height
);
1589 /* brw_generate_mipmap.c */
1590 void brw_generate_mipmap(struct gl_context
*ctx
, GLenum target
,
1591 struct gl_texture_object
*tex_obj
);
1594 gen6_get_sample_position(struct gl_context
*ctx
,
1595 struct gl_framebuffer
*fb
,
1599 gen6_set_sample_maps(struct gl_context
*ctx
);
1601 /* gen8_multisample_state.c */
1602 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1606 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1607 unsigned hs_size
, unsigned ds_size
,
1608 unsigned gs_size
, unsigned fs_size
);
1611 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1612 bool gs_present
, unsigned gs_size
);
1614 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1615 bool gs_present
, bool tess_present
);
1619 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1621 brw_check_for_reset(struct brw_context
*brw
);
1625 brw_init_compute_functions(struct dd_function_table
*functions
);
1627 /* brw_program_binary.c */
1629 brw_program_binary_init(unsigned device_id
);
1631 brw_get_program_binary_driver_sha1(struct gl_context
*ctx
, uint8_t *sha1
);
1633 brw_deserialize_program_binary(struct gl_context
*ctx
,
1634 struct gl_shader_program
*shProg
,
1635 struct gl_program
*prog
);
1637 brw_program_serialize_nir(struct gl_context
*ctx
, struct gl_program
*prog
);
1639 brw_program_deserialize_nir(struct gl_context
*ctx
, struct gl_program
*prog
,
1640 gl_shader_stage stage
);
1642 /*======================================================================
1643 * Inline conversion functions. These are better-typed than the
1644 * macros used previously:
1646 static inline struct brw_context
*
1647 brw_context( struct gl_context
*ctx
)
1649 return (struct brw_context
*)ctx
;
1652 static inline struct brw_program
*
1653 brw_program(struct gl_program
*p
)
1655 return (struct brw_program
*) p
;
1658 static inline const struct brw_program
*
1659 brw_program_const(const struct gl_program
*p
)
1661 return (const struct brw_program
*) p
;
1665 brw_depth_writes_enabled(const struct brw_context
*brw
)
1667 const struct gl_context
*ctx
= &brw
->ctx
;
1669 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1670 * because it would just overwrite the existing depth value with itself.
1672 * These bonus depth writes not only use bandwidth, but they also can
1673 * prevent early depth processing. For example, if the pixel shader
1674 * discards, the hardware must invoke the to determine whether or not
1675 * to do the depth write. If writes are disabled, we may still be able
1676 * to do the depth test before the shader, and skip the shader execution.
1678 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1679 * a programming note saying to disable depth writes for EQUAL.
1681 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1685 brw_emit_depthbuffer(struct brw_context
*brw
);
1688 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1689 struct intel_mipmap_tree
*depth_mt
,
1690 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1691 uint32_t depth_surface_type
,
1692 struct intel_mipmap_tree
*stencil_mt
,
1693 bool hiz
, bool separate_stencil
,
1694 uint32_t width
, uint32_t height
,
1695 uint32_t tile_x
, uint32_t tile_y
);
1698 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1699 struct intel_mipmap_tree
*depth_mt
,
1700 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1701 uint32_t depth_surface_type
,
1702 struct intel_mipmap_tree
*stencil_mt
,
1703 bool hiz
, bool separate_stencil
,
1704 uint32_t width
, uint32_t height
,
1705 uint32_t tile_x
, uint32_t tile_y
);
1708 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1709 struct intel_mipmap_tree
*depth_mt
,
1710 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1711 uint32_t depth_surface_type
,
1712 struct intel_mipmap_tree
*stencil_mt
,
1713 bool hiz
, bool separate_stencil
,
1714 uint32_t width
, uint32_t height
,
1715 uint32_t tile_x
, uint32_t tile_y
);
1717 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1718 struct intel_mipmap_tree
*depth_mt
,
1719 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1720 uint32_t depth_surface_type
,
1721 struct intel_mipmap_tree
*stencil_mt
,
1722 bool hiz
, bool separate_stencil
,
1723 uint32_t width
, uint32_t height
,
1724 uint32_t tile_x
, uint32_t tile_y
);
1726 uint32_t get_hw_prim_for_gl_prim(int mode
);
1729 gen6_upload_push_constants(struct brw_context
*brw
,
1730 const struct gl_program
*prog
,
1731 const struct brw_stage_prog_data
*prog_data
,
1732 struct brw_stage_state
*stage_state
);
1735 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1736 const struct intel_mipmap_tree
*mt
);
1738 /* brw_queryformat.c */
1739 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1740 GLenum internalFormat
, GLenum pname
,