Merge branch 'master' of ../mesa into vulkan
[mesa.git] / src / mesa / drivers / dri / i965 / brw_device_info.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <stdlib.h>
26 #include "brw_device_info.h"
27
28 static const struct brw_device_info brw_device_info_i965 = {
29 .gen = 4,
30 .has_negative_rhw_bug = true,
31 .max_vs_threads = 16,
32 .max_gs_threads = 2,
33 .max_wm_threads = 8 * 4,
34 .urb = {
35 .size = 256,
36 },
37 };
38
39 static const struct brw_device_info brw_device_info_g4x = {
40 .gen = 4,
41 .has_pln = true,
42 .has_compr4 = true,
43 .has_surface_tile_offset = true,
44 .is_g4x = true,
45 .max_vs_threads = 32,
46 .max_gs_threads = 2,
47 .max_wm_threads = 10 * 5,
48 .urb = {
49 .size = 384,
50 },
51 };
52
53 static const struct brw_device_info brw_device_info_ilk = {
54 .gen = 5,
55 .has_pln = true,
56 .has_compr4 = true,
57 .has_surface_tile_offset = true,
58 .max_vs_threads = 72,
59 .max_gs_threads = 32,
60 .max_wm_threads = 12 * 6,
61 .urb = {
62 .size = 1024,
63 },
64 };
65
66 static const struct brw_device_info brw_device_info_snb_gt1 = {
67 .gen = 6,
68 .gt = 1,
69 .has_hiz_and_separate_stencil = true,
70 .has_llc = true,
71 .has_pln = true,
72 .has_surface_tile_offset = true,
73 .needs_unlit_centroid_workaround = true,
74 .max_vs_threads = 24,
75 .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
76 .max_wm_threads = 40,
77 .urb = {
78 .size = 32,
79 .min_vs_entries = 24,
80 .max_vs_entries = 256,
81 .max_gs_entries = 256,
82 },
83 };
84
85 static const struct brw_device_info brw_device_info_snb_gt2 = {
86 .gen = 6,
87 .gt = 2,
88 .has_hiz_and_separate_stencil = true,
89 .has_llc = true,
90 .has_pln = true,
91 .has_surface_tile_offset = true,
92 .needs_unlit_centroid_workaround = true,
93 .max_vs_threads = 60,
94 .max_gs_threads = 60,
95 .max_wm_threads = 80,
96 .urb = {
97 .size = 64,
98 .min_vs_entries = 24,
99 .max_vs_entries = 256,
100 .max_gs_entries = 256,
101 },
102 };
103
104 #define GEN7_FEATURES \
105 .gen = 7, \
106 .has_hiz_and_separate_stencil = true, \
107 .must_use_separate_stencil = true, \
108 .has_llc = true, \
109 .has_pln = true, \
110 .has_surface_tile_offset = true
111
112 static const struct brw_device_info brw_device_info_ivb_gt1 = {
113 GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
114 .needs_unlit_centroid_workaround = true,
115 .max_vs_threads = 36,
116 .max_hs_threads = 36,
117 .max_ds_threads = 36,
118 .max_gs_threads = 36,
119 .max_wm_threads = 48,
120 .max_cs_threads = 36,
121 .urb = {
122 .size = 128,
123 .min_vs_entries = 32,
124 .max_vs_entries = 512,
125 .max_hs_entries = 32,
126 .max_ds_entries = 288,
127 .max_gs_entries = 192,
128 },
129 };
130
131 static const struct brw_device_info brw_device_info_ivb_gt2 = {
132 GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
133 .needs_unlit_centroid_workaround = true,
134 .max_vs_threads = 128,
135 .max_hs_threads = 128,
136 .max_ds_threads = 128,
137 .max_gs_threads = 128,
138 .max_wm_threads = 172,
139 .max_cs_threads = 64,
140 .urb = {
141 .size = 256,
142 .min_vs_entries = 32,
143 .max_vs_entries = 704,
144 .max_hs_entries = 64,
145 .max_ds_entries = 448,
146 .max_gs_entries = 320,
147 },
148 };
149
150 static const struct brw_device_info brw_device_info_byt = {
151 GEN7_FEATURES, .is_baytrail = true, .gt = 1,
152 .needs_unlit_centroid_workaround = true,
153 .has_llc = false,
154 .max_vs_threads = 36,
155 .max_hs_threads = 36,
156 .max_ds_threads = 36,
157 .max_gs_threads = 36,
158 .max_wm_threads = 48,
159 .max_cs_threads = 32,
160 .urb = {
161 .size = 128,
162 .min_vs_entries = 32,
163 .max_vs_entries = 512,
164 .max_hs_entries = 32,
165 .max_ds_entries = 288,
166 .max_gs_entries = 192,
167 },
168 };
169
170 #define HSW_FEATURES \
171 GEN7_FEATURES, \
172 .is_haswell = true, \
173 .supports_simd16_3src = true, \
174 .has_resource_streamer = true
175
176 static const struct brw_device_info brw_device_info_hsw_gt1 = {
177 HSW_FEATURES, .gt = 1,
178 .max_vs_threads = 70,
179 .max_hs_threads = 70,
180 .max_ds_threads = 70,
181 .max_gs_threads = 70,
182 .max_wm_threads = 102,
183 .max_cs_threads = 70,
184 .urb = {
185 .size = 128,
186 .min_vs_entries = 32,
187 .max_vs_entries = 640,
188 .max_hs_entries = 64,
189 .max_ds_entries = 384,
190 .max_gs_entries = 256,
191 },
192 };
193
194 static const struct brw_device_info brw_device_info_hsw_gt2 = {
195 HSW_FEATURES, .gt = 2,
196 .max_vs_threads = 280,
197 .max_hs_threads = 256,
198 .max_ds_threads = 280,
199 .max_gs_threads = 256,
200 .max_wm_threads = 204,
201 .max_cs_threads = 70,
202 .urb = {
203 .size = 256,
204 .min_vs_entries = 64,
205 .max_vs_entries = 1664,
206 .max_hs_entries = 128,
207 .max_ds_entries = 960,
208 .max_gs_entries = 640,
209 },
210 };
211
212 static const struct brw_device_info brw_device_info_hsw_gt3 = {
213 HSW_FEATURES, .gt = 3,
214 .max_vs_threads = 280,
215 .max_hs_threads = 256,
216 .max_ds_threads = 280,
217 .max_gs_threads = 256,
218 .max_wm_threads = 408,
219 .max_cs_threads = 70,
220 .urb = {
221 .size = 512,
222 .min_vs_entries = 64,
223 .max_vs_entries = 1664,
224 .max_hs_entries = 128,
225 .max_ds_entries = 960,
226 .max_gs_entries = 640,
227 },
228 };
229
230 #define GEN8_FEATURES \
231 .gen = 8, \
232 .has_hiz_and_separate_stencil = true, \
233 .has_resource_streamer = true, \
234 .must_use_separate_stencil = true, \
235 .has_llc = true, \
236 .has_pln = true, \
237 .supports_simd16_3src = true, \
238 .max_vs_threads = 504, \
239 .max_hs_threads = 504, \
240 .max_ds_threads = 504, \
241 .max_gs_threads = 504, \
242 .max_wm_threads = 384
243
244 static const struct brw_device_info brw_device_info_bdw_gt1 = {
245 GEN8_FEATURES, .gt = 1,
246 .max_cs_threads = 42,
247 .urb = {
248 .size = 192,
249 .min_vs_entries = 64,
250 .max_vs_entries = 2560,
251 .max_hs_entries = 504,
252 .max_ds_entries = 1536,
253 .max_gs_entries = 960,
254 }
255 };
256
257 static const struct brw_device_info brw_device_info_bdw_gt2 = {
258 GEN8_FEATURES, .gt = 2,
259 .max_cs_threads = 56,
260 .urb = {
261 .size = 384,
262 .min_vs_entries = 64,
263 .max_vs_entries = 2560,
264 .max_hs_entries = 504,
265 .max_ds_entries = 1536,
266 .max_gs_entries = 960,
267 }
268 };
269
270 static const struct brw_device_info brw_device_info_bdw_gt3 = {
271 GEN8_FEATURES, .gt = 3,
272 .max_cs_threads = 56,
273 .urb = {
274 .size = 384,
275 .min_vs_entries = 64,
276 .max_vs_entries = 2560,
277 .max_hs_entries = 504,
278 .max_ds_entries = 1536,
279 .max_gs_entries = 960,
280 }
281 };
282
283 static const struct brw_device_info brw_device_info_chv = {
284 GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
285 .has_llc = false,
286 .max_vs_threads = 80,
287 .max_hs_threads = 80,
288 .max_ds_threads = 80,
289 .max_gs_threads = 80,
290 .max_wm_threads = 128,
291 .max_cs_threads = 28,
292 .urb = {
293 .size = 192,
294 .min_vs_entries = 34,
295 .max_vs_entries = 640,
296 .max_hs_entries = 80,
297 .max_ds_entries = 384,
298 .max_gs_entries = 256,
299 }
300 };
301
302 #define GEN9_FEATURES \
303 .gen = 9, \
304 .has_hiz_and_separate_stencil = true, \
305 .has_resource_streamer = true, \
306 .must_use_separate_stencil = true, \
307 .has_llc = true, \
308 .has_pln = true, \
309 .supports_simd16_3src = true, \
310 .max_vs_threads = 336, \
311 .max_gs_threads = 336, \
312 .max_hs_threads = 336, \
313 .max_ds_threads = 336, \
314 .max_wm_threads = 64 * 6, \
315 .max_cs_threads = 56, \
316 .urb = { \
317 .size = 384, \
318 .min_vs_entries = 64, \
319 .max_vs_entries = 1856, \
320 .max_hs_entries = 672, \
321 .max_ds_entries = 1120, \
322 .max_gs_entries = 640, \
323 }
324
325 static const struct brw_device_info brw_device_info_skl_gt1 = {
326 GEN9_FEATURES, .gt = 1,
327 .urb.size = 192,
328 };
329
330 static const struct brw_device_info brw_device_info_skl_gt2 = {
331 GEN9_FEATURES, .gt = 2,
332 };
333
334 static const struct brw_device_info brw_device_info_skl_gt3 = {
335 GEN9_FEATURES, .gt = 3,
336 };
337
338 static const struct brw_device_info brw_device_info_bxt = {
339 GEN9_FEATURES,
340 .is_broxton = 1,
341 .gt = 1,
342 .has_llc = false,
343
344 /* XXX: These are preliminary thread counts and URB sizes. */
345 .max_vs_threads = 56,
346 .max_hs_threads = 56,
347 .max_ds_threads = 56,
348 .max_gs_threads = 56,
349 .max_wm_threads = 32,
350 .max_cs_threads = 28,
351 .urb = {
352 .size = 64,
353 .min_vs_entries = 34,
354 .max_vs_entries = 640,
355 .max_hs_entries = 80,
356 .max_ds_entries = 80,
357 .max_gs_entries = 256,
358 }
359 };
360
361 const struct brw_device_info *
362 brw_get_device_info(int devid, int revision)
363 {
364 const struct brw_device_info *devinfo;
365 switch (devid) {
366 #undef CHIPSET
367 #define CHIPSET(id, family, name) \
368 case id: devinfo = &brw_device_info_##family; break;
369 #include "pci_ids/i965_pci_ids.h"
370 default:
371 fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
372 return NULL;
373 }
374
375 return devinfo;
376 }
377
378 const char *
379 brw_get_device_name(int devid)
380 {
381 switch (devid) {
382 #undef CHIPSET
383 #define CHIPSET(id, family, name) case id: return name;
384 #include "pci_ids/i965_pci_ids.h"
385 default:
386 return NULL;
387 }
388 }