2 * Copyright © 2013 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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26 #include "brw_device_info.h"
28 static const struct brw_device_info brw_device_info_i965
= {
30 .has_negative_rhw_bug
= true,
31 .needs_unlit_centroid_workaround
= true,
34 .max_wm_threads
= 8 * 4,
40 static const struct brw_device_info brw_device_info_g4x
= {
44 .needs_unlit_centroid_workaround
= true,
48 .max_wm_threads
= 10 * 5,
54 static const struct brw_device_info brw_device_info_ilk
= {
58 .has_surface_tile_offset
= true,
59 .needs_unlit_centroid_workaround
= true,
62 .max_wm_threads
= 12 * 6,
68 static const struct brw_device_info brw_device_info_snb_gt1
= {
71 .has_hiz_and_separate_stencil
= true,
74 .has_surface_tile_offset
= true,
75 .needs_unlit_centroid_workaround
= true,
77 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
82 .max_vs_entries
= 256,
83 .max_gs_entries
= 256,
87 static const struct brw_device_info brw_device_info_snb_gt2
= {
90 .has_hiz_and_separate_stencil
= true,
93 .has_surface_tile_offset
= true,
94 .needs_unlit_centroid_workaround
= true,
100 .min_vs_entries
= 24,
101 .max_vs_entries
= 256,
102 .max_gs_entries
= 256,
106 #define GEN7_FEATURES \
108 .has_hiz_and_separate_stencil = true, \
109 .must_use_separate_stencil = true, \
112 .has_surface_tile_offset = true, \
113 .needs_unlit_centroid_workaround = true
115 static const struct brw_device_info brw_device_info_ivb_gt1
= {
116 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
117 .max_vs_threads
= 36,
118 .max_gs_threads
= 36,
119 .max_wm_threads
= 48,
122 .min_vs_entries
= 32,
123 .max_vs_entries
= 512,
124 .max_gs_entries
= 192,
128 static const struct brw_device_info brw_device_info_ivb_gt2
= {
129 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
130 .max_vs_threads
= 128,
131 .max_gs_threads
= 128,
132 .max_wm_threads
= 172,
135 .min_vs_entries
= 32,
136 .max_vs_entries
= 704,
137 .max_gs_entries
= 320,
141 static const struct brw_device_info brw_device_info_byt
= {
142 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
144 .max_vs_threads
= 36,
145 .max_gs_threads
= 36,
146 .max_wm_threads
= 48,
149 .min_vs_entries
= 32,
150 .max_vs_entries
= 512,
151 .max_gs_entries
= 192,
155 static const struct brw_device_info brw_device_info_hsw_gt1
= {
156 GEN7_FEATURES
, .is_haswell
= true, .gt
= 1,
157 .max_vs_threads
= 70,
158 .max_gs_threads
= 70,
159 .max_wm_threads
= 102,
162 .min_vs_entries
= 32,
163 .max_vs_entries
= 640,
164 .max_gs_entries
= 256,
168 static const struct brw_device_info brw_device_info_hsw_gt2
= {
169 GEN7_FEATURES
, .is_haswell
= true, .gt
= 2,
170 .max_vs_threads
= 280,
171 .max_gs_threads
= 256,
172 .max_wm_threads
= 204,
175 .min_vs_entries
= 64,
176 .max_vs_entries
= 1664,
177 .max_gs_entries
= 640,
181 static const struct brw_device_info brw_device_info_hsw_gt3
= {
182 GEN7_FEATURES
, .is_haswell
= true, .gt
= 3,
183 .max_vs_threads
= 280,
184 .max_gs_threads
= 256,
185 .max_wm_threads
= 408,
188 .min_vs_entries
= 64,
189 .max_vs_entries
= 1664,
190 .max_gs_entries
= 640,
194 const struct brw_device_info
*
195 brw_get_device_info(int devid
)
199 #define CHIPSET(id, family, name) case id: return &brw_device_info_##family;
200 #include "pci_ids/i965_pci_ids.h"
202 fprintf(stderr
, "Unknown Intel device.");