i965: Mark SNB GT1 as a GT1.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_device_info.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <stdlib.h>
26 #include "brw_device_info.h"
27
28 static const struct brw_device_info brw_device_info_i965 = {
29 .gen = 4,
30 .has_negative_rhw_bug = true,
31 .needs_unlit_centroid_workaround = true,
32 .max_vs_threads = 16,
33 .max_gs_threads = 2,
34 .max_wm_threads = 8 * 4,
35 .urb = {
36 .size = 256,
37 },
38 };
39
40 static const struct brw_device_info brw_device_info_g4x = {
41 .gen = 4,
42 .has_pln = true,
43 .has_compr4 = true,
44 .has_surface_tile_offset = true,
45 .needs_unlit_centroid_workaround = true,
46 .is_g4x = true,
47 .max_vs_threads = 32,
48 .max_gs_threads = 2,
49 .max_wm_threads = 10 * 5,
50 .urb = {
51 .size = 384,
52 },
53 };
54
55 static const struct brw_device_info brw_device_info_ilk = {
56 .gen = 5,
57 .has_pln = true,
58 .has_compr4 = true,
59 .has_surface_tile_offset = true,
60 .needs_unlit_centroid_workaround = true,
61 .max_vs_threads = 72,
62 .max_gs_threads = 32,
63 .max_wm_threads = 12 * 6,
64 .urb = {
65 .size = 1024,
66 },
67 };
68
69 static const struct brw_device_info brw_device_info_snb_gt1 = {
70 .gen = 6,
71 .gt = 1,
72 .has_hiz_and_separate_stencil = true,
73 .has_llc = true,
74 .has_pln = true,
75 .has_surface_tile_offset = true,
76 .needs_unlit_centroid_workaround = true,
77 .max_vs_threads = 24,
78 .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
79 .max_wm_threads = 40,
80 .urb = {
81 .size = 32,
82 .min_vs_entries = 24,
83 .max_vs_entries = 256,
84 .max_gs_entries = 256,
85 },
86 };
87
88 static const struct brw_device_info brw_device_info_snb_gt2 = {
89 .gen = 6,
90 .gt = 2,
91 .has_hiz_and_separate_stencil = true,
92 .has_llc = true,
93 .has_pln = true,
94 .has_surface_tile_offset = true,
95 .needs_unlit_centroid_workaround = true,
96 .max_vs_threads = 60,
97 .max_gs_threads = 60,
98 .max_wm_threads = 80,
99 .urb = {
100 .size = 64,
101 .min_vs_entries = 24,
102 .max_vs_entries = 256,
103 .max_gs_entries = 256,
104 },
105 };
106
107 #define GEN7_FEATURES \
108 .gen = 7, \
109 .has_hiz_and_separate_stencil = true, \
110 .must_use_separate_stencil = true, \
111 .has_llc = true, \
112 .has_pln = true, \
113 .has_surface_tile_offset = true, \
114 .needs_unlit_centroid_workaround = true
115
116 static const struct brw_device_info brw_device_info_ivb_gt1 = {
117 GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
118 .max_vs_threads = 36,
119 .max_gs_threads = 36,
120 .max_wm_threads = 48,
121 .urb = {
122 .size = 128,
123 .min_vs_entries = 32,
124 .max_vs_entries = 512,
125 .max_gs_entries = 192,
126 },
127 };
128
129 static const struct brw_device_info brw_device_info_ivb_gt2 = {
130 GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
131 .max_vs_threads = 128,
132 .max_gs_threads = 128,
133 .max_wm_threads = 172,
134 .urb = {
135 .size = 256,
136 .min_vs_entries = 32,
137 .max_vs_entries = 704,
138 .max_gs_entries = 320,
139 },
140 };
141
142 static const struct brw_device_info brw_device_info_byt = {
143 GEN7_FEATURES, .is_baytrail = true, .gt = 1,
144 .has_llc = false,
145 .max_vs_threads = 36,
146 .max_gs_threads = 36,
147 .max_wm_threads = 48,
148 .urb = {
149 .size = 128,
150 .min_vs_entries = 32,
151 .max_vs_entries = 512,
152 .max_gs_entries = 192,
153 },
154 };
155
156 static const struct brw_device_info brw_device_info_hsw_gt1 = {
157 GEN7_FEATURES, .is_haswell = true, .gt = 1,
158 .max_vs_threads = 70,
159 .max_gs_threads = 70,
160 .max_wm_threads = 102,
161 .urb = {
162 .size = 128,
163 .min_vs_entries = 32,
164 .max_vs_entries = 640,
165 .max_gs_entries = 256,
166 },
167 };
168
169 static const struct brw_device_info brw_device_info_hsw_gt2 = {
170 GEN7_FEATURES, .is_haswell = true, .gt = 2,
171 .max_vs_threads = 280,
172 .max_gs_threads = 256,
173 .max_wm_threads = 204,
174 .urb = {
175 .size = 256,
176 .min_vs_entries = 64,
177 .max_vs_entries = 1664,
178 .max_gs_entries = 640,
179 },
180 };
181
182 static const struct brw_device_info brw_device_info_hsw_gt3 = {
183 GEN7_FEATURES, .is_haswell = true, .gt = 3,
184 .max_vs_threads = 280,
185 .max_gs_threads = 256,
186 .max_wm_threads = 408,
187 .urb = {
188 .size = 512,
189 .min_vs_entries = 64,
190 .max_vs_entries = 1664,
191 .max_gs_entries = 640,
192 },
193 };
194
195 /* Thread counts and URB limits are placeholders, and may not be accurate. */
196 #define GEN8_FEATURES \
197 .gen = 8, \
198 .has_hiz_and_separate_stencil = true, \
199 .must_use_separate_stencil = true, \
200 .has_llc = true, \
201 .has_pln = true, \
202 .max_vs_threads = 280, \
203 .max_gs_threads = 256, \
204 .max_wm_threads = 408, \
205 .urb = { \
206 .size = 128, \
207 .min_vs_entries = 64, \
208 .max_vs_entries = 1664, \
209 .max_gs_entries = 640, \
210 }
211
212 static const struct brw_device_info brw_device_info_bdw_gt1 = {
213 GEN8_FEATURES, .gt = 1,
214 };
215
216 static const struct brw_device_info brw_device_info_bdw_gt2 = {
217 GEN8_FEATURES, .gt = 2,
218 };
219
220 static const struct brw_device_info brw_device_info_bdw_gt3 = {
221 GEN8_FEATURES, .gt = 3,
222 };
223
224 /* Thread counts and URB limits are placeholders, and may not be accurate.
225 * These were copied from Haswell GT1, above.
226 */
227 static const struct brw_device_info brw_device_info_chv = {
228 GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
229 .has_llc = false,
230 .max_vs_threads = 70,
231 .max_gs_threads = 70,
232 .max_wm_threads = 102,
233 .urb = {
234 .max_vs_entries = 640,
235 .max_gs_entries = 256,
236 }
237 };
238
239 const struct brw_device_info *
240 brw_get_device_info(int devid)
241 {
242 switch (devid) {
243 #undef CHIPSET
244 #define CHIPSET(id, family, name) case id: return &brw_device_info_##family;
245 #include "pci_ids/i965_pci_ids.h"
246 default:
247 fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
248 return NULL;
249 }
250 }