src/mesa/drivers/dri/i965/brw_device_info.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdio.h>
  25 #include <stdlib.h>
  26 #include "brw_device_info.h"
  27
  28 static const struct brw_device_info brw_device_info_i965 = {
  29    .gen = 4,
  30    .has_negative_rhw_bug = true,
  31    .max_vs_threads = 16,
  32    .max_gs_threads = 2,
  33    .max_wm_threads = 8 * 4,
  34    .urb = {
  35       .size = 256,
  36    },
  37 };
  38
  39 static const struct brw_device_info brw_device_info_g4x = {
  40    .gen = 4,
  41    .has_pln = true,
  42    .has_compr4 = true,
  43    .has_surface_tile_offset = true,
  44    .is_g4x = true,
  45    .max_vs_threads = 32,
  46    .max_gs_threads = 2,
  47    .max_wm_threads = 10 * 5,
  48    .urb = {
  49       .size = 384,
  50    },
  51 };
  52
  53 static const struct brw_device_info brw_device_info_ilk = {
  54    .gen = 5,
  55    .has_pln = true,
  56    .has_compr4 = true,
  57    .has_surface_tile_offset = true,
  58    .max_vs_threads = 72,
  59    .max_gs_threads = 32,
  60    .max_wm_threads = 12 * 6,
  61    .urb = {
  62       .size = 1024,
  63    },
  64 };
  65
  66 static const struct brw_device_info brw_device_info_snb_gt1 = {
  67    .gen = 6,
  68    .gt = 1,
  69    .has_hiz_and_separate_stencil = true,
  70    .has_llc = true,
  71    .has_pln = true,
  72    .has_surface_tile_offset = true,
  73    .needs_unlit_centroid_workaround = true,
  74    .max_vs_threads = 24,
  75    .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
  76    .max_wm_threads = 40,
  77    .urb = {
  78       .size = 32,
  79       .min_vs_entries = 24,
  80       .max_vs_entries = 256,
  81       .max_gs_entries = 256,
  82    },
  83 };
  84
  85 static const struct brw_device_info brw_device_info_snb_gt2 = {
  86    .gen = 6,
  87    .gt = 2,
  88    .has_hiz_and_separate_stencil = true,
  89    .has_llc = true,
  90    .has_pln = true,
  91    .has_surface_tile_offset = true,
  92    .needs_unlit_centroid_workaround = true,
  93    .max_vs_threads = 60,
  94    .max_gs_threads = 60,
  95    .max_wm_threads = 80,
  96    .urb = {
  97       .size = 64,
  98       .min_vs_entries = 24,
  99       .max_vs_entries = 256,
 100       .max_gs_entries = 256,
 101    },
 102 };
 103
 104 #define GEN7_FEATURES                               \
 105    .gen = 7,                                        \
 106    .has_hiz_and_separate_stencil = true,            \
 107    .must_use_separate_stencil = true,               \
 108    .has_llc = true,                                 \
 109    .has_pln = true,                                 \
 110    .has_surface_tile_offset = true
 111
 112 static const struct brw_device_info brw_device_info_ivb_gt1 = {
 113    GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
 114    .needs_unlit_centroid_workaround = true,
 115    .max_vs_threads = 36,
 116    .max_hs_threads = 36,
 117    .max_ds_threads = 36,
 118    .max_gs_threads = 36,
 119    .max_wm_threads = 48,
 120    .urb = {
 121       .size = 128,
 122       .min_vs_entries = 32,
 123       .max_vs_entries = 512,
 124       .max_hs_entries = 32,
 125       .max_ds_entries = 288,
 126       .max_gs_entries = 192,
 127    },
 128 };
 129
 130 static const struct brw_device_info brw_device_info_ivb_gt2 = {
 131    GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
 132    .needs_unlit_centroid_workaround = true,
 133    .max_vs_threads = 128,
 134    .max_hs_threads = 128,
 135    .max_ds_threads = 128,
 136    .max_gs_threads = 128,
 137    .max_wm_threads = 172,
 138    .urb = {
 139       .size = 256,
 140       .min_vs_entries = 32,
 141       .max_vs_entries = 704,
 142       .max_hs_entries = 64,
 143       .max_ds_entries = 448,
 144       .max_gs_entries = 320,
 145    },
 146 };
 147
 148 static const struct brw_device_info brw_device_info_byt = {
 149    GEN7_FEATURES, .is_baytrail = true, .gt = 1,
 150    .needs_unlit_centroid_workaround = true,
 151    .has_llc = false,
 152    .max_vs_threads = 36,
 153    .max_hs_threads = 36,
 154    .max_ds_threads = 36,
 155    .max_gs_threads = 36,
 156    .max_wm_threads = 48,
 157    .urb = {
 158       .size = 128,
 159       .min_vs_entries = 32,
 160       .max_vs_entries = 512,
 161       .max_hs_entries = 32,
 162       .max_ds_entries = 288,
 163       .max_gs_entries = 192,
 164    },
 165 };
 166
 167 #define HSW_FEATURES             \
 168    GEN7_FEATURES,                \
 169    .is_haswell = true
 170
 171 static const struct brw_device_info brw_device_info_hsw_gt1 = {
 172    HSW_FEATURES, .gt = 1,
 173    .max_vs_threads = 70,
 174    .max_hs_threads = 70,
 175    .max_ds_threads = 70,
 176    .max_gs_threads = 70,
 177    .max_wm_threads = 102,
 178    .urb = {
 179       .size = 128,
 180       .min_vs_entries = 32,
 181       .max_vs_entries = 640,
 182       .max_hs_entries = 64,
 183       .max_ds_entries = 384,
 184       .max_gs_entries = 256,
 185    },
 186 };
 187
 188 static const struct brw_device_info brw_device_info_hsw_gt2 = {
 189    HSW_FEATURES, .gt = 2,
 190    .max_vs_threads = 280,
 191    .max_hs_threads = 256,
 192    .max_ds_threads = 280,
 193    .max_gs_threads = 256,
 194    .max_wm_threads = 204,
 195    .urb = {
 196       .size = 256,
 197       .min_vs_entries = 64,
 198       .max_vs_entries = 1664,
 199       .max_hs_entries = 128,
 200       .max_ds_entries = 960,
 201       .max_gs_entries = 640,
 202    },
 203 };
 204
 205 static const struct brw_device_info brw_device_info_hsw_gt3 = {
 206    HSW_FEATURES, .gt = 3,
 207    .max_vs_threads = 280,
 208    .max_hs_threads = 256,
 209    .max_ds_threads = 280,
 210    .max_gs_threads = 256,
 211    .max_wm_threads = 408,
 212    .urb = {
 213       .size = 512,
 214       .min_vs_entries = 64,
 215       .max_vs_entries = 1664,
 216       .max_hs_entries = 128,
 217       .max_ds_entries = 960,
 218       .max_gs_entries = 640,
 219    },
 220 };
 221
 222 #define GEN8_FEATURES                               \
 223    .gen = 8,                                        \
 224    .has_hiz_and_separate_stencil = true,            \
 225    .must_use_separate_stencil = true,               \
 226    .has_llc = true,                                 \
 227    .has_pln = true,                                 \
 228    .max_vs_threads = 504,                           \
 229    .max_hs_threads = 504,                           \
 230    .max_ds_threads = 504,                           \
 231    .max_gs_threads = 504,                           \
 232    .max_wm_threads = 384                            \
 233
 234 static const struct brw_device_info brw_device_info_bdw_gt1 = {
 235    GEN8_FEATURES, .gt = 1,
 236    .urb = {
 237       .size = 192,
 238       .min_vs_entries = 64,
 239       .max_vs_entries = 2560,
 240       .max_hs_entries = 504,
 241       .max_ds_entries = 1536,
 242       .max_gs_entries = 960,
 243    }
 244 };
 245
 246 static const struct brw_device_info brw_device_info_bdw_gt2 = {
 247    GEN8_FEATURES, .gt = 2,
 248    .urb = {
 249       .size = 384,
 250       .min_vs_entries = 64,
 251       .max_vs_entries = 2560,
 252       .max_hs_entries = 504,
 253       .max_ds_entries = 1536,
 254       .max_gs_entries = 960,
 255    }
 256 };
 257
 258 static const struct brw_device_info brw_device_info_bdw_gt3 = {
 259    GEN8_FEATURES, .gt = 3,
 260    .urb = {
 261       .size = 384,
 262       .min_vs_entries = 64,
 263       .max_vs_entries = 2560,
 264       .max_hs_entries = 504,
 265       .max_ds_entries = 1536,
 266       .max_gs_entries = 960,
 267    }
 268 };
 269
 270 /* Thread counts and URB limits are placeholders, and may not be accurate.
 271  * These were copied from Haswell GT1, above.
 272  */
 273 static const struct brw_device_info brw_device_info_chv = {
 274    GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
 275    .has_llc = false,
 276    .max_vs_threads = 80,
 277    .max_hs_threads = 80,
 278    .max_ds_threads = 80,
 279    .max_gs_threads = 80,
 280    .max_wm_threads = 128,
 281    .urb = {
 282       .size = 192,
 283       .min_vs_entries = 34,
 284       .max_vs_entries = 640,
 285       .max_hs_entries = 80,
 286       .max_ds_entries = 384,
 287       .max_gs_entries = 256,
 288    }
 289 };
 290
 291 /* Thread counts and URB limits are placeholders, and may not be accurate. */
 292 #define GEN9_FEATURES                               \
 293    .gen = 9,                                        \
 294    .has_hiz_and_separate_stencil = true,            \
 295    .must_use_separate_stencil = true,               \
 296    .has_llc = true,                                 \
 297    .has_pln = true,                                 \
 298    .max_vs_threads = 280,                           \
 299    .max_gs_threads = 256,                           \
 300    .max_wm_threads = 408,                           \
 301    .urb = {                                         \
 302       .size = 128,                                  \
 303       .min_vs_entries = 64,                         \
 304       .max_vs_entries = 1664,                       \
 305       .max_gs_entries = 640,                        \
 306    }
 307
 308 static const struct brw_device_info brw_device_info_skl_gt1 = {
 309    GEN9_FEATURES, .gt = 1
 310 };
 311
 312 static const struct brw_device_info brw_device_info_skl_gt2 = {
 313    GEN9_FEATURES, .gt = 2
 314 };
 315
 316 static const struct brw_device_info brw_device_info_skl_gt3 = {
 317    GEN9_FEATURES, .gt = 3
 318 };
 319
 320 const struct brw_device_info *
 321 brw_get_device_info(int devid)
 322 {
 323    switch (devid) {
 324 #undef CHIPSET
 325 #define CHIPSET(id, family, name) case id: return &brw_device_info_##family;
 326 #include "pci_ids/i965_pci_ids.h"
 327    default:
 328       fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
 329       return NULL;
 330    }
 331 }