2 * Copyright © 2013 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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26 #include "brw_device_info.h"
28 static const struct brw_device_info brw_device_info_i965
= {
30 .has_negative_rhw_bug
= true,
33 .max_wm_threads
= 8 * 4,
39 static const struct brw_device_info brw_device_info_g4x
= {
43 .has_surface_tile_offset
= true,
47 .max_wm_threads
= 10 * 5,
53 static const struct brw_device_info brw_device_info_ilk
= {
57 .has_surface_tile_offset
= true,
60 .max_wm_threads
= 12 * 6,
66 static const struct brw_device_info brw_device_info_snb_gt1
= {
69 .has_hiz_and_separate_stencil
= true,
72 .has_surface_tile_offset
= true,
73 .needs_unlit_centroid_workaround
= true,
75 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
80 .max_vs_entries
= 256,
81 .max_gs_entries
= 256,
85 static const struct brw_device_info brw_device_info_snb_gt2
= {
88 .has_hiz_and_separate_stencil
= true,
91 .has_surface_tile_offset
= true,
92 .needs_unlit_centroid_workaround
= true,
99 .max_vs_entries
= 256,
100 .max_gs_entries
= 256,
104 #define GEN7_FEATURES \
106 .has_hiz_and_separate_stencil = true, \
107 .must_use_separate_stencil = true, \
110 .has_surface_tile_offset = true
112 static const struct brw_device_info brw_device_info_ivb_gt1
= {
113 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
114 .needs_unlit_centroid_workaround
= true,
115 .max_vs_threads
= 36,
116 .max_hs_threads
= 36,
117 .max_ds_threads
= 36,
118 .max_gs_threads
= 36,
119 .max_wm_threads
= 48,
122 .min_vs_entries
= 32,
123 .max_vs_entries
= 512,
124 .max_hs_entries
= 32,
125 .max_ds_entries
= 288,
126 .max_gs_entries
= 192,
130 static const struct brw_device_info brw_device_info_ivb_gt2
= {
131 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
132 .needs_unlit_centroid_workaround
= true,
133 .max_vs_threads
= 128,
134 .max_hs_threads
= 128,
135 .max_ds_threads
= 128,
136 .max_gs_threads
= 128,
137 .max_wm_threads
= 172,
140 .min_vs_entries
= 32,
141 .max_vs_entries
= 704,
142 .max_hs_entries
= 64,
143 .max_ds_entries
= 448,
144 .max_gs_entries
= 320,
148 static const struct brw_device_info brw_device_info_byt
= {
149 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
150 .needs_unlit_centroid_workaround
= true,
152 .max_vs_threads
= 36,
153 .max_hs_threads
= 36,
154 .max_ds_threads
= 36,
155 .max_gs_threads
= 36,
156 .max_wm_threads
= 48,
159 .min_vs_entries
= 32,
160 .max_vs_entries
= 512,
161 .max_hs_entries
= 32,
162 .max_ds_entries
= 288,
163 .max_gs_entries
= 192,
167 #define HSW_FEATURES \
169 .is_haswell = true, \
170 .supports_simd16_3src = true
172 static const struct brw_device_info brw_device_info_hsw_gt1
= {
173 HSW_FEATURES
, .gt
= 1,
174 .max_vs_threads
= 70,
175 .max_hs_threads
= 70,
176 .max_ds_threads
= 70,
177 .max_gs_threads
= 70,
178 .max_wm_threads
= 102,
181 .min_vs_entries
= 32,
182 .max_vs_entries
= 640,
183 .max_hs_entries
= 64,
184 .max_ds_entries
= 384,
185 .max_gs_entries
= 256,
189 static const struct brw_device_info brw_device_info_hsw_gt2
= {
190 HSW_FEATURES
, .gt
= 2,
191 .max_vs_threads
= 280,
192 .max_hs_threads
= 256,
193 .max_ds_threads
= 280,
194 .max_gs_threads
= 256,
195 .max_wm_threads
= 204,
198 .min_vs_entries
= 64,
199 .max_vs_entries
= 1664,
200 .max_hs_entries
= 128,
201 .max_ds_entries
= 960,
202 .max_gs_entries
= 640,
206 static const struct brw_device_info brw_device_info_hsw_gt3
= {
207 HSW_FEATURES
, .gt
= 3,
208 .max_vs_threads
= 280,
209 .max_hs_threads
= 256,
210 .max_ds_threads
= 280,
211 .max_gs_threads
= 256,
212 .max_wm_threads
= 408,
215 .min_vs_entries
= 64,
216 .max_vs_entries
= 1664,
217 .max_hs_entries
= 128,
218 .max_ds_entries
= 960,
219 .max_gs_entries
= 640,
223 #define GEN8_FEATURES \
225 .has_hiz_and_separate_stencil = true, \
226 .must_use_separate_stencil = true, \
229 .supports_simd16_3src = true, \
230 .max_vs_threads = 504, \
231 .max_hs_threads = 504, \
232 .max_ds_threads = 504, \
233 .max_gs_threads = 504, \
234 .max_wm_threads = 384 \
236 static const struct brw_device_info brw_device_info_bdw_gt1 = {
237 GEN8_FEATURES
, .gt
= 1,
240 .min_vs_entries
= 64,
241 .max_vs_entries
= 2560,
242 .max_hs_entries
= 504,
243 .max_ds_entries
= 1536,
244 .max_gs_entries
= 960,
248 static const struct brw_device_info brw_device_info_bdw_gt2
= {
249 GEN8_FEATURES
, .gt
= 2,
252 .min_vs_entries
= 64,
253 .max_vs_entries
= 2560,
254 .max_hs_entries
= 504,
255 .max_ds_entries
= 1536,
256 .max_gs_entries
= 960,
260 static const struct brw_device_info brw_device_info_bdw_gt3
= {
261 GEN8_FEATURES
, .gt
= 3,
264 .min_vs_entries
= 64,
265 .max_vs_entries
= 2560,
266 .max_hs_entries
= 504,
267 .max_ds_entries
= 1536,
268 .max_gs_entries
= 960,
272 static const struct brw_device_info brw_device_info_chv
= {
273 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
275 .max_vs_threads
= 80,
276 .max_hs_threads
= 80,
277 .max_ds_threads
= 80,
278 .max_gs_threads
= 80,
279 .max_wm_threads
= 128,
282 .min_vs_entries
= 34,
283 .max_vs_entries
= 640,
284 .max_hs_entries
= 80,
285 .max_ds_entries
= 384,
286 .max_gs_entries
= 256,
290 /* Thread counts and URB limits are placeholders, and may not be accurate. */
291 #define GEN9_FEATURES \
293 .has_hiz_and_separate_stencil = true, \
294 .must_use_separate_stencil = true, \
297 .max_vs_threads = 280, \
298 .max_gs_threads = 256, \
299 .max_wm_threads = 408, \
302 .min_vs_entries = 64, \
303 .max_vs_entries = 1664, \
304 .max_gs_entries = 640, \
307 static const struct brw_device_info brw_device_info_skl_early
= {
308 GEN9_FEATURES
, .gt
= 1,
309 .supports_simd16_3src
= false,
312 static const struct brw_device_info brw_device_info_skl_gt1
= {
313 GEN9_FEATURES
, .gt
= 1,
314 .supports_simd16_3src
= true,
317 static const struct brw_device_info brw_device_info_skl_gt2
= {
318 GEN9_FEATURES
, .gt
= 2,
319 .supports_simd16_3src
= true,
322 static const struct brw_device_info brw_device_info_skl_gt3
= {
323 GEN9_FEATURES
, .gt
= 3,
324 .supports_simd16_3src
= true,
327 const struct brw_device_info
*
328 brw_get_device_info(int devid
, int revision
)
330 const struct brw_device_info
*devinfo
;
333 #define CHIPSET(id, family, name) \
334 case id: devinfo = &brw_device_info_##family; break;
335 #include "pci_ids/i965_pci_ids.h"
337 fprintf(stderr
, "i965_dri.so does not support the 0x%x PCI ID.\n", devid
);
341 if (devinfo
->gen
== 9 && (revision
== 2 || revision
== 3 || revision
== -1))
342 return &brw_device_info_skl_early
;