Merge remote branch 'origin/master' into pipe-video
[mesa.git] / src / mesa / drivers / dri / i965 / brw_draw_upload.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "main/glheader.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33
34 #include "brw_draw.h"
35 #include "brw_defines.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
38
39 #include "intel_batchbuffer.h"
40 #include "intel_buffer_objects.h"
41
42 static GLuint double_types[5] = {
43 0,
44 BRW_SURFACEFORMAT_R64_FLOAT,
45 BRW_SURFACEFORMAT_R64G64_FLOAT,
46 BRW_SURFACEFORMAT_R64G64B64_FLOAT,
47 BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
48 };
49
50 static GLuint float_types[5] = {
51 0,
52 BRW_SURFACEFORMAT_R32_FLOAT,
53 BRW_SURFACEFORMAT_R32G32_FLOAT,
54 BRW_SURFACEFORMAT_R32G32B32_FLOAT,
55 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
56 };
57
58 static GLuint half_float_types[5] = {
59 0,
60 BRW_SURFACEFORMAT_R16_FLOAT,
61 BRW_SURFACEFORMAT_R16G16_FLOAT,
62 BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
63 BRW_SURFACEFORMAT_R16G16B16A16_FLOAT
64 };
65
66 static GLuint uint_types_norm[5] = {
67 0,
68 BRW_SURFACEFORMAT_R32_UNORM,
69 BRW_SURFACEFORMAT_R32G32_UNORM,
70 BRW_SURFACEFORMAT_R32G32B32_UNORM,
71 BRW_SURFACEFORMAT_R32G32B32A32_UNORM
72 };
73
74 static GLuint uint_types_scale[5] = {
75 0,
76 BRW_SURFACEFORMAT_R32_USCALED,
77 BRW_SURFACEFORMAT_R32G32_USCALED,
78 BRW_SURFACEFORMAT_R32G32B32_USCALED,
79 BRW_SURFACEFORMAT_R32G32B32A32_USCALED
80 };
81
82 static GLuint int_types_norm[5] = {
83 0,
84 BRW_SURFACEFORMAT_R32_SNORM,
85 BRW_SURFACEFORMAT_R32G32_SNORM,
86 BRW_SURFACEFORMAT_R32G32B32_SNORM,
87 BRW_SURFACEFORMAT_R32G32B32A32_SNORM
88 };
89
90 static GLuint int_types_scale[5] = {
91 0,
92 BRW_SURFACEFORMAT_R32_SSCALED,
93 BRW_SURFACEFORMAT_R32G32_SSCALED,
94 BRW_SURFACEFORMAT_R32G32B32_SSCALED,
95 BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
96 };
97
98 static GLuint ushort_types_norm[5] = {
99 0,
100 BRW_SURFACEFORMAT_R16_UNORM,
101 BRW_SURFACEFORMAT_R16G16_UNORM,
102 BRW_SURFACEFORMAT_R16G16B16_UNORM,
103 BRW_SURFACEFORMAT_R16G16B16A16_UNORM
104 };
105
106 static GLuint ushort_types_scale[5] = {
107 0,
108 BRW_SURFACEFORMAT_R16_USCALED,
109 BRW_SURFACEFORMAT_R16G16_USCALED,
110 BRW_SURFACEFORMAT_R16G16B16_USCALED,
111 BRW_SURFACEFORMAT_R16G16B16A16_USCALED
112 };
113
114 static GLuint short_types_norm[5] = {
115 0,
116 BRW_SURFACEFORMAT_R16_SNORM,
117 BRW_SURFACEFORMAT_R16G16_SNORM,
118 BRW_SURFACEFORMAT_R16G16B16_SNORM,
119 BRW_SURFACEFORMAT_R16G16B16A16_SNORM
120 };
121
122 static GLuint short_types_scale[5] = {
123 0,
124 BRW_SURFACEFORMAT_R16_SSCALED,
125 BRW_SURFACEFORMAT_R16G16_SSCALED,
126 BRW_SURFACEFORMAT_R16G16B16_SSCALED,
127 BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
128 };
129
130 static GLuint ubyte_types_norm[5] = {
131 0,
132 BRW_SURFACEFORMAT_R8_UNORM,
133 BRW_SURFACEFORMAT_R8G8_UNORM,
134 BRW_SURFACEFORMAT_R8G8B8_UNORM,
135 BRW_SURFACEFORMAT_R8G8B8A8_UNORM
136 };
137
138 static GLuint ubyte_types_scale[5] = {
139 0,
140 BRW_SURFACEFORMAT_R8_USCALED,
141 BRW_SURFACEFORMAT_R8G8_USCALED,
142 BRW_SURFACEFORMAT_R8G8B8_USCALED,
143 BRW_SURFACEFORMAT_R8G8B8A8_USCALED
144 };
145
146 static GLuint byte_types_norm[5] = {
147 0,
148 BRW_SURFACEFORMAT_R8_SNORM,
149 BRW_SURFACEFORMAT_R8G8_SNORM,
150 BRW_SURFACEFORMAT_R8G8B8_SNORM,
151 BRW_SURFACEFORMAT_R8G8B8A8_SNORM
152 };
153
154 static GLuint byte_types_scale[5] = {
155 0,
156 BRW_SURFACEFORMAT_R8_SSCALED,
157 BRW_SURFACEFORMAT_R8G8_SSCALED,
158 BRW_SURFACEFORMAT_R8G8B8_SSCALED,
159 BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
160 };
161
162
163 /**
164 * Given vertex array type/size/format/normalized info, return
165 * the appopriate hardware surface type.
166 * Format will be GL_RGBA or possibly GL_BGRA for GLubyte[4] color arrays.
167 */
168 static GLuint get_surface_type( GLenum type, GLuint size,
169 GLenum format, GLboolean normalized )
170 {
171 if (unlikely(INTEL_DEBUG & DEBUG_VERTS))
172 printf("type %s size %d normalized %d\n",
173 _mesa_lookup_enum_by_nr(type), size, normalized);
174
175 if (normalized) {
176 switch (type) {
177 case GL_DOUBLE: return double_types[size];
178 case GL_FLOAT: return float_types[size];
179 case GL_HALF_FLOAT: return half_float_types[size];
180 case GL_INT: return int_types_norm[size];
181 case GL_SHORT: return short_types_norm[size];
182 case GL_BYTE: return byte_types_norm[size];
183 case GL_UNSIGNED_INT: return uint_types_norm[size];
184 case GL_UNSIGNED_SHORT: return ushort_types_norm[size];
185 case GL_UNSIGNED_BYTE:
186 if (format == GL_BGRA) {
187 /* See GL_EXT_vertex_array_bgra */
188 assert(size == 4);
189 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
190 }
191 else {
192 return ubyte_types_norm[size];
193 }
194 default: assert(0); return 0;
195 }
196 }
197 else {
198 assert(format == GL_RGBA); /* sanity check */
199 switch (type) {
200 case GL_DOUBLE: return double_types[size];
201 case GL_FLOAT: return float_types[size];
202 case GL_HALF_FLOAT: return half_float_types[size];
203 case GL_INT: return int_types_scale[size];
204 case GL_SHORT: return short_types_scale[size];
205 case GL_BYTE: return byte_types_scale[size];
206 case GL_UNSIGNED_INT: return uint_types_scale[size];
207 case GL_UNSIGNED_SHORT: return ushort_types_scale[size];
208 case GL_UNSIGNED_BYTE: return ubyte_types_scale[size];
209 default: assert(0); return 0;
210 }
211 }
212 }
213
214
215 static GLuint get_size( GLenum type )
216 {
217 switch (type) {
218 case GL_DOUBLE: return sizeof(GLdouble);
219 case GL_FLOAT: return sizeof(GLfloat);
220 case GL_HALF_FLOAT: return sizeof(GLhalfARB);
221 case GL_INT: return sizeof(GLint);
222 case GL_SHORT: return sizeof(GLshort);
223 case GL_BYTE: return sizeof(GLbyte);
224 case GL_UNSIGNED_INT: return sizeof(GLuint);
225 case GL_UNSIGNED_SHORT: return sizeof(GLushort);
226 case GL_UNSIGNED_BYTE: return sizeof(GLubyte);
227 default: return 0;
228 }
229 }
230
231 static GLuint get_index_type(GLenum type)
232 {
233 switch (type) {
234 case GL_UNSIGNED_BYTE: return BRW_INDEX_BYTE;
235 case GL_UNSIGNED_SHORT: return BRW_INDEX_WORD;
236 case GL_UNSIGNED_INT: return BRW_INDEX_DWORD;
237 default: assert(0); return 0;
238 }
239 }
240
241 static void wrap_buffers( struct brw_context *brw,
242 GLuint size )
243 {
244 if (size < BRW_UPLOAD_INIT_SIZE)
245 size = BRW_UPLOAD_INIT_SIZE;
246
247 brw->vb.upload.offset = 0;
248
249 if (brw->vb.upload.bo != NULL)
250 drm_intel_bo_unreference(brw->vb.upload.bo);
251 brw->vb.upload.bo = drm_intel_bo_alloc(brw->intel.bufmgr, "temporary VBO",
252 size, 1);
253 }
254
255 static void get_space( struct brw_context *brw,
256 GLuint size,
257 drm_intel_bo **bo_return,
258 GLuint *offset_return )
259 {
260 size = ALIGN(size, 64);
261
262 if (brw->vb.upload.bo == NULL ||
263 brw->vb.upload.offset + size > brw->vb.upload.bo->size) {
264 wrap_buffers(brw, size);
265 }
266
267 assert(*bo_return == NULL);
268 drm_intel_bo_reference(brw->vb.upload.bo);
269 *bo_return = brw->vb.upload.bo;
270 *offset_return = brw->vb.upload.offset;
271 brw->vb.upload.offset += size;
272 }
273
274 static void
275 copy_array_to_vbo_array( struct brw_context *brw,
276 struct brw_vertex_element *element,
277 GLuint dst_stride)
278 {
279 GLuint size = element->count * dst_stride;
280
281 get_space(brw, size, &element->bo, &element->offset);
282
283 if (element->glarray->StrideB == 0) {
284 assert(element->count == 1);
285 element->stride = 0;
286 } else {
287 element->stride = dst_stride;
288 }
289
290 if (dst_stride == element->glarray->StrideB) {
291 drm_intel_gem_bo_map_gtt(element->bo);
292 memcpy((char *)element->bo->virtual + element->offset,
293 element->glarray->Ptr, size);
294 drm_intel_gem_bo_unmap_gtt(element->bo);
295 } else {
296 char *dest;
297 const unsigned char *src = element->glarray->Ptr;
298 int i;
299
300 drm_intel_gem_bo_map_gtt(element->bo);
301 dest = element->bo->virtual;
302 dest += element->offset;
303
304 for (i = 0; i < element->count; i++) {
305 memcpy(dest, src, dst_stride);
306 src += element->glarray->StrideB;
307 dest += dst_stride;
308 }
309
310 drm_intel_gem_bo_unmap_gtt(element->bo);
311 }
312 }
313
314 static void brw_prepare_vertices(struct brw_context *brw)
315 {
316 struct gl_context *ctx = &brw->intel.ctx;
317 struct intel_context *intel = intel_context(ctx);
318 GLbitfield vs_inputs = brw->vs.prog_data->inputs_read;
319 GLuint i;
320 const unsigned char *ptr = NULL;
321 GLuint interleave = 0;
322 unsigned int min_index = brw->vb.min_index;
323 unsigned int max_index = brw->vb.max_index;
324
325 struct brw_vertex_element *upload[VERT_ATTRIB_MAX];
326 GLuint nr_uploads = 0;
327
328 /* First build an array of pointers to ve's in vb.inputs_read
329 */
330 if (0)
331 printf("%s %d..%d\n", __FUNCTION__, min_index, max_index);
332
333 /* Accumulate the list of enabled arrays. */
334 brw->vb.nr_enabled = 0;
335 while (vs_inputs) {
336 GLuint i = _mesa_ffsll(vs_inputs) - 1;
337 struct brw_vertex_element *input = &brw->vb.inputs[i];
338
339 vs_inputs &= ~(1 << i);
340 brw->vb.enabled[brw->vb.nr_enabled++] = input;
341 }
342
343 /* XXX: In the rare cases where this happens we fallback all
344 * the way to software rasterization, although a tnl fallback
345 * would be sufficient. I don't know of *any* real world
346 * cases with > 17 vertex attributes enabled, so it probably
347 * isn't an issue at this point.
348 */
349 if (brw->vb.nr_enabled >= BRW_VEP_MAX) {
350 intel->Fallback = GL_TRUE; /* boolean, not bitfield */
351 return;
352 }
353
354 for (i = 0; i < brw->vb.nr_enabled; i++) {
355 struct brw_vertex_element *input = brw->vb.enabled[i];
356
357 input->element_size = get_size(input->glarray->Type) * input->glarray->Size;
358
359 if (_mesa_is_bufferobj(input->glarray->BufferObj)) {
360 struct intel_buffer_object *intel_buffer =
361 intel_buffer_object(input->glarray->BufferObj);
362
363 /* Named buffer object: Just reference its contents directly. */
364 drm_intel_bo_unreference(input->bo);
365 input->bo = intel_bufferobj_buffer(intel, intel_buffer,
366 INTEL_READ);
367 drm_intel_bo_reference(input->bo);
368 input->offset = (unsigned long)input->glarray->Ptr;
369 input->stride = input->glarray->StrideB;
370 input->count = input->glarray->_MaxElement;
371
372 /* This is a common place to reach if the user mistakenly supplies
373 * a pointer in place of a VBO offset. If we just let it go through,
374 * we may end up dereferencing a pointer beyond the bounds of the
375 * GTT. We would hope that the VBO's max_index would save us, but
376 * Mesa appears to hand us min/max values not clipped to the
377 * array object's _MaxElement, and _MaxElement frequently appears
378 * to be wrong anyway.
379 *
380 * The VBO spec allows application termination in this case, and it's
381 * probably a service to the poor programmer to do so rather than
382 * trying to just not render.
383 */
384 assert(input->offset < input->bo->size);
385 } else {
386 input->count = input->glarray->StrideB ? max_index + 1 : 1;
387 if (input->bo != NULL) {
388 /* Already-uploaded vertex data is present from a previous
389 * prepare_vertices, but we had to re-validate state due to
390 * check_aperture failing and a new batch being produced.
391 */
392 continue;
393 }
394
395 /* Queue the buffer object up to be uploaded in the next pass,
396 * when we've decided if we're doing interleaved or not.
397 */
398 if (input->attrib == VERT_ATTRIB_POS) {
399 /* Position array not properly enabled:
400 */
401 if (input->glarray->StrideB == 0) {
402 intel->Fallback = GL_TRUE; /* boolean, not bitfield */
403 return;
404 }
405
406 interleave = input->glarray->StrideB;
407 ptr = input->glarray->Ptr;
408 }
409 else if (interleave != input->glarray->StrideB ||
410 (const unsigned char *)input->glarray->Ptr - ptr < 0 ||
411 (const unsigned char *)input->glarray->Ptr - ptr > interleave)
412 {
413 interleave = 0;
414 }
415
416 upload[nr_uploads++] = input;
417 }
418 }
419
420 /* Handle any arrays to be uploaded. */
421 if (nr_uploads > 1 && interleave && interleave <= 256) {
422 /* All uploads are interleaved, so upload the arrays together as
423 * interleaved. First, upload the contents and set up upload[0].
424 */
425 copy_array_to_vbo_array(brw, upload[0], interleave);
426
427 for (i = 1; i < nr_uploads; i++) {
428 /* Then, just point upload[i] at upload[0]'s buffer. */
429 upload[i]->stride = interleave;
430 upload[i]->offset = upload[0]->offset +
431 ((const unsigned char *)upload[i]->glarray->Ptr - ptr);
432 upload[i]->bo = upload[0]->bo;
433 drm_intel_bo_reference(upload[i]->bo);
434 }
435 }
436 else {
437 /* Upload non-interleaved arrays */
438 for (i = 0; i < nr_uploads; i++) {
439 copy_array_to_vbo_array(brw, upload[i], upload[i]->element_size);
440 }
441 }
442
443 brw_prepare_query_begin(brw);
444
445 for (i = 0; i < brw->vb.nr_enabled; i++) {
446 struct brw_vertex_element *input = brw->vb.enabled[i];
447
448 brw_add_validated_bo(brw, input->bo);
449 }
450 }
451
452 static void brw_emit_vertices(struct brw_context *brw)
453 {
454 struct gl_context *ctx = &brw->intel.ctx;
455 struct intel_context *intel = intel_context(ctx);
456 GLuint i;
457
458 brw_emit_query_begin(brw);
459
460 /* If the VS doesn't read any inputs (calculating vertex position from
461 * a state variable for some reason, for example), emit a single pad
462 * VERTEX_ELEMENT struct and bail.
463 *
464 * The stale VB state stays in place, but they don't do anything unless
465 * a VE loads from them.
466 */
467 if (brw->vb.nr_enabled == 0) {
468 BEGIN_BATCH(3);
469 OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | 1);
470 if (intel->gen >= 6) {
471 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
472 GEN6_VE0_VALID |
473 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
474 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
475 } else {
476 OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
477 BRW_VE0_VALID |
478 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
479 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
480 }
481 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
482 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
483 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
484 (BRW_VE1_COMPONENT_STORE_1_FLT << BRW_VE1_COMPONENT_3_SHIFT));
485 ADVANCE_BATCH();
486 return;
487 }
488
489 /* Now emit VB and VEP state packets.
490 *
491 * This still defines a hardware VB for each input, even if they
492 * are interleaved or from the same VBO. TBD if this makes a
493 * performance difference.
494 */
495 BEGIN_BATCH(1 + brw->vb.nr_enabled * 4);
496 OUT_BATCH((CMD_VERTEX_BUFFER << 16) |
497 ((1 + brw->vb.nr_enabled * 4) - 2));
498
499 for (i = 0; i < brw->vb.nr_enabled; i++) {
500 struct brw_vertex_element *input = brw->vb.enabled[i];
501 uint32_t dw0;
502
503 if (intel->gen >= 6) {
504 dw0 = GEN6_VB0_ACCESS_VERTEXDATA |
505 (i << GEN6_VB0_INDEX_SHIFT);
506 } else {
507 dw0 = BRW_VB0_ACCESS_VERTEXDATA |
508 (i << BRW_VB0_INDEX_SHIFT);
509 }
510
511 OUT_BATCH(dw0 |
512 (input->stride << BRW_VB0_PITCH_SHIFT));
513 OUT_RELOC(input->bo,
514 I915_GEM_DOMAIN_VERTEX, 0,
515 input->offset);
516 if (intel->gen >= 5) {
517 OUT_RELOC(input->bo,
518 I915_GEM_DOMAIN_VERTEX, 0,
519 input->bo->size - 1);
520 } else
521 OUT_BATCH(input->stride ? input->count : 0);
522 OUT_BATCH(0); /* Instance data step rate */
523 }
524 ADVANCE_BATCH();
525
526 BEGIN_BATCH(1 + brw->vb.nr_enabled * 2);
527 OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | ((1 + brw->vb.nr_enabled * 2) - 2));
528 for (i = 0; i < brw->vb.nr_enabled; i++) {
529 struct brw_vertex_element *input = brw->vb.enabled[i];
530 uint32_t format = get_surface_type(input->glarray->Type,
531 input->glarray->Size,
532 input->glarray->Format,
533 input->glarray->Normalized);
534 uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
535 uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
536 uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
537 uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
538
539 switch (input->glarray->Size) {
540 case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
541 case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
542 case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
543 case 3: comp3 = BRW_VE1_COMPONENT_STORE_1_FLT;
544 break;
545 }
546
547 if (intel->gen >= 6) {
548 OUT_BATCH((i << GEN6_VE0_INDEX_SHIFT) |
549 GEN6_VE0_VALID |
550 (format << BRW_VE0_FORMAT_SHIFT) |
551 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
552 } else {
553 OUT_BATCH((i << BRW_VE0_INDEX_SHIFT) |
554 BRW_VE0_VALID |
555 (format << BRW_VE0_FORMAT_SHIFT) |
556 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
557 }
558
559 if (intel->gen >= 5)
560 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
561 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
562 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
563 (comp3 << BRW_VE1_COMPONENT_3_SHIFT));
564 else
565 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
566 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
567 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
568 (comp3 << BRW_VE1_COMPONENT_3_SHIFT) |
569 ((i * 4) << BRW_VE1_DST_OFFSET_SHIFT));
570 }
571 ADVANCE_BATCH();
572 }
573
574 const struct brw_tracked_state brw_vertices = {
575 .dirty = {
576 .mesa = 0,
577 .brw = BRW_NEW_BATCH | BRW_NEW_VERTICES,
578 .cache = 0,
579 },
580 .prepare = brw_prepare_vertices,
581 .emit = brw_emit_vertices,
582 };
583
584 static void brw_prepare_indices(struct brw_context *brw)
585 {
586 struct gl_context *ctx = &brw->intel.ctx;
587 struct intel_context *intel = &brw->intel;
588 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
589 GLuint ib_size;
590 drm_intel_bo *bo = NULL;
591 struct gl_buffer_object *bufferobj;
592 GLuint offset;
593 GLuint ib_type_size;
594
595 if (index_buffer == NULL)
596 return;
597
598 ib_type_size = get_size(index_buffer->type);
599 ib_size = ib_type_size * index_buffer->count;
600 bufferobj = index_buffer->obj;;
601
602 /* Turn into a proper VBO:
603 */
604 if (!_mesa_is_bufferobj(bufferobj)) {
605 brw->ib.start_vertex_offset = 0;
606
607 /* Get new bufferobj, offset:
608 */
609 get_space(brw, ib_size, &bo, &offset);
610
611 /* Straight upload
612 */
613 drm_intel_gem_bo_map_gtt(bo);
614 memcpy((char *)bo->virtual + offset, index_buffer->ptr, ib_size);
615 drm_intel_gem_bo_unmap_gtt(bo);
616 } else {
617 offset = (GLuint) (unsigned long) index_buffer->ptr;
618 brw->ib.start_vertex_offset = 0;
619
620 /* If the index buffer isn't aligned to its element size, we have to
621 * rebase it into a temporary.
622 */
623 if ((get_size(index_buffer->type) - 1) & offset) {
624 GLubyte *map = ctx->Driver.MapBuffer(ctx,
625 GL_ELEMENT_ARRAY_BUFFER_ARB,
626 GL_DYNAMIC_DRAW_ARB,
627 bufferobj);
628 map += offset;
629
630 get_space(brw, ib_size, &bo, &offset);
631
632 drm_intel_bo_subdata(bo, offset, ib_size, map);
633
634 ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER_ARB, bufferobj);
635 } else {
636 bo = intel_bufferobj_buffer(intel, intel_buffer_object(bufferobj),
637 INTEL_READ);
638 drm_intel_bo_reference(bo);
639
640 /* Use CMD_3D_PRIM's start_vertex_offset to avoid re-uploading
641 * the index buffer state when we're just moving the start index
642 * of our drawing.
643 */
644 brw->ib.start_vertex_offset = offset / ib_type_size;
645 offset = 0;
646 ib_size = bo->size;
647 }
648 }
649
650 if (brw->ib.bo != bo ||
651 brw->ib.offset != offset ||
652 brw->ib.size != ib_size)
653 {
654 drm_intel_bo_unreference(brw->ib.bo);
655 brw->ib.bo = bo;
656 brw->ib.offset = offset;
657 brw->ib.size = ib_size;
658
659 brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER;
660 } else {
661 drm_intel_bo_unreference(bo);
662 }
663
664 brw_add_validated_bo(brw, brw->ib.bo);
665 }
666
667 const struct brw_tracked_state brw_indices = {
668 .dirty = {
669 .mesa = 0,
670 .brw = BRW_NEW_INDICES,
671 .cache = 0,
672 },
673 .prepare = brw_prepare_indices,
674 };
675
676 static void brw_emit_index_buffer(struct brw_context *brw)
677 {
678 struct intel_context *intel = &brw->intel;
679 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
680
681 if (index_buffer == NULL)
682 return;
683
684 /* Emit the indexbuffer packet:
685 */
686 {
687 struct brw_indexbuffer ib;
688
689 memset(&ib, 0, sizeof(ib));
690
691 ib.header.bits.opcode = CMD_INDEX_BUFFER;
692 ib.header.bits.length = sizeof(ib)/4 - 2;
693 ib.header.bits.index_format = get_index_type(index_buffer->type);
694 ib.header.bits.cut_index_enable = 0;
695
696 BEGIN_BATCH(4);
697 OUT_BATCH( ib.header.dword );
698 OUT_RELOC(brw->ib.bo,
699 I915_GEM_DOMAIN_VERTEX, 0,
700 brw->ib.offset);
701 OUT_RELOC(brw->ib.bo,
702 I915_GEM_DOMAIN_VERTEX, 0,
703 brw->ib.offset + brw->ib.size - 1);
704 OUT_BATCH( 0 );
705 ADVANCE_BATCH();
706 }
707 }
708
709 const struct brw_tracked_state brw_index_buffer = {
710 .dirty = {
711 .mesa = 0,
712 .brw = BRW_NEW_BATCH | BRW_NEW_INDEX_BUFFER,
713 .cache = 0,
714 },
715 .emit = brw_emit_index_buffer,
716 };