src/mesa/drivers/dri/i965/brw_eu_defines.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32 #ifndef BRW_EU_DEFINES_H
  33 #define BRW_EU_DEFINES_H
  34
  35 #include "util/macros.h"
  36
  37 /* The following hunk, up-to "Execution Unit" is used by both the
  38  * intel/compiler and i965 codebase. */
  39
  40 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
  41 /* Using the GNU statement expression extension */
  42 #define SET_FIELD(value, field)                                         \
  43    ({                                                                   \
  44       uint32_t fieldval = (value) << field ## _SHIFT;                   \
  45       assert((fieldval & ~ field ## _MASK) == 0);                       \
  46       fieldval & field ## _MASK;                                        \
  47    })
  48
  49 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
  50 #define GET_FIELD(word, field) (((word)  & field ## _MASK) >> field ## _SHIFT)
  51
  52 #define _3DPRIM_POINTLIST         0x01
  53 #define _3DPRIM_LINELIST          0x02
  54 #define _3DPRIM_LINESTRIP         0x03
  55 #define _3DPRIM_TRILIST           0x04
  56 #define _3DPRIM_TRISTRIP          0x05
  57 #define _3DPRIM_TRIFAN            0x06
  58 #define _3DPRIM_QUADLIST          0x07
  59 #define _3DPRIM_QUADSTRIP         0x08
  60 #define _3DPRIM_LINELIST_ADJ      0x09 /* G45+ */
  61 #define _3DPRIM_LINESTRIP_ADJ     0x0A /* G45+ */
  62 #define _3DPRIM_TRILIST_ADJ       0x0B /* G45+ */
  63 #define _3DPRIM_TRISTRIP_ADJ      0x0C /* G45+ */
  64 #define _3DPRIM_TRISTRIP_REVERSE  0x0D
  65 #define _3DPRIM_POLYGON           0x0E
  66 #define _3DPRIM_RECTLIST          0x0F
  67 #define _3DPRIM_LINELOOP          0x10
  68 #define _3DPRIM_POINTLIST_BF      0x11
  69 #define _3DPRIM_LINESTRIP_CONT    0x12
  70 #define _3DPRIM_LINESTRIP_BF      0x13
  71 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
  72 #define _3DPRIM_TRIFAN_NOSTIPPLE  0x16
  73 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
  74
  75 enum brw_barycentric_mode {
  76    BRW_BARYCENTRIC_PERSPECTIVE_PIXEL       = 0,
  77    BRW_BARYCENTRIC_PERSPECTIVE_CENTROID    = 1,
  78    BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE      = 2,
  79    BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL    = 3,
  80    BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
  81    BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE   = 5,
  82    BRW_BARYCENTRIC_MODE_COUNT              = 6
  83 };
  84 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
  85    ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
  86     (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
  87     (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
  88
  89 enum brw_pixel_shader_computed_depth_mode {
  90    BRW_PSCDEPTH_OFF   = 0, /* PS does not compute depth */
  91    BRW_PSCDEPTH_ON    = 1, /* PS computes depth; no guarantee about value */
  92    BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */
  93    BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */
  94 };
  95
  96 /* Bitfields for the URB_WRITE message, DW2 of message header: */
  97 #define URB_WRITE_PRIM_END              0x1
  98 #define URB_WRITE_PRIM_START            0x2
  99 #define URB_WRITE_PRIM_TYPE_SHIFT       2
 100
 101 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT          0
 102 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID          1
 103
 104 /* Execution Unit (EU) defines
 105  */
 106
 107 #define BRW_ALIGN_1   0
 108 #define BRW_ALIGN_16  1
 109
 110 #define BRW_ADDRESS_DIRECT                        0
 111 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER    1
 112
 113 #define BRW_CHANNEL_X     0
 114 #define BRW_CHANNEL_Y     1
 115 #define BRW_CHANNEL_Z     2
 116 #define BRW_CHANNEL_W     3
 117
 118 enum brw_compression {
 119    BRW_COMPRESSION_NONE       = 0,
 120    BRW_COMPRESSION_2NDHALF    = 1,
 121    BRW_COMPRESSION_COMPRESSED = 2,
 122 };
 123
 124 #define GEN6_COMPRESSION_1Q             0
 125 #define GEN6_COMPRESSION_2Q             1
 126 #define GEN6_COMPRESSION_3Q             2
 127 #define GEN6_COMPRESSION_4Q             3
 128 #define GEN6_COMPRESSION_1H             0
 129 #define GEN6_COMPRESSION_2H             2
 130
 131 enum PACKED brw_conditional_mod {
 132    BRW_CONDITIONAL_NONE = 0,
 133    BRW_CONDITIONAL_Z    = 1,
 134    BRW_CONDITIONAL_NZ   = 2,
 135    BRW_CONDITIONAL_EQ   = 1,    /* Z */
 136    BRW_CONDITIONAL_NEQ  = 2,    /* NZ */
 137    BRW_CONDITIONAL_G    = 3,
 138    BRW_CONDITIONAL_GE   = 4,
 139    BRW_CONDITIONAL_L    = 5,
 140    BRW_CONDITIONAL_LE   = 6,
 141    BRW_CONDITIONAL_R    = 7,    /* Gen <= 5 */
 142    BRW_CONDITIONAL_O    = 8,
 143    BRW_CONDITIONAL_U    = 9,
 144 };
 145
 146 #define BRW_DEBUG_NONE        0
 147 #define BRW_DEBUG_BREAKPOINT  1
 148
 149 #define BRW_DEPENDENCY_NORMAL         0
 150 #define BRW_DEPENDENCY_NOTCLEARED     1
 151 #define BRW_DEPENDENCY_NOTCHECKED     2
 152 #define BRW_DEPENDENCY_DISABLE        3
 153
 154 enum PACKED brw_execution_size {
 155    BRW_EXECUTE_1  = 0,
 156    BRW_EXECUTE_2  = 1,
 157    BRW_EXECUTE_4  = 2,
 158    BRW_EXECUTE_8  = 3,
 159    BRW_EXECUTE_16 = 4,
 160    BRW_EXECUTE_32 = 5,
 161 };
 162
 163 enum PACKED brw_horizontal_stride {
 164    BRW_HORIZONTAL_STRIDE_0 = 0,
 165    BRW_HORIZONTAL_STRIDE_1 = 1,
 166    BRW_HORIZONTAL_STRIDE_2 = 2,
 167    BRW_HORIZONTAL_STRIDE_4 = 3,
 168 };
 169
 170 #define BRW_INSTRUCTION_NORMAL    0
 171 #define BRW_INSTRUCTION_SATURATE  1
 172
 173 #define BRW_MASK_ENABLE   0
 174 #define BRW_MASK_DISABLE  1
 175
 176 /** @{
 177  *
 178  * Gen6 has replaced "mask enable/disable" with WECtrl, which is
 179  * effectively the same but much simpler to think about.  Now, there
 180  * are two contributors ANDed together to whether channels are
 181  * executed: The predication on the instruction, and the channel write
 182  * enable.
 183  */
 184 /**
 185  * This is the default value.  It means that a channel's write enable is set
 186  * if the per-channel IP is pointing at this instruction.
 187  */
 188 #define BRW_WE_NORMAL           0
 189 /**
 190  * This is used like BRW_MASK_DISABLE, and causes all channels to have
 191  * their write enable set.  Note that predication still contributes to
 192  * whether the channel actually gets written.
 193  */
 194 #define BRW_WE_ALL              1
 195 /** @} */
 196
 197 enum opcode {
 198    /* These are the actual hardware opcodes. */
 199    BRW_OPCODE_ILLEGAL = 0,
 200    BRW_OPCODE_MOV =     1,
 201    BRW_OPCODE_SEL =     2,
 202    BRW_OPCODE_MOVI =    3,   /**< G45+ */
 203    BRW_OPCODE_NOT =     4,
 204    BRW_OPCODE_AND =     5,
 205    BRW_OPCODE_OR =      6,
 206    BRW_OPCODE_XOR =     7,
 207    BRW_OPCODE_SHR =     8,
 208    BRW_OPCODE_SHL =     9,
 209    BRW_OPCODE_DIM =     10,  /**< Gen7.5 only */ /* Reused */
 210    // BRW_OPCODE_SMOV = 10,  /**< Gen8+       */ /* Reused */
 211    /* Reserved - 11 */
 212    BRW_OPCODE_ASR =     12,
 213    /* Reserved - 13-15 */
 214    BRW_OPCODE_CMP =     16,
 215    BRW_OPCODE_CMPN =    17,
 216    BRW_OPCODE_CSEL =    18,  /**< Gen8+ */
 217    BRW_OPCODE_F32TO16 = 19,  /**< Gen7 only */
 218    BRW_OPCODE_F16TO32 = 20,  /**< Gen7 only */
 219    /* Reserved - 21-22 */
 220    BRW_OPCODE_BFREV =   23,  /**< Gen7+ */
 221    BRW_OPCODE_BFE =     24,  /**< Gen7+ */
 222    BRW_OPCODE_BFI1 =    25,  /**< Gen7+ */
 223    BRW_OPCODE_BFI2 =    26,  /**< Gen7+ */
 224    /* Reserved - 27-31 */
 225    BRW_OPCODE_JMPI =    32,
 226    // BRW_OPCODE_BRD =  33,  /**< Gen7+ */
 227    BRW_OPCODE_IF =      34,
 228    BRW_OPCODE_IFF =     35,  /**< Pre-Gen6    */ /* Reused */
 229    // BRW_OPCODE_BRC =  35,  /**< Gen7+       */ /* Reused */
 230    BRW_OPCODE_ELSE =    36,
 231    BRW_OPCODE_ENDIF =   37,
 232    BRW_OPCODE_DO =      38,  /**< Pre-Gen6    */ /* Reused */
 233    // BRW_OPCODE_CASE = 38,  /**< Gen6 only   */ /* Reused */
 234    BRW_OPCODE_WHILE =   39,
 235    BRW_OPCODE_BREAK =   40,
 236    BRW_OPCODE_CONTINUE = 41,
 237    BRW_OPCODE_HALT =    42,
 238    // BRW_OPCODE_CALLA =        43,  /**< Gen7.5+     */
 239    // BRW_OPCODE_MSAVE =        44,  /**< Pre-Gen6    */ /* Reused */
 240    // BRW_OPCODE_CALL = 44,  /**< Gen6+       */ /* Reused */
 241    // BRW_OPCODE_MREST =        45,  /**< Pre-Gen6    */ /* Reused */
 242    // BRW_OPCODE_RET =  45,  /**< Gen6+       */ /* Reused */
 243    // BRW_OPCODE_PUSH = 46,  /**< Pre-Gen6    */ /* Reused */
 244    // BRW_OPCODE_FORK = 46,  /**< Gen6 only   */ /* Reused */
 245    // BRW_OPCODE_GOTO = 46,  /**< Gen8+       */ /* Reused */
 246    // BRW_OPCODE_POP =  47,  /**< Pre-Gen6    */
 247    BRW_OPCODE_WAIT =    48,
 248    BRW_OPCODE_SEND =    49,
 249    BRW_OPCODE_SENDC =   50,
 250    BRW_OPCODE_SENDS =   51,  /**< Gen9+ */
 251    BRW_OPCODE_SENDSC =  52,  /**< Gen9+ */
 252    /* Reserved 53-55 */
 253    BRW_OPCODE_MATH =    56,  /**< Gen6+ */
 254    /* Reserved 57-63 */
 255    BRW_OPCODE_ADD =     64,
 256    BRW_OPCODE_MUL =     65,
 257    BRW_OPCODE_AVG =     66,
 258    BRW_OPCODE_FRC =     67,
 259    BRW_OPCODE_RNDU =    68,
 260    BRW_OPCODE_RNDD =    69,
 261    BRW_OPCODE_RNDE =    70,
 262    BRW_OPCODE_RNDZ =    71,
 263    BRW_OPCODE_MAC =     72,
 264    BRW_OPCODE_MACH =    73,
 265    BRW_OPCODE_LZD =     74,
 266    BRW_OPCODE_FBH =     75,  /**< Gen7+ */
 267    BRW_OPCODE_FBL =     76,  /**< Gen7+ */
 268    BRW_OPCODE_CBIT =    77,  /**< Gen7+ */
 269    BRW_OPCODE_ADDC =    78,  /**< Gen7+ */
 270    BRW_OPCODE_SUBB =    79,  /**< Gen7+ */
 271    BRW_OPCODE_SAD2 =    80,
 272    BRW_OPCODE_SADA2 =   81,
 273    /* Reserved 82-83 */
 274    BRW_OPCODE_DP4 =     84,
 275    BRW_OPCODE_DPH =     85,
 276    BRW_OPCODE_DP3 =     86,
 277    BRW_OPCODE_DP2 =     87,
 278    /* Reserved 88 */
 279    BRW_OPCODE_LINE =    89,
 280    BRW_OPCODE_PLN =     90,  /**< G45+ */
 281    BRW_OPCODE_MAD =     91,  /**< Gen6+ */
 282    BRW_OPCODE_LRP =     92,  /**< Gen6+ */
 283    // BRW_OPCODE_MADM = 93,  /**< Gen8+ */
 284    /* Reserved 94-124 */
 285    BRW_OPCODE_NENOP =   125, /**< G45 only */
 286    BRW_OPCODE_NOP =     126,
 287    /* Reserved 127 */
 288
 289    /* These are compiler backend opcodes that get translated into other
 290     * instructions.
 291     */
 292    FS_OPCODE_FB_WRITE = 128,
 293
 294    /**
 295     * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
 296     * individual sources instead of as a single payload blob. The
 297     * position/ordering of the arguments are defined by the enum
 298     * fb_write_logical_srcs.
 299     */
 300    FS_OPCODE_FB_WRITE_LOGICAL,
 301
 302    FS_OPCODE_REP_FB_WRITE,
 303
 304    FS_OPCODE_FB_READ,
 305    FS_OPCODE_FB_READ_LOGICAL,
 306
 307    SHADER_OPCODE_RCP,
 308    SHADER_OPCODE_RSQ,
 309    SHADER_OPCODE_SQRT,
 310    SHADER_OPCODE_EXP2,
 311    SHADER_OPCODE_LOG2,
 312    SHADER_OPCODE_POW,
 313    SHADER_OPCODE_INT_QUOTIENT,
 314    SHADER_OPCODE_INT_REMAINDER,
 315    SHADER_OPCODE_SIN,
 316    SHADER_OPCODE_COS,
 317
 318    /**
 319     * Texture sampling opcodes.
 320     *
 321     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
 322     * opcode but instead of taking a single payload blob they expect their
 323     * arguments separately as individual sources. The position/ordering of the
 324     * arguments are defined by the enum tex_logical_srcs.
 325     */
 326    SHADER_OPCODE_TEX,
 327    SHADER_OPCODE_TEX_LOGICAL,
 328    SHADER_OPCODE_TXD,
 329    SHADER_OPCODE_TXD_LOGICAL,
 330    SHADER_OPCODE_TXF,
 331    SHADER_OPCODE_TXF_LOGICAL,
 332    SHADER_OPCODE_TXF_LZ,
 333    SHADER_OPCODE_TXL,
 334    SHADER_OPCODE_TXL_LOGICAL,
 335    SHADER_OPCODE_TXL_LZ,
 336    SHADER_OPCODE_TXS,
 337    SHADER_OPCODE_TXS_LOGICAL,
 338    FS_OPCODE_TXB,
 339    FS_OPCODE_TXB_LOGICAL,
 340    SHADER_OPCODE_TXF_CMS,
 341    SHADER_OPCODE_TXF_CMS_LOGICAL,
 342    SHADER_OPCODE_TXF_CMS_W,
 343    SHADER_OPCODE_TXF_CMS_W_LOGICAL,
 344    SHADER_OPCODE_TXF_UMS,
 345    SHADER_OPCODE_TXF_UMS_LOGICAL,
 346    SHADER_OPCODE_TXF_MCS,
 347    SHADER_OPCODE_TXF_MCS_LOGICAL,
 348    SHADER_OPCODE_LOD,
 349    SHADER_OPCODE_LOD_LOGICAL,
 350    SHADER_OPCODE_TG4,
 351    SHADER_OPCODE_TG4_LOGICAL,
 352    SHADER_OPCODE_TG4_OFFSET,
 353    SHADER_OPCODE_TG4_OFFSET_LOGICAL,
 354    SHADER_OPCODE_SAMPLEINFO,
 355    SHADER_OPCODE_SAMPLEINFO_LOGICAL,
 356
 357    /**
 358     * Combines multiple sources of size 1 into a larger virtual GRF.
 359     * For example, parameters for a send-from-GRF message.  Or, updating
 360     * channels of a size 4 VGRF used to store vec4s such as texturing results.
 361     *
 362     * This will be lowered into MOVs from each source to consecutive offsets
 363     * of the destination VGRF.
 364     *
 365     * src[0] may be BAD_FILE.  If so, the lowering pass skips emitting the MOV,
 366     * but still reserves the first channel of the destination VGRF.  This can be
 367     * used to reserve space for, say, a message header set up by the generators.
 368     */
 369    SHADER_OPCODE_LOAD_PAYLOAD,
 370
 371    /**
 372     * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
 373     * acts intra-channel, obtaining the final value for each channel by
 374     * combining the sources values for the same channel, the first source
 375     * occupying the lowest bits and the last source occupying the highest
 376     * bits.
 377     */
 378    FS_OPCODE_PACK,
 379
 380    SHADER_OPCODE_SHADER_TIME_ADD,
 381
 382    /**
 383     * Typed and untyped surface access opcodes.
 384     *
 385     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
 386     * opcode but instead of taking a single payload blob they expect their
 387     * arguments separately as individual sources:
 388     *
 389     * Source 0: [required] Surface coordinates.
 390     * Source 1: [optional] Operation source.
 391     * Source 2: [required] Surface index.
 392     * Source 3: [required] Number of coordinate components (as UD immediate).
 393     * Source 4: [required] Opcode-specific control immediate, same as source 2
 394     *                      of the matching non-LOGICAL opcode.
 395     */
 396    SHADER_OPCODE_UNTYPED_ATOMIC,
 397    SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
 398    SHADER_OPCODE_UNTYPED_SURFACE_READ,
 399    SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
 400    SHADER_OPCODE_UNTYPED_SURFACE_WRITE,
 401    SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
 402
 403    SHADER_OPCODE_TYPED_ATOMIC,
 404    SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
 405    SHADER_OPCODE_TYPED_SURFACE_READ,
 406    SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
 407    SHADER_OPCODE_TYPED_SURFACE_WRITE,
 408    SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
 409
 410    SHADER_OPCODE_MEMORY_FENCE,
 411
 412    SHADER_OPCODE_GEN4_SCRATCH_READ,
 413    SHADER_OPCODE_GEN4_SCRATCH_WRITE,
 414    SHADER_OPCODE_GEN7_SCRATCH_READ,
 415
 416    /**
 417     * Gen8+ SIMD8 URB Read messages.
 418     */
 419    SHADER_OPCODE_URB_READ_SIMD8,
 420    SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
 421
 422    SHADER_OPCODE_URB_WRITE_SIMD8,
 423    SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
 424    SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
 425    SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
 426
 427    /**
 428     * Return the index of an arbitrary live channel (i.e. one of the channels
 429     * enabled in the current execution mask) and assign it to the first
 430     * component of the destination.  Expected to be used as input for the
 431     * BROADCAST pseudo-opcode.
 432     */
 433    SHADER_OPCODE_FIND_LIVE_CHANNEL,
 434
 435    /**
 436     * Pick the channel from its first source register given by the index
 437     * specified as second source.  Useful for variable indexing of surfaces.
 438     *
 439     * Note that because the result of this instruction is by definition
 440     * uniform and it can always be splatted to multiple channels using a
 441     * scalar regioning mode, only the first channel of the destination region
 442     * is guaranteed to be updated, which implies that BROADCAST instructions
 443     * should usually be marked force_writemask_all.
 444     */
 445    SHADER_OPCODE_BROADCAST,
 446
 447    VEC4_OPCODE_MOV_BYTES,
 448    VEC4_OPCODE_PACK_BYTES,
 449    VEC4_OPCODE_UNPACK_UNIFORM,
 450    VEC4_OPCODE_FROM_DOUBLE,
 451    VEC4_OPCODE_TO_DOUBLE,
 452    VEC4_OPCODE_PICK_LOW_32BIT,
 453    VEC4_OPCODE_PICK_HIGH_32BIT,
 454    VEC4_OPCODE_SET_LOW_32BIT,
 455    VEC4_OPCODE_SET_HIGH_32BIT,
 456
 457    FS_OPCODE_DDX_COARSE,
 458    FS_OPCODE_DDX_FINE,
 459    /**
 460     * Compute dFdy(), dFdyCoarse(), or dFdyFine().
 461     */
 462    FS_OPCODE_DDY_COARSE,
 463    FS_OPCODE_DDY_FINE,
 464    FS_OPCODE_CINTERP,
 465    FS_OPCODE_LINTERP,
 466    FS_OPCODE_PIXEL_X,
 467    FS_OPCODE_PIXEL_Y,
 468    FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
 469    FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
 470    FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
 471    FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,
 472    FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
 473    FS_OPCODE_GET_BUFFER_SIZE,
 474    FS_OPCODE_MOV_DISPATCH_TO_FLAGS,
 475    FS_OPCODE_DISCARD_JUMP,
 476    FS_OPCODE_SET_SAMPLE_ID,
 477    FS_OPCODE_PACK_HALF_2x16_SPLIT,
 478    FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X,
 479    FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y,
 480    FS_OPCODE_PLACEHOLDER_HALT,
 481    FS_OPCODE_INTERPOLATE_AT_SAMPLE,
 482    FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
 483    FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
 484
 485    VS_OPCODE_URB_WRITE,
 486    VS_OPCODE_PULL_CONSTANT_LOAD,
 487    VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
 488    VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
 489
 490    VS_OPCODE_GET_BUFFER_SIZE,
 491
 492    VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
 493
 494    /**
 495     * Write geometry shader output data to the URB.
 496     *
 497     * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
 498     * R0 to the first MRF.  This allows the geometry shader to override the
 499     * "Slot {0,1} Offset" fields in the message header.
 500     */
 501    GS_OPCODE_URB_WRITE,
 502
 503    /**
 504     * Write geometry shader output data to the URB and request a new URB
 505     * handle (gen6).
 506     *
 507     * This opcode doesn't do an implied move from R0 to the first MRF.
 508     */
 509    GS_OPCODE_URB_WRITE_ALLOCATE,
 510
 511    /**
 512     * Terminate the geometry shader thread by doing an empty URB write.
 513     *
 514     * This opcode doesn't do an implied move from R0 to the first MRF.  This
 515     * allows the geometry shader to override the "GS Number of Output Vertices
 516     * for Slot {0,1}" fields in the message header.
 517     */
 518    GS_OPCODE_THREAD_END,
 519
 520    /**
 521     * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
 522     *
 523     * - dst is the MRF containing the message header.
 524     *
 525     * - src0.x indicates which portion of the URB should be written to (e.g. a
 526     *   vertex number)
 527     *
 528     * - src1 is an immediate multiplier which will be applied to src0
 529     *   (e.g. the size of a single vertex in the URB).
 530     *
 531     * Note: the hardware will apply this offset *in addition to* the offset in
 532     * vec4_instruction::offset.
 533     */
 534    GS_OPCODE_SET_WRITE_OFFSET,
 535
 536    /**
 537     * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
 538     * URB_WRITE message header.
 539     *
 540     * - dst is the MRF containing the message header.
 541     *
 542     * - src0.x is the vertex count.  The upper 16 bits will be ignored.
 543     */
 544    GS_OPCODE_SET_VERTEX_COUNT,
 545
 546    /**
 547     * Set DWORD 2 of dst to the value in src.
 548     */
 549    GS_OPCODE_SET_DWORD_2,
 550
 551    /**
 552     * Prepare the dst register for storage in the "Channel Mask" fields of a
 553     * URB_WRITE message header.
 554     *
 555     * DWORD 4 of dst is shifted left by 4 bits, so that later,
 556     * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
 557     * final channel mask.
 558     *
 559     * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
 560     * form the final channel mask, DWORDs 0 and 4 of the dst register must not
 561     * have any extraneous bits set prior to execution of this opcode (that is,
 562     * they should be in the range 0x0 to 0xf).
 563     */
 564    GS_OPCODE_PREPARE_CHANNEL_MASKS,
 565
 566    /**
 567     * Set the "Channel Mask" fields of a URB_WRITE message header.
 568     *
 569     * - dst is the MRF containing the message header.
 570     *
 571     * - src.x is the channel mask, as prepared by
 572     *   GS_OPCODE_PREPARE_CHANNEL_MASKS.  DWORDs 0 and 4 are OR'ed together to
 573     *   form the final channel mask.
 574     */
 575    GS_OPCODE_SET_CHANNEL_MASKS,
 576
 577    /**
 578     * Get the "Instance ID" fields from the payload.
 579     *
 580     * - dst is the GRF for gl_InvocationID.
 581     */
 582    GS_OPCODE_GET_INSTANCE_ID,
 583
 584    /**
 585     * Send a FF_SYNC message to allocate initial URB handles (gen6).
 586     *
 587     * - dst will be used as the writeback register for the FF_SYNC operation.
 588     *
 589     * - src0 is the number of primitives written.
 590     *
 591     * - src1 is the value to hold in M0.0: number of SO vertices to write
 592     *   and number of SO primitives needed. Its value will be overwritten
 593     *   with the SVBI values if transform feedback is enabled.
 594     *
 595     * Note: This opcode uses an implicit MRF register for the ff_sync message
 596     * header, so the caller is expected to set inst->base_mrf and initialize
 597     * that MRF register to r0. This opcode will also write to this MRF register
 598     * to include the allocated URB handle so it can then be reused directly as
 599     * the header in the URB write operation we are allocating the handle for.
 600     */
 601    GS_OPCODE_FF_SYNC,
 602
 603    /**
 604     * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
 605     * register.
 606     *
 607     * - dst is the GRF where PrimitiveID information will be moved.
 608     */
 609    GS_OPCODE_SET_PRIMITIVE_ID,
 610
 611    /**
 612     * Write transform feedback data to the SVB by sending a SVB WRITE message.
 613     * Used in gen6.
 614     *
 615     * - dst is the MRF register containing the message header.
 616     *
 617     * - src0 is the register where the vertex data is going to be copied from.
 618     *
 619     * - src1 is the destination register when write commit occurs.
 620     */
 621    GS_OPCODE_SVB_WRITE,
 622
 623    /**
 624     * Set destination index in the SVB write message payload (M0.5). Used
 625     * in gen6 for transform feedback.
 626     *
 627     * - dst is the header to save the destination indices for SVB WRITE.
 628     * - src is the register that holds the destination indices value.
 629     */
 630    GS_OPCODE_SVB_SET_DST_INDEX,
 631
 632    /**
 633     * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
 634     * Used in gen6 for transform feedback.
 635     *
 636     * - dst will hold the register with the final Mx.0 value.
 637     *
 638     * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
 639     *
 640     * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
 641     *
 642     * - src2 is the value to hold in M0: number of SO vertices to write
 643     *   and number of SO primitives needed.
 644     */
 645    GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
 646
 647    /**
 648     * Terminate the compute shader.
 649     */
 650    CS_OPCODE_CS_TERMINATE,
 651
 652    /**
 653     * GLSL barrier()
 654     */
 655    SHADER_OPCODE_BARRIER,
 656
 657    /**
 658     * Calculate the high 32-bits of a 32x32 multiply.
 659     */
 660    SHADER_OPCODE_MULH,
 661
 662    /**
 663     * A MOV that uses VxH indirect addressing.
 664     *
 665     * Source 0: A register to start from (HW_REG).
 666     * Source 1: An indirect offset (in bytes, UD GRF).
 667     * Source 2: The length of the region that could be accessed (in bytes,
 668     *           UD immediate).
 669     */
 670    SHADER_OPCODE_MOV_INDIRECT,
 671
 672    VEC4_OPCODE_URB_READ,
 673    TCS_OPCODE_GET_INSTANCE_ID,
 674    TCS_OPCODE_URB_WRITE,
 675    TCS_OPCODE_SET_INPUT_URB_OFFSETS,
 676    TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
 677    TCS_OPCODE_GET_PRIMITIVE_ID,
 678    TCS_OPCODE_CREATE_BARRIER_HEADER,
 679    TCS_OPCODE_SRC0_010_IS_ZERO,
 680    TCS_OPCODE_RELEASE_INPUT,
 681    TCS_OPCODE_THREAD_END,
 682
 683    TES_OPCODE_GET_PRIMITIVE_ID,
 684    TES_OPCODE_CREATE_INPUT_READ_HEADER,
 685    TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
 686 };
 687
 688 enum brw_urb_write_flags {
 689    BRW_URB_WRITE_NO_FLAGS = 0,
 690
 691    /**
 692     * Causes a new URB entry to be allocated, and its address stored in the
 693     * destination register (gen < 7).
 694     */
 695    BRW_URB_WRITE_ALLOCATE = 0x1,
 696
 697    /**
 698     * Causes the current URB entry to be deallocated (gen < 7).
 699     */
 700    BRW_URB_WRITE_UNUSED = 0x2,
 701
 702    /**
 703     * Causes the thread to terminate.
 704     */
 705    BRW_URB_WRITE_EOT = 0x4,
 706
 707    /**
 708     * Indicates that the given URB entry is complete, and may be sent further
 709     * down the 3D pipeline (gen < 7).
 710     */
 711    BRW_URB_WRITE_COMPLETE = 0x8,
 712
 713    /**
 714     * Indicates that an additional offset (which may be different for the two
 715     * vec4 slots) is stored in the message header (gen == 7).
 716     */
 717    BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
 718
 719    /**
 720     * Indicates that the channel masks in the URB_WRITE message header should
 721     * not be overridden to 0xff (gen == 7).
 722     */
 723    BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
 724
 725    /**
 726     * Indicates that the data should be sent to the URB using the
 727     * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7).  This
 728     * causes offsets to be interpreted as multiples of an OWORD instead of an
 729     * HWORD, and only allows one OWORD to be written.
 730     */
 731    BRW_URB_WRITE_OWORD = 0x40,
 732
 733    /**
 734     * Convenient combination of flags: end the thread while simultaneously
 735     * marking the given URB entry as complete.
 736     */
 737    BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
 738
 739    /**
 740     * Convenient combination of flags: mark the given URB entry as complete
 741     * and simultaneously allocate a new one.
 742     */
 743    BRW_URB_WRITE_ALLOCATE_COMPLETE =
 744       BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
 745 };
 746
 747 enum fb_write_logical_srcs {
 748    FB_WRITE_LOGICAL_SRC_COLOR0,      /* REQUIRED */
 749    FB_WRITE_LOGICAL_SRC_COLOR1,      /* for dual source blend messages */
 750    FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
 751    FB_WRITE_LOGICAL_SRC_SRC_DEPTH,   /* gl_FragDepth */
 752    FB_WRITE_LOGICAL_SRC_DST_DEPTH,   /* GEN4-5: passthrough from thread */
 753    FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
 754    FB_WRITE_LOGICAL_SRC_OMASK,       /* Sample Mask (gl_SampleMask) */
 755    FB_WRITE_LOGICAL_SRC_COMPONENTS,  /* REQUIRED */
 756    FB_WRITE_LOGICAL_NUM_SRCS
 757 };
 758
 759 enum tex_logical_srcs {
 760    /** Texture coordinates */
 761    TEX_LOGICAL_SRC_COORDINATE,
 762    /** Shadow comparator */
 763    TEX_LOGICAL_SRC_SHADOW_C,
 764    /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
 765    TEX_LOGICAL_SRC_LOD,
 766    /** dPdy if the operation takes explicit derivatives */
 767    TEX_LOGICAL_SRC_LOD2,
 768    /** Sample index */
 769    TEX_LOGICAL_SRC_SAMPLE_INDEX,
 770    /** MCS data */
 771    TEX_LOGICAL_SRC_MCS,
 772    /** REQUIRED: Texture surface index */
 773    TEX_LOGICAL_SRC_SURFACE,
 774    /** Texture sampler index */
 775    TEX_LOGICAL_SRC_SAMPLER,
 776    /** Texel offset for gathers */
 777    TEX_LOGICAL_SRC_TG4_OFFSET,
 778    /** REQUIRED: Number of coordinate components (as UD immediate) */
 779    TEX_LOGICAL_SRC_COORD_COMPONENTS,
 780    /** REQUIRED: Number of derivative components (as UD immediate) */
 781    TEX_LOGICAL_SRC_GRAD_COMPONENTS,
 782
 783    TEX_LOGICAL_NUM_SRCS,
 784 };
 785
 786 #ifdef __cplusplus
 787 /**
 788  * Allow brw_urb_write_flags enums to be ORed together.
 789  */
 790 inline brw_urb_write_flags
 791 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
 792 {
 793    return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
 794                                            static_cast<int>(y));
 795 }
 796 #endif
 797
 798 enum PACKED brw_predicate {
 799    BRW_PREDICATE_NONE                =  0,
 800    BRW_PREDICATE_NORMAL              =  1,
 801    BRW_PREDICATE_ALIGN1_ANYV         =  2,
 802    BRW_PREDICATE_ALIGN1_ALLV         =  3,
 803    BRW_PREDICATE_ALIGN1_ANY2H        =  4,
 804    BRW_PREDICATE_ALIGN1_ALL2H        =  5,
 805    BRW_PREDICATE_ALIGN1_ANY4H        =  6,
 806    BRW_PREDICATE_ALIGN1_ALL4H        =  7,
 807    BRW_PREDICATE_ALIGN1_ANY8H        =  8,
 808    BRW_PREDICATE_ALIGN1_ALL8H        =  9,
 809    BRW_PREDICATE_ALIGN1_ANY16H       = 10,
 810    BRW_PREDICATE_ALIGN1_ALL16H       = 11,
 811    BRW_PREDICATE_ALIGN1_ANY32H       = 12,
 812    BRW_PREDICATE_ALIGN1_ALL32H       = 13,
 813    BRW_PREDICATE_ALIGN16_REPLICATE_X =  2,
 814    BRW_PREDICATE_ALIGN16_REPLICATE_Y =  3,
 815    BRW_PREDICATE_ALIGN16_REPLICATE_Z =  4,
 816    BRW_PREDICATE_ALIGN16_REPLICATE_W =  5,
 817    BRW_PREDICATE_ALIGN16_ANY4H       =  6,
 818    BRW_PREDICATE_ALIGN16_ALL4H       =  7,
 819 };
 820
 821 enum PACKED brw_reg_file {
 822    BRW_ARCHITECTURE_REGISTER_FILE = 0,
 823    BRW_GENERAL_REGISTER_FILE      = 1,
 824    BRW_MESSAGE_REGISTER_FILE      = 2,
 825    BRW_IMMEDIATE_VALUE            = 3,
 826
 827    ARF = BRW_ARCHITECTURE_REGISTER_FILE,
 828    FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
 829    MRF = BRW_MESSAGE_REGISTER_FILE,
 830    IMM = BRW_IMMEDIATE_VALUE,
 831
 832    /* These are not hardware values */
 833    VGRF,
 834    ATTR,
 835    UNIFORM, /* prog_data->params[reg] */
 836    BAD_FILE,
 837 };
 838
 839 #define BRW_HW_REG_TYPE_UD  0
 840 #define BRW_HW_REG_TYPE_D   1
 841 #define BRW_HW_REG_TYPE_UW  2
 842 #define BRW_HW_REG_TYPE_W   3
 843 #define BRW_HW_REG_TYPE_F   7
 844 #define GEN8_HW_REG_TYPE_UQ 8
 845 #define GEN8_HW_REG_TYPE_Q  9
 846
 847 #define BRW_HW_REG_NON_IMM_TYPE_UB  4
 848 #define BRW_HW_REG_NON_IMM_TYPE_B   5
 849 #define GEN7_HW_REG_NON_IMM_TYPE_DF 6
 850 #define GEN8_HW_REG_NON_IMM_TYPE_HF 10
 851
 852 #define BRW_HW_REG_IMM_TYPE_UV  4 /* Gen6+ packed unsigned immediate vector */
 853 #define BRW_HW_REG_IMM_TYPE_VF  5 /* packed float immediate vector */
 854 #define BRW_HW_REG_IMM_TYPE_V   6 /* packed int imm. vector; uword dest only */
 855 #define GEN8_HW_REG_IMM_TYPE_DF 10
 856 #define GEN8_HW_REG_IMM_TYPE_HF 11
 857
 858 /* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
 859  * the types were implied. IVB adds BFE and BFI2 that operate on doublewords
 860  * and unsigned doublewords, so a new field is also available in the da3src
 861  * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select
 862  * dst and shared-src types. The values are different from BRW_REGISTER_TYPE_*.
 863  */
 864 #define BRW_3SRC_TYPE_F  0
 865 #define BRW_3SRC_TYPE_D  1
 866 #define BRW_3SRC_TYPE_UD 2
 867 #define BRW_3SRC_TYPE_DF 3
 868
 869 #define BRW_ARF_NULL                  0x00
 870 #define BRW_ARF_ADDRESS               0x10
 871 #define BRW_ARF_ACCUMULATOR           0x20
 872 #define BRW_ARF_FLAG                  0x30
 873 #define BRW_ARF_MASK                  0x40
 874 #define BRW_ARF_MASK_STACK            0x50
 875 #define BRW_ARF_MASK_STACK_DEPTH      0x60
 876 #define BRW_ARF_STATE                 0x70
 877 #define BRW_ARF_CONTROL               0x80
 878 #define BRW_ARF_NOTIFICATION_COUNT    0x90
 879 #define BRW_ARF_IP                    0xA0
 880 #define BRW_ARF_TDR                   0xB0
 881 #define BRW_ARF_TIMESTAMP             0xC0
 882
 883 #define BRW_MRF_COMPR4                  (1 << 7)
 884
 885 #define BRW_AMASK   0
 886 #define BRW_IMASK   1
 887 #define BRW_LMASK   2
 888 #define BRW_CMASK   3
 889
 890
 891
 892 #define BRW_THREAD_NORMAL     0
 893 #define BRW_THREAD_ATOMIC     1
 894 #define BRW_THREAD_SWITCH     2
 895
 896 enum PACKED brw_vertical_stride {
 897    BRW_VERTICAL_STRIDE_0               = 0,
 898    BRW_VERTICAL_STRIDE_1               = 1,
 899    BRW_VERTICAL_STRIDE_2               = 2,
 900    BRW_VERTICAL_STRIDE_4               = 3,
 901    BRW_VERTICAL_STRIDE_8               = 4,
 902    BRW_VERTICAL_STRIDE_16              = 5,
 903    BRW_VERTICAL_STRIDE_32              = 6,
 904    BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
 905 };
 906
 907 enum PACKED brw_width {
 908    BRW_WIDTH_1  = 0,
 909    BRW_WIDTH_2  = 1,
 910    BRW_WIDTH_4  = 2,
 911    BRW_WIDTH_8  = 3,
 912    BRW_WIDTH_16 = 4,
 913 };
 914
 915 /**
 916  * Message target: Shared Function ID for where to SEND a message.
 917  *
 918  * These are enumerated in the ISA reference under "send - Send Message".
 919  * In particular, see the following tables:
 920  * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
 921  * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
 922  * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
 923  */
 924 enum brw_message_target {
 925    BRW_SFID_NULL                     = 0,
 926    BRW_SFID_MATH                     = 1, /* Only valid on Gen4-5 */
 927    BRW_SFID_SAMPLER                  = 2,
 928    BRW_SFID_MESSAGE_GATEWAY          = 3,
 929    BRW_SFID_DATAPORT_READ            = 4,
 930    BRW_SFID_DATAPORT_WRITE           = 5,
 931    BRW_SFID_URB                      = 6,
 932    BRW_SFID_THREAD_SPAWNER           = 7,
 933    BRW_SFID_VME                      = 8,
 934
 935    GEN6_SFID_DATAPORT_SAMPLER_CACHE  = 4,
 936    GEN6_SFID_DATAPORT_RENDER_CACHE   = 5,
 937    GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
 938
 939    GEN7_SFID_DATAPORT_DATA_CACHE     = 10,
 940    GEN7_SFID_PIXEL_INTERPOLATOR      = 11,
 941    HSW_SFID_DATAPORT_DATA_CACHE_1    = 12,
 942    HSW_SFID_CRE                      = 13,
 943 };
 944
 945 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE     10
 946
 947 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32     0
 948 #define BRW_SAMPLER_RETURN_FORMAT_UINT32      2
 949 #define BRW_SAMPLER_RETURN_FORMAT_SINT32      3
 950
 951 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE              0
 952 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE             0
 953 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS        0
 954 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX             1
 955 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD        1
 956 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD         1
 957 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS  2
 958 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS    2
 959 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE    0
 960 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE     2
 961 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
 962 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
 963 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE  1
 964 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO           2
 965 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO            2
 966 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD                3
 967 #define BRW_SAMPLER_MESSAGE_SIMD8_LD                  3
 968 #define BRW_SAMPLER_MESSAGE_SIMD16_LD                 3
 969
 970 #define GEN5_SAMPLER_MESSAGE_SAMPLE              0
 971 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS         1
 972 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD          2
 973 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE      3
 974 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS       4
 975 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
 976 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE  6
 977 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD           7
 978 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4      8
 979 #define GEN5_SAMPLER_MESSAGE_LOD                 9
 980 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO      10
 981 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO   11
 982 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C    16
 983 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO   17
 984 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
 985 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
 986 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ           24
 987 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ         25
 988 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ        26
 989 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W     28
 990 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS       29
 991 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS       30
 992 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS       31
 993
 994 /* for GEN5 only */
 995 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2                   0
 996 #define BRW_SAMPLER_SIMD_MODE_SIMD8                     1
 997 #define BRW_SAMPLER_SIMD_MODE_SIMD16                    2
 998 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64                 3
 999
1000 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
1001  * behavior by setting bit 22 of dword 2 in the message header. */
1002 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D                   0
1003 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2        (1 << 22)
1004
1005 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW   0
1006 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH  1
1007 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS     2
1008 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS     3
1009 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS     4
1010 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n)              \
1011    ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW :    \
1012     (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS :      \
1013     (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS :     \
1014     (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS :     \
1015     (abort(), ~0))
1016
1017 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD     0
1018 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS    2
1019
1020 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS   2
1021 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS  3
1022
1023 /* This one stays the same across generations. */
1024 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ          0
1025 /* GEN4 */
1026 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     1
1027 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          2
1028 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      3
1029 /* G45, GEN5 */
1030 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ         1
1031 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     2
1032 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ      3
1033 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          4
1034 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      6
1035 /* GEN6 */
1036 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ        1
1037 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     2
1038 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          4
1039 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ  5
1040 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      6
1041
1042 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE      0
1043 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE    1
1044 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE   2
1045
1046 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE                0
1047 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED     1
1048 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01         2
1049 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23         3
1050 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01       4
1051
1052 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE                0
1053 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE           1
1054 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE                2
1055 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE            3
1056 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE              4
1057 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE     5
1058 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE               7
1059
1060 /* GEN6 */
1061 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE              7
1062 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE               8
1063 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE          9
1064 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE               10
1065 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE           11
1066 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE             12
1067 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE               13
1068 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE       14
1069
1070 /* GEN7 */
1071 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ                           4
1072 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ                         5
1073 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP                            6
1074 #define GEN7_DATAPORT_RC_MEMORY_FENCE                               7
1075 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE                          10
1076 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE                        12
1077 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE                        13
1078 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ                           0
1079 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ                 1
1080 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ                      2
1081 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ                       3
1082 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ                        4
1083 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ                       5
1084 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP                          6
1085 #define GEN7_DATAPORT_DC_MEMORY_FENCE                               7
1086 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE                          8
1087 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE                     10
1088 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE                      11
1089 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE                       12
1090 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE                      13
1091
1092 #define GEN7_DATAPORT_SCRATCH_READ                            ((1 << 18) | \
1093                                                                (0 << 17))
1094 #define GEN7_DATAPORT_SCRATCH_WRITE                           ((1 << 18) | \
1095                                                                (1 << 17))
1096 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT                        12
1097
1098 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET     0
1099 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE            1
1100 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID          2
1101 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET   3
1102
1103 /* HSW */
1104 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ                      0
1105 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ            1
1106 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ                 2
1107 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ                  3
1108 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ                   4
1109 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE                          7
1110 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE                     8
1111 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE                10
1112 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE                 11
1113 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE                  12
1114
1115 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ                  1
1116 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP                     2
1117 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2             3
1118 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ                      4
1119 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ                    5
1120 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP                       6
1121 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2               7
1122 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE                 9
1123 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE                     10
1124 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP                     11
1125 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2             12
1126 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE                   13
1127
1128 /* GEN9 */
1129 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE                        12
1130 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ                         13
1131
1132 /* Dataport special binding table indices: */
1133 #define BRW_BTI_STATELESS                255
1134 #define GEN7_BTI_SLM                     254
1135 /* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the
1136  * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW,
1137  * CHV and at least some pre-production steppings of SKL due to
1138  * WaForceEnableNonCoherent, HDC memory access may have been overridden by the
1139  * kernel to be non-coherent (matching the behavior of the same BTI on
1140  * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253.
1141  */
1142 #define GEN8_BTI_STATELESS_IA_COHERENT   255
1143 #define GEN8_BTI_STATELESS_NON_COHERENT  253
1144
1145 /* dataport atomic operations. */
1146 #define BRW_AOP_AND                   1
1147 #define BRW_AOP_OR                    2
1148 #define BRW_AOP_XOR                   3
1149 #define BRW_AOP_MOV                   4
1150 #define BRW_AOP_INC                   5
1151 #define BRW_AOP_DEC                   6
1152 #define BRW_AOP_ADD                   7
1153 #define BRW_AOP_SUB                   8
1154 #define BRW_AOP_REVSUB                9
1155 #define BRW_AOP_IMAX                  10
1156 #define BRW_AOP_IMIN                  11
1157 #define BRW_AOP_UMAX                  12
1158 #define BRW_AOP_UMIN                  13
1159 #define BRW_AOP_CMPWR                 14
1160 #define BRW_AOP_PREDEC                15
1161
1162 #define BRW_MATH_FUNCTION_INV                              1
1163 #define BRW_MATH_FUNCTION_LOG                              2
1164 #define BRW_MATH_FUNCTION_EXP                              3
1165 #define BRW_MATH_FUNCTION_SQRT                             4
1166 #define BRW_MATH_FUNCTION_RSQ                              5
1167 #define BRW_MATH_FUNCTION_SIN                              6
1168 #define BRW_MATH_FUNCTION_COS                              7
1169 #define BRW_MATH_FUNCTION_SINCOS                           8 /* gen4, gen5 */
1170 #define BRW_MATH_FUNCTION_FDIV                             9 /* gen6+ */
1171 #define BRW_MATH_FUNCTION_POW                              10
1172 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER   11
1173 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT                 12
1174 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER                13
1175 #define GEN8_MATH_FUNCTION_INVM                            14
1176 #define GEN8_MATH_FUNCTION_RSQRTM                          15
1177
1178 #define BRW_MATH_INTEGER_UNSIGNED     0
1179 #define BRW_MATH_INTEGER_SIGNED       1
1180
1181 #define BRW_MATH_PRECISION_FULL        0
1182 #define BRW_MATH_PRECISION_PARTIAL     1
1183
1184 #define BRW_MATH_SATURATE_NONE         0
1185 #define BRW_MATH_SATURATE_SATURATE     1
1186
1187 #define BRW_MATH_DATA_VECTOR  0
1188 #define BRW_MATH_DATA_SCALAR  1
1189
1190 #define BRW_URB_OPCODE_WRITE_HWORD  0
1191 #define BRW_URB_OPCODE_WRITE_OWORD  1
1192 #define BRW_URB_OPCODE_READ_HWORD   2
1193 #define BRW_URB_OPCODE_READ_OWORD   3
1194 #define GEN7_URB_OPCODE_ATOMIC_MOV  4
1195 #define GEN7_URB_OPCODE_ATOMIC_INC  5
1196 #define GEN8_URB_OPCODE_ATOMIC_ADD  6
1197 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1198 #define GEN8_URB_OPCODE_SIMD8_READ  8
1199
1200 #define BRW_URB_SWIZZLE_NONE          0
1201 #define BRW_URB_SWIZZLE_INTERLEAVE    1
1202 #define BRW_URB_SWIZZLE_TRANSPOSE     2
1203
1204 #define BRW_SCRATCH_SPACE_SIZE_1K     0
1205 #define BRW_SCRATCH_SPACE_SIZE_2K     1
1206 #define BRW_SCRATCH_SPACE_SIZE_4K     2
1207 #define BRW_SCRATCH_SPACE_SIZE_8K     3
1208 #define BRW_SCRATCH_SPACE_SIZE_16K    4
1209 #define BRW_SCRATCH_SPACE_SIZE_32K    5
1210 #define BRW_SCRATCH_SPACE_SIZE_64K    6
1211 #define BRW_SCRATCH_SPACE_SIZE_128K   7
1212 #define BRW_SCRATCH_SPACE_SIZE_256K   8
1213 #define BRW_SCRATCH_SPACE_SIZE_512K   9
1214 #define BRW_SCRATCH_SPACE_SIZE_1M     10
1215 #define BRW_SCRATCH_SPACE_SIZE_2M     11
1216
1217 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY         0
1218 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY        1
1219 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG          2
1220 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP        3
1221 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG          4
1222 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1223 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE      6
1224
1225
1226 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1227  * is 2^9, or 512.  It's counted in multiples of 64 bytes.
1228  *
1229  * Identical for VS, DS, and HS.
1230  */
1231 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES                (512*64)
1232 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES                (512*64)
1233 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES                (512*64)
1234 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES                (512*64)
1235
1236 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1237  * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1238  */
1239 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES                (5*128)
1240
1241 /* GS Thread Payload
1242  */
1243 /* R0 */
1244 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT              27
1245
1246 #endif /* BRW_EU_DEFINES_H */