2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "program/hash_table.h"
38 #include "brw_context.h"
43 #include "../glsl/glsl_types.h"
44 #include "../glsl/ir_optimization.h"
45 #include "../glsl/ir_print_visitor.h"
48 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
49 GRF
= BRW_GENERAL_REGISTER_FILE
,
50 MRF
= BRW_MESSAGE_REGISTER_FILE
,
51 IMM
= BRW_IMMEDIATE_VALUE
,
52 FIXED_HW_REG
, /* a struct brw_reg */
53 UNIFORM
, /* prog_data->params[hw_reg] */
58 FS_OPCODE_FB_WRITE
= 256,
76 static int using_new_fs
= -1;
79 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
81 struct brw_shader
*shader
;
83 shader
= talloc_zero(NULL
, struct brw_shader
);
85 shader
->base
.Type
= type
;
86 shader
->base
.Name
= name
;
87 _mesa_init_shader(ctx
, &shader
->base
);
93 struct gl_shader_program
*
94 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
96 struct brw_shader_program
*prog
;
97 prog
= talloc_zero(NULL
, struct brw_shader_program
);
99 prog
->base
.Name
= name
;
100 _mesa_init_shader_program(ctx
, &prog
->base
);
106 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
108 if (!_mesa_ir_compile_shader(ctx
, shader
))
115 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
117 if (using_new_fs
== -1)
118 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
120 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
121 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
123 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
124 void *mem_ctx
= talloc_new(NULL
);
128 talloc_free(shader
->ir
);
129 shader
->ir
= new(shader
) exec_list
;
130 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
132 do_mat_op_to_vec(shader
->ir
);
133 do_mod_to_fract(shader
->ir
);
134 do_div_to_mul_rcp(shader
->ir
);
135 do_sub_to_add_neg(shader
->ir
);
136 do_explog_to_explog2(shader
->ir
);
138 brw_do_channel_expressions(shader
->ir
);
139 brw_do_vector_splitting(shader
->ir
);
144 progress
= do_common_optimization(shader
->ir
, true) || progress
;
147 validate_ir_tree(shader
->ir
);
149 reparent_ir(shader
->ir
, shader
->ir
);
150 talloc_free(mem_ctx
);
154 if (!_mesa_ir_link_shader(ctx
, prog
))
161 type_size(const struct glsl_type
*type
)
163 unsigned int size
, i
;
165 switch (type
->base_type
) {
168 case GLSL_TYPE_FLOAT
:
170 return type
->components();
171 case GLSL_TYPE_ARRAY
:
172 /* FINISHME: uniform/varying arrays. */
173 return type_size(type
->fields
.array
) * type
->length
;
174 case GLSL_TYPE_STRUCT
:
176 for (i
= 0; i
< type
->length
; i
++) {
177 size
+= type_size(type
->fields
.structure
[i
].type
);
180 case GLSL_TYPE_SAMPLER
:
181 /* Samplers take up no register space, since they're baked in at
186 assert(!"not reached");
193 /* Callers of this talloc-based new need not call delete. It's
194 * easier to just talloc_free 'ctx' (or any of its ancestors). */
195 static void* operator new(size_t size
, void *ctx
)
199 node
= talloc_size(ctx
, size
);
200 assert(node
!= NULL
);
205 /** Generic unset register constructor. */
208 this->file
= BAD_FILE
;
210 this->reg_offset
= 0;
216 /** Immediate value constructor. */
222 this->type
= BRW_REGISTER_TYPE_F
;
228 /** Immediate value constructor. */
234 this->type
= BRW_REGISTER_TYPE_D
;
240 /** Immediate value constructor. */
246 this->type
= BRW_REGISTER_TYPE_UD
;
252 /** Fixed brw_reg Immediate value constructor. */
253 fs_reg(struct brw_reg fixed_hw_reg
)
255 this->file
= FIXED_HW_REG
;
256 this->fixed_hw_reg
= fixed_hw_reg
;
259 this->type
= fixed_hw_reg
.type
;
264 fs_reg(enum register_file file
, int hw_reg
);
265 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
267 /** Register file: ARF, GRF, MRF, IMM. */
268 enum register_file file
;
269 /** Abstract register number. 0 = fixed hw reg */
271 /** Offset within the abstract register. */
273 /** HW register number. Generally unset until register allocation. */
275 /** Register type. BRW_REGISTER_TYPE_* */
279 struct brw_reg fixed_hw_reg
;
281 /** Value for file == BRW_IMMMEDIATE_FILE */
289 static const fs_reg reg_undef
;
290 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
292 class fs_inst
: public exec_node
{
294 /* Callers of this talloc-based new need not call delete. It's
295 * easier to just talloc_free 'ctx' (or any of its ancestors). */
296 static void* operator new(size_t size
, void *ctx
)
300 node
= talloc_zero_size(ctx
, size
);
301 assert(node
!= NULL
);
308 this->opcode
= BRW_OPCODE_NOP
;
309 this->saturate
= false;
310 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
311 this->predicated
= false;
313 this->shadow_compare
= false;
324 this->opcode
= opcode
;
327 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
330 this->opcode
= opcode
;
335 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
338 this->opcode
= opcode
;
344 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
347 this->opcode
= opcode
;
354 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
359 int conditional_mod
; /**< BRW_CONDITIONAL_* */
361 int mlen
; /** SEND message length */
366 * Annotation for the generated IR. One of the two can be set.
369 const char *annotation
;
373 class fs_visitor
: public ir_visitor
377 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
382 this->intel
= &brw
->intel
;
383 this->ctx
= &intel
->ctx
;
384 this->mem_ctx
= talloc_new(NULL
);
385 this->shader
= shader
;
387 this->next_abstract_grf
= 1;
388 this->variable_ht
= hash_table_ctor(0,
389 hash_table_pointer_hash
,
390 hash_table_pointer_compare
);
392 this->frag_color
= NULL
;
393 this->frag_data
= NULL
;
394 this->frag_depth
= NULL
;
395 this->first_non_payload_grf
= 0;
397 this->current_annotation
= NULL
;
398 this->annotation_string
= NULL
;
399 this->annotation_ir
= NULL
;
403 talloc_free(this->mem_ctx
);
404 hash_table_dtor(this->variable_ht
);
407 fs_reg
*variable_storage(ir_variable
*var
);
409 void visit(ir_variable
*ir
);
410 void visit(ir_assignment
*ir
);
411 void visit(ir_dereference_variable
*ir
);
412 void visit(ir_dereference_record
*ir
);
413 void visit(ir_dereference_array
*ir
);
414 void visit(ir_expression
*ir
);
415 void visit(ir_texture
*ir
);
416 void visit(ir_if
*ir
);
417 void visit(ir_constant
*ir
);
418 void visit(ir_swizzle
*ir
);
419 void visit(ir_return
*ir
);
420 void visit(ir_loop
*ir
);
421 void visit(ir_loop_jump
*ir
);
422 void visit(ir_discard
*ir
);
423 void visit(ir_call
*ir
);
424 void visit(ir_function
*ir
);
425 void visit(ir_function_signature
*ir
);
427 fs_inst
*emit(fs_inst inst
);
428 void assign_curb_setup();
429 void assign_urb_setup();
431 void generate_code();
432 void generate_fb_write(fs_inst
*inst
);
433 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
434 struct brw_reg
*src
);
435 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
436 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
437 void generate_discard(fs_inst
*inst
);
439 void emit_dummy_fs();
440 void emit_interpolation();
441 void emit_pinterp(int location
);
442 void emit_fb_writes();
444 struct brw_reg
interp_reg(int location
, int channel
);
446 struct brw_context
*brw
;
447 struct intel_context
*intel
;
449 struct brw_wm_compile
*c
;
450 struct brw_compile
*p
;
451 struct brw_shader
*shader
;
453 exec_list instructions
;
454 int next_abstract_grf
;
455 struct hash_table
*variable_ht
;
456 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
457 int first_non_payload_grf
;
459 /** @{ debug annotation info */
460 const char *current_annotation
;
461 ir_instruction
*base_ir
;
462 const char **annotation_string
;
463 ir_instruction
**annotation_ir
;
468 /* Result of last visit() method. */
476 fs_reg interp_attrs
[64];
482 /** Fixed HW reg constructor. */
483 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
487 this->reg_offset
= 0;
488 this->hw_reg
= hw_reg
;
489 this->type
= BRW_REGISTER_TYPE_F
;
494 /** Automatic reg constructor. */
495 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
498 this->reg
= v
->next_abstract_grf
;
499 this->reg_offset
= 0;
500 v
->next_abstract_grf
+= type_size(type
);
505 switch (type
->base_type
) {
506 case GLSL_TYPE_FLOAT
:
507 this->type
= BRW_REGISTER_TYPE_F
;
511 this->type
= BRW_REGISTER_TYPE_D
;
514 this->type
= BRW_REGISTER_TYPE_UD
;
517 assert(!"not reached");
518 this->type
= BRW_REGISTER_TYPE_F
;
524 fs_visitor::variable_storage(ir_variable
*var
)
526 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
530 fs_visitor::visit(ir_variable
*ir
)
534 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
535 this->frag_color
= ir
;
536 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
537 this->frag_data
= ir
;
538 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
539 this->frag_depth
= ir
;
540 assert(!"FINISHME: this hangs currently.");
543 if (ir
->mode
== ir_var_in
) {
544 reg
= &this->interp_attrs
[ir
->location
];
547 if (ir
->mode
== ir_var_uniform
) {
548 const float *vec_values
;
549 int param_index
= c
->prog_data
.nr_params
;
551 /* FINISHME: This is wildly incomplete. */
552 assert(ir
->type
->is_scalar() || ir
->type
->is_vector() ||
553 ir
->type
->is_sampler());
555 const struct gl_program
*fp
= &this->brw
->fragment_program
->Base
;
556 /* Our support for uniforms is piggy-backed on the struct
557 * gl_fragment_program, because that's where the values actually
558 * get stored, rather than in some global gl_shader_program uniform
561 vec_values
= fp
->Parameters
->ParameterValues
[ir
->location
];
562 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
563 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
566 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
570 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
572 hash_table_insert(this->variable_ht
, reg
, ir
);
576 fs_visitor::visit(ir_dereference_variable
*ir
)
578 fs_reg
*reg
= variable_storage(ir
->var
);
583 fs_visitor::visit(ir_dereference_record
*ir
)
589 fs_visitor::visit(ir_dereference_array
*ir
)
594 ir
->array
->accept(this);
595 index
= ir
->array_index
->as_constant();
597 if (ir
->type
->is_matrix()) {
598 element_size
= ir
->type
->vector_elements
;
600 element_size
= type_size(ir
->type
);
604 assert(this->result
.file
== UNIFORM
||
605 (this->result
.file
== GRF
&&
606 this->result
.reg
!= 0));
607 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
609 assert(!"FINISHME: non-constant matrix column");
614 fs_visitor::visit(ir_expression
*ir
)
616 unsigned int operand
;
621 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
622 ir
->operands
[operand
]->accept(this);
623 if (this->result
.file
== BAD_FILE
) {
625 printf("Failed to get tree for expression operand:\n");
626 ir
->operands
[operand
]->accept(&v
);
629 op
[operand
] = this->result
;
631 /* Matrix expression operands should have been broken down to vector
632 * operations already.
634 assert(!ir
->operands
[operand
]->type
->is_matrix());
635 /* And then those vector operands should have been broken down to scalar.
637 assert(!ir
->operands
[operand
]->type
->is_vector());
640 /* Storage for our result. If our result goes into an assignment, it will
641 * just get copy-propagated out, so no worries.
643 this->result
= fs_reg(this, ir
->type
);
645 switch (ir
->operation
) {
646 case ir_unop_logic_not
:
647 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
650 op
[0].negate
= ~op
[0].negate
;
651 this->result
= op
[0];
655 this->result
= op
[0];
658 temp
= fs_reg(this, ir
->type
);
660 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
662 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
663 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
664 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
665 inst
->predicated
= true;
667 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
668 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
669 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
670 inst
->predicated
= true;
674 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
678 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
681 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
685 assert(!"not reached: should be handled by ir_explog_to_explog2");
688 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
691 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
695 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
698 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
702 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
705 assert(!"not reached: should be handled by ir_sub_to_add_neg");
709 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
712 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
715 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
719 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
720 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
721 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
723 case ir_binop_greater
:
724 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
725 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
726 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
728 case ir_binop_lequal
:
729 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
730 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
731 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
733 case ir_binop_gequal
:
734 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
735 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
736 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
739 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
740 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
741 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
743 case ir_binop_nequal
:
744 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
745 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
746 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
749 case ir_binop_logic_xor
:
750 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
753 case ir_binop_logic_or
:
754 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
757 case ir_binop_logic_and
:
758 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
764 assert(!"not reached: should be handled by brw_channel_expressions");
768 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
772 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
778 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
781 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
785 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
786 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
789 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
792 op
[0].negate
= ~op
[0].negate
;
793 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
794 this->result
.negate
= true;
797 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
800 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
804 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
805 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
807 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
808 inst
->predicated
= true;
811 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
812 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
814 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
815 inst
->predicated
= true;
819 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
822 case ir_unop_bit_not
:
824 case ir_binop_lshift
:
825 case ir_binop_rshift
:
826 case ir_binop_bit_and
:
827 case ir_binop_bit_xor
:
828 case ir_binop_bit_or
:
829 assert(!"GLSL 1.30 features unsupported");
835 fs_visitor::visit(ir_assignment
*ir
)
842 /* FINISHME: arrays on the lhs */
843 ir
->lhs
->accept(this);
846 ir
->rhs
->accept(this);
849 /* FINISHME: This should really set to the correct maximal writemask for each
850 * FINISHME: component written (in the loops below). This case can only
851 * FINISHME: occur for matrices, arrays, and structures.
853 if (ir
->write_mask
== 0) {
854 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
855 write_mask
= WRITEMASK_XYZW
;
857 assert(ir
->lhs
->type
->is_vector() || ir
->lhs
->type
->is_scalar());
858 write_mask
= ir
->write_mask
;
861 assert(l
.file
!= BAD_FILE
);
862 assert(r
.file
!= BAD_FILE
);
865 /* Get the condition bool into the predicate. */
866 ir
->condition
->accept(this);
867 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, fs_reg(0)));
868 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
871 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
872 if (i
>= 4 || (write_mask
& (1 << i
))) {
873 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
875 inst
->predicated
= true;
883 fs_visitor::visit(ir_texture
*ir
)
886 fs_inst
*inst
= NULL
;
887 unsigned int mlen
= 0;
889 ir
->coordinate
->accept(this);
890 fs_reg coordinate
= this->result
;
893 fs_reg inv_proj
= fs_reg(this, glsl_type::float_type
);
895 ir
->projector
->accept(this);
896 emit(fs_inst(FS_OPCODE_RCP
, inv_proj
, this->result
));
898 fs_reg proj_coordinate
= fs_reg(this, ir
->coordinate
->type
);
899 for (unsigned int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
900 emit(fs_inst(BRW_OPCODE_MUL
, proj_coordinate
, coordinate
, inv_proj
));
901 coordinate
.reg_offset
++;
902 proj_coordinate
.reg_offset
++;
904 proj_coordinate
.reg_offset
= 0;
906 coordinate
= proj_coordinate
;
909 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
910 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
911 coordinate
.reg_offset
++;
914 /* Pre-Ironlake, the 8-wide sampler always took u,v,r. */
918 if (ir
->shadow_comparitor
) {
919 /* For shadow comparisons, we have to supply u,v,r. */
922 ir
->shadow_comparitor
->accept(this);
923 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
927 /* Do we ever want to handle writemasking on texture samples? Is it
928 * performance relevant?
930 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
934 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
937 ir
->lod_info
.bias
->accept(this);
938 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
941 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
944 ir
->lod_info
.lod
->accept(this);
945 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
948 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
952 assert(!"GLSL 1.30 features unsupported");
958 if (ir
->shadow_comparitor
)
959 inst
->shadow_compare
= true;
964 fs_visitor::visit(ir_swizzle
*ir
)
966 ir
->val
->accept(this);
967 fs_reg val
= this->result
;
969 fs_reg result
= fs_reg(this, ir
->type
);
970 this->result
= result
;
972 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
973 fs_reg channel
= val
;
991 channel
.reg_offset
+= swiz
;
992 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
998 fs_visitor::visit(ir_discard
*ir
)
1000 assert(ir
->condition
== NULL
); /* FINISHME */
1002 emit(fs_inst(FS_OPCODE_DISCARD
));
1006 fs_visitor::visit(ir_constant
*ir
)
1008 fs_reg
reg(this, ir
->type
);
1011 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1012 switch (ir
->type
->base_type
) {
1013 case GLSL_TYPE_FLOAT
:
1014 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1016 case GLSL_TYPE_UINT
:
1017 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1020 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1022 case GLSL_TYPE_BOOL
:
1023 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1026 assert(!"Non-float/uint/int/bool constant");
1033 fs_visitor::visit(ir_if
*ir
)
1037 /* Don't point the annotation at the if statement, because then it plus
1038 * the then and else blocks get printed.
1040 this->base_ir
= ir
->condition
;
1042 /* Generate the condition into the condition code. */
1043 ir
->condition
->accept(this);
1044 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1045 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1047 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1048 inst
->predicated
= true;
1050 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1051 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1057 if (!ir
->else_instructions
.is_empty()) {
1058 emit(fs_inst(BRW_OPCODE_ELSE
));
1060 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1061 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1068 emit(fs_inst(BRW_OPCODE_ENDIF
));
1072 fs_visitor::visit(ir_loop
*ir
)
1076 assert(!ir
->increment
);
1077 assert(!ir
->counter
);
1079 emit(fs_inst(BRW_OPCODE_DO
));
1081 /* Start a safety counter. If the user messed up their loop
1082 * counting, we don't want to hang the GPU.
1084 fs_reg max_iter
= fs_reg(this, glsl_type::int_type
);
1085 emit(fs_inst(BRW_OPCODE_MOV
, max_iter
, fs_reg(10000)));
1087 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1088 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1094 /* Check the maximum loop iters counter. */
1095 inst
= emit(fs_inst(BRW_OPCODE_ADD
, max_iter
, max_iter
, fs_reg(-1)));
1096 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1098 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1099 inst
->predicated
= true;
1102 emit(fs_inst(BRW_OPCODE_WHILE
));
1106 fs_visitor::visit(ir_loop_jump
*ir
)
1109 case ir_loop_jump::jump_break
:
1110 emit(fs_inst(BRW_OPCODE_BREAK
));
1112 case ir_loop_jump::jump_continue
:
1113 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1119 fs_visitor::visit(ir_call
*ir
)
1121 assert(!"FINISHME");
1125 fs_visitor::visit(ir_return
*ir
)
1127 assert(!"FINISHME");
1131 fs_visitor::visit(ir_function
*ir
)
1133 /* Ignore function bodies other than main() -- we shouldn't see calls to
1134 * them since they should all be inlined before we get to ir_to_mesa.
1136 if (strcmp(ir
->name
, "main") == 0) {
1137 const ir_function_signature
*sig
;
1140 sig
= ir
->matching_signature(&empty
);
1144 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1145 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1154 fs_visitor::visit(ir_function_signature
*ir
)
1156 assert(!"not reached");
1161 fs_visitor::emit(fs_inst inst
)
1163 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1166 list_inst
->annotation
= this->current_annotation
;
1167 list_inst
->ir
= this->base_ir
;
1169 this->instructions
.push_tail(list_inst
);
1174 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1176 fs_visitor::emit_dummy_fs()
1178 /* Everyone's favorite color. */
1179 emit(fs_inst(BRW_OPCODE_MOV
,
1182 emit(fs_inst(BRW_OPCODE_MOV
,
1185 emit(fs_inst(BRW_OPCODE_MOV
,
1188 emit(fs_inst(BRW_OPCODE_MOV
,
1193 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1198 /* The register location here is relative to the start of the URB
1199 * data. It will get adjusted to be a real location before
1200 * generate_code() time.
1203 fs_visitor::interp_reg(int location
, int channel
)
1205 int regnr
= location
* 2 + channel
/ 2;
1206 int stride
= (channel
& 1) * 4;
1208 return brw_vec1_grf(regnr
, stride
);
1211 /** Emits the interpolation for the varying inputs. */
1213 fs_visitor::emit_interpolation()
1215 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1216 /* For now, the source regs for the setup URB data will be unset,
1217 * since we don't know until codegen how many push constants we'll
1218 * use, and therefore what the setup URB offset is.
1220 fs_reg src_reg
= reg_undef
;
1222 this->current_annotation
= "compute pixel centers";
1223 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1224 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1225 emit(fs_inst(BRW_OPCODE_ADD
,
1227 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1228 fs_reg(brw_imm_v(0x10101010))));
1229 emit(fs_inst(BRW_OPCODE_ADD
,
1231 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1232 fs_reg(brw_imm_v(0x11001100))));
1234 this->current_annotation
= "compute pixel deltas from v0";
1235 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1236 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1237 emit(fs_inst(BRW_OPCODE_ADD
,
1240 fs_reg(negate(brw_vec1_grf(1, 0)))));
1241 emit(fs_inst(BRW_OPCODE_ADD
,
1244 fs_reg(brw_vec1_grf(1, 1))));
1246 this->current_annotation
= "compute pos.w and 1/pos.w";
1247 /* Compute wpos. Unlike many other varying inputs, we usually need it
1248 * to produce 1/w, and the varying variable wouldn't show up.
1250 fs_reg wpos
= fs_reg(this, glsl_type::vec4_type
);
1251 this->interp_attrs
[FRAG_ATTRIB_WPOS
] = wpos
;
1252 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
)); /* FINISHME: ARB_fcc */
1254 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
)); /* FINISHME: ARB_fcc */
1256 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1257 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
1259 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1260 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1261 /* Compute the pixel W value from wpos.w. */
1262 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1263 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos
));
1265 /* FINISHME: gl_FrontFacing */
1267 foreach_iter(exec_list_iterator
, iter
, *this->shader
->ir
) {
1268 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1269 ir_variable
*var
= ir
->as_variable();
1274 if (var
->mode
!= ir_var_in
)
1277 /* If it's already set up (WPOS), skip. */
1278 if (var
->location
== 0)
1281 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1283 "(FRAG_ATTRIB[%d])",
1286 emit_pinterp(var
->location
);
1288 this->current_annotation
= NULL
;
1292 fs_visitor::emit_pinterp(int location
)
1294 fs_reg interp_attr
= fs_reg(this, glsl_type::vec4_type
);
1295 this->interp_attrs
[location
] = interp_attr
;
1297 for (unsigned int i
= 0; i
< 4; i
++) {
1298 struct brw_reg interp
= interp_reg(location
, i
);
1299 emit(fs_inst(FS_OPCODE_LINTERP
,
1304 interp_attr
.reg_offset
++;
1306 interp_attr
.reg_offset
-= 4;
1308 for (unsigned int i
= 0; i
< 4; i
++) {
1309 emit(fs_inst(BRW_OPCODE_MUL
,
1313 interp_attr
.reg_offset
++;
1318 fs_visitor::emit_fb_writes()
1320 this->current_annotation
= "FB write";
1322 assert(this->frag_color
|| !"FINISHME: MRT");
1323 fs_reg color
= *(variable_storage(this->frag_color
));
1325 for (int i
= 0; i
< 4; i
++) {
1326 emit(fs_inst(BRW_OPCODE_MOV
,
1332 emit(fs_inst(FS_OPCODE_FB_WRITE
,
1336 this->current_annotation
= NULL
;
1340 fs_visitor::generate_fb_write(fs_inst
*inst
)
1342 GLboolean eot
= 1; /* FINISHME: MRT */
1343 /* FINISHME: AADS */
1345 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1348 brw_push_insn_state(p
);
1349 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1350 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1353 brw_vec8_grf(1, 0));
1354 brw_pop_insn_state(p
);
1359 8, /* dispatch_width */
1360 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1362 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1363 0, /* FINISHME: MRT target */
1370 fs_visitor::generate_linterp(fs_inst
*inst
,
1371 struct brw_reg dst
, struct brw_reg
*src
)
1373 struct brw_reg delta_x
= src
[0];
1374 struct brw_reg delta_y
= src
[1];
1375 struct brw_reg interp
= src
[2];
1378 delta_y
.nr
== delta_x
.nr
+ 1 &&
1379 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1380 brw_PLN(p
, dst
, interp
, delta_x
);
1382 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1383 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
1388 fs_visitor::generate_math(fs_inst
*inst
,
1389 struct brw_reg dst
, struct brw_reg
*src
)
1393 switch (inst
->opcode
) {
1395 op
= BRW_MATH_FUNCTION_INV
;
1398 op
= BRW_MATH_FUNCTION_RSQ
;
1400 case FS_OPCODE_SQRT
:
1401 op
= BRW_MATH_FUNCTION_SQRT
;
1403 case FS_OPCODE_EXP2
:
1404 op
= BRW_MATH_FUNCTION_EXP
;
1406 case FS_OPCODE_LOG2
:
1407 op
= BRW_MATH_FUNCTION_LOG
;
1410 op
= BRW_MATH_FUNCTION_POW
;
1413 op
= BRW_MATH_FUNCTION_SIN
;
1416 op
= BRW_MATH_FUNCTION_COS
;
1419 assert(!"not reached: unknown math function");
1424 if (inst
->opcode
== FS_OPCODE_POW
) {
1425 brw_MOV(p
, brw_message_reg(3), src
[1]);
1430 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
1431 BRW_MATH_SATURATE_NONE
,
1433 BRW_MATH_DATA_VECTOR
,
1434 BRW_MATH_PRECISION_FULL
);
1438 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
1443 if (intel
->gen
== 5) {
1444 switch (inst
->opcode
) {
1446 if (inst
->shadow_compare
) {
1447 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
1449 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
1453 if (inst
->shadow_compare
) {
1454 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
1456 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
1461 switch (inst
->opcode
) {
1463 /* Note that G45 and older determines shadow compare and dispatch width
1464 * from message length for most messages.
1466 if (inst
->shadow_compare
) {
1467 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1469 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1472 if (inst
->shadow_compare
) {
1473 assert(!"FINISHME: shadow compare with bias.");
1474 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1476 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1482 assert(msg_type
!= -1);
1488 retype(dst
, BRW_REGISTER_TYPE_UW
),
1490 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1491 SURF_INDEX_TEXTURE(inst
->sampler
),
1499 BRW_SAMPLER_SIMD_MODE_SIMD8
);
1503 fs_visitor::generate_discard(fs_inst
*inst
)
1505 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1506 brw_push_insn_state(p
);
1507 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1508 brw_NOT(p
, c
->emit_mask_reg
, brw_mask_reg(1)); /* IMASK */
1509 brw_AND(p
, g0
, c
->emit_mask_reg
, g0
);
1510 brw_pop_insn_state(p
);
1514 trivial_assign_reg(int header_size
, fs_reg
*reg
)
1516 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
1517 reg
->hw_reg
= header_size
+ reg
->reg
- 1 + reg
->reg_offset
;
1523 fs_visitor::assign_curb_setup()
1525 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
1526 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1528 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1529 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1530 fs_inst
*inst
= (fs_inst
*)iter
.get();
1532 for (unsigned int i
= 0; i
< 3; i
++) {
1533 if (inst
->src
[i
].file
== UNIFORM
) {
1534 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
1535 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
1539 inst
->src
[i
].file
= FIXED_HW_REG
;
1540 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
1547 fs_visitor::assign_urb_setup()
1549 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
1550 int interp_reg_nr
[FRAG_ATTRIB_MAX
];
1552 c
->prog_data
.urb_read_length
= 0;
1554 /* Figure out where each of the incoming setup attributes lands. */
1555 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1556 interp_reg_nr
[i
] = -1;
1558 if (i
!= FRAG_ATTRIB_WPOS
&&
1559 !(brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
1562 /* Each attribute is 4 setup channels, each of which is half a reg. */
1563 interp_reg_nr
[i
] = urb_start
+ c
->prog_data
.urb_read_length
;
1564 c
->prog_data
.urb_read_length
+= 2;
1567 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses
1568 * the correct setup input.
1570 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1571 fs_inst
*inst
= (fs_inst
*)iter
.get();
1573 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
1576 assert(inst
->src
[2].file
== FIXED_HW_REG
);
1578 int location
= inst
->src
[2].fixed_hw_reg
.nr
/ 2;
1579 assert(interp_reg_nr
[location
] != -1);
1580 inst
->src
[2].fixed_hw_reg
.nr
= (interp_reg_nr
[location
] +
1581 (inst
->src
[2].fixed_hw_reg
.nr
& 1));
1584 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
1588 fs_visitor::assign_regs()
1590 int header_size
= this->first_non_payload_grf
;
1593 /* FINISHME: trivial assignment of register numbers */
1594 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1595 fs_inst
*inst
= (fs_inst
*)iter
.get();
1597 trivial_assign_reg(header_size
, &inst
->dst
);
1598 trivial_assign_reg(header_size
, &inst
->src
[0]);
1599 trivial_assign_reg(header_size
, &inst
->src
[1]);
1601 last_grf
= MAX2(last_grf
, inst
->dst
.hw_reg
);
1602 last_grf
= MAX2(last_grf
, inst
->src
[0].hw_reg
);
1603 last_grf
= MAX2(last_grf
, inst
->src
[1].hw_reg
);
1606 this->grf_used
= last_grf
+ 1;
1609 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
1611 struct brw_reg brw_reg
;
1613 switch (reg
->file
) {
1617 brw_reg
= brw_vec8_reg(reg
->file
,
1619 brw_reg
= retype(brw_reg
, reg
->type
);
1622 switch (reg
->type
) {
1623 case BRW_REGISTER_TYPE_F
:
1624 brw_reg
= brw_imm_f(reg
->imm
.f
);
1626 case BRW_REGISTER_TYPE_D
:
1627 brw_reg
= brw_imm_d(reg
->imm
.i
);
1629 case BRW_REGISTER_TYPE_UD
:
1630 brw_reg
= brw_imm_ud(reg
->imm
.u
);
1633 assert(!"not reached");
1638 brw_reg
= reg
->fixed_hw_reg
;
1641 /* Probably unused. */
1642 brw_reg
= brw_null_reg();
1645 assert(!"not reached");
1646 brw_reg
= brw_null_reg();
1650 brw_reg
= brw_abs(brw_reg
);
1652 brw_reg
= negate(brw_reg
);
1658 fs_visitor::generate_code()
1660 unsigned int annotation_len
= 0;
1661 int last_native_inst
= 0;
1662 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
1663 int if_stack_depth
= 0, loop_stack_depth
= 0;
1664 int if_depth_in_loop
[16];
1666 if_depth_in_loop
[loop_stack_depth
] = 0;
1668 memset(&if_stack
, 0, sizeof(if_stack
));
1669 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1670 fs_inst
*inst
= (fs_inst
*)iter
.get();
1671 struct brw_reg src
[3], dst
;
1673 for (unsigned int i
= 0; i
< 3; i
++) {
1674 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1676 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1678 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1679 brw_set_predicate_control(p
, inst
->predicated
);
1681 switch (inst
->opcode
) {
1682 case BRW_OPCODE_MOV
:
1683 brw_MOV(p
, dst
, src
[0]);
1685 case BRW_OPCODE_ADD
:
1686 brw_ADD(p
, dst
, src
[0], src
[1]);
1688 case BRW_OPCODE_MUL
:
1689 brw_MUL(p
, dst
, src
[0], src
[1]);
1692 case BRW_OPCODE_FRC
:
1693 brw_FRC(p
, dst
, src
[0]);
1695 case BRW_OPCODE_RNDD
:
1696 brw_RNDD(p
, dst
, src
[0]);
1698 case BRW_OPCODE_RNDZ
:
1699 brw_RNDZ(p
, dst
, src
[0]);
1702 case BRW_OPCODE_AND
:
1703 brw_AND(p
, dst
, src
[0], src
[1]);
1706 brw_OR(p
, dst
, src
[0], src
[1]);
1708 case BRW_OPCODE_XOR
:
1709 brw_XOR(p
, dst
, src
[0], src
[1]);
1712 case BRW_OPCODE_CMP
:
1713 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1715 case BRW_OPCODE_SEL
:
1716 brw_SEL(p
, dst
, src
[0], src
[1]);
1720 assert(if_stack_depth
< 16);
1721 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
1724 case BRW_OPCODE_ELSE
:
1725 if_stack
[if_stack_depth
- 1] =
1726 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
1728 case BRW_OPCODE_ENDIF
:
1730 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
1734 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
1735 if_depth_in_loop
[loop_stack_depth
] = 0;
1738 case BRW_OPCODE_BREAK
:
1739 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
1740 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1742 case BRW_OPCODE_CONTINUE
:
1743 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
1744 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1747 case BRW_OPCODE_WHILE
: {
1748 struct brw_instruction
*inst0
, *inst1
;
1751 if (intel
->gen
== 5)
1754 assert(loop_stack_depth
> 0);
1756 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
1757 /* patch all the BREAK/CONT instructions from last BGNLOOP */
1758 while (inst0
> loop_stack
[loop_stack_depth
]) {
1760 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
1761 inst0
->bits3
.if_else
.jump_count
== 0) {
1762 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
1764 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
1765 inst0
->bits3
.if_else
.jump_count
== 0) {
1766 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
1774 case FS_OPCODE_SQRT
:
1775 case FS_OPCODE_EXP2
:
1776 case FS_OPCODE_LOG2
:
1780 generate_math(inst
, dst
, src
);
1782 case FS_OPCODE_LINTERP
:
1783 generate_linterp(inst
, dst
, src
);
1788 generate_tex(inst
, dst
, src
[0]);
1790 case FS_OPCODE_DISCARD
:
1791 generate_discard(inst
);
1793 case FS_OPCODE_FB_WRITE
:
1794 generate_fb_write(inst
);
1797 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
1798 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
1799 brw_opcodes
[inst
->opcode
].name
);
1801 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
1806 if (annotation_len
< p
->nr_insn
) {
1807 annotation_len
*= 2;
1808 if (annotation_len
< 16)
1809 annotation_len
= 16;
1811 this->annotation_string
= talloc_realloc(this->mem_ctx
,
1815 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
1821 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
1822 this->annotation_string
[i
] = inst
->annotation
;
1823 this->annotation_ir
[i
] = inst
->ir
;
1825 last_native_inst
= p
->nr_insn
;
1830 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
1832 struct brw_compile
*p
= &c
->func
;
1833 struct intel_context
*intel
= &brw
->intel
;
1834 GLcontext
*ctx
= &intel
->ctx
;
1835 struct brw_shader
*shader
= NULL
;
1836 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
1844 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
1845 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
1846 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
1853 /* We always use 8-wide mode, at least for now. For one, flow
1854 * control only works in 8-wide. Also, when we're fragment shader
1855 * bound, we're almost always under register pressure as well, so
1856 * 8-wide would save us from the performance cliff of spilling
1859 c
->dispatch_width
= 8;
1861 if (INTEL_DEBUG
& DEBUG_WM
) {
1862 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
1863 _mesa_print_ir(shader
->ir
, NULL
);
1867 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1869 fs_visitor
v(c
, shader
);
1874 v
.emit_interpolation();
1876 /* Generate FS IR for main(). (the visitor only descends into
1877 * functions called "main").
1879 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
1880 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1889 v
.assign_curb_setup();
1890 v
.assign_urb_setup();
1896 if (INTEL_DEBUG
& DEBUG_WM
) {
1897 const char *last_annotation_string
= NULL
;
1898 ir_instruction
*last_annotation_ir
= NULL
;
1900 printf("Native code for fragment shader %d:\n", prog
->Name
);
1901 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
1902 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
1903 last_annotation_ir
= v
.annotation_ir
[i
];
1904 if (last_annotation_ir
) {
1906 last_annotation_ir
->print();
1910 if (last_annotation_string
!= v
.annotation_string
[i
]) {
1911 last_annotation_string
= v
.annotation_string
[i
];
1912 if (last_annotation_string
)
1913 printf(" %s\n", last_annotation_string
);
1915 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
1920 c
->prog_data
.total_grf
= v
.grf_used
;
1921 c
->prog_data
.total_scratch
= 0;