2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "glsl/nir/glsl_types.h"
46 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
47 const fs_reg
*src
, unsigned sources
)
49 memset(this, 0, sizeof(*this));
51 this->src
= new fs_reg
[MAX2(sources
, 3)];
52 for (unsigned i
= 0; i
< sources
; i
++)
53 this->src
[i
] = src
[i
];
55 this->opcode
= opcode
;
57 this->sources
= sources
;
58 this->exec_size
= exec_size
;
60 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
62 assert(this->exec_size
!= 0);
64 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
66 /* This will be the case for almost all instructions. */
73 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
77 this->regs_written
= 0;
81 unreachable("Invalid destination register file");
84 this->writes_accumulator
= false;
89 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
92 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
94 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
99 init(opcode
, exec_size
, dst
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
105 const fs_reg src
[1] = { src0
};
106 init(opcode
, exec_size
, dst
, src
, 1);
109 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg
&src0
, const fs_reg
&src1
)
112 const fs_reg src
[2] = { src0
, src1
};
113 init(opcode
, exec_size
, dst
, src
, 2);
116 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
117 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
119 const fs_reg src
[3] = { src0
, src1
, src2
};
120 init(opcode
, exec_size
, dst
, src
, 3);
123 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
124 const fs_reg src
[], unsigned sources
)
126 init(opcode
, exec_width
, dst
, src
, sources
);
129 fs_inst::fs_inst(const fs_inst
&that
)
131 memcpy(this, &that
, sizeof(that
));
133 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
135 for (unsigned i
= 0; i
< that
.sources
; i
++)
136 this->src
[i
] = that
.src
[i
];
145 fs_inst::resize_sources(uint8_t num_sources
)
147 if (this->sources
!= num_sources
) {
148 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
150 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
151 src
[i
] = this->src
[i
];
155 this->sources
= num_sources
;
160 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
162 const fs_reg
&surf_index
,
163 const fs_reg
&varying_offset
,
164 uint32_t const_offset
)
166 /* We have our constant surface use a pitch of 4 bytes, so our index can
167 * be any component of a vector, and then we load 4 contiguous
168 * components starting from that.
170 * We break down the const_offset to a portion added to the variable
171 * offset and a portion done using reg_offset, which means that if you
172 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
173 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
174 * CSE can later notice that those loads are all the same and eliminate
175 * the redundant ones.
177 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
178 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
181 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
182 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
183 * u, v, r) as parameters, or we can just use the SIMD16 message
184 * consisting of (header, u). We choose the second, at the cost of a
185 * longer return length.
191 if (devinfo
->gen
>= 7)
192 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
194 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
196 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
197 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
198 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
199 inst
->regs_written
= regs_written
;
201 if (devinfo
->gen
< 7) {
202 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
203 inst
->header_size
= 1;
204 if (devinfo
->gen
== 4)
207 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
210 bld
.MOV(dst
, offset(vec4_result
, bld
, ((const_offset
& 0xf) / 4) * scale
));
214 * A helper for MOV generation for fixing up broken hardware SEND dependency
218 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
220 /* The caller always wants uncompressed to emit the minimal extra
221 * dependencies, and to avoid having to deal with aligning its regs to 2.
223 const fs_builder ubld
= bld
.annotate("send dependency resolve")
226 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
230 fs_inst::equals(fs_inst
*inst
) const
232 return (opcode
== inst
->opcode
&&
233 dst
.equals(inst
->dst
) &&
234 src
[0].equals(inst
->src
[0]) &&
235 src
[1].equals(inst
->src
[1]) &&
236 src
[2].equals(inst
->src
[2]) &&
237 saturate
== inst
->saturate
&&
238 predicate
== inst
->predicate
&&
239 conditional_mod
== inst
->conditional_mod
&&
240 mlen
== inst
->mlen
&&
241 base_mrf
== inst
->base_mrf
&&
242 target
== inst
->target
&&
244 header_size
== inst
->header_size
&&
245 shadow_compare
== inst
->shadow_compare
&&
246 exec_size
== inst
->exec_size
&&
247 offset
== inst
->offset
);
251 fs_inst::overwrites_reg(const fs_reg
®
) const
253 return reg
.in_range(dst
, regs_written
);
257 fs_inst::is_send_from_grf() const
260 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
261 case SHADER_OPCODE_SHADER_TIME_ADD
:
262 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
263 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
264 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
265 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
266 case SHADER_OPCODE_UNTYPED_ATOMIC
:
267 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
268 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
269 case SHADER_OPCODE_TYPED_ATOMIC
:
270 case SHADER_OPCODE_TYPED_SURFACE_READ
:
271 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
272 case SHADER_OPCODE_URB_WRITE_SIMD8
:
273 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
274 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
275 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
276 case SHADER_OPCODE_URB_READ_SIMD8
:
277 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
279 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
280 return src
[1].file
== VGRF
;
281 case FS_OPCODE_FB_WRITE
:
282 return src
[0].file
== VGRF
;
285 return src
[0].file
== VGRF
;
292 * Returns true if this instruction's sources and destinations cannot
293 * safely be the same register.
295 * In most cases, a register can be written over safely by the same
296 * instruction that is its last use. For a single instruction, the
297 * sources are dereferenced before writing of the destination starts
300 * However, there are a few cases where this can be problematic:
302 * - Virtual opcodes that translate to multiple instructions in the
303 * code generator: if src == dst and one instruction writes the
304 * destination before a later instruction reads the source, then
305 * src will have been clobbered.
307 * - SIMD16 compressed instructions with certain regioning (see below).
309 * The register allocator uses this information to set up conflicts between
310 * GRF sources and the destination.
313 fs_inst::has_source_and_destination_hazard() const
316 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
317 /* Multiple partial writes to the destination */
320 /* The SIMD16 compressed instruction
322 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
324 * is actually decoded in hardware as:
326 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
327 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
329 * Which is safe. However, if we have uniform accesses
330 * happening, we get into trouble:
332 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
333 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
335 * Now our destination for the first instruction overwrote the
336 * second instruction's src0, and we get garbage for those 8
337 * pixels. There's a similar issue for the pre-gen6
338 * pixel_x/pixel_y, which are registers of 16-bit values and thus
339 * would get stomped by the first decode as well.
341 if (exec_size
== 16) {
342 for (int i
= 0; i
< sources
; i
++) {
343 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
344 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
345 src
[i
].type
== BRW_REGISTER_TYPE_W
||
346 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
347 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
357 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
359 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
362 fs_reg reg
= this->src
[0];
363 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
366 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
369 for (int i
= 0; i
< this->sources
; i
++) {
370 reg
.type
= this->src
[i
].type
;
371 if (!this->src
[i
].equals(reg
))
374 if (i
< this->header_size
) {
377 reg
.reg_offset
+= this->exec_size
/ 8;
385 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
387 if (devinfo
->gen
== 6 && is_math())
390 if (is_send_from_grf())
393 if (!backend_instruction::can_do_source_mods())
400 fs_inst::can_change_types() const
402 return dst
.type
== src
[0].type
&&
403 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
404 (opcode
== BRW_OPCODE_MOV
||
405 (opcode
== BRW_OPCODE_SEL
&&
406 dst
.type
== src
[1].type
&&
407 predicate
!= BRW_PREDICATE_NONE
&&
408 !src
[1].abs
&& !src
[1].negate
));
412 fs_inst::has_side_effects() const
414 return this->eot
|| backend_instruction::has_side_effects();
420 memset(this, 0, sizeof(*this));
424 /** Generic unset register constructor. */
428 this->file
= BAD_FILE
;
431 fs_reg::fs_reg(struct ::brw_reg reg
) :
434 this->reg_offset
= 0;
435 this->subreg_offset
= 0;
437 if (this->file
== IMM
&&
438 (this->type
!= BRW_REGISTER_TYPE_V
&&
439 this->type
!= BRW_REGISTER_TYPE_UV
&&
440 this->type
!= BRW_REGISTER_TYPE_VF
)) {
446 fs_reg::equals(const fs_reg
&r
) const
448 return (this->backend_reg::equals(r
) &&
449 subreg_offset
== r
.subreg_offset
&&
454 fs_reg::set_smear(unsigned subreg
)
456 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
457 subreg_offset
= subreg
* type_sz(type
);
463 fs_reg::is_contiguous() const
469 fs_reg::component_size(unsigned width
) const
471 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
474 return MAX2(width
* stride
, 1) * type_sz(type
);
478 type_size_scalar(const struct glsl_type
*type
)
480 unsigned int size
, i
;
482 switch (type
->base_type
) {
485 case GLSL_TYPE_FLOAT
:
487 return type
->components();
488 case GLSL_TYPE_ARRAY
:
489 return type_size_scalar(type
->fields
.array
) * type
->length
;
490 case GLSL_TYPE_STRUCT
:
492 for (i
= 0; i
< type
->length
; i
++) {
493 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
496 case GLSL_TYPE_SAMPLER
:
497 /* Samplers take up no register space, since they're baked in at
501 case GLSL_TYPE_ATOMIC_UINT
:
503 case GLSL_TYPE_SUBROUTINE
:
505 case GLSL_TYPE_IMAGE
:
506 return BRW_IMAGE_PARAM_SIZE
;
508 case GLSL_TYPE_ERROR
:
509 case GLSL_TYPE_INTERFACE
:
510 case GLSL_TYPE_DOUBLE
:
511 case GLSL_TYPE_FUNCTION
:
512 unreachable("not reached");
519 * Returns the number of scalar components needed to store type, assuming
520 * that vectors are padded out to vec4.
522 * This has the packing rules of type_size_vec4(), but counts components
523 * similar to type_size_scalar().
526 type_size_vec4_times_4(const struct glsl_type
*type
)
528 return 4 * type_size_vec4(type
);
532 * Create a MOV to read the timestamp register.
534 * The caller is responsible for emitting the MOV. The return value is
535 * the destination of the MOV, with extra parameters set.
538 fs_visitor::get_timestamp(const fs_builder
&bld
)
540 assert(devinfo
->gen
>= 7);
542 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
545 BRW_REGISTER_TYPE_UD
));
547 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
549 /* We want to read the 3 fields we care about even if it's not enabled in
552 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
558 fs_visitor::emit_shader_time_begin()
560 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
562 /* We want only the low 32 bits of the timestamp. Since it's running
563 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
564 * which is plenty of time for our purposes. It is identical across the
565 * EUs, but since it's tracking GPU core speed it will increment at a
566 * varying rate as render P-states change.
568 shader_start_time
.set_smear(0);
572 fs_visitor::emit_shader_time_end()
574 /* Insert our code just before the final SEND with EOT. */
575 exec_node
*end
= this->instructions
.get_tail();
576 assert(end
&& ((fs_inst
*) end
)->eot
);
577 const fs_builder ibld
= bld
.annotate("shader time end")
578 .exec_all().at(NULL
, end
);
580 fs_reg shader_end_time
= get_timestamp(ibld
);
582 /* We only use the low 32 bits of the timestamp - see
583 * emit_shader_time_begin()).
585 * We could also check if render P-states have changed (or anything
586 * else that might disrupt timing) by setting smear to 2 and checking if
587 * that field is != 0.
589 shader_end_time
.set_smear(0);
591 /* Check that there weren't any timestamp reset events (assuming these
592 * were the only two timestamp reads that happened).
594 fs_reg reset
= shader_end_time
;
596 set_condmod(BRW_CONDITIONAL_Z
,
597 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
598 ibld
.IF(BRW_PREDICATE_NORMAL
);
600 fs_reg start
= shader_start_time
;
602 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
605 const fs_builder cbld
= ibld
.group(1, 0);
606 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
608 /* If there were no instructions between the two timestamp gets, the diff
609 * is 2 cycles. Remove that overhead, so I can forget about that when
610 * trying to determine the time taken for single instructions.
612 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
613 SHADER_TIME_ADD(cbld
, 0, diff
);
614 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
615 ibld
.emit(BRW_OPCODE_ELSE
);
616 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
617 ibld
.emit(BRW_OPCODE_ENDIF
);
621 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
622 int shader_time_subindex
,
625 int index
= shader_time_index
* 3 + shader_time_subindex
;
626 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
629 if (dispatch_width
== 8)
630 payload
= vgrf(glsl_type::uvec2_type
);
632 payload
= vgrf(glsl_type::uint_type
);
634 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
638 fs_visitor::vfail(const char *format
, va_list va
)
647 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
648 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
650 this->fail_msg
= msg
;
653 fprintf(stderr
, "%s", msg
);
658 fs_visitor::fail(const char *format
, ...)
662 va_start(va
, format
);
668 * Mark this program as impossible to compile in SIMD16 mode.
670 * During the SIMD8 compile (which happens first), we can detect and flag
671 * things that are unsupported in SIMD16 mode, so the compiler can skip
672 * the SIMD16 compile altogether.
674 * During a SIMD16 compile (if one happens anyway), this just calls fail().
677 fs_visitor::no16(const char *msg
)
679 if (dispatch_width
== 16) {
682 simd16_unsupported
= true;
684 compiler
->shader_perf_log(log_data
,
685 "SIMD16 shader failed to compile: %s", msg
);
690 * Returns true if the instruction has a flag that means it won't
691 * update an entire destination register.
693 * For example, dead code elimination and live variable analysis want to know
694 * when a write to a variable screens off any preceding values that were in
698 fs_inst::is_partial_write() const
700 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
701 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
702 !this->dst
.is_contiguous());
706 fs_inst::components_read(unsigned i
) const
709 case FS_OPCODE_LINTERP
:
715 case FS_OPCODE_PIXEL_X
:
716 case FS_OPCODE_PIXEL_Y
:
720 case FS_OPCODE_FB_WRITE_LOGICAL
:
721 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
722 /* First/second FB write color. */
724 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
728 case SHADER_OPCODE_TEX_LOGICAL
:
729 case SHADER_OPCODE_TXD_LOGICAL
:
730 case SHADER_OPCODE_TXF_LOGICAL
:
731 case SHADER_OPCODE_TXL_LOGICAL
:
732 case SHADER_OPCODE_TXS_LOGICAL
:
733 case FS_OPCODE_TXB_LOGICAL
:
734 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
735 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
736 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
737 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
738 case SHADER_OPCODE_LOD_LOGICAL
:
739 case SHADER_OPCODE_TG4_LOGICAL
:
740 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
741 assert(src
[9].file
== IMM
&& src
[10].file
== IMM
);
742 /* Texture coordinates. */
745 /* Texture derivatives. */
746 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
748 /* Texture offset. */
752 else if (i
== 5 && opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
757 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
758 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
759 assert(src
[3].file
== IMM
);
760 /* Surface coordinates. */
763 /* Surface operation source (ignored for reads). */
769 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
770 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
771 assert(src
[3].file
== IMM
&&
773 /* Surface coordinates. */
776 /* Surface operation source. */
782 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
783 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
784 assert(src
[3].file
== IMM
&&
786 const unsigned op
= src
[4].ud
;
787 /* Surface coordinates. */
790 /* Surface operation source. */
791 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
793 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
794 op
== BRW_AOP_PREDEC
))
806 fs_inst::regs_read(int arg
) const
809 case FS_OPCODE_FB_WRITE
:
810 case SHADER_OPCODE_URB_WRITE_SIMD8
:
811 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
812 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
813 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
814 case SHADER_OPCODE_URB_READ_SIMD8
:
815 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
816 case SHADER_OPCODE_UNTYPED_ATOMIC
:
817 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
818 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
819 case SHADER_OPCODE_TYPED_ATOMIC
:
820 case SHADER_OPCODE_TYPED_SURFACE_READ
:
821 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
822 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
827 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
828 /* The payload is actually stored in src1 */
833 case FS_OPCODE_LINTERP
:
838 case SHADER_OPCODE_LOAD_PAYLOAD
:
839 if (arg
< this->header_size
)
843 case CS_OPCODE_CS_TERMINATE
:
844 case SHADER_OPCODE_BARRIER
:
847 case SHADER_OPCODE_MOV_INDIRECT
:
849 assert(src
[2].file
== IMM
);
850 unsigned region_length
= src
[2].ud
;
852 if (src
[0].file
== UNIFORM
) {
853 assert(region_length
% 4 == 0);
854 return region_length
/ 4;
855 } else if (src
[0].file
== FIXED_GRF
) {
856 /* If the start of the region is not register aligned, then
857 * there's some portion of the register that's technically
858 * unread at the beginning.
860 * However, the register allocator works in terms of whole
861 * registers, and does not use subnr. It assumes that the
862 * read starts at the beginning of the register, and extends
863 * regs_read() whole registers beyond that.
865 * To compensate, we extend the region length to include this
866 * unread portion at the beginning.
869 region_length
+= src
[0].subnr
;
871 return DIV_ROUND_UP(region_length
, REG_SIZE
);
873 assert(!"Invalid register file");
879 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
884 switch (src
[arg
].file
) {
894 return DIV_ROUND_UP(components_read(arg
) *
895 src
[arg
].component_size(exec_size
),
898 unreachable("MRF registers are not allowed as sources");
904 fs_inst::reads_flag() const
910 fs_inst::writes_flag() const
912 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
913 opcode
!= BRW_OPCODE_IF
&&
914 opcode
!= BRW_OPCODE_WHILE
)) ||
915 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
919 * Returns how many MRFs an FS opcode will write over.
921 * Note that this is not the 0 or 1 implied writes in an actual gen
922 * instruction -- the FS opcodes often generate MOVs in addition.
925 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
930 if (inst
->base_mrf
== -1)
933 switch (inst
->opcode
) {
934 case SHADER_OPCODE_RCP
:
935 case SHADER_OPCODE_RSQ
:
936 case SHADER_OPCODE_SQRT
:
937 case SHADER_OPCODE_EXP2
:
938 case SHADER_OPCODE_LOG2
:
939 case SHADER_OPCODE_SIN
:
940 case SHADER_OPCODE_COS
:
941 return 1 * dispatch_width
/ 8;
942 case SHADER_OPCODE_POW
:
943 case SHADER_OPCODE_INT_QUOTIENT
:
944 case SHADER_OPCODE_INT_REMAINDER
:
945 return 2 * dispatch_width
/ 8;
946 case SHADER_OPCODE_TEX
:
948 case SHADER_OPCODE_TXD
:
949 case SHADER_OPCODE_TXF
:
950 case SHADER_OPCODE_TXF_CMS
:
951 case SHADER_OPCODE_TXF_CMS_W
:
952 case SHADER_OPCODE_TXF_MCS
:
953 case SHADER_OPCODE_TG4
:
954 case SHADER_OPCODE_TG4_OFFSET
:
955 case SHADER_OPCODE_TXL
:
956 case SHADER_OPCODE_TXS
:
957 case SHADER_OPCODE_LOD
:
958 case SHADER_OPCODE_SAMPLEINFO
:
960 case FS_OPCODE_FB_WRITE
:
962 case FS_OPCODE_GET_BUFFER_SIZE
:
963 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
964 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
966 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
968 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
970 case SHADER_OPCODE_UNTYPED_ATOMIC
:
971 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
972 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
973 case SHADER_OPCODE_TYPED_ATOMIC
:
974 case SHADER_OPCODE_TYPED_SURFACE_READ
:
975 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
976 case SHADER_OPCODE_URB_WRITE_SIMD8
:
977 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
978 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
979 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
980 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
981 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
982 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
983 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
986 unreachable("not reached");
991 fs_visitor::vgrf(const glsl_type
*const type
)
993 int reg_width
= dispatch_width
/ 8;
994 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
995 brw_type_for_base_type(type
));
998 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1003 this->type
= BRW_REGISTER_TYPE_F
;
1004 this->stride
= (file
== UNIFORM
? 0 : 1);
1007 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1013 this->stride
= (file
== UNIFORM
? 0 : 1);
1016 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1017 * This brings in those uniform definitions
1020 fs_visitor::import_uniforms(fs_visitor
*v
)
1022 this->push_constant_loc
= v
->push_constant_loc
;
1023 this->pull_constant_loc
= v
->pull_constant_loc
;
1024 this->uniforms
= v
->uniforms
;
1028 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
1029 bool origin_upper_left
)
1031 assert(stage
== MESA_SHADER_FRAGMENT
);
1032 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1033 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1035 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1037 /* gl_FragCoord.x */
1038 if (pixel_center_integer
) {
1039 bld
.MOV(wpos
, this->pixel_x
);
1041 bld
.ADD(wpos
, this->pixel_x
, brw_imm_f(0.5f
));
1043 wpos
= offset(wpos
, bld
, 1);
1045 /* gl_FragCoord.y */
1046 if (!flip
&& pixel_center_integer
) {
1047 bld
.MOV(wpos
, this->pixel_y
);
1049 fs_reg pixel_y
= this->pixel_y
;
1050 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1053 pixel_y
.negate
= true;
1054 offset
+= key
->drawable_height
- 1.0f
;
1057 bld
.ADD(wpos
, pixel_y
, brw_imm_f(offset
));
1059 wpos
= offset(wpos
, bld
, 1);
1061 /* gl_FragCoord.z */
1062 if (devinfo
->gen
>= 6) {
1063 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1065 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1066 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1067 interp_reg(VARYING_SLOT_POS
, 2));
1069 wpos
= offset(wpos
, bld
, 1);
1071 /* gl_FragCoord.w: Already set up in emit_interpolation */
1072 bld
.MOV(wpos
, this->wpos_w
);
1078 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1079 glsl_interp_qualifier interpolation_mode
,
1080 bool is_centroid
, bool is_sample
)
1082 brw_wm_barycentric_interp_mode barycoord_mode
;
1083 if (devinfo
->gen
>= 6) {
1085 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1086 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1088 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1089 } else if (is_sample
) {
1090 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1091 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1093 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1095 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1096 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1098 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1101 /* On Ironlake and below, there is only one interpolation mode.
1102 * Centroid interpolation doesn't mean anything on this hardware --
1103 * there is no multisampling.
1105 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1107 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1108 this->delta_xy
[barycoord_mode
], interp
);
1112 fs_visitor::emit_general_interpolation(fs_reg
*attr
, const char *name
,
1113 const glsl_type
*type
,
1114 glsl_interp_qualifier interpolation_mode
,
1115 int *location
, bool mod_centroid
,
1118 assert(stage
== MESA_SHADER_FRAGMENT
);
1119 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1120 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1122 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1124 *location
== VARYING_SLOT_COL0
|| *location
== VARYING_SLOT_COL1
;
1125 if (key
->flat_shade
&& is_gl_Color
) {
1126 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1128 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1132 if (type
->is_array() || type
->is_matrix()) {
1133 const glsl_type
*elem_type
= glsl_get_array_element(type
);
1134 const unsigned length
= glsl_get_length(type
);
1136 for (unsigned i
= 0; i
< length
; i
++) {
1137 emit_general_interpolation(attr
, name
, elem_type
, interpolation_mode
,
1138 location
, mod_centroid
, mod_sample
);
1140 } else if (type
->is_record()) {
1141 for (unsigned i
= 0; i
< type
->length
; i
++) {
1142 const glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
1143 emit_general_interpolation(attr
, name
, field_type
, interpolation_mode
,
1144 location
, mod_centroid
, mod_sample
);
1147 assert(type
->is_scalar() || type
->is_vector());
1149 if (prog_data
->urb_setup
[*location
] == -1) {
1150 /* If there's no incoming setup data for this slot, don't
1151 * emit interpolation for it.
1153 *attr
= offset(*attr
, bld
, type
->vector_elements
);
1158 attr
->type
= brw_type_for_base_type(type
->get_scalar_type());
1160 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1161 /* Constant interpolation (flat shading) case. The SF has
1162 * handed us defined values in only the constant offset
1163 * field of the setup reg.
1165 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1166 struct brw_reg interp
= interp_reg(*location
, i
);
1167 interp
= suboffset(interp
, 3);
1168 interp
.type
= attr
->type
;
1169 bld
.emit(FS_OPCODE_CINTERP
, *attr
, fs_reg(interp
));
1170 *attr
= offset(*attr
, bld
, 1);
1173 /* Smooth/noperspective interpolation case. */
1174 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1175 struct brw_reg interp
= interp_reg(*location
, i
);
1176 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1177 /* Get the pixel/sample mask into f0 so that we know
1178 * which pixels are lit. Then, for each channel that is
1179 * unlit, replace the centroid data with non-centroid
1182 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1185 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1187 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1188 inst
->predicate_inverse
= true;
1189 if (devinfo
->has_pln
)
1190 inst
->no_dd_clear
= true;
1192 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1193 mod_centroid
&& !key
->persample_shading
,
1194 mod_sample
|| key
->persample_shading
);
1195 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1196 inst
->predicate_inverse
= false;
1197 if (devinfo
->has_pln
)
1198 inst
->no_dd_check
= true;
1201 emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1202 mod_centroid
&& !key
->persample_shading
,
1203 mod_sample
|| key
->persample_shading
);
1205 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1206 bld
.MUL(*attr
, *attr
, this->pixel_w
);
1208 *attr
= offset(*attr
, bld
, 1);
1216 fs_visitor::emit_frontfacing_interpolation()
1218 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1220 if (devinfo
->gen
>= 6) {
1221 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1222 * a boolean result from this (~0/true or 0/false).
1224 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1225 * this task in only one instruction:
1226 * - a negation source modifier will flip the bit; and
1227 * - a W -> D type conversion will sign extend the bit into the high
1228 * word of the destination.
1230 * An ASR 15 fills the low word of the destination.
1232 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1235 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1237 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1238 * a boolean result from this (1/true or 0/false).
1240 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1241 * the negation source modifier to flip it. Unfortunately the SHR
1242 * instruction only operates on UD (or D with an abs source modifier)
1243 * sources without negation.
1245 * Instead, use ASR (which will give ~0/true or 0/false).
1247 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1250 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1257 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1259 assert(stage
== MESA_SHADER_FRAGMENT
);
1260 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1261 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1263 if (key
->compute_pos_offset
) {
1264 /* Convert int_sample_pos to floating point */
1265 bld
.MOV(dst
, int_sample_pos
);
1266 /* Scale to the range [0, 1] */
1267 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1270 /* From ARB_sample_shading specification:
1271 * "When rendering to a non-multisample buffer, or if multisample
1272 * rasterization is disabled, gl_SamplePosition will always be
1275 bld
.MOV(dst
, brw_imm_f(0.5f
));
1280 fs_visitor::emit_samplepos_setup()
1282 assert(devinfo
->gen
>= 6);
1284 const fs_builder abld
= bld
.annotate("compute sample position");
1285 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1287 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1288 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1290 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1291 * mode will be enabled.
1293 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1294 * R31.1:0 Position Offset X/Y for Slot[3:0]
1295 * R31.3:2 Position Offset X/Y for Slot[7:4]
1298 * The X, Y sample positions come in as bytes in thread payload. So, read
1299 * the positions using vstride=16, width=8, hstride=2.
1301 struct brw_reg sample_pos_reg
=
1302 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1303 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1305 if (dispatch_width
== 8) {
1306 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1308 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1309 abld
.half(1).MOV(half(int_sample_x
, 1),
1310 fs_reg(suboffset(sample_pos_reg
, 16)));
1312 /* Compute gl_SamplePosition.x */
1313 compute_sample_position(pos
, int_sample_x
);
1314 pos
= offset(pos
, abld
, 1);
1315 if (dispatch_width
== 8) {
1316 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1318 abld
.half(0).MOV(half(int_sample_y
, 0),
1319 fs_reg(suboffset(sample_pos_reg
, 1)));
1320 abld
.half(1).MOV(half(int_sample_y
, 1),
1321 fs_reg(suboffset(sample_pos_reg
, 17)));
1323 /* Compute gl_SamplePosition.y */
1324 compute_sample_position(pos
, int_sample_y
);
1329 fs_visitor::emit_sampleid_setup()
1331 assert(stage
== MESA_SHADER_FRAGMENT
);
1332 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1333 assert(devinfo
->gen
>= 6);
1335 const fs_builder abld
= bld
.annotate("compute sample id");
1336 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1338 if (key
->compute_sample_id
) {
1339 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1341 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1343 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1344 * 8x multisampling, subspan 0 will represent sample N (where N
1345 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1346 * 7. We can find the value of N by looking at R0.0 bits 7:6
1347 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1348 * (since samples are always delivered in pairs). That is, we
1349 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1350 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1351 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1352 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1353 * populating a temporary variable with the sequence (0, 1, 2, 3),
1354 * and then reading from it using vstride=1, width=4, hstride=0.
1355 * These computations hold good for 4x multisampling as well.
1357 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1358 * the first four slots are sample 0 of subspan 0; the next four
1359 * are sample 1 of subspan 0; the third group is sample 0 of
1360 * subspan 1, and finally sample 1 of subspan 1.
1363 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1364 * accomodate 16x MSAA.
1366 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1368 abld
.exec_all().group(1, 0)
1369 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1370 brw_imm_ud(sspi_mask
));
1371 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1373 /* This works for both SIMD8 and SIMD16 */
1374 abld
.exec_all().group(4, 0)
1375 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1377 /* This special instruction takes care of setting vstride=1,
1378 * width=4, hstride=0 of t2 during an ADD instruction.
1380 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1382 /* As per GL_ARB_sample_shading specification:
1383 * "When rendering to a non-multisample buffer, or if multisample
1384 * rasterization is disabled, gl_SampleID will always be zero."
1386 abld
.MOV(*reg
, brw_imm_d(0));
1393 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1395 if (!src
.abs
&& !src
.negate
)
1398 fs_reg temp
= bld
.vgrf(src
.type
);
1405 fs_visitor::emit_discard_jump()
1407 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1409 /* For performance, after a discard, jump to the end of the
1410 * shader if all relevant channels have been discarded.
1412 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1413 discard_jump
->flag_subreg
= 1;
1415 discard_jump
->predicate
= (dispatch_width
== 8)
1416 ? BRW_PREDICATE_ALIGN1_ANY8H
1417 : BRW_PREDICATE_ALIGN1_ANY16H
;
1418 discard_jump
->predicate_inverse
= true;
1422 fs_visitor::emit_gs_thread_end()
1424 assert(stage
== MESA_SHADER_GEOMETRY
);
1426 struct brw_gs_prog_data
*gs_prog_data
=
1427 (struct brw_gs_prog_data
*) prog_data
;
1429 if (gs_compile
->control_data_header_size_bits
> 0) {
1430 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1433 const fs_builder abld
= bld
.annotate("thread end");
1436 if (gs_prog_data
->static_vertex_count
!= -1) {
1437 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1438 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1439 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1440 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1441 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1444 /* Delete now dead instructions. */
1445 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1451 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1455 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1456 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1457 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1460 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1461 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1462 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1463 sources
[1] = this->final_gs_vertex_count
;
1464 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1465 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1473 fs_visitor::assign_curb_setup()
1475 if (dispatch_width
== 8) {
1476 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1478 if (stage
== MESA_SHADER_FRAGMENT
) {
1479 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1480 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1481 } else if (stage
== MESA_SHADER_COMPUTE
) {
1482 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1483 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1485 unreachable("Unsupported shader type!");
1489 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1491 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1492 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1493 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1494 if (inst
->src
[i
].file
== UNIFORM
) {
1495 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1497 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1498 constant_nr
= push_constant_loc
[uniform_nr
];
1500 /* Section 5.11 of the OpenGL 4.1 spec says:
1501 * "Out-of-bounds reads return undefined values, which include
1502 * values from other variables of the active program or zero."
1503 * Just return the first push constant.
1508 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1511 brw_reg
.abs
= inst
->src
[i
].abs
;
1512 brw_reg
.negate
= inst
->src
[i
].negate
;
1514 assert(inst
->src
[i
].stride
== 0);
1515 inst
->src
[i
] = byte_offset(
1516 retype(brw_reg
, inst
->src
[i
].type
),
1517 inst
->src
[i
].subreg_offset
);
1522 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1523 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1527 fs_visitor::calculate_urb_setup()
1529 assert(stage
== MESA_SHADER_FRAGMENT
);
1530 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1531 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1533 memset(prog_data
->urb_setup
, -1,
1534 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1537 /* Figure out where each of the incoming setup attributes lands. */
1538 if (devinfo
->gen
>= 6) {
1539 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1540 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1541 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1542 * first 16 varying inputs, so we can put them wherever we want.
1543 * Just put them in order.
1545 * This is useful because it means that (a) inputs not used by the
1546 * fragment shader won't take up valuable register space, and (b) we
1547 * won't have to recompile the fragment shader if it gets paired with
1548 * a different vertex (or geometry) shader.
1550 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1551 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1552 BITFIELD64_BIT(i
)) {
1553 prog_data
->urb_setup
[i
] = urb_next
++;
1557 bool include_vue_header
=
1558 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1560 /* We have enough input varyings that the SF/SBE pipeline stage can't
1561 * arbitrarily rearrange them to suit our whim; we have to put them
1562 * in an order that matches the output of the previous pipeline stage
1563 * (geometry or vertex shader).
1565 struct brw_vue_map prev_stage_vue_map
;
1566 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1567 key
->input_slots_valid
,
1568 nir
->info
.separate_shader
);
1570 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1572 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1573 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1575 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1576 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1577 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1578 BITFIELD64_BIT(varying
))) {
1579 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1582 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1585 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1586 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1587 /* Point size is packed into the header, not as a general attribute */
1588 if (i
== VARYING_SLOT_PSIZ
)
1591 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1592 /* The back color slot is skipped when the front color is
1593 * also written to. In addition, some slots can be
1594 * written in the vertex shader and not read in the
1595 * fragment shader. So the register number must always be
1596 * incremented, mapped or not.
1598 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1599 prog_data
->urb_setup
[i
] = urb_next
;
1605 * It's a FS only attribute, and we did interpolation for this attribute
1606 * in SF thread. So, count it here, too.
1608 * See compile_sf_prog() for more info.
1610 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1611 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1614 prog_data
->num_varying_inputs
= urb_next
;
1618 fs_visitor::assign_urb_setup()
1620 assert(stage
== MESA_SHADER_FRAGMENT
);
1621 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1623 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1625 /* Offset all the urb_setup[] index by the actual position of the
1626 * setup regs, now that the location of the constants has been chosen.
1628 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1629 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1630 assert(inst
->src
[1].file
== FIXED_GRF
);
1631 inst
->src
[1].nr
+= urb_start
;
1634 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1635 assert(inst
->src
[0].file
== FIXED_GRF
);
1636 inst
->src
[0].nr
+= urb_start
;
1640 /* Each attribute is 4 setup channels, each of which is half a reg. */
1641 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1645 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1647 for (int i
= 0; i
< inst
->sources
; i
++) {
1648 if (inst
->src
[i
].file
== ATTR
) {
1649 int grf
= payload
.num_regs
+
1650 prog_data
->curb_read_length
+
1652 inst
->src
[i
].reg_offset
;
1654 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1655 struct brw_reg reg
=
1656 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1657 inst
->src
[i
].subreg_offset
),
1658 inst
->exec_size
* inst
->src
[i
].stride
,
1659 width
, inst
->src
[i
].stride
);
1660 reg
.abs
= inst
->src
[i
].abs
;
1661 reg
.negate
= inst
->src
[i
].negate
;
1669 fs_visitor::assign_vs_urb_setup()
1671 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1673 assert(stage
== MESA_SHADER_VERTEX
);
1675 /* Each attribute is 4 regs. */
1676 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1678 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1680 /* Rewrite all ATTR file references to the hw grf that they land in. */
1681 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1682 convert_attr_sources_to_hw_regs(inst
);
1687 fs_visitor::assign_tes_urb_setup()
1689 assert(stage
== MESA_SHADER_TESS_EVAL
);
1691 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1693 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1695 /* Rewrite all ATTR file references to HW_REGs. */
1696 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1697 convert_attr_sources_to_hw_regs(inst
);
1702 fs_visitor::assign_gs_urb_setup()
1704 assert(stage
== MESA_SHADER_GEOMETRY
);
1706 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1708 first_non_payload_grf
+=
1709 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1711 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1712 /* Rewrite all ATTR file references to GRFs. */
1713 convert_attr_sources_to_hw_regs(inst
);
1719 * Split large virtual GRFs into separate components if we can.
1721 * This is mostly duplicated with what brw_fs_vector_splitting does,
1722 * but that's really conservative because it's afraid of doing
1723 * splitting that doesn't result in real progress after the rest of
1724 * the optimization phases, which would cause infinite looping in
1725 * optimization. We can do it once here, safely. This also has the
1726 * opportunity to split interpolated values, or maybe even uniforms,
1727 * which we don't have at the IR level.
1729 * We want to split, because virtual GRFs are what we register
1730 * allocate and spill (due to contiguousness requirements for some
1731 * instructions), and they're what we naturally generate in the
1732 * codegen process, but most virtual GRFs don't actually need to be
1733 * contiguous sets of GRFs. If we split, we'll end up with reduced
1734 * live intervals and better dead code elimination and coalescing.
1737 fs_visitor::split_virtual_grfs()
1739 int num_vars
= this->alloc
.count
;
1741 /* Count the total number of registers */
1743 int vgrf_to_reg
[num_vars
];
1744 for (int i
= 0; i
< num_vars
; i
++) {
1745 vgrf_to_reg
[i
] = reg_count
;
1746 reg_count
+= alloc
.sizes
[i
];
1749 /* An array of "split points". For each register slot, this indicates
1750 * if this slot can be separated from the previous slot. Every time an
1751 * instruction uses multiple elements of a register (as a source or
1752 * destination), we mark the used slots as inseparable. Then we go
1753 * through and split the registers into the smallest pieces we can.
1755 bool split_points
[reg_count
];
1756 memset(split_points
, 0, sizeof(split_points
));
1758 /* Mark all used registers as fully splittable */
1759 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1760 if (inst
->dst
.file
== VGRF
) {
1761 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1762 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1763 split_points
[reg
+ j
] = true;
1766 for (int i
= 0; i
< inst
->sources
; i
++) {
1767 if (inst
->src
[i
].file
== VGRF
) {
1768 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1769 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1770 split_points
[reg
+ j
] = true;
1775 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1776 if (inst
->dst
.file
== VGRF
) {
1777 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1778 for (int j
= 1; j
< inst
->regs_written
; j
++)
1779 split_points
[reg
+ j
] = false;
1781 for (int i
= 0; i
< inst
->sources
; i
++) {
1782 if (inst
->src
[i
].file
== VGRF
) {
1783 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1784 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1785 split_points
[reg
+ j
] = false;
1790 int new_virtual_grf
[reg_count
];
1791 int new_reg_offset
[reg_count
];
1794 for (int i
= 0; i
< num_vars
; i
++) {
1795 /* The first one should always be 0 as a quick sanity check. */
1796 assert(split_points
[reg
] == false);
1799 new_reg_offset
[reg
] = 0;
1804 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1805 /* If this is a split point, reset the offset to 0 and allocate a
1806 * new virtual GRF for the previous offset many registers
1808 if (split_points
[reg
]) {
1809 assert(offset
<= MAX_VGRF_SIZE
);
1810 int grf
= alloc
.allocate(offset
);
1811 for (int k
= reg
- offset
; k
< reg
; k
++)
1812 new_virtual_grf
[k
] = grf
;
1815 new_reg_offset
[reg
] = offset
;
1820 /* The last one gets the original register number */
1821 assert(offset
<= MAX_VGRF_SIZE
);
1822 alloc
.sizes
[i
] = offset
;
1823 for (int k
= reg
- offset
; k
< reg
; k
++)
1824 new_virtual_grf
[k
] = i
;
1826 assert(reg
== reg_count
);
1828 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1829 if (inst
->dst
.file
== VGRF
) {
1830 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1831 inst
->dst
.nr
= new_virtual_grf
[reg
];
1832 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1833 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1835 for (int i
= 0; i
< inst
->sources
; i
++) {
1836 if (inst
->src
[i
].file
== VGRF
) {
1837 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1838 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1839 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1840 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1844 invalidate_live_intervals();
1848 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1850 * During code generation, we create tons of temporary variables, many of
1851 * which get immediately killed and are never used again. Yet, in later
1852 * optimization and analysis passes, such as compute_live_intervals, we need
1853 * to loop over all the virtual GRFs. Compacting them can save a lot of
1857 fs_visitor::compact_virtual_grfs()
1859 bool progress
= false;
1860 int remap_table
[this->alloc
.count
];
1861 memset(remap_table
, -1, sizeof(remap_table
));
1863 /* Mark which virtual GRFs are used. */
1864 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1865 if (inst
->dst
.file
== VGRF
)
1866 remap_table
[inst
->dst
.nr
] = 0;
1868 for (int i
= 0; i
< inst
->sources
; i
++) {
1869 if (inst
->src
[i
].file
== VGRF
)
1870 remap_table
[inst
->src
[i
].nr
] = 0;
1874 /* Compact the GRF arrays. */
1876 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1877 if (remap_table
[i
] == -1) {
1878 /* We just found an unused register. This means that we are
1879 * actually going to compact something.
1883 remap_table
[i
] = new_index
;
1884 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1885 invalidate_live_intervals();
1890 this->alloc
.count
= new_index
;
1892 /* Patch all the instructions to use the newly renumbered registers */
1893 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1894 if (inst
->dst
.file
== VGRF
)
1895 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1897 for (int i
= 0; i
< inst
->sources
; i
++) {
1898 if (inst
->src
[i
].file
== VGRF
)
1899 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1903 /* Patch all the references to delta_xy, since they're used in register
1904 * allocation. If they're unused, switch them to BAD_FILE so we don't
1905 * think some random VGRF is delta_xy.
1907 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1908 if (delta_xy
[i
].file
== VGRF
) {
1909 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1910 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1912 delta_xy
[i
].file
= BAD_FILE
;
1921 * Assign UNIFORM file registers to either push constants or pull constants.
1923 * We allow a fragment shader to have more than the specified minimum
1924 * maximum number of fragment shader uniform components (64). If
1925 * there are too many of these, they'd fill up all of register space.
1926 * So, this will push some of them out to the pull constant buffer and
1927 * update the program to load them.
1930 fs_visitor::assign_constant_locations()
1932 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1933 if (dispatch_width
!= 8)
1936 bool is_live
[uniforms
];
1937 memset(is_live
, 0, sizeof(is_live
));
1939 /* For each uniform slot, a value of true indicates that the given slot and
1940 * the next slot must remain contiguous. This is used to keep us from
1941 * splitting arrays apart.
1943 bool contiguous
[uniforms
];
1944 memset(contiguous
, 0, sizeof(contiguous
));
1946 /* First, we walk through the instructions and do two things:
1948 * 1) Figure out which uniforms are live.
1950 * 2) Mark any indirectly used ranges of registers as contiguous.
1952 * Note that we don't move constant-indexed accesses to arrays. No
1953 * testing has been done of the performance impact of this choice.
1955 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1956 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1957 if (inst
->src
[i
].file
!= UNIFORM
)
1960 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1962 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
1963 assert(inst
->src
[2].ud
% 4 == 0);
1964 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
1965 assert(last
< uniforms
);
1967 for (unsigned j
= constant_nr
; j
< last
; j
++) {
1969 contiguous
[j
] = true;
1971 is_live
[last
] = true;
1973 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1974 is_live
[constant_nr
] = true;
1979 /* Only allow 16 registers (128 uniform components) as push constants.
1981 * Just demote the end of the list. We could probably do better
1982 * here, demoting things that are rarely used in the program first.
1984 * If changing this value, note the limitation about total_regs in
1987 const unsigned int max_push_components
= 16 * 8;
1989 /* For vulkan we don't limit the max_chunk_size. We set it to 32 float =
1990 * 128 bytes, which is the maximum vulkan push constant size.
1992 const unsigned int max_chunk_size
= 32;
1994 unsigned int num_push_constants
= 0;
1995 unsigned int num_pull_constants
= 0;
1997 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1998 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2000 int chunk_start
= -1;
2001 for (unsigned u
= 0; u
< uniforms
; u
++) {
2002 push_constant_loc
[u
] = -1;
2003 pull_constant_loc
[u
] = -1;
2008 /* This is the first live uniform in the chunk */
2009 if (chunk_start
< 0)
2012 /* If this element does not need to be contiguous with the next, we
2013 * split at this point and everthing between chunk_start and u forms a
2016 if (!contiguous
[u
]) {
2017 unsigned chunk_size
= u
- chunk_start
+ 1;
2019 if (num_push_constants
+ chunk_size
<= max_push_components
&&
2020 chunk_size
<= max_chunk_size
) {
2021 for (unsigned j
= chunk_start
; j
<= u
; j
++)
2022 push_constant_loc
[j
] = num_push_constants
++;
2024 for (unsigned j
= chunk_start
; j
<= u
; j
++)
2025 pull_constant_loc
[j
] = num_pull_constants
++;
2032 stage_prog_data
->nr_params
= num_push_constants
;
2033 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2035 /* Up until now, the param[] array has been indexed by reg + reg_offset
2036 * of UNIFORM registers. Move pull constants into pull_param[] and
2037 * condense param[] to only contain the uniforms we chose to push.
2039 * NOTE: Because we are condensing the params[] array, we know that
2040 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2041 * having to make a copy.
2043 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2044 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
2046 if (pull_constant_loc
[i
] != -1) {
2047 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2048 } else if (push_constant_loc
[i
] != -1) {
2049 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2055 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2056 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2059 fs_visitor::lower_constant_loads()
2061 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2063 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2064 /* Set up the annotation tracking for new generated instructions. */
2065 const fs_builder
ibld(this, block
, inst
);
2067 for (int i
= 0; i
< inst
->sources
; i
++) {
2068 if (inst
->src
[i
].file
!= UNIFORM
)
2071 /* We'll handle this case later */
2072 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2075 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2076 if (location
>= uniforms
)
2077 continue; /* Out of bounds access */
2079 int pull_index
= pull_constant_loc
[location
];
2081 if (pull_index
== -1)
2084 assert(inst
->src
[i
].stride
== 0);
2086 fs_reg dst
= vgrf(glsl_type::float_type
);
2087 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2088 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2089 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2090 dst
, brw_imm_ud(index
), offset
);
2092 /* Rewrite the instruction to use the temporary VGRF. */
2093 inst
->src
[i
].file
= VGRF
;
2094 inst
->src
[i
].nr
= dst
.nr
;
2095 inst
->src
[i
].reg_offset
= 0;
2096 inst
->src
[i
].set_smear(pull_index
& 3);
2098 brw_mark_surface_used(prog_data
, index
);
2101 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2102 inst
->src
[0].file
== UNIFORM
) {
2104 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].reg_offset
;
2105 if (location
>= uniforms
)
2106 continue; /* Out of bounds access */
2108 int pull_index
= pull_constant_loc
[location
];
2110 if (pull_index
== -1)
2113 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2117 inst
->remove(block
);
2119 brw_mark_surface_used(prog_data
, index
);
2122 invalidate_live_intervals();
2126 fs_visitor::opt_algebraic()
2128 bool progress
= false;
2130 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2131 switch (inst
->opcode
) {
2132 case BRW_OPCODE_MOV
:
2133 if (inst
->src
[0].file
!= IMM
)
2136 if (inst
->saturate
) {
2137 if (inst
->dst
.type
!= inst
->src
[0].type
)
2138 assert(!"unimplemented: saturate mixed types");
2140 if (brw_saturate_immediate(inst
->dst
.type
,
2141 &inst
->src
[0].as_brw_reg())) {
2142 inst
->saturate
= false;
2148 case BRW_OPCODE_MUL
:
2149 if (inst
->src
[1].file
!= IMM
)
2153 if (inst
->src
[1].is_one()) {
2154 inst
->opcode
= BRW_OPCODE_MOV
;
2155 inst
->src
[1] = reg_undef
;
2161 if (inst
->src
[1].is_negative_one()) {
2162 inst
->opcode
= BRW_OPCODE_MOV
;
2163 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2164 inst
->src
[1] = reg_undef
;
2170 if (inst
->src
[1].is_zero()) {
2171 inst
->opcode
= BRW_OPCODE_MOV
;
2172 inst
->src
[0] = inst
->src
[1];
2173 inst
->src
[1] = reg_undef
;
2178 if (inst
->src
[0].file
== IMM
) {
2179 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2180 inst
->opcode
= BRW_OPCODE_MOV
;
2181 inst
->src
[0].f
*= inst
->src
[1].f
;
2182 inst
->src
[1] = reg_undef
;
2187 case BRW_OPCODE_ADD
:
2188 if (inst
->src
[1].file
!= IMM
)
2192 if (inst
->src
[1].is_zero()) {
2193 inst
->opcode
= BRW_OPCODE_MOV
;
2194 inst
->src
[1] = reg_undef
;
2199 if (inst
->src
[0].file
== IMM
) {
2200 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2201 inst
->opcode
= BRW_OPCODE_MOV
;
2202 inst
->src
[0].f
+= inst
->src
[1].f
;
2203 inst
->src
[1] = reg_undef
;
2209 if (inst
->src
[0].equals(inst
->src
[1])) {
2210 inst
->opcode
= BRW_OPCODE_MOV
;
2211 inst
->src
[1] = reg_undef
;
2216 case BRW_OPCODE_LRP
:
2217 if (inst
->src
[1].equals(inst
->src
[2])) {
2218 inst
->opcode
= BRW_OPCODE_MOV
;
2219 inst
->src
[0] = inst
->src
[1];
2220 inst
->src
[1] = reg_undef
;
2221 inst
->src
[2] = reg_undef
;
2226 case BRW_OPCODE_CMP
:
2227 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2229 inst
->src
[0].negate
&&
2230 inst
->src
[1].is_zero()) {
2231 inst
->src
[0].abs
= false;
2232 inst
->src
[0].negate
= false;
2233 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2238 case BRW_OPCODE_SEL
:
2239 if (inst
->src
[0].equals(inst
->src
[1])) {
2240 inst
->opcode
= BRW_OPCODE_MOV
;
2241 inst
->src
[1] = reg_undef
;
2242 inst
->predicate
= BRW_PREDICATE_NONE
;
2243 inst
->predicate_inverse
= false;
2245 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2246 switch (inst
->conditional_mod
) {
2247 case BRW_CONDITIONAL_LE
:
2248 case BRW_CONDITIONAL_L
:
2249 switch (inst
->src
[1].type
) {
2250 case BRW_REGISTER_TYPE_F
:
2251 if (inst
->src
[1].f
>= 1.0f
) {
2252 inst
->opcode
= BRW_OPCODE_MOV
;
2253 inst
->src
[1] = reg_undef
;
2254 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2262 case BRW_CONDITIONAL_GE
:
2263 case BRW_CONDITIONAL_G
:
2264 switch (inst
->src
[1].type
) {
2265 case BRW_REGISTER_TYPE_F
:
2266 if (inst
->src
[1].f
<= 0.0f
) {
2267 inst
->opcode
= BRW_OPCODE_MOV
;
2268 inst
->src
[1] = reg_undef
;
2269 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2281 case BRW_OPCODE_MAD
:
2282 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2283 inst
->opcode
= BRW_OPCODE_MOV
;
2284 inst
->src
[1] = reg_undef
;
2285 inst
->src
[2] = reg_undef
;
2287 } else if (inst
->src
[0].is_zero()) {
2288 inst
->opcode
= BRW_OPCODE_MUL
;
2289 inst
->src
[0] = inst
->src
[2];
2290 inst
->src
[2] = reg_undef
;
2292 } else if (inst
->src
[1].is_one()) {
2293 inst
->opcode
= BRW_OPCODE_ADD
;
2294 inst
->src
[1] = inst
->src
[2];
2295 inst
->src
[2] = reg_undef
;
2297 } else if (inst
->src
[2].is_one()) {
2298 inst
->opcode
= BRW_OPCODE_ADD
;
2299 inst
->src
[2] = reg_undef
;
2301 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2302 inst
->opcode
= BRW_OPCODE_ADD
;
2303 inst
->src
[1].f
*= inst
->src
[2].f
;
2304 inst
->src
[2] = reg_undef
;
2308 case SHADER_OPCODE_RCP
: {
2309 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2310 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2311 if (inst
->src
[0].equals(prev
->dst
)) {
2312 inst
->opcode
= SHADER_OPCODE_RSQ
;
2313 inst
->src
[0] = prev
->src
[0];
2319 case SHADER_OPCODE_BROADCAST
:
2320 if (is_uniform(inst
->src
[0])) {
2321 inst
->opcode
= BRW_OPCODE_MOV
;
2323 inst
->force_writemask_all
= true;
2325 } else if (inst
->src
[1].file
== IMM
) {
2326 inst
->opcode
= BRW_OPCODE_MOV
;
2327 inst
->src
[0] = component(inst
->src
[0],
2330 inst
->force_writemask_all
= true;
2339 /* Swap if src[0] is immediate. */
2340 if (progress
&& inst
->is_commutative()) {
2341 if (inst
->src
[0].file
== IMM
) {
2342 fs_reg tmp
= inst
->src
[1];
2343 inst
->src
[1] = inst
->src
[0];
2352 * Optimize sample messages that have constant zero values for the trailing
2353 * texture coordinates. We can just reduce the message length for these
2354 * instructions instead of reserving a register for it. Trailing parameters
2355 * that aren't sent default to zero anyway. This will cause the dead code
2356 * eliminator to remove the MOV instruction that would otherwise be emitted to
2357 * set up the zero value.
2360 fs_visitor::opt_zero_samples()
2362 /* Gen4 infers the texturing opcode based on the message length so we can't
2365 if (devinfo
->gen
< 5)
2368 bool progress
= false;
2370 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2371 if (!inst
->is_tex())
2374 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2376 if (load_payload
->is_head_sentinel() ||
2377 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2380 /* We don't want to remove the message header or the first parameter.
2381 * Removing the first parameter is not allowed, see the Haswell PRM
2382 * volume 7, page 149:
2384 * "Parameter 0 is required except for the sampleinfo message, which
2385 * has no parameter 0"
2387 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2388 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2389 (inst
->exec_size
/ 8) +
2390 inst
->header_size
- 1].is_zero()) {
2391 inst
->mlen
-= inst
->exec_size
/ 8;
2397 invalidate_live_intervals();
2403 * Optimize sample messages which are followed by the final RT write.
2405 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2406 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2407 * final texturing results copied to the framebuffer write payload and modify
2408 * them to write to the framebuffer directly.
2411 fs_visitor::opt_sampler_eot()
2413 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2415 if (stage
!= MESA_SHADER_FRAGMENT
)
2418 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2421 /* FINISHME: It should be possible to implement this optimization when there
2422 * are multiple drawbuffers.
2424 if (key
->nr_color_regions
!= 1)
2427 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2428 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2429 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2430 assert(fb_write
->eot
);
2431 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2433 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2435 /* There wasn't one; nothing to do. */
2436 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2439 /* 3D Sampler » Messages » Message Format
2441 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2442 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2444 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2445 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2446 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2447 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2448 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2451 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2452 * It's very likely to be the previous instruction.
2454 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2455 if (load_payload
->is_head_sentinel() ||
2456 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2459 assert(!tex_inst
->eot
); /* We can't get here twice */
2460 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2462 const fs_builder
ibld(this, block
, tex_inst
);
2464 tex_inst
->offset
|= fb_write
->target
<< 24;
2465 tex_inst
->eot
= true;
2466 tex_inst
->dst
= ibld
.null_reg_ud();
2467 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2469 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2470 * to create a new LOAD_PAYLOAD command with the same sources and a space
2471 * saved for the header. Using a new destination register not only makes sure
2472 * we have enough space, but it will make sure the dead code eliminator kills
2473 * the instruction that this will replace.
2475 if (tex_inst
->header_size
!= 0)
2478 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2479 load_payload
->sources
+ 1);
2480 fs_reg
*new_sources
=
2481 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2483 new_sources
[0] = fs_reg();
2484 for (int i
= 0; i
< load_payload
->sources
; i
++)
2485 new_sources
[i
+1] = load_payload
->src
[i
];
2487 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2488 * requires a lot of information about the sources to appropriately figure
2489 * out the number of registers needed to be used. Given this stage in our
2490 * optimization, we may not have the appropriate GRFs required by
2491 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2492 * manually emit the instruction.
2494 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2495 load_payload
->exec_size
,
2498 load_payload
->sources
+ 1);
2500 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2501 new_load_payload
->header_size
= 1;
2503 tex_inst
->header_size
= 1;
2504 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2505 tex_inst
->src
[0] = send_header
;
2511 fs_visitor::opt_register_renaming()
2513 bool progress
= false;
2516 int remap
[alloc
.count
];
2517 memset(remap
, -1, sizeof(int) * alloc
.count
);
2519 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2520 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2522 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2523 inst
->opcode
== BRW_OPCODE_WHILE
) {
2527 /* Rewrite instruction sources. */
2528 for (int i
= 0; i
< inst
->sources
; i
++) {
2529 if (inst
->src
[i
].file
== VGRF
&&
2530 remap
[inst
->src
[i
].nr
] != -1 &&
2531 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2532 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2537 const int dst
= inst
->dst
.nr
;
2540 inst
->dst
.file
== VGRF
&&
2541 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2542 !inst
->is_partial_write()) {
2543 if (remap
[dst
] == -1) {
2546 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2547 inst
->dst
.nr
= remap
[dst
];
2550 } else if (inst
->dst
.file
== VGRF
&&
2552 remap
[dst
] != dst
) {
2553 inst
->dst
.nr
= remap
[dst
];
2559 invalidate_live_intervals();
2561 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2562 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2563 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2572 * Remove redundant or useless discard jumps.
2574 * For example, we can eliminate jumps in the following sequence:
2576 * discard-jump (redundant with the next jump)
2577 * discard-jump (useless; jumps to the next instruction)
2581 fs_visitor::opt_redundant_discard_jumps()
2583 bool progress
= false;
2585 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2587 fs_inst
*placeholder_halt
= NULL
;
2588 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2589 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2590 placeholder_halt
= inst
;
2595 if (!placeholder_halt
)
2598 /* Delete any HALTs immediately before the placeholder halt. */
2599 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2600 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2601 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2602 prev
->remove(last_bblock
);
2607 invalidate_live_intervals();
2613 fs_visitor::compute_to_mrf()
2615 bool progress
= false;
2618 /* No MRFs on Gen >= 7. */
2619 if (devinfo
->gen
>= 7)
2622 calculate_live_intervals();
2624 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2628 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2629 inst
->is_partial_write() ||
2630 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2631 inst
->dst
.type
!= inst
->src
[0].type
||
2632 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2633 !inst
->src
[0].is_contiguous() ||
2634 inst
->src
[0].subreg_offset
)
2637 /* Work out which hardware MRF registers are written by this
2640 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2642 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2643 mrf_high
= mrf_low
+ 4;
2644 } else if (inst
->exec_size
== 16) {
2645 mrf_high
= mrf_low
+ 1;
2650 /* Can't compute-to-MRF this GRF if someone else was going to
2653 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2656 /* Found a move of a GRF to a MRF. Let's see if we can go
2657 * rewrite the thing that made this GRF to write into the MRF.
2659 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2660 if (scan_inst
->dst
.file
== VGRF
&&
2661 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2662 /* Found the last thing to write our reg we want to turn
2663 * into a compute-to-MRF.
2666 /* If this one instruction didn't populate all the
2667 * channels, bail. We might be able to rewrite everything
2668 * that writes that reg, but it would require smarter
2669 * tracking to delay the rewriting until complete success.
2671 if (scan_inst
->is_partial_write())
2674 /* Things returning more than one register would need us to
2675 * understand coalescing out more than one MOV at a time.
2677 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2680 /* SEND instructions can't have MRF as a destination. */
2681 if (scan_inst
->mlen
)
2684 if (devinfo
->gen
== 6) {
2685 /* gen6 math instructions must have the destination be
2686 * GRF, so no compute-to-MRF for them.
2688 if (scan_inst
->is_math()) {
2693 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2694 /* Found the creator of our MRF's source value. */
2695 scan_inst
->dst
.file
= MRF
;
2696 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2697 scan_inst
->saturate
|= inst
->saturate
;
2698 inst
->remove(block
);
2704 /* We don't handle control flow here. Most computation of
2705 * values that end up in MRFs are shortly before the MRF
2708 if (block
->start() == scan_inst
)
2711 /* You can't read from an MRF, so if someone else reads our
2712 * MRF's source GRF that we wanted to rewrite, that stops us.
2714 bool interfered
= false;
2715 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2716 if (scan_inst
->src
[i
].file
== VGRF
&&
2717 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2718 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2725 if (scan_inst
->dst
.file
== MRF
) {
2726 /* If somebody else writes our MRF here, we can't
2727 * compute-to-MRF before that.
2729 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2732 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2733 scan_mrf_high
= scan_mrf_low
+ 4;
2734 } else if (scan_inst
->exec_size
== 16) {
2735 scan_mrf_high
= scan_mrf_low
+ 1;
2737 scan_mrf_high
= scan_mrf_low
;
2740 if (mrf_low
== scan_mrf_low
||
2741 mrf_low
== scan_mrf_high
||
2742 mrf_high
== scan_mrf_low
||
2743 mrf_high
== scan_mrf_high
) {
2748 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2749 /* Found a SEND instruction, which means that there are
2750 * live values in MRFs from base_mrf to base_mrf +
2751 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2754 if (mrf_low
>= scan_inst
->base_mrf
&&
2755 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2758 if (mrf_high
>= scan_inst
->base_mrf
&&
2759 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2767 invalidate_live_intervals();
2773 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2774 * flow. We could probably do better here with some form of divergence
2778 fs_visitor::eliminate_find_live_channel()
2780 bool progress
= false;
2783 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2784 switch (inst
->opcode
) {
2790 case BRW_OPCODE_ENDIF
:
2791 case BRW_OPCODE_WHILE
:
2795 case FS_OPCODE_DISCARD_JUMP
:
2796 /* This can potentially make control flow non-uniform until the end
2801 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2803 inst
->opcode
= BRW_OPCODE_MOV
;
2804 inst
->src
[0] = brw_imm_ud(0u);
2806 inst
->force_writemask_all
= true;
2820 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2821 * instructions to FS_OPCODE_REP_FB_WRITE.
2824 fs_visitor::emit_repclear_shader()
2826 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2828 int color_mrf
= base_mrf
+ 2;
2831 if (uniforms
== 1) {
2832 mov
= bld
.exec_all().group(4, 0)
2833 .MOV(brw_message_reg(color_mrf
),
2834 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2836 struct brw_reg reg
=
2837 brw_reg(BRW_GENERAL_REGISTER_FILE
,
2838 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2839 BRW_VERTICAL_STRIDE_8
,
2841 BRW_HORIZONTAL_STRIDE_4
, BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2843 mov
= bld
.exec_all().group(4, 0)
2844 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2848 if (key
->nr_color_regions
== 1) {
2849 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2850 write
->saturate
= key
->clamp_fragment_color
;
2851 write
->base_mrf
= color_mrf
;
2853 write
->header_size
= 0;
2856 assume(key
->nr_color_regions
> 0);
2857 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2858 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2859 write
->saturate
= key
->clamp_fragment_color
;
2860 write
->base_mrf
= base_mrf
;
2862 write
->header_size
= 2;
2870 assign_constant_locations();
2871 assign_curb_setup();
2873 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2874 if (uniforms
== 1) {
2875 assert(mov
->src
[0].file
== FIXED_GRF
);
2876 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2881 * Walks through basic blocks, looking for repeated MRF writes and
2882 * removing the later ones.
2885 fs_visitor::remove_duplicate_mrf_writes()
2887 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2888 bool progress
= false;
2890 /* Need to update the MRF tracking for compressed instructions. */
2891 if (dispatch_width
== 16)
2894 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2896 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2897 if (inst
->is_control_flow()) {
2898 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2901 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2902 inst
->dst
.file
== MRF
) {
2903 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2904 if (prev_inst
&& inst
->equals(prev_inst
)) {
2905 inst
->remove(block
);
2911 /* Clear out the last-write records for MRFs that were overwritten. */
2912 if (inst
->dst
.file
== MRF
) {
2913 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2916 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2917 /* Found a SEND instruction, which will include two or fewer
2918 * implied MRF writes. We could do better here.
2920 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2921 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2925 /* Clear out any MRF move records whose sources got overwritten. */
2926 if (inst
->dst
.file
== VGRF
) {
2927 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2928 if (last_mrf_move
[i
] &&
2929 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
2930 last_mrf_move
[i
] = NULL
;
2935 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2936 inst
->dst
.file
== MRF
&&
2937 inst
->src
[0].file
== VGRF
&&
2938 !inst
->is_partial_write()) {
2939 last_mrf_move
[inst
->dst
.nr
] = inst
;
2944 invalidate_live_intervals();
2950 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2952 /* Clear the flag for registers that actually got read (as expected). */
2953 for (int i
= 0; i
< inst
->sources
; i
++) {
2955 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
2956 grf
= inst
->src
[i
].nr
;
2961 if (grf
>= first_grf
&&
2962 grf
< first_grf
+ grf_len
) {
2963 deps
[grf
- first_grf
] = false;
2964 if (inst
->exec_size
== 16)
2965 deps
[grf
- first_grf
+ 1] = false;
2971 * Implements this workaround for the original 965:
2973 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2974 * check for post destination dependencies on this instruction, software
2975 * must ensure that there is no destination hazard for the case of ‘write
2976 * followed by a posted write’ shown in the following example.
2979 * 2. send r3.xy <rest of send instruction>
2982 * Due to no post-destination dependency check on the ‘send’, the above
2983 * code sequence could have two instructions (1 and 2) in flight at the
2984 * same time that both consider ‘r3’ as the target of their final writes.
2987 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2990 int write_len
= inst
->regs_written
;
2991 int first_write_grf
= inst
->dst
.nr
;
2992 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2993 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2995 memset(needs_dep
, false, sizeof(needs_dep
));
2996 memset(needs_dep
, true, write_len
);
2998 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3000 /* Walk backwards looking for writes to registers we're writing which
3001 * aren't read since being written. If we hit the start of the program,
3002 * we assume that there are no outstanding dependencies on entry to the
3005 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3006 /* If we hit control flow, assume that there *are* outstanding
3007 * dependencies, and force their cleanup before our instruction.
3009 if (block
->start() == scan_inst
) {
3010 for (int i
= 0; i
< write_len
; i
++) {
3012 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3013 first_write_grf
+ i
);
3018 /* We insert our reads as late as possible on the assumption that any
3019 * instruction but a MOV that might have left us an outstanding
3020 * dependency has more latency than a MOV.
3022 if (scan_inst
->dst
.file
== VGRF
) {
3023 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3024 int reg
= scan_inst
->dst
.nr
+ i
;
3026 if (reg
>= first_write_grf
&&
3027 reg
< first_write_grf
+ write_len
&&
3028 needs_dep
[reg
- first_write_grf
]) {
3029 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3030 needs_dep
[reg
- first_write_grf
] = false;
3031 if (scan_inst
->exec_size
== 16)
3032 needs_dep
[reg
- first_write_grf
+ 1] = false;
3037 /* Clear the flag for registers that actually got read (as expected). */
3038 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3040 /* Continue the loop only if we haven't resolved all the dependencies */
3042 for (i
= 0; i
< write_len
; i
++) {
3052 * Implements this workaround for the original 965:
3054 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3055 * used as a destination register until after it has been sourced by an
3056 * instruction with a different destination register.
3059 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3061 int write_len
= inst
->regs_written
;
3062 int first_write_grf
= inst
->dst
.nr
;
3063 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3064 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3066 memset(needs_dep
, false, sizeof(needs_dep
));
3067 memset(needs_dep
, true, write_len
);
3068 /* Walk forwards looking for writes to registers we're writing which aren't
3069 * read before being written.
3071 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3072 /* If we hit control flow, force resolve all remaining dependencies. */
3073 if (block
->end() == scan_inst
) {
3074 for (int i
= 0; i
< write_len
; i
++) {
3076 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3077 first_write_grf
+ i
);
3082 /* Clear the flag for registers that actually got read (as expected). */
3083 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3085 /* We insert our reads as late as possible since they're reading the
3086 * result of a SEND, which has massive latency.
3088 if (scan_inst
->dst
.file
== VGRF
&&
3089 scan_inst
->dst
.nr
>= first_write_grf
&&
3090 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3091 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3092 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3094 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3097 /* Continue the loop only if we haven't resolved all the dependencies */
3099 for (i
= 0; i
< write_len
; i
++) {
3109 fs_visitor::insert_gen4_send_dependency_workarounds()
3111 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3114 bool progress
= false;
3116 /* Note that we're done with register allocation, so GRF fs_regs always
3117 * have a .reg_offset of 0.
3120 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3121 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3122 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3123 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3129 invalidate_live_intervals();
3133 * Turns the generic expression-style uniform pull constant load instruction
3134 * into a hardware-specific series of instructions for loading a pull
3137 * The expression style allows the CSE pass before this to optimize out
3138 * repeated loads from the same offset, and gives the pre-register-allocation
3139 * scheduling full flexibility, while the conversion to native instructions
3140 * allows the post-register-allocation scheduler the best information
3143 * Note that execution masking for setting up pull constant loads is special:
3144 * the channels that need to be written are unrelated to the current execution
3145 * mask, since a later instruction will use one of the result channels as a
3146 * source operand for all 8 or 16 of its channels.
3149 fs_visitor::lower_uniform_pull_constant_loads()
3151 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3152 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3155 if (devinfo
->gen
>= 7) {
3156 /* The offset arg is a vec4-aligned immediate byte offset. */
3157 fs_reg const_offset_reg
= inst
->src
[1];
3158 assert(const_offset_reg
.file
== IMM
&&
3159 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3160 assert(const_offset_reg
.ud
% 16 == 0);
3162 fs_reg payload
, offset
;
3163 if (devinfo
->gen
>= 9) {
3164 /* We have to use a message header on Skylake to get SIMD4x2
3165 * mode. Reserve space for the register.
3167 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3168 offset
.reg_offset
++;
3171 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3175 /* This is actually going to be a MOV, but since only the first dword
3176 * is accessed, we have a special opcode to do just that one. Note
3177 * that this needs to be an operation that will be considered a def
3178 * by live variable analysis, or register allocation will explode.
3180 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3181 8, offset
, const_offset_reg
);
3182 setup
->force_writemask_all
= true;
3184 setup
->ir
= inst
->ir
;
3185 setup
->annotation
= inst
->annotation
;
3186 inst
->insert_before(block
, setup
);
3188 /* Similarly, this will only populate the first 4 channels of the
3189 * result register (since we only use smear values from 0-3), but we
3190 * don't tell the optimizer.
3192 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3193 inst
->src
[1] = payload
;
3194 inst
->base_mrf
= -1;
3196 invalidate_live_intervals();
3198 /* Before register allocation, we didn't tell the scheduler about the
3199 * MRF we use. We know it's safe to use this MRF because nothing
3200 * else does except for register spill/unspill, which generates and
3201 * uses its MRF within a single IR instruction.
3203 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3210 fs_visitor::lower_load_payload()
3212 bool progress
= false;
3214 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3215 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3218 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3219 assert(inst
->saturate
== false);
3220 fs_reg dst
= inst
->dst
;
3222 /* Get rid of COMPR4. We'll add it back in if we need it */
3223 if (dst
.file
== MRF
)
3224 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3226 const fs_builder
ibld(this, block
, inst
);
3227 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3229 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3230 if (inst
->src
[i
].file
!= BAD_FILE
) {
3231 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3232 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3233 hbld
.MOV(mov_dst
, mov_src
);
3235 dst
= offset(dst
, hbld
, 1);
3238 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3239 inst
->exec_size
> 8) {
3240 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3241 * a straightforward copy. Instead, the result of the
3242 * LOAD_PAYLOAD is treated as interleaved and the first four
3243 * non-header sources are unpacked as:
3254 * This is used for gen <= 5 fb writes.
3256 assert(inst
->exec_size
== 16);
3257 assert(inst
->header_size
+ 4 <= inst
->sources
);
3258 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3259 if (inst
->src
[i
].file
!= BAD_FILE
) {
3260 if (devinfo
->has_compr4
) {
3261 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3262 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3263 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3265 /* Platform doesn't have COMPR4. We have to fake it */
3266 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3267 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3269 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3276 /* The loop above only ever incremented us through the first set
3277 * of 4 registers. However, thanks to the magic of COMPR4, we
3278 * actually wrote to the first 8 registers, so we need to take
3279 * that into account now.
3283 /* The COMPR4 code took care of the first 4 sources. We'll let
3284 * the regular path handle any remaining sources. Yes, we are
3285 * modifying the instruction but we're about to delete it so
3286 * this really doesn't hurt anything.
3288 inst
->header_size
+= 4;
3291 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3292 if (inst
->src
[i
].file
!= BAD_FILE
)
3293 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3294 dst
= offset(dst
, ibld
, 1);
3297 inst
->remove(block
);
3302 invalidate_live_intervals();
3308 fs_visitor::lower_integer_multiplication()
3310 bool progress
= false;
3312 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3313 const fs_builder
ibld(this, block
, inst
);
3315 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3316 if (inst
->dst
.is_accumulator() ||
3317 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3318 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3321 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3322 * operation directly, but CHV/BXT cannot.
3324 if (devinfo
->gen
>= 8 &&
3325 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3328 if (inst
->src
[1].file
== IMM
&&
3329 inst
->src
[1].ud
< (1 << 16)) {
3330 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3331 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3334 * If multiplying by an immediate value that fits in 16-bits, do a
3335 * single MUL instruction with that value in the proper location.
3337 if (devinfo
->gen
< 7) {
3338 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3340 ibld
.MOV(imm
, inst
->src
[1]);
3341 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3343 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3346 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3347 * do 32-bit integer multiplication in one instruction, but instead
3348 * must do a sequence (which actually calculates a 64-bit result):
3350 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3351 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3352 * mov(8) g2<1>D acc0<8,8,1>D
3354 * But on Gen > 6, the ability to use second accumulator register
3355 * (acc1) for non-float data types was removed, preventing a simple
3356 * implementation in SIMD16. A 16-channel result can be calculated by
3357 * executing the three instructions twice in SIMD8, once with quarter
3358 * control of 1Q for the first eight channels and again with 2Q for
3359 * the second eight channels.
3361 * Which accumulator register is implicitly accessed (by AccWrEnable
3362 * for instance) is determined by the quarter control. Unfortunately
3363 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3364 * implicit accumulator access by an instruction with 2Q will access
3365 * acc1 regardless of whether the data type is usable in acc1.
3367 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3368 * integer data types.
3370 * Since we only want the low 32-bits of the result, we can do two
3371 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3372 * adjust the high result and add them (like the mach is doing):
3374 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3375 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3376 * shl(8) g9<1>D g8<8,8,1>D 16D
3377 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3379 * We avoid the shl instruction by realizing that we only want to add
3380 * the low 16-bits of the "high" result to the high 16-bits of the
3381 * "low" result and using proper regioning on the add:
3383 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3384 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3385 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3387 * Since it does not use the (single) accumulator register, we can
3388 * schedule multi-component multiplications much better.
3391 fs_reg orig_dst
= inst
->dst
;
3392 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3393 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3396 fs_reg low
= inst
->dst
;
3397 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3400 if (devinfo
->gen
>= 7) {
3401 fs_reg src1_0_w
= inst
->src
[1];
3402 fs_reg src1_1_w
= inst
->src
[1];
3404 if (inst
->src
[1].file
== IMM
) {
3405 src1_0_w
.ud
&= 0xffff;
3408 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3409 if (src1_0_w
.stride
!= 0) {
3410 assert(src1_0_w
.stride
== 1);
3411 src1_0_w
.stride
= 2;
3414 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3415 if (src1_1_w
.stride
!= 0) {
3416 assert(src1_1_w
.stride
== 1);
3417 src1_1_w
.stride
= 2;
3419 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3421 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3422 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3424 fs_reg src0_0_w
= inst
->src
[0];
3425 fs_reg src0_1_w
= inst
->src
[0];
3427 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3428 if (src0_0_w
.stride
!= 0) {
3429 assert(src0_0_w
.stride
== 1);
3430 src0_0_w
.stride
= 2;
3433 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3434 if (src0_1_w
.stride
!= 0) {
3435 assert(src0_1_w
.stride
== 1);
3436 src0_1_w
.stride
= 2;
3438 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3440 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3441 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3444 fs_reg dst
= inst
->dst
;
3445 dst
.type
= BRW_REGISTER_TYPE_UW
;
3446 dst
.subreg_offset
= 2;
3449 high
.type
= BRW_REGISTER_TYPE_UW
;
3452 low
.type
= BRW_REGISTER_TYPE_UW
;
3453 low
.subreg_offset
= 2;
3456 ibld
.ADD(dst
, low
, high
);
3458 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3459 set_condmod(inst
->conditional_mod
,
3460 ibld
.MOV(orig_dst
, inst
->dst
));
3464 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3465 /* Should have been lowered to 8-wide. */
3466 assert(inst
->exec_size
<= 8);
3467 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3469 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3470 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3472 if (devinfo
->gen
>= 8) {
3473 /* Until Gen8, integer multiplies read 32-bits from one source,
3474 * and 16-bits from the other, and relying on the MACH instruction
3475 * to generate the high bits of the result.
3477 * On Gen8, the multiply instruction does a full 32x32-bit
3478 * multiply, but in order to do a 64-bit multiply we can simulate
3479 * the previous behavior and then use a MACH instruction.
3481 * FINISHME: Don't use source modifiers on src1.
3483 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3484 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3485 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3486 mul
->src
[1].stride
*= 2;
3488 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3489 inst
->force_sechalf
) {
3490 /* Among other things the quarter control bits influence which
3491 * accumulator register is used by the hardware for instructions
3492 * that access the accumulator implicitly (e.g. MACH). A
3493 * second-half instruction would normally map to acc1, which
3494 * doesn't exist on Gen7 and up (the hardware does emulate it for
3495 * floating-point instructions *only* by taking advantage of the
3496 * extra precision of acc0 not normally used for floating point
3499 * HSW and up are careful enough not to try to access an
3500 * accumulator register that doesn't exist, but on earlier Gen7
3501 * hardware we need to make sure that the quarter control bits are
3502 * zero to avoid non-deterministic behaviour and emit an extra MOV
3503 * to get the result masked correctly according to the current
3506 mach
->force_sechalf
= false;
3507 mach
->force_writemask_all
= true;
3508 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3509 ibld
.MOV(inst
->dst
, mach
->dst
);
3515 inst
->remove(block
);
3520 invalidate_live_intervals();
3526 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3527 fs_reg
*dst
, fs_reg color
, unsigned components
)
3529 if (key
->clamp_fragment_color
) {
3530 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3531 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3533 for (unsigned i
= 0; i
< components
; i
++)
3535 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3540 for (unsigned i
= 0; i
< components
; i
++)
3541 dst
[i
] = offset(color
, bld
, i
);
3545 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3546 const brw_wm_prog_data
*prog_data
,
3547 const brw_wm_prog_key
*key
,
3548 const fs_visitor::thread_payload
&payload
)
3550 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3551 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3552 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3553 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3554 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3555 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3556 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3557 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3558 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3559 const unsigned components
=
3560 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3562 /* We can potentially have a message length of up to 15, so we have to set
3563 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3566 int header_size
= 2, payload_header_size
;
3567 unsigned length
= 0;
3569 /* From the Sandy Bridge PRM, volume 4, page 198:
3571 * "Dispatched Pixel Enables. One bit per pixel indicating
3572 * which pixels were originally enabled when the thread was
3573 * dispatched. This field is only required for the end-of-
3574 * thread message and on all dual-source messages."
3576 if (devinfo
->gen
>= 6 &&
3577 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3578 color1
.file
== BAD_FILE
&&
3579 key
->nr_color_regions
== 1) {
3583 if (header_size
!= 0) {
3584 assert(header_size
== 2);
3585 /* Allocate 2 registers for a header */
3589 if (payload
.aa_dest_stencil_reg
) {
3590 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3591 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3592 .MOV(sources
[length
],
3593 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3597 if (prog_data
->uses_omask
) {
3598 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3599 BRW_REGISTER_TYPE_UD
);
3601 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3602 * relevant. Since it's unsigned single words one vgrf is always
3603 * 16-wide, but only the lower or higher 8 channels will be used by the
3604 * hardware when doing a SIMD8 write depending on whether we have
3605 * selected the subspans for the first or second half respectively.
3607 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3608 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3609 sample_mask
.stride
*= 2;
3611 bld
.exec_all().annotate("FB write oMask")
3612 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3613 inst
->force_sechalf
),
3618 payload_header_size
= length
;
3620 if (src0_alpha
.file
!= BAD_FILE
) {
3621 /* FIXME: This is being passed at the wrong location in the payload and
3622 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3623 * It's supposed to be immediately before oMask but there seems to be no
3624 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3625 * requires header sources to form a contiguous segment at the beginning
3626 * of the message and src0_alpha has per-channel semantics.
3628 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3632 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3635 if (color1
.file
!= BAD_FILE
) {
3636 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3640 if (src_depth
.file
!= BAD_FILE
) {
3641 sources
[length
] = src_depth
;
3645 if (dst_depth
.file
!= BAD_FILE
) {
3646 sources
[length
] = dst_depth
;
3650 if (src_stencil
.file
!= BAD_FILE
) {
3651 assert(devinfo
->gen
>= 9);
3652 assert(bld
.dispatch_width() != 16);
3654 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3655 * available on gen9+. As such it's impossible to have both enabled at the
3656 * same time and therefore length cannot overrun the array.
3658 assert(length
< 15);
3660 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3661 bld
.exec_all().annotate("FB write OS")
3662 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3663 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3668 if (devinfo
->gen
>= 7) {
3669 /* Send from the GRF */
3670 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3671 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3672 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3673 load
->dst
= payload
;
3675 inst
->src
[0] = payload
;
3676 inst
->resize_sources(1);
3677 inst
->base_mrf
= -1;
3679 /* Send from the MRF */
3680 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3681 sources
, length
, payload_header_size
);
3683 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3684 * will do this for us if we just give it a COMPR4 destination.
3686 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3687 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3689 inst
->resize_sources(0);
3693 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3694 inst
->mlen
= load
->regs_written
;
3695 inst
->header_size
= header_size
;
3699 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3700 const fs_reg
&coordinate
,
3701 const fs_reg
&shadow_c
,
3702 const fs_reg
&lod
, const fs_reg
&lod2
,
3703 const fs_reg
&surface
,
3704 const fs_reg
&sampler
,
3705 unsigned coord_components
,
3706 unsigned grad_components
)
3708 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3709 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3710 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3711 fs_reg msg_end
= msg_begin
;
3714 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3716 for (unsigned i
= 0; i
< coord_components
; i
++)
3717 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3718 offset(coordinate
, bld
, i
));
3720 msg_end
= offset(msg_end
, bld
, coord_components
);
3722 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3723 * require all three components to be present and zero if they are unused.
3725 if (coord_components
> 0 &&
3726 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3727 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3728 for (unsigned i
= coord_components
; i
< 3; i
++)
3729 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3731 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3734 if (op
== SHADER_OPCODE_TXD
) {
3735 /* TXD unsupported in SIMD16 mode. */
3736 assert(bld
.dispatch_width() == 8);
3738 /* the slots for u and v are always present, but r is optional */
3739 if (coord_components
< 2)
3740 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3743 * dPdx = dudx, dvdx, drdx
3744 * dPdy = dudy, dvdy, drdy
3746 * 1-arg: Does not exist.
3748 * 2-arg: dudx dvdx dudy dvdy
3749 * dPdx.x dPdx.y dPdy.x dPdy.y
3752 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3753 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3754 * m5 m6 m7 m8 m9 m10
3756 for (unsigned i
= 0; i
< grad_components
; i
++)
3757 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3759 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3761 for (unsigned i
= 0; i
< grad_components
; i
++)
3762 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3764 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3768 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3769 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3771 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3772 bld
.dispatch_width() == 16);
3774 const brw_reg_type type
=
3775 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3776 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3777 bld
.MOV(retype(msg_end
, type
), lod
);
3778 msg_end
= offset(msg_end
, bld
, 1);
3781 if (shadow_c
.file
!= BAD_FILE
) {
3782 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3783 /* There's no plain shadow compare message, so we use shadow
3784 * compare with a bias of 0.0.
3786 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3787 msg_end
= offset(msg_end
, bld
, 1);
3790 bld
.MOV(msg_end
, shadow_c
);
3791 msg_end
= offset(msg_end
, bld
, 1);
3795 inst
->src
[0] = reg_undef
;
3796 inst
->src
[1] = surface
;
3797 inst
->src
[2] = sampler
;
3798 inst
->resize_sources(3);
3799 inst
->base_mrf
= msg_begin
.nr
;
3800 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3801 inst
->header_size
= 1;
3805 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3807 const fs_reg
&shadow_c
,
3808 fs_reg lod
, fs_reg lod2
,
3809 const fs_reg
&sample_index
,
3810 const fs_reg
&surface
,
3811 const fs_reg
&sampler
,
3812 const fs_reg
&offset_value
,
3813 unsigned coord_components
,
3814 unsigned grad_components
)
3816 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3817 fs_reg msg_coords
= message
;
3818 unsigned header_size
= 0;
3820 if (offset_value
.file
!= BAD_FILE
) {
3821 /* The offsets set up by the visitor are in the m1 header, so we can't
3828 for (unsigned i
= 0; i
< coord_components
; i
++) {
3829 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3830 coordinate
= offset(coordinate
, bld
, 1);
3832 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3833 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3835 if (shadow_c
.file
!= BAD_FILE
) {
3836 fs_reg msg_shadow
= msg_lod
;
3837 bld
.MOV(msg_shadow
, shadow_c
);
3838 msg_lod
= offset(msg_shadow
, bld
, 1);
3843 case SHADER_OPCODE_TXL
:
3845 bld
.MOV(msg_lod
, lod
);
3846 msg_end
= offset(msg_lod
, bld
, 1);
3848 case SHADER_OPCODE_TXD
:
3851 * dPdx = dudx, dvdx, drdx
3852 * dPdy = dudy, dvdy, drdy
3854 * Load up these values:
3855 * - dudx dudy dvdx dvdy drdx drdy
3856 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3859 for (unsigned i
= 0; i
< grad_components
; i
++) {
3860 bld
.MOV(msg_end
, lod
);
3861 lod
= offset(lod
, bld
, 1);
3862 msg_end
= offset(msg_end
, bld
, 1);
3864 bld
.MOV(msg_end
, lod2
);
3865 lod2
= offset(lod2
, bld
, 1);
3866 msg_end
= offset(msg_end
, bld
, 1);
3869 case SHADER_OPCODE_TXS
:
3870 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3871 bld
.MOV(msg_lod
, lod
);
3872 msg_end
= offset(msg_lod
, bld
, 1);
3874 case SHADER_OPCODE_TXF
:
3875 msg_lod
= offset(msg_coords
, bld
, 3);
3876 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3877 msg_end
= offset(msg_lod
, bld
, 1);
3879 case SHADER_OPCODE_TXF_CMS
:
3880 msg_lod
= offset(msg_coords
, bld
, 3);
3882 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3884 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3885 msg_end
= offset(msg_lod
, bld
, 2);
3892 inst
->src
[0] = reg_undef
;
3893 inst
->src
[1] = surface
;
3894 inst
->src
[2] = sampler
;
3895 inst
->resize_sources(3);
3896 inst
->base_mrf
= message
.nr
;
3897 inst
->mlen
= msg_end
.nr
- message
.nr
;
3898 inst
->header_size
= header_size
;
3900 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3901 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3905 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3907 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3910 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3914 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3916 const fs_reg
&shadow_c
,
3917 fs_reg lod
, fs_reg lod2
,
3918 const fs_reg
&sample_index
,
3920 const fs_reg
&surface
,
3921 const fs_reg
&sampler
,
3922 fs_reg offset_value
,
3923 unsigned coord_components
,
3924 unsigned grad_components
)
3926 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3927 int reg_width
= bld
.dispatch_width() / 8;
3928 unsigned header_size
= 0, length
= 0;
3929 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3930 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3931 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3933 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3934 offset_value
.file
!= BAD_FILE
||
3935 is_high_sampler(devinfo
, sampler
)) {
3936 /* For general texture offsets (no txf workaround), we need a header to
3937 * put them in. Note that we're only reserving space for it in the
3938 * message payload as it will be initialized implicitly by the
3941 * TG4 needs to place its channel select in the header, for interaction
3942 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3943 * larger sampler numbers we need to offset the Sampler State Pointer in
3947 sources
[0] = fs_reg();
3951 if (shadow_c
.file
!= BAD_FILE
) {
3952 bld
.MOV(sources
[length
], shadow_c
);
3956 bool coordinate_done
= false;
3958 /* The sampler can only meaningfully compute LOD for fragment shader
3959 * messages. For all other stages, we change the opcode to TXL and
3960 * hardcode the LOD to 0.
3962 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3963 op
== SHADER_OPCODE_TEX
) {
3964 op
= SHADER_OPCODE_TXL
;
3965 lod
= brw_imm_f(0.0f
);
3968 /* Set up the LOD info */
3971 case SHADER_OPCODE_TXL
:
3972 bld
.MOV(sources
[length
], lod
);
3975 case SHADER_OPCODE_TXD
:
3976 /* TXD should have been lowered in SIMD16 mode. */
3977 assert(bld
.dispatch_width() == 8);
3979 /* Load dPdx and the coordinate together:
3980 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3982 for (unsigned i
= 0; i
< coord_components
; i
++) {
3983 bld
.MOV(sources
[length
], coordinate
);
3984 coordinate
= offset(coordinate
, bld
, 1);
3987 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3988 * only derivatives for (u, v, r).
3990 if (i
< grad_components
) {
3991 bld
.MOV(sources
[length
], lod
);
3992 lod
= offset(lod
, bld
, 1);
3995 bld
.MOV(sources
[length
], lod2
);
3996 lod2
= offset(lod2
, bld
, 1);
4001 coordinate_done
= true;
4003 case SHADER_OPCODE_TXS
:
4004 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4007 case SHADER_OPCODE_TXF
:
4008 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4009 * On Gen9 they are u, v, lod, r
4011 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4012 coordinate
= offset(coordinate
, bld
, 1);
4015 if (devinfo
->gen
>= 9) {
4016 if (coord_components
>= 2) {
4017 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4018 coordinate
= offset(coordinate
, bld
, 1);
4023 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4026 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
4027 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4028 coordinate
= offset(coordinate
, bld
, 1);
4032 coordinate_done
= true;
4034 case SHADER_OPCODE_TXF_CMS
:
4035 case SHADER_OPCODE_TXF_CMS_W
:
4036 case SHADER_OPCODE_TXF_UMS
:
4037 case SHADER_OPCODE_TXF_MCS
:
4038 if (op
== SHADER_OPCODE_TXF_UMS
||
4039 op
== SHADER_OPCODE_TXF_CMS
||
4040 op
== SHADER_OPCODE_TXF_CMS_W
) {
4041 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4045 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4046 /* Data from the multisample control surface. */
4047 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4050 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4053 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4054 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4057 offset(mcs
, bld
, 1));
4062 /* There is no offsetting for this message; just copy in the integer
4063 * texture coordinates.
4065 for (unsigned i
= 0; i
< coord_components
; i
++) {
4066 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4067 coordinate
= offset(coordinate
, bld
, 1);
4071 coordinate_done
= true;
4073 case SHADER_OPCODE_TG4_OFFSET
:
4074 /* gather4_po_c should have been lowered in SIMD16 mode. */
4075 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4077 /* More crazy intermixing */
4078 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
4079 bld
.MOV(sources
[length
], coordinate
);
4080 coordinate
= offset(coordinate
, bld
, 1);
4084 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
4085 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
4086 offset_value
= offset(offset_value
, bld
, 1);
4090 if (coord_components
== 3) { /* r if present */
4091 bld
.MOV(sources
[length
], coordinate
);
4092 coordinate
= offset(coordinate
, bld
, 1);
4096 coordinate_done
= true;
4102 /* Set up the coordinate (except for cases where it was done above) */
4103 if (!coordinate_done
) {
4104 for (unsigned i
= 0; i
< coord_components
; i
++) {
4105 bld
.MOV(sources
[length
], coordinate
);
4106 coordinate
= offset(coordinate
, bld
, 1);
4113 mlen
= length
* reg_width
- header_size
;
4115 mlen
= length
* reg_width
;
4117 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4118 BRW_REGISTER_TYPE_F
);
4119 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4121 /* Generate the SEND. */
4123 inst
->src
[0] = src_payload
;
4124 inst
->src
[1] = surface
;
4125 inst
->src
[2] = sampler
;
4126 inst
->resize_sources(3);
4127 inst
->base_mrf
= -1;
4129 inst
->header_size
= header_size
;
4131 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4132 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4136 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4138 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4139 const fs_reg
&coordinate
= inst
->src
[0];
4140 const fs_reg
&shadow_c
= inst
->src
[1];
4141 const fs_reg
&lod
= inst
->src
[2];
4142 const fs_reg
&lod2
= inst
->src
[3];
4143 const fs_reg
&sample_index
= inst
->src
[4];
4144 const fs_reg
&mcs
= inst
->src
[5];
4145 const fs_reg
&surface
= inst
->src
[6];
4146 const fs_reg
&sampler
= inst
->src
[7];
4147 const fs_reg
&offset_value
= inst
->src
[8];
4148 assert(inst
->src
[9].file
== IMM
&& inst
->src
[10].file
== IMM
);
4149 const unsigned coord_components
= inst
->src
[9].ud
;
4150 const unsigned grad_components
= inst
->src
[10].ud
;
4152 if (devinfo
->gen
>= 7) {
4153 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4154 shadow_c
, lod
, lod2
, sample_index
,
4155 mcs
, surface
, sampler
, offset_value
,
4156 coord_components
, grad_components
);
4157 } else if (devinfo
->gen
>= 5) {
4158 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4159 shadow_c
, lod
, lod2
, sample_index
,
4160 surface
, sampler
, offset_value
,
4161 coord_components
, grad_components
);
4163 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4164 shadow_c
, lod
, lod2
,
4166 coord_components
, grad_components
);
4171 * Initialize the header present in some typed and untyped surface
4175 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4177 fs_builder ubld
= bld
.exec_all().group(8, 0);
4178 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4179 ubld
.MOV(dst
, brw_imm_d(0));
4180 ubld
.MOV(component(dst
, 7), sample_mask
);
4185 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4186 const fs_reg
&sample_mask
)
4188 /* Get the logical send arguments. */
4189 const fs_reg
&addr
= inst
->src
[0];
4190 const fs_reg
&src
= inst
->src
[1];
4191 const fs_reg
&surface
= inst
->src
[2];
4192 const UNUSED fs_reg
&dims
= inst
->src
[3];
4193 const fs_reg
&arg
= inst
->src
[4];
4195 /* Calculate the total number of components of the payload. */
4196 const unsigned addr_sz
= inst
->components_read(0);
4197 const unsigned src_sz
= inst
->components_read(1);
4198 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4199 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4201 /* Allocate space for the payload. */
4202 fs_reg
*const components
= new fs_reg
[sz
];
4203 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4206 /* Construct the payload. */
4208 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4210 for (unsigned i
= 0; i
< addr_sz
; i
++)
4211 components
[n
++] = offset(addr
, bld
, i
);
4213 for (unsigned i
= 0; i
< src_sz
; i
++)
4214 components
[n
++] = offset(src
, bld
, i
);
4216 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4218 /* Update the original instruction. */
4220 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4221 inst
->header_size
= header_sz
;
4223 inst
->src
[0] = payload
;
4224 inst
->src
[1] = surface
;
4226 inst
->resize_sources(3);
4228 delete[] components
;
4232 fs_visitor::lower_logical_sends()
4234 bool progress
= false;
4236 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4237 const fs_builder
ibld(this, block
, inst
);
4239 switch (inst
->opcode
) {
4240 case FS_OPCODE_FB_WRITE_LOGICAL
:
4241 assert(stage
== MESA_SHADER_FRAGMENT
);
4242 lower_fb_write_logical_send(ibld
, inst
,
4243 (const brw_wm_prog_data
*)prog_data
,
4244 (const brw_wm_prog_key
*)key
,
4248 case SHADER_OPCODE_TEX_LOGICAL
:
4249 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4252 case SHADER_OPCODE_TXD_LOGICAL
:
4253 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4256 case SHADER_OPCODE_TXF_LOGICAL
:
4257 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4260 case SHADER_OPCODE_TXL_LOGICAL
:
4261 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4264 case SHADER_OPCODE_TXS_LOGICAL
:
4265 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4268 case FS_OPCODE_TXB_LOGICAL
:
4269 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4272 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4273 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4276 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4277 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4280 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4281 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4284 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4285 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4288 case SHADER_OPCODE_LOD_LOGICAL
:
4289 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4292 case SHADER_OPCODE_TG4_LOGICAL
:
4293 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4296 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4297 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4300 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4301 lower_surface_logical_send(ibld
, inst
,
4302 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4306 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4307 lower_surface_logical_send(ibld
, inst
,
4308 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4309 ibld
.sample_mask_reg());
4312 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4313 lower_surface_logical_send(ibld
, inst
,
4314 SHADER_OPCODE_UNTYPED_ATOMIC
,
4315 ibld
.sample_mask_reg());
4318 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4319 lower_surface_logical_send(ibld
, inst
,
4320 SHADER_OPCODE_TYPED_SURFACE_READ
,
4324 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4325 lower_surface_logical_send(ibld
, inst
,
4326 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4327 ibld
.sample_mask_reg());
4330 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4331 lower_surface_logical_send(ibld
, inst
,
4332 SHADER_OPCODE_TYPED_ATOMIC
,
4333 ibld
.sample_mask_reg());
4344 invalidate_live_intervals();
4350 * Get the closest native SIMD width supported by the hardware for instruction
4351 * \p inst. The instruction will be left untouched by
4352 * fs_visitor::lower_simd_width() if the returned value is equal to the
4353 * original execution size.
4356 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4357 const fs_inst
*inst
)
4359 switch (inst
->opcode
) {
4360 case BRW_OPCODE_MOV
:
4361 case BRW_OPCODE_SEL
:
4362 case BRW_OPCODE_NOT
:
4363 case BRW_OPCODE_AND
:
4365 case BRW_OPCODE_XOR
:
4366 case BRW_OPCODE_SHR
:
4367 case BRW_OPCODE_SHL
:
4368 case BRW_OPCODE_ASR
:
4369 case BRW_OPCODE_CMP
:
4370 case BRW_OPCODE_CMPN
:
4371 case BRW_OPCODE_CSEL
:
4372 case BRW_OPCODE_F32TO16
:
4373 case BRW_OPCODE_F16TO32
:
4374 case BRW_OPCODE_BFREV
:
4375 case BRW_OPCODE_BFE
:
4376 case BRW_OPCODE_BFI1
:
4377 case BRW_OPCODE_BFI2
:
4378 case BRW_OPCODE_ADD
:
4379 case BRW_OPCODE_MUL
:
4380 case BRW_OPCODE_AVG
:
4381 case BRW_OPCODE_FRC
:
4382 case BRW_OPCODE_RNDU
:
4383 case BRW_OPCODE_RNDD
:
4384 case BRW_OPCODE_RNDE
:
4385 case BRW_OPCODE_RNDZ
:
4386 case BRW_OPCODE_LZD
:
4387 case BRW_OPCODE_FBH
:
4388 case BRW_OPCODE_FBL
:
4389 case BRW_OPCODE_CBIT
:
4390 case BRW_OPCODE_SAD2
:
4391 case BRW_OPCODE_MAD
:
4392 case BRW_OPCODE_LRP
:
4393 case SHADER_OPCODE_RCP
:
4394 case SHADER_OPCODE_RSQ
:
4395 case SHADER_OPCODE_SQRT
:
4396 case SHADER_OPCODE_EXP2
:
4397 case SHADER_OPCODE_LOG2
:
4398 case SHADER_OPCODE_POW
:
4399 case SHADER_OPCODE_INT_QUOTIENT
:
4400 case SHADER_OPCODE_INT_REMAINDER
:
4401 case SHADER_OPCODE_SIN
:
4402 case SHADER_OPCODE_COS
: {
4403 /* According to the PRMs:
4404 * "A. In Direct Addressing mode, a source cannot span more than 2
4405 * adjacent GRF registers.
4406 * B. A destination cannot span more than 2 adjacent GRF registers."
4408 * Look for the source or destination with the largest register region
4409 * which is the one that is going to limit the overal execution size of
4410 * the instruction due to this rule.
4412 unsigned reg_count
= inst
->regs_written
;
4414 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4415 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4417 /* Calculate the maximum execution size of the instruction based on the
4418 * factor by which it goes over the hardware limit of 2 GRFs.
4420 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4422 case SHADER_OPCODE_MULH
:
4423 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4424 * is 8-wide on Gen7+.
4426 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4428 case FS_OPCODE_FB_WRITE_LOGICAL
:
4429 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4432 assert(devinfo
->gen
!= 6 ||
4433 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4434 inst
->exec_size
== 8);
4435 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4436 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4437 8 : inst
->exec_size
);
4439 case SHADER_OPCODE_TXD_LOGICAL
:
4440 /* TXD is unsupported in SIMD16 mode. */
4443 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4444 /* gather4_po_c is unsupported in SIMD16 mode. */
4445 const fs_reg
&shadow_c
= inst
->src
[1];
4446 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4448 case SHADER_OPCODE_TXL_LOGICAL
:
4449 case FS_OPCODE_TXB_LOGICAL
: {
4450 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4451 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4452 * mode because the message exceeds the maximum length of 11.
4454 const fs_reg
&shadow_c
= inst
->src
[1];
4455 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4457 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4460 return inst
->exec_size
;
4462 case SHADER_OPCODE_TXF_LOGICAL
:
4463 case SHADER_OPCODE_TXS_LOGICAL
:
4464 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4465 * messages. Use SIMD16 instead.
4467 if (devinfo
->gen
== 4)
4470 return inst
->exec_size
;
4472 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4473 /* This opcode can take up to 6 arguments which means that in some
4474 * circumstances it can end up with a message that is too long in SIMD16
4477 const unsigned coord_components
= inst
->src
[8].ud
;
4478 /* First three arguments are the sample index and the two arguments for
4481 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4484 return inst
->exec_size
;
4487 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4488 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4489 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4492 case SHADER_OPCODE_MOV_INDIRECT
:
4493 /* Prior to Broadwell, we only have 8 address subregisters */
4494 return devinfo
->gen
< 8 ? 8 : inst
->exec_size
;
4497 return inst
->exec_size
;
4502 * The \p rows array of registers represents a \p num_rows by \p num_columns
4503 * matrix in row-major order, write it in column-major order into the register
4504 * passed as destination. \p stride gives the separation between matrix
4505 * elements in the input in fs_builder::dispatch_width() units.
4508 emit_transpose(const fs_builder
&bld
,
4509 const fs_reg
&dst
, const fs_reg
*rows
,
4510 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4512 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4514 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4515 for (unsigned j
= 0; j
< num_rows
; ++j
)
4516 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4519 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4521 delete[] components
;
4525 fs_visitor::lower_simd_width()
4527 bool progress
= false;
4529 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4530 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4532 if (lower_width
!= inst
->exec_size
) {
4533 /* Builder matching the original instruction. We may also need to
4534 * emit an instruction of width larger than the original, set the
4535 * execution size of the builder to the highest of both for now so
4536 * we're sure that both cases can be handled.
4538 const fs_builder ibld
= bld
.at(block
, inst
)
4539 .exec_all(inst
->force_writemask_all
)
4540 .group(MAX2(inst
->exec_size
, lower_width
),
4541 inst
->force_sechalf
);
4543 /* Split the copies in chunks of the execution width of either the
4544 * original or the lowered instruction, whichever is lower.
4546 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4547 const unsigned n
= inst
->exec_size
/ copy_width
;
4548 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4549 inst
->dst
.component_size(inst
->exec_size
);
4552 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4553 !inst
->writes_accumulator
&& !inst
->mlen
);
4555 for (unsigned i
= 0; i
< n
; i
++) {
4556 /* Emit a copy of the original instruction with the lowered width.
4557 * If the EOT flag was set throw it away except for the last
4558 * instruction to avoid killing the thread prematurely.
4560 fs_inst split_inst
= *inst
;
4561 split_inst
.exec_size
= lower_width
;
4562 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4564 /* Select the correct channel enables for the i-th group, then
4565 * transform the sources and destination and emit the lowered
4568 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4570 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4571 if (inst
->src
[j
].file
!= BAD_FILE
&&
4572 !is_uniform(inst
->src
[j
])) {
4573 /* Get the i-th copy_width-wide chunk of the source. */
4574 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4575 const unsigned src_size
= inst
->components_read(j
);
4577 /* Use a trivial transposition to copy one every n
4578 * copy_width-wide components of the register into a
4579 * temporary passed as source to the lowered instruction.
4581 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4582 emit_transpose(lbld
.group(copy_width
, 0),
4583 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4587 if (inst
->regs_written
) {
4588 /* Allocate enough space to hold the result of the lowered
4589 * instruction and fix up the number of registers written.
4591 split_inst
.dst
= dsts
[i
] =
4592 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4593 split_inst
.regs_written
=
4594 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4598 lbld
.emit(split_inst
);
4601 if (inst
->regs_written
) {
4602 /* Distance between useful channels in the temporaries, skipping
4603 * garbage if the lowered instruction is wider than the original.
4605 const unsigned m
= lower_width
/ copy_width
;
4607 /* Interleave the components of the result from the lowered
4608 * instructions. We need to set exec_all() when copying more than
4609 * one half per component, because LOAD_PAYLOAD (in terms of which
4610 * emit_transpose is implemented) can only use the same channel
4611 * enable signals for all of its non-header sources.
4613 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4614 .group(copy_width
, 0),
4615 inst
->dst
, dsts
, n
, dst_size
, m
);
4618 inst
->remove(block
);
4624 invalidate_live_intervals();
4630 fs_visitor::dump_instructions()
4632 dump_instructions(NULL
);
4636 fs_visitor::dump_instructions(const char *name
)
4638 FILE *file
= stderr
;
4639 if (name
&& geteuid() != 0) {
4640 file
= fopen(name
, "w");
4646 calculate_register_pressure();
4647 int ip
= 0, max_pressure
= 0;
4648 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4649 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4650 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4651 dump_instruction(inst
, file
);
4654 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4657 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4658 fprintf(file
, "%4d: ", ip
++);
4659 dump_instruction(inst
, file
);
4663 if (file
!= stderr
) {
4669 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4671 dump_instruction(be_inst
, stderr
);
4675 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4677 fs_inst
*inst
= (fs_inst
*)be_inst
;
4679 if (inst
->predicate
) {
4680 fprintf(file
, "(%cf0.%d) ",
4681 inst
->predicate_inverse
? '-' : '+',
4685 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4687 fprintf(file
, ".sat");
4688 if (inst
->conditional_mod
) {
4689 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4690 if (!inst
->predicate
&&
4691 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4692 inst
->opcode
!= BRW_OPCODE_IF
&&
4693 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4694 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4697 fprintf(file
, "(%d) ", inst
->exec_size
);
4700 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4703 switch (inst
->dst
.file
) {
4705 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4706 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4707 inst
->dst
.subreg_offset
)
4708 fprintf(file
, "+%d.%d",
4709 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4712 fprintf(file
, "g%d", inst
->dst
.nr
);
4715 fprintf(file
, "m%d", inst
->dst
.nr
);
4718 fprintf(file
, "(null)");
4721 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4724 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4727 switch (inst
->dst
.nr
) {
4729 fprintf(file
, "null");
4731 case BRW_ARF_ADDRESS
:
4732 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4734 case BRW_ARF_ACCUMULATOR
:
4735 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4738 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4741 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4744 if (inst
->dst
.subnr
)
4745 fprintf(file
, "+%d", inst
->dst
.subnr
);
4748 unreachable("not reached");
4750 if (inst
->dst
.stride
!= 1)
4751 fprintf(file
, "<%u>", inst
->dst
.stride
);
4752 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4754 for (int i
= 0; i
< inst
->sources
; i
++) {
4755 if (inst
->src
[i
].negate
)
4757 if (inst
->src
[i
].abs
)
4759 switch (inst
->src
[i
].file
) {
4761 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4762 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4763 inst
->src
[i
].subreg_offset
)
4764 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4765 inst
->src
[i
].subreg_offset
);
4768 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4771 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4774 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4777 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4778 if (inst
->src
[i
].subreg_offset
) {
4779 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4780 inst
->src
[i
].subreg_offset
);
4784 fprintf(file
, "(null)");
4787 switch (inst
->src
[i
].type
) {
4788 case BRW_REGISTER_TYPE_F
:
4789 fprintf(file
, "%ff", inst
->src
[i
].f
);
4791 case BRW_REGISTER_TYPE_W
:
4792 case BRW_REGISTER_TYPE_D
:
4793 fprintf(file
, "%dd", inst
->src
[i
].d
);
4795 case BRW_REGISTER_TYPE_UW
:
4796 case BRW_REGISTER_TYPE_UD
:
4797 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4799 case BRW_REGISTER_TYPE_VF
:
4800 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4801 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4802 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4803 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4804 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4807 fprintf(file
, "???");
4812 switch (inst
->src
[i
].nr
) {
4814 fprintf(file
, "null");
4816 case BRW_ARF_ADDRESS
:
4817 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4819 case BRW_ARF_ACCUMULATOR
:
4820 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4823 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4826 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4829 if (inst
->src
[i
].subnr
)
4830 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4833 if (inst
->src
[i
].abs
)
4836 if (inst
->src
[i
].file
!= IMM
) {
4838 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
4839 unsigned hstride
= inst
->src
[i
].hstride
;
4840 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
4842 stride
= inst
->src
[i
].stride
;
4845 fprintf(file
, "<%u>", stride
);
4847 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4850 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4851 fprintf(file
, ", ");
4856 if (inst
->force_writemask_all
)
4857 fprintf(file
, "NoMask ");
4859 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4860 if (inst
->force_sechalf
)
4861 fprintf(file
, "2ndhalf ");
4863 fprintf(file
, "1sthalf ");
4866 fprintf(file
, "\n");
4870 * Possibly returns an instruction that set up @param reg.
4872 * Sometimes we want to take the result of some expression/variable
4873 * dereference tree and rewrite the instruction generating the result
4874 * of the tree. When processing the tree, we know that the
4875 * instructions generated are all writing temporaries that are dead
4876 * outside of this tree. So, if we have some instructions that write
4877 * a temporary, we're free to point that temp write somewhere else.
4879 * Note that this doesn't guarantee that the instruction generated
4880 * only reg -- it might be the size=4 destination of a texture instruction.
4883 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4888 end
->is_partial_write() ||
4889 !reg
.equals(end
->dst
)) {
4897 fs_visitor::setup_payload_gen6()
4900 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4901 unsigned barycentric_interp_modes
=
4902 (stage
== MESA_SHADER_FRAGMENT
) ?
4903 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4905 assert(devinfo
->gen
>= 6);
4907 /* R0-1: masks, pixel X/Y coordinates. */
4908 payload
.num_regs
= 2;
4909 /* R2: only for 32-pixel dispatch.*/
4911 /* R3-26: barycentric interpolation coordinates. These appear in the
4912 * same order that they appear in the brw_wm_barycentric_interp_mode
4913 * enum. Each set of coordinates occupies 2 registers if dispatch width
4914 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4915 * appear if they were enabled using the "Barycentric Interpolation
4916 * Mode" bits in WM_STATE.
4918 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4919 if (barycentric_interp_modes
& (1 << i
)) {
4920 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4921 payload
.num_regs
+= 2;
4922 if (dispatch_width
== 16) {
4923 payload
.num_regs
+= 2;
4928 /* R27: interpolated depth if uses source depth */
4930 payload
.source_depth_reg
= payload
.num_regs
;
4932 if (dispatch_width
== 16) {
4933 /* R28: interpolated depth if not SIMD8. */
4937 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4939 payload
.source_w_reg
= payload
.num_regs
;
4941 if (dispatch_width
== 16) {
4942 /* R30: interpolated W if not SIMD8. */
4947 if (stage
== MESA_SHADER_FRAGMENT
) {
4948 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4949 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4950 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4951 /* R31: MSAA position offsets. */
4952 if (prog_data
->uses_pos_offset
) {
4953 payload
.sample_pos_reg
= payload
.num_regs
;
4958 /* R32: MSAA input coverage mask */
4959 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4960 assert(devinfo
->gen
>= 7);
4961 payload
.sample_mask_in_reg
= payload
.num_regs
;
4963 if (dispatch_width
== 16) {
4964 /* R33: input coverage mask if not SIMD8. */
4969 /* R34-: bary for 32-pixel. */
4970 /* R58-59: interp W for 32-pixel. */
4972 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4973 source_depth_to_render_target
= true;
4978 fs_visitor::setup_vs_payload()
4980 /* R0: thread header, R1: urb handles */
4981 payload
.num_regs
= 2;
4985 * We are building the local ID push constant data using the simplest possible
4986 * method. We simply push the local IDs directly as they should appear in the
4987 * registers for the uvec3 gl_LocalInvocationID variable.
4989 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4990 * registers worth of push constant space.
4992 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4993 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4996 * FINISHME: There are a few easy optimizations to consider.
4998 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4999 * no need for using push constant space for that dimension.
5001 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
5002 * easily use 16-bit words rather than 32-bit dwords in the push constant
5005 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
5006 * conveying the data, and thereby reduce push constant usage.
5010 fs_visitor::setup_gs_payload()
5012 assert(stage
== MESA_SHADER_GEOMETRY
);
5014 struct brw_gs_prog_data
*gs_prog_data
=
5015 (struct brw_gs_prog_data
*) prog_data
;
5016 struct brw_vue_prog_data
*vue_prog_data
=
5017 (struct brw_vue_prog_data
*) prog_data
;
5019 /* R0: thread header, R1: output URB handles */
5020 payload
.num_regs
= 2;
5022 if (gs_prog_data
->include_primitive_id
) {
5023 /* R2: Primitive ID 0..7 */
5027 /* Use a maximum of 32 registers for push-model inputs. */
5028 const unsigned max_push_components
= 32;
5030 /* If pushing our inputs would take too many registers, reduce the URB read
5031 * length (which is in HWords, or 8 registers), and resort to pulling.
5033 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5034 * have to multiply by VerticesIn to obtain the total storage requirement.
5036 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5037 max_push_components
) {
5038 gs_prog_data
->base
.include_vue_handles
= true;
5040 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5041 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5043 vue_prog_data
->urb_read_length
=
5044 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5049 fs_visitor::setup_cs_payload()
5051 assert(devinfo
->gen
>= 7);
5052 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
5054 payload
.num_regs
= 1;
5056 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
5057 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
5058 payload
.local_invocation_id_reg
= payload
.num_regs
;
5059 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
5064 fs_visitor::calculate_register_pressure()
5066 invalidate_live_intervals();
5067 calculate_live_intervals();
5069 unsigned num_instructions
= 0;
5070 foreach_block(block
, cfg
)
5071 num_instructions
+= block
->instructions
.length();
5073 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5075 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5076 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5077 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5082 fs_visitor::optimize()
5084 /* Start by validating the shader we currently have. */
5087 /* bld is the common builder object pointing at the end of the program we
5088 * used to translate it into i965 IR. For the optimization and lowering
5089 * passes coming next, any code added after the end of the program without
5090 * having explicitly called fs_builder::at() clearly points at a mistake.
5091 * Ideally optimization passes wouldn't be part of the visitor so they
5092 * wouldn't have access to bld at all, but they do, so just in case some
5093 * pass forgets to ask for a location explicitly set it to NULL here to
5094 * make it trip. The dispatch width is initialized to a bogus value to
5095 * make sure that optimizations set the execution controls explicitly to
5096 * match the code they are manipulating instead of relying on the defaults.
5098 bld
= fs_builder(this, 64);
5100 assign_constant_locations();
5101 lower_constant_loads();
5105 split_virtual_grfs();
5108 #define OPT(pass, args...) ({ \
5110 bool this_progress = pass(args); \
5112 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5113 char filename[64]; \
5114 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5115 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5117 backend_shader::dump_instructions(filename); \
5122 progress = progress || this_progress; \
5126 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5128 snprintf(filename
, 64, "%s%d-%s-00-start",
5129 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5131 backend_shader::dump_instructions(filename
);
5134 bool progress
= false;
5138 OPT(lower_simd_width
);
5139 OPT(lower_logical_sends
);
5146 OPT(remove_duplicate_mrf_writes
);
5150 OPT(opt_copy_propagate
);
5151 OPT(opt_predicated_break
, this);
5152 OPT(opt_cmod_propagation
);
5153 OPT(dead_code_eliminate
);
5154 OPT(opt_peephole_sel
);
5155 OPT(dead_control_flow_eliminate
, this);
5156 OPT(opt_register_renaming
);
5157 OPT(opt_redundant_discard_jumps
);
5158 OPT(opt_saturate_propagation
);
5159 OPT(opt_zero_samples
);
5160 OPT(register_coalesce
);
5161 OPT(compute_to_mrf
);
5162 OPT(eliminate_find_live_channel
);
5164 OPT(compact_virtual_grfs
);
5169 OPT(opt_sampler_eot
);
5171 if (OPT(lower_load_payload
)) {
5172 split_virtual_grfs();
5173 OPT(register_coalesce
);
5174 OPT(compute_to_mrf
);
5175 OPT(dead_code_eliminate
);
5178 OPT(opt_combine_constants
);
5179 OPT(lower_integer_multiplication
);
5181 lower_uniform_pull_constant_loads();
5187 * Three source instruction must have a GRF/MRF destination register.
5188 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5191 fs_visitor::fixup_3src_null_dest()
5193 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5194 if (inst
->is_3src() && inst
->dst
.is_null()) {
5195 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5202 fs_visitor::allocate_registers()
5204 bool allocated_without_spills
;
5206 static const enum instruction_scheduler_mode pre_modes
[] = {
5208 SCHEDULE_PRE_NON_LIFO
,
5212 /* Try each scheduling heuristic to see if it can successfully register
5213 * allocate without spilling. They should be ordered by decreasing
5214 * performance but increasing likelihood of allocating.
5216 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5217 schedule_instructions(pre_modes
[i
]);
5220 assign_regs_trivial();
5221 allocated_without_spills
= true;
5223 allocated_without_spills
= assign_regs(false);
5225 if (allocated_without_spills
)
5229 if (!allocated_without_spills
) {
5230 /* We assume that any spilling is worse than just dropping back to
5231 * SIMD8. There's probably actually some intermediate point where
5232 * SIMD16 with a couple of spills is still better.
5234 if (dispatch_width
== 16) {
5235 fail("Failure to register allocate. Reduce number of "
5236 "live scalar values to avoid this.");
5238 compiler
->shader_perf_log(log_data
,
5239 "%s shader triggered register spilling. "
5240 "Try reducing the number of live scalar "
5241 "values to improve performance.\n",
5245 /* Since we're out of heuristics, just go spill registers until we
5246 * get an allocation.
5248 while (!assign_regs(true)) {
5254 /* This must come after all optimization and register allocation, since
5255 * it inserts dead code that happens to have side effects, and it does
5256 * so based on the actual physical registers in use.
5258 insert_gen4_send_dependency_workarounds();
5263 schedule_instructions(SCHEDULE_POST
);
5265 if (last_scratch
> 0)
5266 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5270 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5272 assert(stage
== MESA_SHADER_VERTEX
);
5276 if (shader_time_index
>= 0)
5277 emit_shader_time_begin();
5284 compute_clip_distance(clip_planes
);
5288 if (shader_time_index
>= 0)
5289 emit_shader_time_end();
5295 assign_curb_setup();
5296 assign_vs_urb_setup();
5298 fixup_3src_null_dest();
5299 allocate_registers();
5305 fs_visitor::run_tes()
5307 assert(stage
== MESA_SHADER_TESS_EVAL
);
5309 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
5310 payload
.num_regs
= 5;
5312 if (shader_time_index
>= 0)
5313 emit_shader_time_begin();
5322 if (shader_time_index
>= 0)
5323 emit_shader_time_end();
5329 assign_curb_setup();
5330 assign_tes_urb_setup();
5332 fixup_3src_null_dest();
5333 allocate_registers();
5339 fs_visitor::run_gs()
5341 assert(stage
== MESA_SHADER_GEOMETRY
);
5345 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5347 if (gs_compile
->control_data_header_size_bits
> 0) {
5348 /* Create a VGRF to store accumulated control data bits. */
5349 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5351 /* If we're outputting more than 32 control data bits, then EmitVertex()
5352 * will set control_data_bits to 0 after emitting the first vertex.
5353 * Otherwise, we need to initialize it to 0 here.
5355 if (gs_compile
->control_data_header_size_bits
<= 32) {
5356 const fs_builder abld
= bld
.annotate("initialize control data bits");
5357 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
5361 if (shader_time_index
>= 0)
5362 emit_shader_time_begin();
5366 emit_gs_thread_end();
5368 if (shader_time_index
>= 0)
5369 emit_shader_time_end();
5378 assign_curb_setup();
5379 assign_gs_urb_setup();
5381 fixup_3src_null_dest();
5382 allocate_registers();
5388 fs_visitor::run_fs(bool do_rep_send
)
5390 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5391 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5393 assert(stage
== MESA_SHADER_FRAGMENT
);
5395 if (devinfo
->gen
>= 6)
5396 setup_payload_gen6();
5398 setup_payload_gen4();
5402 } else if (do_rep_send
) {
5403 assert(dispatch_width
== 16);
5404 emit_repclear_shader();
5406 if (shader_time_index
>= 0)
5407 emit_shader_time_begin();
5409 calculate_urb_setup();
5410 if (nir
->info
.inputs_read
> 0) {
5411 if (devinfo
->gen
< 6)
5412 emit_interpolation_setup_gen4();
5414 emit_interpolation_setup_gen6();
5417 /* We handle discards by keeping track of the still-live pixels in f0.1.
5418 * Initialize it with the dispatched pixels.
5420 if (wm_prog_data
->uses_kill
) {
5421 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5422 discard_init
->flag_subreg
= 1;
5425 /* Generate FS IR for main(). (the visitor only descends into
5426 * functions called "main").
5433 if (wm_prog_data
->uses_kill
)
5434 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5436 if (wm_key
->alpha_test_func
)
5441 if (shader_time_index
>= 0)
5442 emit_shader_time_end();
5448 assign_curb_setup();
5451 fixup_3src_null_dest();
5452 allocate_registers();
5458 if (dispatch_width
== 8)
5459 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5461 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5467 fs_visitor::run_cs()
5469 assert(stage
== MESA_SHADER_COMPUTE
);
5473 if (shader_time_index
>= 0)
5474 emit_shader_time_begin();
5481 emit_cs_terminate();
5483 if (shader_time_index
>= 0)
5484 emit_shader_time_end();
5490 assign_curb_setup();
5492 fixup_3src_null_dest();
5493 allocate_registers();
5502 * Return a bitfield where bit n is set if barycentric interpolation mode n
5503 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5506 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5507 bool shade_model_flat
,
5508 bool persample_shading
,
5509 const nir_shader
*shader
)
5511 unsigned barycentric_interp_modes
= 0;
5513 nir_foreach_variable(var
, &shader
->inputs
) {
5514 enum glsl_interp_qualifier interp_qualifier
=
5515 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5516 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5517 bool is_sample
= var
->data
.sample
|| persample_shading
;
5518 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5519 (var
->data
.location
== VARYING_SLOT_COL1
);
5521 /* Ignore WPOS and FACE, because they don't require interpolation. */
5522 if (var
->data
.location
== VARYING_SLOT_POS
||
5523 var
->data
.location
== VARYING_SLOT_FACE
)
5526 /* Determine the set (or sets) of barycentric coordinates needed to
5527 * interpolate this variable. Note that when
5528 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5529 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5530 * for lit pixels, so we need both sets of barycentric coordinates.
5532 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5534 barycentric_interp_modes
|=
5535 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5536 } else if (is_sample
) {
5537 barycentric_interp_modes
|=
5538 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5540 if ((!is_centroid
&& !is_sample
) ||
5541 devinfo
->needs_unlit_centroid_workaround
) {
5542 barycentric_interp_modes
|=
5543 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5545 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5546 (!(shade_model_flat
&& is_gl_Color
) &&
5547 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5549 barycentric_interp_modes
|=
5550 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5551 } else if (is_sample
) {
5552 barycentric_interp_modes
|=
5553 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5555 if ((!is_centroid
&& !is_sample
) ||
5556 devinfo
->needs_unlit_centroid_workaround
) {
5557 barycentric_interp_modes
|=
5558 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5563 return barycentric_interp_modes
;
5567 computed_depth_mode(const nir_shader
*shader
)
5569 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5570 switch (shader
->info
.fs
.depth_layout
) {
5571 case FRAG_DEPTH_LAYOUT_NONE
:
5572 case FRAG_DEPTH_LAYOUT_ANY
:
5573 return BRW_PSCDEPTH_ON
;
5574 case FRAG_DEPTH_LAYOUT_GREATER
:
5575 return BRW_PSCDEPTH_ON_GE
;
5576 case FRAG_DEPTH_LAYOUT_LESS
:
5577 return BRW_PSCDEPTH_ON_LE
;
5578 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5579 return BRW_PSCDEPTH_OFF
;
5582 return BRW_PSCDEPTH_OFF
;
5586 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5588 const struct brw_wm_prog_key
*key
,
5589 struct brw_wm_prog_data
*prog_data
,
5590 const nir_shader
*src_shader
,
5591 struct gl_program
*prog
,
5592 int shader_time_index8
, int shader_time_index16
,
5594 unsigned *final_assembly_size
,
5597 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5598 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5600 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5602 /* key->alpha_test_func means simulating alpha testing via discards,
5603 * so the shader definitely kills pixels.
5605 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5606 prog_data
->uses_omask
=
5607 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5608 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5609 prog_data
->computed_stencil
=
5610 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5612 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5614 prog_data
->barycentric_interp_modes
=
5615 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5617 key
->persample_shading
,
5620 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5621 &prog_data
->base
, prog
, shader
, 8,
5622 shader_time_index8
);
5623 if (!v
.run_fs(false /* do_rep_send */)) {
5625 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5630 cfg_t
*simd16_cfg
= NULL
;
5631 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5632 &prog_data
->base
, prog
, shader
, 16,
5633 shader_time_index16
);
5634 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5635 if (!v
.simd16_unsupported
) {
5636 /* Try a SIMD16 compile */
5637 v2
.import_uniforms(&v
);
5638 if (!v2
.run_fs(use_rep_send
)) {
5639 compiler
->shader_perf_log(log_data
,
5640 "SIMD16 shader failed to compile: %s",
5643 simd16_cfg
= v2
.cfg
;
5649 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5650 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5652 prog_data
->no_8
= true;
5655 prog_data
->no_8
= false;
5658 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5659 v
.promoted_constants
, v
.runtime_check_aads_emit
,
5660 MESA_SHADER_FRAGMENT
);
5662 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5663 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5664 shader
->info
.label
? shader
->info
.label
:
5666 shader
->info
.name
));
5670 g
.generate_code(simd8_cfg
, 8);
5672 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5674 return g
.get_assembly(final_assembly_size
);
5678 fs_visitor::emit_cs_local_invocation_id_setup()
5680 assert(stage
== MESA_SHADER_COMPUTE
);
5682 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5684 struct brw_reg src
=
5685 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5686 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5688 src
.nr
+= dispatch_width
/ 8;
5689 bld
.MOV(offset(*reg
, bld
, 1), src
);
5690 src
.nr
+= dispatch_width
/ 8;
5691 bld
.MOV(offset(*reg
, bld
, 2), src
);
5697 fs_visitor::emit_cs_work_group_id_setup()
5699 assert(stage
== MESA_SHADER_COMPUTE
);
5701 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5703 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5704 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5705 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5707 bld
.MOV(*reg
, r0_1
);
5708 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5709 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5715 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5717 const struct brw_cs_prog_key
*key
,
5718 struct brw_cs_prog_data
*prog_data
,
5719 const nir_shader
*src_shader
,
5720 int shader_time_index
,
5721 unsigned *final_assembly_size
,
5724 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5725 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5727 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5729 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5730 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5731 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5732 unsigned local_workgroup_size
=
5733 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5734 shader
->info
.cs
.local_size
[2];
5736 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5739 const char *fail_msg
= NULL
;
5741 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5743 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5744 NULL
, /* Never used in core profile */
5745 shader
, 8, shader_time_index
);
5747 fail_msg
= v8
.fail_msg
;
5748 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5750 prog_data
->simd_size
= 8;
5753 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5754 NULL
, /* Never used in core profile */
5755 shader
, 16, shader_time_index
);
5756 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5757 !fail_msg
&& !v8
.simd16_unsupported
&&
5758 local_workgroup_size
<= 16 * max_cs_threads
) {
5759 /* Try a SIMD16 compile */
5760 v16
.import_uniforms(&v8
);
5761 if (!v16
.run_cs()) {
5762 compiler
->shader_perf_log(log_data
,
5763 "SIMD16 shader failed to compile: %s",
5767 "Couldn't generate SIMD16 program and not "
5768 "enough threads for SIMD8";
5772 prog_data
->simd_size
= 16;
5776 if (unlikely(cfg
== NULL
)) {
5779 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5784 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5785 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
5786 MESA_SHADER_COMPUTE
);
5787 if (INTEL_DEBUG
& DEBUG_CS
) {
5788 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5789 shader
->info
.label
? shader
->info
.label
:
5792 g
.enable_debug(name
);
5795 g
.generate_code(cfg
, prog_data
->simd_size
);
5797 return g
.get_assembly(final_assembly_size
);
5801 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5802 void *buffer
, uint32_t threads
, uint32_t stride
)
5804 if (prog_data
->local_invocation_id_regs
== 0)
5807 /* 'stride' should be an integer number of registers, that is, a multiple
5810 assert(stride
% 32 == 0);
5812 unsigned x
= 0, y
= 0, z
= 0;
5813 for (unsigned t
= 0; t
< threads
; t
++) {
5814 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5816 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5817 param
[0 * prog_data
->simd_size
+ i
] = x
;
5818 param
[1 * prog_data
->simd_size
+ i
] = y
;
5819 param
[2 * prog_data
->simd_size
+ i
] = z
;
5822 if (x
== prog_data
->local_size
[0]) {
5825 if (y
== prog_data
->local_size
[1]) {
5828 if (z
== prog_data
->local_size
[2])