2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= talloc_zero(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= talloc_zero(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
83 if (!_mesa_ir_compile_shader(ctx
, shader
))
90 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
92 struct brw_shader
*shader
=
93 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
95 void *mem_ctx
= talloc_new(NULL
);
99 talloc_free(shader
->ir
);
100 shader
->ir
= new(shader
) exec_list
;
101 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
103 do_mat_op_to_vec(shader
->ir
);
104 lower_instructions(shader
->ir
,
110 do_lower_texture_projection(shader
->ir
);
111 brw_do_cubemap_normalize(shader
->ir
);
116 brw_do_channel_expressions(shader
->ir
);
117 brw_do_vector_splitting(shader
->ir
);
119 progress
= do_lower_jumps(shader
->ir
, true, true,
120 true, /* main return */
121 false, /* continue */
125 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
127 progress
= lower_noise(shader
->ir
) || progress
;
129 lower_variable_index_to_cond_assign(shader
->ir
,
131 GL_TRUE
, /* output */
133 GL_TRUE
/* uniform */
135 progress
= lower_quadop_vector(shader
->ir
, false) || progress
;
138 validate_ir_tree(shader
->ir
);
140 reparent_ir(shader
->ir
, shader
->ir
);
141 talloc_free(mem_ctx
);
144 if (!_mesa_ir_link_shader(ctx
, prog
))
151 type_size(const struct glsl_type
*type
)
153 unsigned int size
, i
;
155 switch (type
->base_type
) {
158 case GLSL_TYPE_FLOAT
:
160 return type
->components();
161 case GLSL_TYPE_ARRAY
:
162 return type_size(type
->fields
.array
) * type
->length
;
163 case GLSL_TYPE_STRUCT
:
165 for (i
= 0; i
< type
->length
; i
++) {
166 size
+= type_size(type
->fields
.structure
[i
].type
);
169 case GLSL_TYPE_SAMPLER
:
170 /* Samplers take up no register space, since they're baked in at
175 assert(!"not reached");
181 * Returns how many MRFs an FS opcode will write over.
183 * Note that this is not the 0 or 1 implied writes in an actual gen
184 * instruction -- the FS opcodes often generate MOVs in addition.
187 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
192 switch (inst
->opcode
) {
207 case FS_OPCODE_FB_WRITE
:
209 case FS_OPCODE_PULL_CONSTANT_LOAD
:
210 case FS_OPCODE_UNSPILL
:
212 case FS_OPCODE_SPILL
:
215 assert(!"not reached");
221 fs_visitor::virtual_grf_alloc(int size
)
223 if (virtual_grf_array_size
<= virtual_grf_next
) {
224 if (virtual_grf_array_size
== 0)
225 virtual_grf_array_size
= 16;
227 virtual_grf_array_size
*= 2;
228 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
229 int, virtual_grf_array_size
);
231 /* This slot is always unused. */
232 virtual_grf_sizes
[0] = 0;
234 virtual_grf_sizes
[virtual_grf_next
] = size
;
235 return virtual_grf_next
++;
238 /** Fixed HW reg constructor. */
239 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
243 this->hw_reg
= hw_reg
;
244 this->type
= BRW_REGISTER_TYPE_F
;
247 /** Fixed HW reg constructor. */
248 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
252 this->hw_reg
= hw_reg
;
257 brw_type_for_base_type(const struct glsl_type
*type
)
259 switch (type
->base_type
) {
260 case GLSL_TYPE_FLOAT
:
261 return BRW_REGISTER_TYPE_F
;
264 return BRW_REGISTER_TYPE_D
;
266 return BRW_REGISTER_TYPE_UD
;
267 case GLSL_TYPE_ARRAY
:
268 case GLSL_TYPE_STRUCT
:
269 case GLSL_TYPE_SAMPLER
:
270 /* These should be overridden with the type of the member when
271 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
272 * way to trip up if we don't.
274 return BRW_REGISTER_TYPE_UD
;
276 assert(!"not reached");
277 return BRW_REGISTER_TYPE_F
;
281 /** Automatic reg constructor. */
282 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
287 this->reg
= v
->virtual_grf_alloc(type_size(type
));
288 this->reg_offset
= 0;
289 this->type
= brw_type_for_base_type(type
);
293 fs_visitor::variable_storage(ir_variable
*var
)
295 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
298 /* Our support for uniforms is piggy-backed on the struct
299 * gl_fragment_program, because that's where the values actually
300 * get stored, rather than in some global gl_shader_program uniform
304 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
306 unsigned int offset
= 0;
309 if (type
->is_matrix()) {
310 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
311 type
->vector_elements
,
314 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
315 offset
+= setup_uniform_values(loc
+ offset
, column
);
321 switch (type
->base_type
) {
322 case GLSL_TYPE_FLOAT
:
326 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
327 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
328 unsigned int param
= c
->prog_data
.nr_params
++;
330 assert(param
< ARRAY_SIZE(c
->prog_data
.param
));
332 switch (type
->base_type
) {
333 case GLSL_TYPE_FLOAT
:
334 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
337 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2U
;
340 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2I
;
343 c
->prog_data
.param_convert
[param
] = PARAM_CONVERT_F2B
;
346 assert(!"not reached");
347 c
->prog_data
.param_convert
[param
] = PARAM_NO_CONVERT
;
351 c
->prog_data
.param
[param
] = &vec_values
[i
];
355 case GLSL_TYPE_STRUCT
:
356 for (unsigned int i
= 0; i
< type
->length
; i
++) {
357 offset
+= setup_uniform_values(loc
+ offset
,
358 type
->fields
.structure
[i
].type
);
362 case GLSL_TYPE_ARRAY
:
363 for (unsigned int i
= 0; i
< type
->length
; i
++) {
364 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
368 case GLSL_TYPE_SAMPLER
:
369 /* The sampler takes up a slot, but we don't use any values from it. */
373 assert(!"not reached");
379 /* Our support for builtin uniforms is even scarier than non-builtin.
380 * It sits on top of the PROG_STATE_VAR parameters that are
381 * automatically updated from GL context state.
384 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
386 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
388 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
389 statevar
= &_mesa_builtin_uniform_desc
[i
];
390 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
394 if (!statevar
->name
) {
396 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
401 if (ir
->type
->is_array()) {
402 array_count
= ir
->type
->length
;
407 for (int a
= 0; a
< array_count
; a
++) {
408 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
409 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
410 int tokens
[STATE_LENGTH
];
412 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
413 if (ir
->type
->is_array()) {
417 /* This state reference has already been setup by ir_to_mesa,
418 * but we'll get the same index back here.
420 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
421 (gl_state_index
*)tokens
);
422 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
424 /* Add each of the unique swizzles of the element as a
425 * parameter. This'll end up matching the expected layout of
426 * the array/matrix/structure we're trying to fill in.
429 for (unsigned int i
= 0; i
< 4; i
++) {
430 int swiz
= GET_SWZ(element
->swizzle
, i
);
431 if (swiz
== last_swiz
)
435 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
437 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
444 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
446 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
448 fs_reg neg_y
= this->pixel_y
;
450 bool flip
= !ir
->origin_upper_left
^ c
->key
.render_to_fbo
;
453 if (ir
->pixel_center_integer
) {
454 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
456 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
461 if (!flip
&& ir
->pixel_center_integer
) {
462 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
464 fs_reg pixel_y
= this->pixel_y
;
465 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
468 pixel_y
.negate
= true;
469 offset
+= c
->key
.drawable_height
- 1.0;
472 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
477 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
478 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
481 /* gl_FragCoord.w: Already set up in emit_interpolation */
482 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
488 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
490 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
491 /* Interpolation is always in floating point regs. */
492 reg
->type
= BRW_REGISTER_TYPE_F
;
495 unsigned int array_elements
;
496 const glsl_type
*type
;
498 if (ir
->type
->is_array()) {
499 array_elements
= ir
->type
->length
;
500 if (array_elements
== 0) {
503 type
= ir
->type
->fields
.array
;
509 int location
= ir
->location
;
510 for (unsigned int i
= 0; i
< array_elements
; i
++) {
511 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
512 if (urb_setup
[location
] == -1) {
513 /* If there's no incoming setup data for this slot, don't
514 * emit interpolation for it.
516 attr
.reg_offset
+= type
->vector_elements
;
521 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
522 struct brw_reg interp
= interp_reg(location
, c
);
523 emit(fs_inst(FS_OPCODE_LINTERP
,
531 if (intel
->gen
< 6) {
532 attr
.reg_offset
-= type
->vector_elements
;
533 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
534 emit(fs_inst(BRW_OPCODE_MUL
,
549 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
551 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
553 /* The frontfacing comes in as a bit in the thread payload. */
554 if (intel
->gen
>= 6) {
555 emit(fs_inst(BRW_OPCODE_ASR
,
557 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
559 emit(fs_inst(BRW_OPCODE_NOT
,
562 emit(fs_inst(BRW_OPCODE_AND
,
567 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
568 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
571 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
575 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
576 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
583 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
595 assert(!"not reached: bad math opcode");
599 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
600 * might be able to do better by doing execsize = 1 math and then
601 * expanding that result out, but we would need to be careful with
604 if (intel
->gen
>= 6 && src
.file
== UNIFORM
) {
605 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
606 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src
));
610 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
612 if (intel
->gen
< 6) {
621 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
626 assert(opcode
== FS_OPCODE_POW
);
628 if (intel
->gen
>= 6) {
629 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
630 if (src0
.file
== UNIFORM
) {
631 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
632 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src0
));
636 if (src1
.file
== UNIFORM
) {
637 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
638 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src1
));
642 inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
644 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
));
645 inst
= emit(fs_inst(opcode
, dst
, src0
, reg_null_f
));
647 inst
->base_mrf
= base_mrf
;
654 fs_visitor::visit(ir_variable
*ir
)
658 if (variable_storage(ir
))
661 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
662 this->frag_color
= ir
;
663 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
664 this->frag_data
= ir
;
665 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
666 this->frag_depth
= ir
;
669 if (ir
->mode
== ir_var_in
) {
670 if (!strcmp(ir
->name
, "gl_FragCoord")) {
671 reg
= emit_fragcoord_interpolation(ir
);
672 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
673 reg
= emit_frontfacing_interpolation(ir
);
675 reg
= emit_general_interpolation(ir
);
678 hash_table_insert(this->variable_ht
, reg
, ir
);
682 if (ir
->mode
== ir_var_uniform
) {
683 int param_index
= c
->prog_data
.nr_params
;
685 if (!strncmp(ir
->name
, "gl_", 3)) {
686 setup_builtin_uniform_values(ir
);
688 setup_uniform_values(ir
->location
, ir
->type
);
691 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
692 reg
->type
= brw_type_for_base_type(ir
->type
);
696 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
698 hash_table_insert(this->variable_ht
, reg
, ir
);
702 fs_visitor::visit(ir_dereference_variable
*ir
)
704 fs_reg
*reg
= variable_storage(ir
->var
);
709 fs_visitor::visit(ir_dereference_record
*ir
)
711 const glsl_type
*struct_type
= ir
->record
->type
;
713 ir
->record
->accept(this);
715 unsigned int offset
= 0;
716 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
717 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
719 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
721 this->result
.reg_offset
+= offset
;
722 this->result
.type
= brw_type_for_base_type(ir
->type
);
726 fs_visitor::visit(ir_dereference_array
*ir
)
731 ir
->array
->accept(this);
732 index
= ir
->array_index
->as_constant();
734 element_size
= type_size(ir
->type
);
735 this->result
.type
= brw_type_for_base_type(ir
->type
);
738 assert(this->result
.file
== UNIFORM
||
739 (this->result
.file
== GRF
&&
740 this->result
.reg
!= 0));
741 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
743 assert(!"FINISHME: non-constant array element");
747 /* Instruction selection: Produce a MOV.sat instead of
748 * MIN(MAX(val, 0), 1) when possible.
751 fs_visitor::try_emit_saturate(ir_expression
*ir
)
753 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
758 sat_val
->accept(this);
759 fs_reg src
= this->result
;
761 this->result
= fs_reg(this, ir
->type
);
762 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, src
));
763 inst
->saturate
= true;
769 fs_visitor::visit(ir_expression
*ir
)
771 unsigned int operand
;
775 assert(ir
->get_num_operands() <= 2);
777 if (try_emit_saturate(ir
))
780 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
781 ir
->operands
[operand
]->accept(this);
782 if (this->result
.file
== BAD_FILE
) {
784 printf("Failed to get tree for expression operand:\n");
785 ir
->operands
[operand
]->accept(&v
);
788 op
[operand
] = this->result
;
790 /* Matrix expression operands should have been broken down to vector
791 * operations already.
793 assert(!ir
->operands
[operand
]->type
->is_matrix());
794 /* And then those vector operands should have been broken down to scalar.
796 assert(!ir
->operands
[operand
]->type
->is_vector());
799 /* Storage for our result. If our result goes into an assignment, it will
800 * just get copy-propagated out, so no worries.
802 this->result
= fs_reg(this, ir
->type
);
804 switch (ir
->operation
) {
805 case ir_unop_logic_not
:
806 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
807 * ones complement of the whole register, not just bit 0.
809 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1)));
812 op
[0].negate
= !op
[0].negate
;
813 this->result
= op
[0];
817 this->result
= op
[0];
820 temp
= fs_reg(this, ir
->type
);
822 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
824 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
825 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
826 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
827 inst
->predicated
= true;
829 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
830 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
831 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
832 inst
->predicated
= true;
836 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
840 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
843 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
847 assert(!"not reached: should be handled by ir_explog_to_explog2");
850 case ir_unop_sin_reduced
:
851 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
854 case ir_unop_cos_reduced
:
855 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
859 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
862 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
866 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
869 assert(!"not reached: should be handled by ir_sub_to_add_neg");
873 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
876 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
879 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
883 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
884 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
885 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
887 case ir_binop_greater
:
888 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
889 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
890 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
892 case ir_binop_lequal
:
893 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
894 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
895 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
897 case ir_binop_gequal
:
898 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
899 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
900 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
903 case ir_binop_all_equal
: /* same as nequal for scalars */
904 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
905 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
906 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
908 case ir_binop_nequal
:
909 case ir_binop_any_nequal
: /* same as nequal for scalars */
910 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
911 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
912 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
915 case ir_binop_logic_xor
:
916 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
919 case ir_binop_logic_or
:
920 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
923 case ir_binop_logic_and
:
924 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
929 assert(!"not reached: should be handled by brw_fs_channel_expressions");
933 assert(!"not reached: should be handled by lower_noise");
937 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
941 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
948 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
952 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
953 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
954 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
,
955 this->result
, fs_reg(1)));
959 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
962 op
[0].negate
= !op
[0].negate
;
963 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
964 this->result
.negate
= true;
967 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
970 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
972 case ir_unop_round_even
:
973 emit(fs_inst(BRW_OPCODE_RNDE
, this->result
, op
[0]));
977 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
978 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
980 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
981 inst
->predicated
= true;
984 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
985 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
987 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
988 inst
->predicated
= true;
992 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
995 case ir_unop_bit_not
:
996 inst
= emit(fs_inst(BRW_OPCODE_NOT
, this->result
, op
[0]));
998 case ir_binop_bit_and
:
999 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1001 case ir_binop_bit_xor
:
1002 inst
= emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1004 case ir_binop_bit_or
:
1005 inst
= emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1009 case ir_binop_lshift
:
1010 case ir_binop_rshift
:
1011 assert(!"GLSL 1.30 features unsupported");
1017 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1018 const glsl_type
*type
, bool predicated
)
1020 switch (type
->base_type
) {
1021 case GLSL_TYPE_FLOAT
:
1022 case GLSL_TYPE_UINT
:
1024 case GLSL_TYPE_BOOL
:
1025 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1026 l
.type
= brw_type_for_base_type(type
);
1027 r
.type
= brw_type_for_base_type(type
);
1029 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1030 inst
->predicated
= predicated
;
1036 case GLSL_TYPE_ARRAY
:
1037 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1038 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1042 case GLSL_TYPE_STRUCT
:
1043 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1044 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1049 case GLSL_TYPE_SAMPLER
:
1053 assert(!"not reached");
1059 fs_visitor::visit(ir_assignment
*ir
)
1064 /* FINISHME: arrays on the lhs */
1065 ir
->lhs
->accept(this);
1068 ir
->rhs
->accept(this);
1071 assert(l
.file
!= BAD_FILE
);
1072 assert(r
.file
!= BAD_FILE
);
1074 if (ir
->condition
) {
1075 emit_bool_to_cond_code(ir
->condition
);
1078 if (ir
->lhs
->type
->is_scalar() ||
1079 ir
->lhs
->type
->is_vector()) {
1080 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1081 if (ir
->write_mask
& (1 << i
)) {
1082 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1084 inst
->predicated
= true;
1090 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1095 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1099 bool simd16
= false;
1105 if (ir
->shadow_comparitor
) {
1106 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1107 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1109 coordinate
.reg_offset
++;
1111 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1114 if (ir
->op
== ir_tex
) {
1115 /* There's no plain shadow compare message, so we use shadow
1116 * compare with a bias of 0.0.
1118 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1121 } else if (ir
->op
== ir_txb
) {
1122 ir
->lod_info
.bias
->accept(this);
1123 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1127 assert(ir
->op
== ir_txl
);
1128 ir
->lod_info
.lod
->accept(this);
1129 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1134 ir
->shadow_comparitor
->accept(this);
1135 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1137 } else if (ir
->op
== ir_tex
) {
1138 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1139 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1141 coordinate
.reg_offset
++;
1143 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1146 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1147 * instructions. We'll need to do SIMD16 here.
1149 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1151 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1152 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1154 coordinate
.reg_offset
++;
1157 /* lod/bias appears after u/v/r. */
1160 if (ir
->op
== ir_txb
) {
1161 ir
->lod_info
.bias
->accept(this);
1162 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1166 ir
->lod_info
.lod
->accept(this);
1167 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1172 /* The unused upper half. */
1175 /* Now, since we're doing simd16, the return is 2 interleaved
1176 * vec4s where the odd-indexed ones are junk. We'll need to move
1177 * this weirdness around to the expected layout.
1181 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1183 dst
.type
= BRW_REGISTER_TYPE_F
;
1186 fs_inst
*inst
= NULL
;
1189 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1192 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1195 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1199 assert(!"GLSL 1.30 features unsupported");
1202 inst
->base_mrf
= base_mrf
;
1206 for (int i
= 0; i
< 4; i
++) {
1207 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1208 orig_dst
.reg_offset
++;
1209 dst
.reg_offset
+= 2;
1217 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1219 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1220 * optional parameters like shadow comparitor or LOD bias. If
1221 * optional parameters aren't present, those base slots are
1222 * optional and don't need to be included in the message.
1224 * We don't fill in the unnecessary slots regardless, which may
1225 * look surprising in the disassembly.
1227 int mlen
= 1; /* g0 header always present. */
1230 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1231 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1233 coordinate
.reg_offset
++;
1235 mlen
+= ir
->coordinate
->type
->vector_elements
;
1237 if (ir
->shadow_comparitor
) {
1238 mlen
= MAX2(mlen
, 5);
1240 ir
->shadow_comparitor
->accept(this);
1241 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1245 fs_inst
*inst
= NULL
;
1248 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1251 ir
->lod_info
.bias
->accept(this);
1252 mlen
= MAX2(mlen
, 5);
1253 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1256 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1259 ir
->lod_info
.lod
->accept(this);
1260 mlen
= MAX2(mlen
, 5);
1261 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1264 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1268 assert(!"GLSL 1.30 features unsupported");
1271 inst
->base_mrf
= base_mrf
;
1278 fs_visitor::visit(ir_texture
*ir
)
1281 fs_inst
*inst
= NULL
;
1283 ir
->coordinate
->accept(this);
1284 fs_reg coordinate
= this->result
;
1286 /* Should be lowered by do_lower_texture_projection */
1287 assert(!ir
->projector
);
1289 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1290 ctx
->Shader
.CurrentFragmentProgram
,
1291 &brw
->fragment_program
->Base
);
1292 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1294 /* The 965 requires the EU to do the normalization of GL rectangle
1295 * texture coordinates. We use the program parameter state
1296 * tracking to get the scaling factor.
1298 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1299 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1300 int tokens
[STATE_LENGTH
] = {
1302 STATE_TEXRECT_SCALE
,
1308 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1310 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1313 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1314 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1315 GLuint index
= _mesa_add_state_reference(params
,
1316 (gl_state_index
*)tokens
);
1317 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
1319 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[0];
1320 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[1];
1322 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1323 fs_reg src
= coordinate
;
1326 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_x
));
1329 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_y
));
1332 /* Writemasking doesn't eliminate channels on SIMD8 texture
1333 * samples, so don't worry about them.
1335 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1337 if (intel
->gen
< 5) {
1338 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1340 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1343 inst
->sampler
= sampler
;
1347 if (ir
->shadow_comparitor
)
1348 inst
->shadow_compare
= true;
1350 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1351 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1353 for (int i
= 0; i
< 4; i
++) {
1354 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1355 fs_reg l
= swizzle_dst
;
1358 if (swiz
== SWIZZLE_ZERO
) {
1359 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1360 } else if (swiz
== SWIZZLE_ONE
) {
1361 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1364 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1365 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1368 this->result
= swizzle_dst
;
1373 fs_visitor::visit(ir_swizzle
*ir
)
1375 ir
->val
->accept(this);
1376 fs_reg val
= this->result
;
1378 if (ir
->type
->vector_elements
== 1) {
1379 this->result
.reg_offset
+= ir
->mask
.x
;
1383 fs_reg result
= fs_reg(this, ir
->type
);
1384 this->result
= result
;
1386 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1387 fs_reg channel
= val
;
1405 channel
.reg_offset
+= swiz
;
1406 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1407 result
.reg_offset
++;
1412 fs_visitor::visit(ir_discard
*ir
)
1414 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1416 assert(ir
->condition
== NULL
); /* FINISHME */
1418 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
));
1419 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
));
1420 kill_emitted
= true;
1424 fs_visitor::visit(ir_constant
*ir
)
1426 fs_reg
reg(this, ir
->type
);
1429 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1430 switch (ir
->type
->base_type
) {
1431 case GLSL_TYPE_FLOAT
:
1432 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1434 case GLSL_TYPE_UINT
:
1435 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1438 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1440 case GLSL_TYPE_BOOL
:
1441 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1444 assert(!"Non-float/uint/int/bool constant");
1451 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1453 ir_expression
*expr
= ir
->as_expression();
1459 assert(expr
->get_num_operands() <= 2);
1460 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1461 assert(expr
->operands
[i
]->type
->is_scalar());
1463 expr
->operands
[i
]->accept(this);
1464 op
[i
] = this->result
;
1467 switch (expr
->operation
) {
1468 case ir_unop_logic_not
:
1469 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1)));
1470 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1473 case ir_binop_logic_xor
:
1474 inst
= emit(fs_inst(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]));
1475 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1478 case ir_binop_logic_or
:
1479 inst
= emit(fs_inst(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]));
1480 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1483 case ir_binop_logic_and
:
1484 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]));
1485 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1489 if (intel
->gen
>= 6) {
1490 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1491 op
[0], fs_reg(0.0f
)));
1493 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1495 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1499 if (intel
->gen
>= 6) {
1500 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0)));
1502 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1504 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1507 case ir_binop_greater
:
1508 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1509 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1511 case ir_binop_gequal
:
1512 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1513 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1516 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1517 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1519 case ir_binop_lequal
:
1520 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1521 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1523 case ir_binop_equal
:
1524 case ir_binop_all_equal
:
1525 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1526 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1528 case ir_binop_nequal
:
1529 case ir_binop_any_nequal
:
1530 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1531 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1534 assert(!"not reached");
1543 if (intel
->gen
>= 6) {
1544 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
,
1545 this->result
, fs_reg(1)));
1546 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1548 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, this->result
));
1549 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1554 * Emit a gen6 IF statement with the comparison folded into the IF
1558 fs_visitor::emit_if_gen6(ir_if
*ir
)
1560 ir_expression
*expr
= ir
->condition
->as_expression();
1567 assert(expr
->get_num_operands() <= 2);
1568 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1569 assert(expr
->operands
[i
]->type
->is_scalar());
1571 expr
->operands
[i
]->accept(this);
1572 op
[i
] = this->result
;
1575 switch (expr
->operation
) {
1576 case ir_unop_logic_not
:
1577 inst
= emit(fs_inst(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(1)));
1578 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1581 case ir_binop_logic_xor
:
1582 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1583 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1586 case ir_binop_logic_or
:
1587 temp
= fs_reg(this, glsl_type::bool_type
);
1588 emit(fs_inst(BRW_OPCODE_OR
, temp
, op
[0], op
[1]));
1589 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1590 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1593 case ir_binop_logic_and
:
1594 temp
= fs_reg(this, glsl_type::bool_type
);
1595 emit(fs_inst(BRW_OPCODE_AND
, temp
, op
[0], op
[1]));
1596 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1597 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1601 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0)));
1602 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1606 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1607 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1610 case ir_binop_greater
:
1611 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1612 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1614 case ir_binop_gequal
:
1615 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1616 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1619 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1620 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1622 case ir_binop_lequal
:
1623 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1624 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1626 case ir_binop_equal
:
1627 case ir_binop_all_equal
:
1628 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1629 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1631 case ir_binop_nequal
:
1632 case ir_binop_any_nequal
:
1633 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1634 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1637 assert(!"not reached");
1638 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1639 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1646 ir
->condition
->accept(this);
1648 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0)));
1649 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1653 fs_visitor::visit(ir_if
*ir
)
1657 /* Don't point the annotation at the if statement, because then it plus
1658 * the then and else blocks get printed.
1660 this->base_ir
= ir
->condition
;
1662 if (intel
->gen
>= 6) {
1665 emit_bool_to_cond_code(ir
->condition
);
1667 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1668 inst
->predicated
= true;
1671 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1672 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1678 if (!ir
->else_instructions
.is_empty()) {
1679 emit(fs_inst(BRW_OPCODE_ELSE
));
1681 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1682 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1689 emit(fs_inst(BRW_OPCODE_ENDIF
));
1693 fs_visitor::visit(ir_loop
*ir
)
1695 fs_reg counter
= reg_undef
;
1698 this->base_ir
= ir
->counter
;
1699 ir
->counter
->accept(this);
1700 counter
= *(variable_storage(ir
->counter
));
1703 this->base_ir
= ir
->from
;
1704 ir
->from
->accept(this);
1706 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1710 emit(fs_inst(BRW_OPCODE_DO
));
1713 this->base_ir
= ir
->to
;
1714 ir
->to
->accept(this);
1716 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1717 counter
, this->result
));
1719 case ir_binop_equal
:
1720 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1722 case ir_binop_nequal
:
1723 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1725 case ir_binop_gequal
:
1726 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1728 case ir_binop_lequal
:
1729 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1731 case ir_binop_greater
:
1732 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1735 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1738 assert(!"not reached: unknown loop condition");
1743 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1744 inst
->predicated
= true;
1747 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1748 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1754 if (ir
->increment
) {
1755 this->base_ir
= ir
->increment
;
1756 ir
->increment
->accept(this);
1757 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1760 emit(fs_inst(BRW_OPCODE_WHILE
));
1764 fs_visitor::visit(ir_loop_jump
*ir
)
1767 case ir_loop_jump::jump_break
:
1768 emit(fs_inst(BRW_OPCODE_BREAK
));
1770 case ir_loop_jump::jump_continue
:
1771 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1777 fs_visitor::visit(ir_call
*ir
)
1779 assert(!"FINISHME");
1783 fs_visitor::visit(ir_return
*ir
)
1785 assert(!"FINISHME");
1789 fs_visitor::visit(ir_function
*ir
)
1791 /* Ignore function bodies other than main() -- we shouldn't see calls to
1792 * them since they should all be inlined before we get to ir_to_mesa.
1794 if (strcmp(ir
->name
, "main") == 0) {
1795 const ir_function_signature
*sig
;
1798 sig
= ir
->matching_signature(&empty
);
1802 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1803 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1812 fs_visitor::visit(ir_function_signature
*ir
)
1814 assert(!"not reached");
1819 fs_visitor::emit(fs_inst inst
)
1821 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1824 list_inst
->annotation
= this->current_annotation
;
1825 list_inst
->ir
= this->base_ir
;
1827 this->instructions
.push_tail(list_inst
);
1832 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1834 fs_visitor::emit_dummy_fs()
1836 /* Everyone's favorite color. */
1837 emit(fs_inst(BRW_OPCODE_MOV
,
1840 emit(fs_inst(BRW_OPCODE_MOV
,
1843 emit(fs_inst(BRW_OPCODE_MOV
,
1846 emit(fs_inst(BRW_OPCODE_MOV
,
1851 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1854 write
->base_mrf
= 0;
1857 /* The register location here is relative to the start of the URB
1858 * data. It will get adjusted to be a real location before
1859 * generate_code() time.
1862 fs_visitor::interp_reg(int location
, int channel
)
1864 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1865 int stride
= (channel
& 1) * 4;
1867 assert(urb_setup
[location
] != -1);
1869 return brw_vec1_grf(regnr
, stride
);
1872 /** Emits the interpolation for the varying inputs. */
1874 fs_visitor::emit_interpolation_setup_gen4()
1876 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1878 this->current_annotation
= "compute pixel centers";
1879 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1880 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1881 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1882 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1883 emit(fs_inst(BRW_OPCODE_ADD
,
1885 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1886 fs_reg(brw_imm_v(0x10101010))));
1887 emit(fs_inst(BRW_OPCODE_ADD
,
1889 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1890 fs_reg(brw_imm_v(0x11001100))));
1892 this->current_annotation
= "compute pixel deltas from v0";
1894 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1895 this->delta_y
= this->delta_x
;
1896 this->delta_y
.reg_offset
++;
1898 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1899 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1901 emit(fs_inst(BRW_OPCODE_ADD
,
1904 fs_reg(negate(brw_vec1_grf(1, 0)))));
1905 emit(fs_inst(BRW_OPCODE_ADD
,
1908 fs_reg(negate(brw_vec1_grf(1, 1)))));
1910 this->current_annotation
= "compute pos.w and 1/pos.w";
1911 /* Compute wpos.w. It's always in our setup, since it's needed to
1912 * interpolate the other attributes.
1914 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1915 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1916 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1917 /* Compute the pixel 1/W value from wpos.w. */
1918 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1919 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1920 this->current_annotation
= NULL
;
1923 /** Emits the interpolation for the varying inputs. */
1925 fs_visitor::emit_interpolation_setup_gen6()
1927 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1929 /* If the pixel centers end up used, the setup is the same as for gen4. */
1930 this->current_annotation
= "compute pixel centers";
1931 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1932 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1933 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1934 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1935 emit(fs_inst(BRW_OPCODE_ADD
,
1937 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1938 fs_reg(brw_imm_v(0x10101010))));
1939 emit(fs_inst(BRW_OPCODE_ADD
,
1941 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1942 fs_reg(brw_imm_v(0x11001100))));
1944 /* As of gen6, we can no longer mix float and int sources. We have
1945 * to turn the integer pixel centers into floats for their actual
1948 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1949 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1950 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
));
1951 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
));
1953 this->current_annotation
= "compute 1/pos.w";
1954 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1955 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1956 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1958 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1959 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1961 this->current_annotation
= NULL
;
1965 fs_visitor::emit_fb_writes()
1967 this->current_annotation
= "FB write header";
1968 GLboolean header_present
= GL_TRUE
;
1971 if (intel
->gen
>= 6 &&
1972 !this->kill_emitted
&&
1973 c
->key
.nr_color_regions
== 1) {
1974 header_present
= false;
1977 if (header_present
) {
1982 if (c
->key
.aa_dest_stencil_reg
) {
1983 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1984 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1987 /* Reserve space for color. It'll be filled in per MRT below. */
1991 if (c
->key
.source_depth_to_render_target
) {
1992 if (c
->key
.computes_depth
) {
1993 /* Hand over gl_FragDepth. */
1994 assert(this->frag_depth
);
1995 fs_reg depth
= *(variable_storage(this->frag_depth
));
1997 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1999 /* Pass through the payload depth. */
2000 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2001 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
2005 if (c
->key
.dest_depth_reg
) {
2006 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2007 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
2010 fs_reg color
= reg_undef
;
2011 if (this->frag_color
)
2012 color
= *(variable_storage(this->frag_color
));
2013 else if (this->frag_data
)
2014 color
= *(variable_storage(this->frag_data
));
2016 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2017 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
2018 "FB write target %d",
2020 if (this->frag_color
|| this->frag_data
) {
2021 for (int i
= 0; i
< 4; i
++) {
2022 emit(fs_inst(BRW_OPCODE_MOV
,
2023 fs_reg(MRF
, color_mrf
+ i
),
2029 if (this->frag_color
)
2030 color
.reg_offset
-= 4;
2032 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2033 reg_undef
, reg_undef
));
2034 inst
->target
= target
;
2037 if (target
== c
->key
.nr_color_regions
- 1)
2039 inst
->header_present
= header_present
;
2042 if (c
->key
.nr_color_regions
== 0) {
2043 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
2044 reg_undef
, reg_undef
));
2048 inst
->header_present
= header_present
;
2051 this->current_annotation
= NULL
;
2055 fs_visitor::generate_fb_write(fs_inst
*inst
)
2057 GLboolean eot
= inst
->eot
;
2058 struct brw_reg implied_header
;
2060 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
2063 brw_push_insn_state(p
);
2064 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2065 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2067 if (inst
->header_present
) {
2068 if (intel
->gen
>= 6) {
2070 brw_message_reg(inst
->base_mrf
),
2071 brw_vec8_grf(0, 0));
2073 if (inst
->target
> 0) {
2074 /* Set the render target index for choosing BLEND_STATE. */
2075 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 2),
2076 BRW_REGISTER_TYPE_UD
),
2077 brw_imm_ud(inst
->target
));
2080 /* Clear viewport index, render target array index. */
2081 brw_AND(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 0),
2082 BRW_REGISTER_TYPE_UD
),
2083 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2084 brw_imm_ud(0xf7ff));
2086 implied_header
= brw_null_reg();
2088 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2092 brw_message_reg(inst
->base_mrf
+ 1),
2093 brw_vec8_grf(1, 0));
2095 implied_header
= brw_null_reg();
2098 brw_pop_insn_state(p
);
2101 8, /* dispatch_width */
2102 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2112 fs_visitor::generate_linterp(fs_inst
*inst
,
2113 struct brw_reg dst
, struct brw_reg
*src
)
2115 struct brw_reg delta_x
= src
[0];
2116 struct brw_reg delta_y
= src
[1];
2117 struct brw_reg interp
= src
[2];
2120 delta_y
.nr
== delta_x
.nr
+ 1 &&
2121 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2122 brw_PLN(p
, dst
, interp
, delta_x
);
2124 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2125 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2130 fs_visitor::generate_math(fs_inst
*inst
,
2131 struct brw_reg dst
, struct brw_reg
*src
)
2135 switch (inst
->opcode
) {
2137 op
= BRW_MATH_FUNCTION_INV
;
2140 op
= BRW_MATH_FUNCTION_RSQ
;
2142 case FS_OPCODE_SQRT
:
2143 op
= BRW_MATH_FUNCTION_SQRT
;
2145 case FS_OPCODE_EXP2
:
2146 op
= BRW_MATH_FUNCTION_EXP
;
2148 case FS_OPCODE_LOG2
:
2149 op
= BRW_MATH_FUNCTION_LOG
;
2152 op
= BRW_MATH_FUNCTION_POW
;
2155 op
= BRW_MATH_FUNCTION_SIN
;
2158 op
= BRW_MATH_FUNCTION_COS
;
2161 assert(!"not reached: unknown math function");
2166 if (intel
->gen
>= 6) {
2167 assert(inst
->mlen
== 0);
2169 if (inst
->opcode
== FS_OPCODE_POW
) {
2170 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2174 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2175 BRW_MATH_SATURATE_NONE
,
2177 BRW_MATH_DATA_VECTOR
,
2178 BRW_MATH_PRECISION_FULL
);
2181 assert(inst
->mlen
>= 1);
2185 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2186 BRW_MATH_SATURATE_NONE
,
2187 inst
->base_mrf
, src
[0],
2188 BRW_MATH_DATA_VECTOR
,
2189 BRW_MATH_PRECISION_FULL
);
2194 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
2198 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2200 if (intel
->gen
>= 5) {
2201 switch (inst
->opcode
) {
2203 if (inst
->shadow_compare
) {
2204 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2206 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2210 if (inst
->shadow_compare
) {
2211 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2213 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2218 switch (inst
->opcode
) {
2220 /* Note that G45 and older determines shadow compare and dispatch width
2221 * from message length for most messages.
2223 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2224 if (inst
->shadow_compare
) {
2225 assert(inst
->mlen
== 6);
2227 assert(inst
->mlen
<= 4);
2231 if (inst
->shadow_compare
) {
2232 assert(inst
->mlen
== 6);
2233 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2235 assert(inst
->mlen
== 9);
2236 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2237 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2242 assert(msg_type
!= -1);
2244 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2250 retype(dst
, BRW_REGISTER_TYPE_UW
),
2252 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2253 SURF_INDEX_TEXTURE(inst
->sampler
),
2265 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2268 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2270 * and we're trying to produce:
2273 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2274 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2275 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2276 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2277 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2278 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2279 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2280 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2282 * and add another set of two more subspans if in 16-pixel dispatch mode.
2284 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2285 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2286 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2287 * between each other. We could probably do it like ddx and swizzle the right
2288 * order later, but bail for now and just produce
2289 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2292 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2294 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2295 BRW_REGISTER_TYPE_F
,
2296 BRW_VERTICAL_STRIDE_2
,
2298 BRW_HORIZONTAL_STRIDE_0
,
2299 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2300 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2301 BRW_REGISTER_TYPE_F
,
2302 BRW_VERTICAL_STRIDE_2
,
2304 BRW_HORIZONTAL_STRIDE_0
,
2305 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2306 brw_ADD(p
, dst
, src0
, negate(src1
));
2310 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2312 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2313 BRW_REGISTER_TYPE_F
,
2314 BRW_VERTICAL_STRIDE_4
,
2316 BRW_HORIZONTAL_STRIDE_0
,
2317 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2318 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2319 BRW_REGISTER_TYPE_F
,
2320 BRW_VERTICAL_STRIDE_4
,
2322 BRW_HORIZONTAL_STRIDE_0
,
2323 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2324 brw_ADD(p
, dst
, src0
, negate(src1
));
2328 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2330 if (intel
->gen
>= 6) {
2331 /* Gen6 no longer has the mask reg for us to just read the
2332 * active channels from. However, cmp updates just the channels
2333 * of the flag reg that are enabled, so we can get at the
2334 * channel enables that way. In this step, make a reg of ones
2337 brw_MOV(p
, mask
, brw_imm_ud(1));
2339 brw_push_insn_state(p
);
2340 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2341 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2342 brw_pop_insn_state(p
);
2347 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2349 if (intel
->gen
>= 6) {
2350 struct brw_reg f0
= brw_flag_reg();
2351 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
2353 brw_push_insn_state(p
);
2354 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2355 brw_MOV(p
, f0
, brw_imm_uw(0xffff)); /* inactive channels undiscarded */
2356 brw_pop_insn_state(p
);
2358 brw_CMP(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
2359 BRW_CONDITIONAL_Z
, mask
, brw_imm_ud(0)); /* active channels fail test */
2360 /* Undo CMP's whacking of predication*/
2361 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2363 brw_push_insn_state(p
);
2364 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2365 brw_AND(p
, g1
, f0
, g1
);
2366 brw_pop_insn_state(p
);
2368 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2370 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2372 brw_push_insn_state(p
);
2373 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2374 brw_AND(p
, g0
, mask
, g0
);
2375 brw_pop_insn_state(p
);
2380 fs_visitor::generate_spill(fs_inst
*inst
, struct brw_reg src
)
2382 assert(inst
->mlen
!= 0);
2385 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
2386 retype(src
, BRW_REGISTER_TYPE_UD
));
2387 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
2392 fs_visitor::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
2394 assert(inst
->mlen
!= 0);
2396 /* Clear any post destination dependencies that would be ignored by
2397 * the block read. See the B-Spec for pre-gen5 send instruction.
2399 * This could use a better solution, since texture sampling and
2400 * math reads could potentially run into it as well -- anywhere
2401 * that we have a SEND with a destination that is a register that
2402 * was written but not read within the last N instructions (what's
2403 * N? unsure). This is rare because of dead code elimination, but
2406 if (intel
->gen
== 4 && !intel
->is_g4x
)
2407 brw_MOV(p
, brw_null_reg(), dst
);
2409 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
2412 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2413 /* gen4 errata: destination from a send can't be used as a
2414 * destination until it's been read. Just read it so we don't
2417 brw_MOV(p
, brw_null_reg(), dst
);
2423 fs_visitor::generate_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
)
2425 assert(inst
->mlen
!= 0);
2427 /* Clear any post destination dependencies that would be ignored by
2428 * the block read. See the B-Spec for pre-gen5 send instruction.
2430 * This could use a better solution, since texture sampling and
2431 * math reads could potentially run into it as well -- anywhere
2432 * that we have a SEND with a destination that is a register that
2433 * was written but not read within the last N instructions (what's
2434 * N? unsure). This is rare because of dead code elimination, but
2437 if (intel
->gen
== 4 && !intel
->is_g4x
)
2438 brw_MOV(p
, brw_null_reg(), dst
);
2440 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
2441 inst
->offset
, SURF_INDEX_FRAG_CONST_BUFFER
);
2443 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2444 /* gen4 errata: destination from a send can't be used as a
2445 * destination until it's been read. Just read it so we don't
2448 brw_MOV(p
, brw_null_reg(), dst
);
2453 fs_visitor::assign_curb_setup()
2455 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2456 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2458 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2459 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2460 fs_inst
*inst
= (fs_inst
*)iter
.get();
2462 for (unsigned int i
= 0; i
< 3; i
++) {
2463 if (inst
->src
[i
].file
== UNIFORM
) {
2464 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2465 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2469 inst
->src
[i
].file
= FIXED_HW_REG
;
2470 inst
->src
[i
].fixed_hw_reg
= retype(brw_reg
, inst
->src
[i
].type
);
2477 fs_visitor::calculate_urb_setup()
2479 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2484 /* Figure out where each of the incoming setup attributes lands. */
2485 if (intel
->gen
>= 6) {
2486 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2487 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2488 urb_setup
[i
] = urb_next
++;
2492 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2493 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2494 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2497 if (i
>= VERT_RESULT_VAR0
)
2498 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2499 else if (i
<= VERT_RESULT_TEX7
)
2505 urb_setup
[fp_index
] = urb_next
++;
2510 /* Each attribute is 4 setup channels, each of which is half a reg. */
2511 c
->prog_data
.urb_read_length
= urb_next
* 2;
2515 fs_visitor::assign_urb_setup()
2517 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2519 /* Offset all the urb_setup[] index by the actual position of the
2520 * setup regs, now that the location of the constants has been chosen.
2522 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2523 fs_inst
*inst
= (fs_inst
*)iter
.get();
2525 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2528 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2530 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2533 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2537 * Split large virtual GRFs into separate components if we can.
2539 * This is mostly duplicated with what brw_fs_vector_splitting does,
2540 * but that's really conservative because it's afraid of doing
2541 * splitting that doesn't result in real progress after the rest of
2542 * the optimization phases, which would cause infinite looping in
2543 * optimization. We can do it once here, safely. This also has the
2544 * opportunity to split interpolated values, or maybe even uniforms,
2545 * which we don't have at the IR level.
2547 * We want to split, because virtual GRFs are what we register
2548 * allocate and spill (due to contiguousness requirements for some
2549 * instructions), and they're what we naturally generate in the
2550 * codegen process, but most virtual GRFs don't actually need to be
2551 * contiguous sets of GRFs. If we split, we'll end up with reduced
2552 * live intervals and better dead code elimination and coalescing.
2555 fs_visitor::split_virtual_grfs()
2557 int num_vars
= this->virtual_grf_next
;
2558 bool split_grf
[num_vars
];
2559 int new_virtual_grf
[num_vars
];
2561 /* Try to split anything > 0 sized. */
2562 for (int i
= 0; i
< num_vars
; i
++) {
2563 if (this->virtual_grf_sizes
[i
] != 1)
2564 split_grf
[i
] = true;
2566 split_grf
[i
] = false;
2570 /* PLN opcodes rely on the delta_xy being contiguous. */
2571 split_grf
[this->delta_x
.reg
] = false;
2574 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2575 fs_inst
*inst
= (fs_inst
*)iter
.get();
2577 /* Texturing produces 4 contiguous registers, so no splitting. */
2578 if ((inst
->opcode
== FS_OPCODE_TEX
||
2579 inst
->opcode
== FS_OPCODE_TXB
||
2580 inst
->opcode
== FS_OPCODE_TXL
) &&
2581 inst
->dst
.file
== GRF
) {
2582 split_grf
[inst
->dst
.reg
] = false;
2586 /* Allocate new space for split regs. Note that the virtual
2587 * numbers will be contiguous.
2589 for (int i
= 0; i
< num_vars
; i
++) {
2591 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2592 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2593 int reg
= virtual_grf_alloc(1);
2594 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2597 this->virtual_grf_sizes
[i
] = 1;
2601 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2602 fs_inst
*inst
= (fs_inst
*)iter
.get();
2604 if (inst
->dst
.file
== GRF
&&
2605 split_grf
[inst
->dst
.reg
] &&
2606 inst
->dst
.reg_offset
!= 0) {
2607 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2608 inst
->dst
.reg_offset
- 1);
2609 inst
->dst
.reg_offset
= 0;
2611 for (int i
= 0; i
< 3; i
++) {
2612 if (inst
->src
[i
].file
== GRF
&&
2613 split_grf
[inst
->src
[i
].reg
] &&
2614 inst
->src
[i
].reg_offset
!= 0) {
2615 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2616 inst
->src
[i
].reg_offset
- 1);
2617 inst
->src
[i
].reg_offset
= 0;
2624 * Choose accesses from the UNIFORM file to demote to using the pull
2627 * We allow a fragment shader to have more than the specified minimum
2628 * maximum number of fragment shader uniform components (64). If
2629 * there are too many of these, they'd fill up all of register space.
2630 * So, this will push some of them out to the pull constant buffer and
2631 * update the program to load them.
2634 fs_visitor::setup_pull_constants()
2636 /* Only allow 16 registers (128 uniform components) as push constants. */
2637 unsigned int max_uniform_components
= 16 * 8;
2638 if (c
->prog_data
.nr_params
<= max_uniform_components
)
2641 /* Just demote the end of the list. We could probably do better
2642 * here, demoting things that are rarely used in the program first.
2644 int pull_uniform_base
= max_uniform_components
;
2645 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
2647 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2648 fs_inst
*inst
= (fs_inst
*)iter
.get();
2650 for (int i
= 0; i
< 3; i
++) {
2651 if (inst
->src
[i
].file
!= UNIFORM
)
2654 int uniform_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2655 if (uniform_nr
< pull_uniform_base
)
2658 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
2659 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
2661 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
2662 pull
->ir
= inst
->ir
;
2663 pull
->annotation
= inst
->annotation
;
2664 pull
->base_mrf
= 14;
2667 inst
->insert_before(pull
);
2669 inst
->src
[i
].file
= GRF
;
2670 inst
->src
[i
].reg
= dst
.reg
;
2671 inst
->src
[i
].reg_offset
= 0;
2672 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
2676 for (int i
= 0; i
< pull_uniform_count
; i
++) {
2677 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
2678 c
->prog_data
.pull_param_convert
[i
] =
2679 c
->prog_data
.param_convert
[pull_uniform_base
+ i
];
2681 c
->prog_data
.nr_params
-= pull_uniform_count
;
2682 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
2686 fs_visitor::calculate_live_intervals()
2688 int num_vars
= this->virtual_grf_next
;
2689 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2690 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2693 int bb_header_ip
= 0;
2695 for (int i
= 0; i
< num_vars
; i
++) {
2701 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2702 fs_inst
*inst
= (fs_inst
*)iter
.get();
2704 if (inst
->opcode
== BRW_OPCODE_DO
) {
2705 if (loop_depth
++ == 0)
2707 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2710 if (loop_depth
== 0) {
2711 /* Patches up the use of vars marked for being live across
2714 for (int i
= 0; i
< num_vars
; i
++) {
2715 if (use
[i
] == loop_start
) {
2721 for (unsigned int i
= 0; i
< 3; i
++) {
2722 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2723 int reg
= inst
->src
[i
].reg
;
2725 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2726 def
[reg
] >= bb_header_ip
)) {
2729 def
[reg
] = MIN2(loop_start
, def
[reg
]);
2730 use
[reg
] = loop_start
;
2732 /* Nobody else is going to go smash our start to
2733 * later in the loop now, because def[reg] now
2734 * points before the bb header.
2739 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2740 int reg
= inst
->dst
.reg
;
2742 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2743 !inst
->predicated
)) {
2744 def
[reg
] = MIN2(def
[reg
], ip
);
2746 def
[reg
] = MIN2(def
[reg
], loop_start
);
2753 /* Set the basic block header IP. This is used for determining
2754 * if a complete def of single-register virtual GRF in a loop
2755 * dominates a use in the same basic block. It's a quick way to
2756 * reduce the live interval range of most register used in a
2759 if (inst
->opcode
== BRW_OPCODE_IF
||
2760 inst
->opcode
== BRW_OPCODE_ELSE
||
2761 inst
->opcode
== BRW_OPCODE_ENDIF
||
2762 inst
->opcode
== BRW_OPCODE_DO
||
2763 inst
->opcode
== BRW_OPCODE_WHILE
||
2764 inst
->opcode
== BRW_OPCODE_BREAK
||
2765 inst
->opcode
== BRW_OPCODE_CONTINUE
) {
2770 talloc_free(this->virtual_grf_def
);
2771 talloc_free(this->virtual_grf_use
);
2772 this->virtual_grf_def
= def
;
2773 this->virtual_grf_use
= use
;
2777 * Attempts to move immediate constants into the immediate
2778 * constant slot of following instructions.
2780 * Immediate constants are a bit tricky -- they have to be in the last
2781 * operand slot, you can't do abs/negate on them,
2785 fs_visitor::propagate_constants()
2787 bool progress
= false;
2789 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2790 fs_inst
*inst
= (fs_inst
*)iter
.get();
2792 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2794 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2795 inst
->dst
.type
!= inst
->src
[0].type
)
2798 /* Don't bother with cases where we should have had the
2799 * operation on the constant folded in GLSL already.
2804 /* Found a move of a constant to a GRF. Find anything else using the GRF
2805 * before it's written, and replace it with the constant if we can.
2807 exec_list_iterator scan_iter
= iter
;
2809 for (; scan_iter
.has_next(); scan_iter
.next()) {
2810 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2812 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2813 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2814 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2815 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2819 for (int i
= 2; i
>= 0; i
--) {
2820 if (scan_inst
->src
[i
].file
!= GRF
||
2821 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2822 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2825 /* Don't bother with cases where we should have had the
2826 * operation on the constant folded in GLSL already.
2828 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2831 switch (scan_inst
->opcode
) {
2832 case BRW_OPCODE_MOV
:
2833 scan_inst
->src
[i
] = inst
->src
[0];
2837 case BRW_OPCODE_MUL
:
2838 case BRW_OPCODE_ADD
:
2840 scan_inst
->src
[i
] = inst
->src
[0];
2842 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2843 /* Fit this constant in by commuting the operands */
2844 scan_inst
->src
[0] = scan_inst
->src
[1];
2845 scan_inst
->src
[1] = inst
->src
[0];
2848 case BRW_OPCODE_CMP
:
2849 case BRW_OPCODE_SEL
:
2851 scan_inst
->src
[i
] = inst
->src
[0];
2857 if (scan_inst
->dst
.file
== GRF
&&
2858 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2859 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2860 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2869 * Must be called after calculate_live_intervales() to remove unused
2870 * writes to registers -- register allocation will fail otherwise
2871 * because something deffed but not used won't be considered to
2872 * interfere with other regs.
2875 fs_visitor::dead_code_eliminate()
2877 bool progress
= false;
2880 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2881 fs_inst
*inst
= (fs_inst
*)iter
.get();
2883 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
2895 fs_visitor::register_coalesce()
2897 bool progress
= false;
2899 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2900 fs_inst
*inst
= (fs_inst
*)iter
.get();
2902 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2905 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
2906 inst
->dst
.type
!= inst
->src
[0].type
)
2909 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2910 * them: check for no writes to either one until the exit of the
2913 bool interfered
= false;
2914 exec_list_iterator scan_iter
= iter
;
2916 for (; scan_iter
.has_next(); scan_iter
.next()) {
2917 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2919 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2920 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2921 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2927 if (scan_inst
->dst
.file
== GRF
) {
2928 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2929 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2930 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2934 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
2935 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
2936 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2946 /* Update live interval so we don't have to recalculate. */
2947 this->virtual_grf_use
[inst
->src
[0].reg
] = MAX2(virtual_grf_use
[inst
->src
[0].reg
],
2948 virtual_grf_use
[inst
->dst
.reg
]);
2950 /* Rewrite the later usage to point at the source of the move to
2953 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
2955 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2957 for (int i
= 0; i
< 3; i
++) {
2958 if (scan_inst
->src
[i
].file
== GRF
&&
2959 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
2960 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
2961 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
2962 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
2963 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
2964 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
2965 scan_inst
->src
[i
].smear
= inst
->src
[0].smear
;
2979 fs_visitor::compute_to_mrf()
2981 bool progress
= false;
2984 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2985 fs_inst
*inst
= (fs_inst
*)iter
.get();
2990 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2992 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2993 inst
->dst
.type
!= inst
->src
[0].type
||
2994 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
2997 /* Can't compute-to-MRF this GRF if someone else was going to
3000 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
3003 /* Found a move of a GRF to a MRF. Let's see if we can go
3004 * rewrite the thing that made this GRF to write into the MRF.
3007 for (scan_inst
= (fs_inst
*)inst
->prev
;
3008 scan_inst
->prev
!= NULL
;
3009 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
3010 if (scan_inst
->dst
.file
== GRF
&&
3011 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
3012 /* Found the last thing to write our reg we want to turn
3013 * into a compute-to-MRF.
3016 if (scan_inst
->opcode
== FS_OPCODE_TEX
) {
3017 /* texturing writes several continuous regs, so we can't
3018 * compute-to-mrf that.
3023 /* If it's predicated, it (probably) didn't populate all
3026 if (scan_inst
->predicated
)
3029 /* SEND instructions can't have MRF as a destination. */
3030 if (scan_inst
->mlen
)
3033 if (intel
->gen
>= 6) {
3034 /* gen6 math instructions must have the destination be
3035 * GRF, so no compute-to-MRF for them.
3037 if (scan_inst
->opcode
== FS_OPCODE_RCP
||
3038 scan_inst
->opcode
== FS_OPCODE_RSQ
||
3039 scan_inst
->opcode
== FS_OPCODE_SQRT
||
3040 scan_inst
->opcode
== FS_OPCODE_EXP2
||
3041 scan_inst
->opcode
== FS_OPCODE_LOG2
||
3042 scan_inst
->opcode
== FS_OPCODE_SIN
||
3043 scan_inst
->opcode
== FS_OPCODE_COS
||
3044 scan_inst
->opcode
== FS_OPCODE_POW
) {
3049 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
3050 /* Found the creator of our MRF's source value. */
3051 scan_inst
->dst
.file
= MRF
;
3052 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
3053 scan_inst
->saturate
|= inst
->saturate
;
3060 /* We don't handle flow control here. Most computation of
3061 * values that end up in MRFs are shortly before the MRF
3064 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
3065 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
3066 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
3070 /* You can't read from an MRF, so if someone else reads our
3071 * MRF's source GRF that we wanted to rewrite, that stops us.
3073 bool interfered
= false;
3074 for (int i
= 0; i
< 3; i
++) {
3075 if (scan_inst
->src
[i
].file
== GRF
&&
3076 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
3077 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
3084 if (scan_inst
->dst
.file
== MRF
&&
3085 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
3086 /* Somebody else wrote our MRF here, so we can't can't
3087 * compute-to-MRF before that.
3092 if (scan_inst
->mlen
> 0) {
3093 /* Found a SEND instruction, which means that there are
3094 * live values in MRFs from base_mrf to base_mrf +
3095 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3098 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
3099 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
3110 * Walks through basic blocks, locking for repeated MRF writes and
3111 * removing the later ones.
3114 fs_visitor::remove_duplicate_mrf_writes()
3116 fs_inst
*last_mrf_move
[16];
3117 bool progress
= false;
3119 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3121 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3122 fs_inst
*inst
= (fs_inst
*)iter
.get();
3124 switch (inst
->opcode
) {
3126 case BRW_OPCODE_WHILE
:
3128 case BRW_OPCODE_ELSE
:
3129 case BRW_OPCODE_ENDIF
:
3130 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3136 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3137 inst
->dst
.file
== MRF
) {
3138 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.hw_reg
];
3139 if (prev_inst
&& inst
->equals(prev_inst
)) {
3146 /* Clear out the last-write records for MRFs that were overwritten. */
3147 if (inst
->dst
.file
== MRF
) {
3148 last_mrf_move
[inst
->dst
.hw_reg
] = NULL
;
3151 if (inst
->mlen
> 0) {
3152 /* Found a SEND instruction, which will include two of fewer
3153 * implied MRF writes. We could do better here.
3155 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3156 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3160 /* Clear out any MRF move records whose sources got overwritten. */
3161 if (inst
->dst
.file
== GRF
) {
3162 for (unsigned int i
= 0; i
< Elements(last_mrf_move
); i
++) {
3163 if (last_mrf_move
[i
] &&
3164 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
3165 last_mrf_move
[i
] = NULL
;
3170 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3171 inst
->dst
.file
== MRF
&&
3172 inst
->src
[0].file
== GRF
&&
3173 !inst
->predicated
) {
3174 last_mrf_move
[inst
->dst
.hw_reg
] = inst
;
3182 fs_visitor::virtual_grf_interferes(int a
, int b
)
3184 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
3185 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
3187 /* For dead code, just check if the def interferes with the other range. */
3188 if (this->virtual_grf_use
[a
] == -1) {
3189 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
3190 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
3192 if (this->virtual_grf_use
[b
] == -1) {
3193 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
3194 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
3200 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
3202 struct brw_reg brw_reg
;
3204 switch (reg
->file
) {
3208 if (reg
->smear
== -1) {
3209 brw_reg
= brw_vec8_reg(reg
->file
,
3212 brw_reg
= brw_vec1_reg(reg
->file
,
3213 reg
->hw_reg
, reg
->smear
);
3215 brw_reg
= retype(brw_reg
, reg
->type
);
3218 switch (reg
->type
) {
3219 case BRW_REGISTER_TYPE_F
:
3220 brw_reg
= brw_imm_f(reg
->imm
.f
);
3222 case BRW_REGISTER_TYPE_D
:
3223 brw_reg
= brw_imm_d(reg
->imm
.i
);
3225 case BRW_REGISTER_TYPE_UD
:
3226 brw_reg
= brw_imm_ud(reg
->imm
.u
);
3229 assert(!"not reached");
3234 brw_reg
= reg
->fixed_hw_reg
;
3237 /* Probably unused. */
3238 brw_reg
= brw_null_reg();
3241 assert(!"not reached");
3242 brw_reg
= brw_null_reg();
3246 brw_reg
= brw_abs(brw_reg
);
3248 brw_reg
= negate(brw_reg
);
3254 fs_visitor::generate_code()
3256 int last_native_inst
= 0;
3257 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
3258 int if_stack_depth
= 0, loop_stack_depth
= 0;
3259 int if_depth_in_loop
[16];
3260 const char *last_annotation_string
= NULL
;
3261 ir_instruction
*last_annotation_ir
= NULL
;
3263 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3264 printf("Native code for fragment shader %d:\n",
3265 ctx
->Shader
.CurrentFragmentProgram
->Name
);
3268 if_depth_in_loop
[loop_stack_depth
] = 0;
3270 memset(&if_stack
, 0, sizeof(if_stack
));
3271 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3272 fs_inst
*inst
= (fs_inst
*)iter
.get();
3273 struct brw_reg src
[3], dst
;
3275 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3276 if (last_annotation_ir
!= inst
->ir
) {
3277 last_annotation_ir
= inst
->ir
;
3278 if (last_annotation_ir
) {
3280 last_annotation_ir
->print();
3284 if (last_annotation_string
!= inst
->annotation
) {
3285 last_annotation_string
= inst
->annotation
;
3286 if (last_annotation_string
)
3287 printf(" %s\n", last_annotation_string
);
3291 for (unsigned int i
= 0; i
< 3; i
++) {
3292 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3294 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3296 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3297 brw_set_predicate_control(p
, inst
->predicated
);
3298 brw_set_saturate(p
, inst
->saturate
);
3300 switch (inst
->opcode
) {
3301 case BRW_OPCODE_MOV
:
3302 brw_MOV(p
, dst
, src
[0]);
3304 case BRW_OPCODE_ADD
:
3305 brw_ADD(p
, dst
, src
[0], src
[1]);
3307 case BRW_OPCODE_MUL
:
3308 brw_MUL(p
, dst
, src
[0], src
[1]);
3311 case BRW_OPCODE_FRC
:
3312 brw_FRC(p
, dst
, src
[0]);
3314 case BRW_OPCODE_RNDD
:
3315 brw_RNDD(p
, dst
, src
[0]);
3317 case BRW_OPCODE_RNDE
:
3318 brw_RNDE(p
, dst
, src
[0]);
3320 case BRW_OPCODE_RNDZ
:
3321 brw_RNDZ(p
, dst
, src
[0]);
3324 case BRW_OPCODE_AND
:
3325 brw_AND(p
, dst
, src
[0], src
[1]);
3328 brw_OR(p
, dst
, src
[0], src
[1]);
3330 case BRW_OPCODE_XOR
:
3331 brw_XOR(p
, dst
, src
[0], src
[1]);
3333 case BRW_OPCODE_NOT
:
3334 brw_NOT(p
, dst
, src
[0]);
3336 case BRW_OPCODE_ASR
:
3337 brw_ASR(p
, dst
, src
[0], src
[1]);
3339 case BRW_OPCODE_SHR
:
3340 brw_SHR(p
, dst
, src
[0], src
[1]);
3342 case BRW_OPCODE_SHL
:
3343 brw_SHL(p
, dst
, src
[0], src
[1]);
3346 case BRW_OPCODE_CMP
:
3347 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3349 case BRW_OPCODE_SEL
:
3350 brw_SEL(p
, dst
, src
[0], src
[1]);
3354 assert(if_stack_depth
< 16);
3355 if (inst
->src
[0].file
!= BAD_FILE
) {
3356 assert(intel
->gen
>= 6);
3357 if_stack
[if_stack_depth
] = brw_IF_gen6(p
, inst
->conditional_mod
, src
[0], src
[1]);
3359 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3361 if_depth_in_loop
[loop_stack_depth
]++;
3365 case BRW_OPCODE_ELSE
:
3366 if_stack
[if_stack_depth
- 1] =
3367 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3369 case BRW_OPCODE_ENDIF
:
3371 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3372 if_depth_in_loop
[loop_stack_depth
]--;
3376 /* FINISHME: We need to write the loop instruction support still. */
3377 if (intel
->gen
>= 6)
3380 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3381 if_depth_in_loop
[loop_stack_depth
] = 0;
3384 case BRW_OPCODE_BREAK
:
3385 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3386 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3388 case BRW_OPCODE_CONTINUE
:
3389 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3390 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3393 case BRW_OPCODE_WHILE
: {
3394 struct brw_instruction
*inst0
, *inst1
;
3397 if (intel
->gen
>= 5)
3400 assert(loop_stack_depth
> 0);
3402 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3403 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3404 while (inst0
> loop_stack
[loop_stack_depth
]) {
3406 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3407 inst0
->bits3
.if_else
.jump_count
== 0) {
3408 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3410 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3411 inst0
->bits3
.if_else
.jump_count
== 0) {
3412 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3420 case FS_OPCODE_SQRT
:
3421 case FS_OPCODE_EXP2
:
3422 case FS_OPCODE_LOG2
:
3426 generate_math(inst
, dst
, src
);
3428 case FS_OPCODE_LINTERP
:
3429 generate_linterp(inst
, dst
, src
);
3434 generate_tex(inst
, dst
);
3436 case FS_OPCODE_DISCARD_NOT
:
3437 generate_discard_not(inst
, dst
);
3439 case FS_OPCODE_DISCARD_AND
:
3440 generate_discard_and(inst
, src
[0]);
3443 generate_ddx(inst
, dst
, src
[0]);
3446 generate_ddy(inst
, dst
, src
[0]);
3449 case FS_OPCODE_SPILL
:
3450 generate_spill(inst
, src
[0]);
3453 case FS_OPCODE_UNSPILL
:
3454 generate_unspill(inst
, dst
);
3457 case FS_OPCODE_PULL_CONSTANT_LOAD
:
3458 generate_pull_constant_load(inst
, dst
);
3461 case FS_OPCODE_FB_WRITE
:
3462 generate_fb_write(inst
);
3465 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3466 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3467 brw_opcodes
[inst
->opcode
].name
);
3469 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3474 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3475 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3477 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3478 ((uint32_t *)&p
->store
[i
])[3],
3479 ((uint32_t *)&p
->store
[i
])[2],
3480 ((uint32_t *)&p
->store
[i
])[1],
3481 ((uint32_t *)&p
->store
[i
])[0]);
3483 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3487 last_native_inst
= p
->nr_insn
;
3492 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3494 struct intel_context
*intel
= &brw
->intel
;
3495 struct gl_context
*ctx
= &intel
->ctx
;
3496 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentFragmentProgram
;
3501 struct brw_shader
*shader
=
3502 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3506 /* We always use 8-wide mode, at least for now. For one, flow
3507 * control only works in 8-wide. Also, when we're fragment shader
3508 * bound, we're almost always under register pressure as well, so
3509 * 8-wide would save us from the performance cliff of spilling
3512 c
->dispatch_width
= 8;
3514 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
3515 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3516 _mesa_print_ir(shader
->ir
, NULL
);
3520 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3522 fs_visitor
v(c
, shader
);
3527 v
.calculate_urb_setup();
3529 v
.emit_interpolation_setup_gen4();
3531 v
.emit_interpolation_setup_gen6();
3533 /* Generate FS IR for main(). (the visitor only descends into
3534 * functions called "main").
3536 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3537 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3544 v
.split_virtual_grfs();
3545 v
.setup_pull_constants();
3547 v
.assign_curb_setup();
3548 v
.assign_urb_setup();
3554 progress
= v
.remove_duplicate_mrf_writes() || progress
;
3556 v
.calculate_live_intervals();
3557 progress
= v
.propagate_constants() || progress
;
3558 progress
= v
.register_coalesce() || progress
;
3559 progress
= v
.compute_to_mrf() || progress
;
3560 progress
= v
.dead_code_eliminate() || progress
;
3564 /* Debug of register spilling: Go spill everything. */
3565 int virtual_grf_count
= v
.virtual_grf_next
;
3566 for (int i
= 1; i
< virtual_grf_count
; i
++) {
3569 v
.calculate_live_intervals();
3573 v
.assign_regs_trivial();
3575 while (!v
.assign_regs()) {
3579 v
.calculate_live_intervals();
3587 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3592 c
->prog_data
.total_grf
= v
.grf_used
;