glsl: move to compiler/
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #pragma once
29
30 #include "brw_shader.h"
31 #include "brw_ir_fs.h"
32 #include "brw_fs_builder.h"
33 #include "compiler/glsl/ir.h"
34 #include "compiler/nir/nir.h"
35
36 struct bblock_t;
37 namespace {
38 struct acp_entry;
39 }
40
41 namespace brw {
42 class fs_live_variables;
43 }
44
45 struct brw_gs_compile;
46
47 static inline fs_reg
48 offset(fs_reg reg, const brw::fs_builder& bld, unsigned delta)
49 {
50 switch (reg.file) {
51 case BAD_FILE:
52 break;
53 case ARF:
54 case FIXED_GRF:
55 case MRF:
56 case VGRF:
57 case ATTR:
58 return byte_offset(reg,
59 delta * reg.component_size(bld.dispatch_width()));
60 case UNIFORM:
61 reg.reg_offset += delta;
62 break;
63 case IMM:
64 assert(delta == 0);
65 }
66 return reg;
67 }
68
69 /**
70 * The fragment shader front-end.
71 *
72 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
73 */
74 class fs_visitor : public backend_shader
75 {
76 public:
77 fs_visitor(const struct brw_compiler *compiler, void *log_data,
78 void *mem_ctx,
79 const void *key,
80 struct brw_stage_prog_data *prog_data,
81 struct gl_program *prog,
82 const nir_shader *shader,
83 unsigned dispatch_width,
84 int shader_time_index,
85 const struct brw_vue_map *input_vue_map = NULL);
86 fs_visitor(const struct brw_compiler *compiler, void *log_data,
87 void *mem_ctx,
88 struct brw_gs_compile *gs_compile,
89 struct brw_gs_prog_data *prog_data,
90 const nir_shader *shader,
91 int shader_time_index);
92 void init();
93 ~fs_visitor();
94
95 fs_reg vgrf(const glsl_type *const type);
96 void import_uniforms(fs_visitor *v);
97 void setup_uniform_clipplane_values(gl_clip_plane *clip_planes);
98 void compute_clip_distance(gl_clip_plane *clip_planes);
99
100 fs_inst *get_instruction_generating_reg(fs_inst *start,
101 fs_inst *end,
102 const fs_reg &reg);
103
104 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
105 const fs_reg &dst,
106 const fs_reg &surf_index,
107 const fs_reg &varying_offset,
108 uint32_t const_offset);
109 void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
110
111 bool run_fs(bool do_rep_send);
112 bool run_vs(gl_clip_plane *clip_planes);
113 bool run_tes();
114 bool run_gs();
115 bool run_cs();
116 void optimize();
117 void allocate_registers();
118 void setup_payload_gen4();
119 void setup_payload_gen6();
120 void setup_vs_payload();
121 void setup_gs_payload();
122 void setup_cs_payload();
123 void fixup_3src_null_dest();
124 void assign_curb_setup();
125 void calculate_urb_setup();
126 void assign_urb_setup();
127 void convert_attr_sources_to_hw_regs(fs_inst *inst);
128 void assign_vs_urb_setup();
129 void assign_tes_urb_setup();
130 void assign_gs_urb_setup();
131 bool assign_regs(bool allow_spilling);
132 void assign_regs_trivial();
133 void calculate_payload_ranges(int payload_node_count,
134 int *payload_last_use_ip);
135 void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
136 int first_payload_node);
137 int choose_spill_reg(struct ra_graph *g);
138 void spill_reg(int spill_reg);
139 void split_virtual_grfs();
140 bool compact_virtual_grfs();
141 void assign_constant_locations();
142 void demote_pull_constants();
143 void invalidate_live_intervals();
144 void calculate_live_intervals();
145 void calculate_register_pressure();
146 void validate();
147 bool opt_algebraic();
148 bool opt_redundant_discard_jumps();
149 bool opt_cse();
150 bool opt_cse_local(bblock_t *block);
151 bool opt_copy_propagate();
152 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
153 bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
154 bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
155 exec_list *acp);
156 bool opt_register_renaming();
157 bool register_coalesce();
158 bool compute_to_mrf();
159 bool eliminate_find_live_channel();
160 bool dead_code_eliminate();
161 bool remove_duplicate_mrf_writes();
162
163 bool opt_sampler_eot();
164 bool virtual_grf_interferes(int a, int b);
165 void schedule_instructions(instruction_scheduler_mode mode);
166 void insert_gen4_send_dependency_workarounds();
167 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
168 fs_inst *inst);
169 void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
170 fs_inst *inst);
171 void vfail(const char *msg, va_list args);
172 void fail(const char *msg, ...);
173 void no16(const char *msg);
174 void lower_uniform_pull_constant_loads();
175 bool lower_load_payload();
176 bool lower_logical_sends();
177 bool lower_integer_multiplication();
178 bool lower_simd_width();
179 bool opt_combine_constants();
180
181 void emit_dummy_fs();
182 void emit_repclear_shader();
183 fs_reg *emit_fragcoord_interpolation(bool pixel_center_integer,
184 bool origin_upper_left);
185 fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
186 glsl_interp_qualifier interpolation_mode,
187 bool is_centroid, bool is_sample);
188 fs_reg *emit_frontfacing_interpolation();
189 fs_reg *emit_samplepos_setup();
190 fs_reg *emit_sampleid_setup();
191 void emit_general_interpolation(fs_reg *attr, const char *name,
192 const glsl_type *type,
193 glsl_interp_qualifier interpolation_mode,
194 int *location, bool mod_centroid,
195 bool mod_sample);
196 fs_reg *emit_vs_system_value(int location);
197 void emit_interpolation_setup_gen4();
198 void emit_interpolation_setup_gen6();
199 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
200 void emit_texture(ir_texture_opcode op,
201 const glsl_type *dest_type,
202 fs_reg coordinate, int components,
203 fs_reg shadow_c,
204 fs_reg lod, fs_reg dpdy, int grad_components,
205 fs_reg sample_index,
206 fs_reg offset,
207 fs_reg mcs,
208 int gather_component,
209 bool is_cube_array,
210 uint32_t sampler,
211 fs_reg sampler_reg);
212 fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
213 const fs_reg &sampler);
214 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
215 fs_reg resolve_source_modifiers(const fs_reg &src);
216 void emit_discard_jump();
217 bool opt_peephole_sel();
218 bool opt_peephole_predicated_break();
219 bool opt_saturate_propagation();
220 bool opt_cmod_propagation();
221 bool opt_zero_samples();
222 void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
223 uint32_t spill_offset, int count);
224 void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
225 uint32_t spill_offset, int count);
226
227 void emit_nir_code();
228 void nir_setup_inputs();
229 void nir_setup_single_output_varying(fs_reg *reg, const glsl_type *type,
230 unsigned *location);
231 void nir_setup_outputs();
232 void nir_setup_uniforms();
233 void nir_emit_system_values();
234 void nir_emit_impl(nir_function_impl *impl);
235 void nir_emit_cf_list(exec_list *list);
236 void nir_emit_if(nir_if *if_stmt);
237 void nir_emit_loop(nir_loop *loop);
238 void nir_emit_block(nir_block *block);
239 void nir_emit_instr(nir_instr *instr);
240 void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
241 void nir_emit_load_const(const brw::fs_builder &bld,
242 nir_load_const_instr *instr);
243 void nir_emit_undef(const brw::fs_builder &bld,
244 nir_ssa_undef_instr *instr);
245 void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
246 nir_intrinsic_instr *instr);
247 void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
248 nir_intrinsic_instr *instr);
249 void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
250 nir_intrinsic_instr *instr);
251 void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
252 nir_intrinsic_instr *instr);
253 void nir_emit_intrinsic(const brw::fs_builder &bld,
254 nir_intrinsic_instr *instr);
255 void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
256 nir_intrinsic_instr *instr);
257 void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
258 int op, nir_intrinsic_instr *instr);
259 void nir_emit_shared_atomic(const brw::fs_builder &bld,
260 int op, nir_intrinsic_instr *instr);
261 void nir_emit_texture(const brw::fs_builder &bld,
262 nir_tex_instr *instr);
263 void nir_emit_jump(const brw::fs_builder &bld,
264 nir_jump_instr *instr);
265 fs_reg get_nir_src(nir_src src);
266 fs_reg get_nir_dest(nir_dest dest);
267 fs_reg get_nir_image_deref(const nir_deref_var *deref);
268 fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
269 void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
270 unsigned wr_mask);
271
272 bool optimize_frontfacing_ternary(nir_alu_instr *instr,
273 const fs_reg &result);
274
275 void emit_alpha_test();
276 fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
277 fs_reg color1, fs_reg color2,
278 fs_reg src0_alpha, unsigned components);
279 void emit_fb_writes();
280 void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
281 void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
282 unsigned stream_id);
283 void emit_gs_control_data_bits(const fs_reg &vertex_count);
284 void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
285 void emit_gs_vertex(const nir_src &vertex_count_nir_src,
286 unsigned stream_id);
287 void emit_gs_thread_end();
288 void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
289 unsigned base_offset, const nir_src &offset_src,
290 unsigned num_components);
291 void emit_cs_terminate();
292 fs_reg *emit_cs_local_invocation_id_setup();
293 fs_reg *emit_cs_work_group_id_setup();
294
295 void emit_barrier();
296
297 void emit_shader_time_begin();
298 void emit_shader_time_end();
299 void SHADER_TIME_ADD(const brw::fs_builder &bld,
300 int shader_time_subindex,
301 fs_reg value);
302
303 fs_reg get_timestamp(const brw::fs_builder &bld);
304
305 struct brw_reg interp_reg(int location, int channel);
306
307 int implied_mrf_writes(fs_inst *inst);
308
309 virtual void dump_instructions();
310 virtual void dump_instructions(const char *name);
311 void dump_instruction(backend_instruction *inst);
312 void dump_instruction(backend_instruction *inst, FILE *file);
313
314 const void *const key;
315 const struct brw_sampler_prog_key_data *key_tex;
316
317 struct brw_gs_compile *gs_compile;
318
319 struct brw_stage_prog_data *prog_data;
320 struct gl_program *prog;
321
322 const struct brw_vue_map *input_vue_map;
323
324 int *param_size;
325
326 int *virtual_grf_start;
327 int *virtual_grf_end;
328 brw::fs_live_variables *live_intervals;
329
330 int *regs_live_at_ip;
331
332 /** Number of uniform variable components visited. */
333 unsigned uniforms;
334
335 /** Byte-offset for the next available spot in the scratch space buffer. */
336 unsigned last_scratch;
337
338 /**
339 * Array mapping UNIFORM register numbers to the pull parameter index,
340 * or -1 if this uniform register isn't being uploaded as a pull constant.
341 */
342 int *pull_constant_loc;
343
344 /**
345 * Array mapping UNIFORM register numbers to the push parameter index,
346 * or -1 if this uniform register isn't being uploaded as a push constant.
347 */
348 int *push_constant_loc;
349
350 fs_reg frag_depth;
351 fs_reg frag_stencil;
352 fs_reg sample_mask;
353 fs_reg outputs[VARYING_SLOT_MAX];
354 unsigned output_components[VARYING_SLOT_MAX];
355 fs_reg dual_src_output;
356 bool do_dual_src;
357 int first_non_payload_grf;
358 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
359 unsigned max_grf;
360
361 fs_reg *nir_locals;
362 fs_reg *nir_ssa_values;
363 fs_reg nir_inputs;
364 fs_reg nir_outputs;
365 fs_reg *nir_system_values;
366
367 bool failed;
368 char *fail_msg;
369 bool simd16_unsupported;
370 char *no16_msg;
371
372 /* Result of last visit() method. Still used by emit_texture() */
373 fs_reg result;
374
375 /** Register numbers for thread payload fields. */
376 struct thread_payload {
377 uint8_t source_depth_reg;
378 uint8_t source_w_reg;
379 uint8_t aa_dest_stencil_reg;
380 uint8_t dest_depth_reg;
381 uint8_t sample_pos_reg;
382 uint8_t sample_mask_in_reg;
383 uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
384 uint8_t local_invocation_id_reg;
385
386 /** The number of thread payload registers the hardware will supply. */
387 uint8_t num_regs;
388 } payload;
389
390 bool source_depth_to_render_target;
391 bool runtime_check_aads_emit;
392
393 fs_reg pixel_x;
394 fs_reg pixel_y;
395 fs_reg wpos_w;
396 fs_reg pixel_w;
397 fs_reg delta_xy[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
398 fs_reg shader_start_time;
399 fs_reg userplane[MAX_CLIP_PLANES];
400 fs_reg final_gs_vertex_count;
401 fs_reg control_data_bits;
402
403 unsigned grf_used;
404 bool spilled_any_registers;
405
406 const unsigned dispatch_width; /**< 8 or 16 */
407
408 int shader_time_index;
409
410 unsigned promoted_constants;
411 brw::fs_builder bld;
412 };
413
414 /**
415 * The fragment shader code generator.
416 *
417 * Translates FS IR to actual i965 assembly code.
418 */
419 class fs_generator
420 {
421 public:
422 fs_generator(const struct brw_compiler *compiler, void *log_data,
423 void *mem_ctx,
424 const void *key,
425 struct brw_stage_prog_data *prog_data,
426 unsigned promoted_constants,
427 bool runtime_check_aads_emit,
428 gl_shader_stage stage);
429 ~fs_generator();
430
431 void enable_debug(const char *shader_name);
432 int generate_code(const cfg_t *cfg, int dispatch_width);
433 const unsigned *get_assembly(unsigned int *assembly_size);
434
435 private:
436 void fire_fb_write(fs_inst *inst,
437 struct brw_reg payload,
438 struct brw_reg implied_header,
439 GLuint nr);
440 void generate_fb_write(fs_inst *inst, struct brw_reg payload);
441 void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
442 void generate_urb_write(fs_inst *inst, struct brw_reg payload);
443 void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
444 void generate_stencil_ref_packing(fs_inst *inst, struct brw_reg dst,
445 struct brw_reg src);
446 void generate_barrier(fs_inst *inst, struct brw_reg src);
447 void generate_blorp_fb_write(fs_inst *inst);
448 void generate_linterp(fs_inst *inst, struct brw_reg dst,
449 struct brw_reg *src);
450 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
451 struct brw_reg sampler_index);
452 void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
453 struct brw_reg src,
454 struct brw_reg surf_index);
455 void generate_math_gen6(fs_inst *inst,
456 struct brw_reg dst,
457 struct brw_reg src0,
458 struct brw_reg src1);
459 void generate_math_gen4(fs_inst *inst,
460 struct brw_reg dst,
461 struct brw_reg src);
462 void generate_math_g45(fs_inst *inst,
463 struct brw_reg dst,
464 struct brw_reg src);
465 void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
466 void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src,
467 bool negate_value);
468 void generate_scratch_write(fs_inst *inst, struct brw_reg src);
469 void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
470 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
471 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
472 struct brw_reg index,
473 struct brw_reg offset);
474 void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
475 struct brw_reg dst,
476 struct brw_reg surf_index,
477 struct brw_reg offset);
478 void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
479 struct brw_reg index,
480 struct brw_reg offset);
481 void generate_varying_pull_constant_load_gen7(fs_inst *inst,
482 struct brw_reg dst,
483 struct brw_reg index,
484 struct brw_reg offset);
485 void generate_mov_dispatch_to_flags(fs_inst *inst);
486
487 void generate_pixel_interpolator_query(fs_inst *inst,
488 struct brw_reg dst,
489 struct brw_reg src,
490 struct brw_reg msg_data,
491 unsigned msg_type);
492
493 void generate_set_sample_id(fs_inst *inst,
494 struct brw_reg dst,
495 struct brw_reg src0,
496 struct brw_reg src1);
497
498 void generate_set_simd4x2_offset(fs_inst *inst,
499 struct brw_reg dst,
500 struct brw_reg offset);
501 void generate_discard_jump(fs_inst *inst);
502
503 void generate_pack_half_2x16_split(fs_inst *inst,
504 struct brw_reg dst,
505 struct brw_reg x,
506 struct brw_reg y);
507 void generate_unpack_half_2x16_split(fs_inst *inst,
508 struct brw_reg dst,
509 struct brw_reg src);
510
511 void generate_shader_time_add(fs_inst *inst,
512 struct brw_reg payload,
513 struct brw_reg offset,
514 struct brw_reg value);
515
516 void generate_mov_indirect(fs_inst *inst,
517 struct brw_reg dst,
518 struct brw_reg reg,
519 struct brw_reg indirect_byte_offset);
520
521 bool patch_discard_jumps_to_fb_writes();
522
523 const struct brw_compiler *compiler;
524 void *log_data; /* Passed to compiler->*_log functions */
525
526 const struct brw_device_info *devinfo;
527
528 struct brw_codegen *p;
529 const void * const key;
530 struct brw_stage_prog_data * const prog_data;
531
532 unsigned dispatch_width; /**< 8 or 16 */
533
534 exec_list discard_halt_patches;
535 unsigned promoted_constants;
536 bool runtime_check_aads_emit;
537 bool debug_flag;
538 const char *shader_name;
539 gl_shader_stage stage;
540 void *mem_ctx;
541 };
542
543 bool brw_do_channel_expressions(struct exec_list *instructions);
544 bool brw_do_vector_splitting(struct exec_list *instructions);