2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
30 #include "main/macros.h"
31 #include "brw_context.h"
36 static enum brw_reg_file
37 brw_file_from_reg(fs_reg
*reg
)
41 return BRW_ARCHITECTURE_REGISTER_FILE
;
44 return BRW_GENERAL_REGISTER_FILE
;
46 return BRW_MESSAGE_REGISTER_FILE
;
48 return BRW_IMMEDIATE_VALUE
;
52 unreachable("not reached");
54 return BRW_ARCHITECTURE_REGISTER_FILE
;
58 brw_reg_from_fs_reg(fs_inst
*inst
, fs_reg
*reg
, unsigned gen
)
60 struct brw_reg brw_reg
;
64 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(gen
));
67 if (reg
->stride
== 0) {
68 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 } else if (inst
->exec_size
< 8) {
70 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
71 brw_reg
= stride(brw_reg
, inst
->exec_size
* reg
->stride
,
72 inst
->exec_size
, reg
->stride
);
74 /* From the Haswell PRM:
76 * VertStride must be used to cross GRF register boundaries. This
77 * rule implies that elements within a 'Width' cannot cross GRF
80 * So, for registers with width > 8, we have to use a width of 8
81 * and trust the compression state to sort out the exec size.
83 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
84 brw_reg
= stride(brw_reg
, 8 * reg
->stride
, 8, reg
->stride
);
87 brw_reg
= retype(brw_reg
, reg
->type
);
88 brw_reg
= byte_offset(brw_reg
, reg
->subreg_offset
);
89 brw_reg
.abs
= reg
->abs
;
90 brw_reg
.negate
= reg
->negate
;
95 brw_reg
= *static_cast<struct brw_reg
*>(reg
);
98 /* Probably unused. */
99 brw_reg
= brw_null_reg();
103 unreachable("not reached");
109 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
112 struct brw_stage_prog_data
*prog_data
,
113 unsigned promoted_constants
,
114 bool runtime_check_aads_emit
,
115 const char *stage_abbrev
)
117 : compiler(compiler
), log_data(log_data
),
118 devinfo(compiler
->devinfo
), key(key
),
119 prog_data(prog_data
),
120 promoted_constants(promoted_constants
),
121 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
122 stage_abbrev(stage_abbrev
), mem_ctx(mem_ctx
)
124 p
= rzalloc(mem_ctx
, struct brw_codegen
);
125 brw_init_codegen(devinfo
, p
, mem_ctx
);
128 fs_generator::~fs_generator()
132 class ip_record
: public exec_node
{
134 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
145 fs_generator::patch_discard_jumps_to_fb_writes()
147 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
150 int scale
= brw_jump_scale(p
->devinfo
);
152 /* There is a somewhat strange undocumented requirement of using
153 * HALT, according to the simulator. If some channel has HALTed to
154 * a particular UIP, then by the end of the program, every channel
155 * must have HALTed to that UIP. Furthermore, the tracking is a
156 * stack, so you can't do the final halt of a UIP after starting
157 * halting to a new UIP.
159 * Symptoms of not emitting this instruction on actual hardware
160 * included GPU hangs and sparkly rendering on the piglit discard
163 brw_inst
*last_halt
= gen6_HALT(p
);
164 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
165 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
169 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
170 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
172 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
173 /* HALT takes a half-instruction distance from the pre-incremented IP. */
174 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
177 this->discard_halt_patches
.make_empty();
182 fs_generator::fire_fb_write(fs_inst
*inst
,
183 struct brw_reg payload
,
184 struct brw_reg implied_header
,
187 uint32_t msg_control
;
189 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
191 if (devinfo
->gen
< 6) {
192 brw_push_insn_state(p
);
193 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
194 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
195 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
196 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
197 brw_MOV(p
, offset(payload
, 1), brw_vec8_grf(1, 0));
198 brw_pop_insn_state(p
);
201 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
202 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
203 else if (prog_data
->dual_src_blend
) {
204 if (!inst
->force_sechalf
)
205 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
207 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
208 } else if (inst
->exec_size
== 16)
209 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
211 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
213 uint32_t surf_index
=
214 prog_data
->binding_table
.render_target_start
+ inst
->target
;
216 bool last_render_target
= inst
->eot
||
217 (prog_data
->dual_src_blend
&& dispatch_width
== 16);
230 inst
->header_size
!= 0);
232 brw_mark_surface_used(&prog_data
->base
, surf_index
);
236 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
238 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
239 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
240 struct brw_reg implied_header
;
242 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
243 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
246 if (inst
->base_mrf
>= 0)
247 payload
= brw_message_reg(inst
->base_mrf
);
249 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
252 if (inst
->header_size
!= 0) {
253 brw_push_insn_state(p
);
254 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
255 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
256 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
257 brw_set_default_flag_reg(p
, 0, 0);
259 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
262 if (prog_data
->uses_kill
) {
263 struct brw_reg pixel_mask
;
265 if (devinfo
->gen
>= 6)
266 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
268 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
270 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
273 if (devinfo
->gen
>= 6) {
274 brw_push_insn_state(p
);
275 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
276 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
278 retype(payload
, BRW_REGISTER_TYPE_UD
),
279 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
280 brw_pop_insn_state(p
);
282 if (inst
->target
> 0 && key
->replicate_alpha
) {
283 /* Set "Source0 Alpha Present to RenderTarget" bit in message
287 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
288 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
289 brw_imm_ud(0x1 << 11));
292 if (inst
->target
> 0) {
293 /* Set the render target index for choosing BLEND_STATE. */
294 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
295 BRW_REGISTER_TYPE_UD
),
296 brw_imm_ud(inst
->target
));
299 /* Set computes stencil to render target */
300 if (prog_data
->computed_stencil
) {
302 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
303 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
304 brw_imm_ud(0x1 << 14));
307 implied_header
= brw_null_reg();
309 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
312 brw_pop_insn_state(p
);
314 implied_header
= brw_null_reg();
317 if (!runtime_check_aads_emit
) {
318 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
320 /* This can only happen in gen < 6 */
321 assert(devinfo
->gen
< 6);
323 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
325 /* Check runtime bit to detect if we have to send AA data or not */
326 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
329 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
331 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
333 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
334 brw_inst_set_exec_size(p
->devinfo
, brw_last_inst
, BRW_EXECUTE_1
);
336 /* Don't send AA data */
337 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
339 brw_land_fwd_jump(p
, jmp
);
340 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
345 fs_generator::generate_mov_indirect(fs_inst
*inst
,
348 struct brw_reg indirect_byte_offset
)
350 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
351 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
353 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
355 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
356 struct brw_reg addr
= vec8(brw_address_reg(0));
358 /* The destination stride of an instruction (in bytes) must be greater
359 * than or equal to the size of the rest of the instruction. Since the
360 * address register is of type UW, we can't use a D-type instruction.
361 * In order to get around this, re re-type to UW and use a stride.
363 indirect_byte_offset
=
364 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
366 /* Prior to Broadwell, there are only 8 address registers. */
367 assert(inst
->exec_size
== 8 || devinfo
->gen
>= 8);
369 brw_MOV(p
, addr
, indirect_byte_offset
);
370 brw_inst_set_mask_control(devinfo
, brw_last_inst
, BRW_MASK_DISABLE
);
371 brw_MOV(p
, dst
, retype(brw_VxH_indirect(0, imm_byte_offset
), dst
.type
));
375 fs_generator::generate_urb_read(fs_inst
*inst
,
377 struct brw_reg header
)
379 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
380 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
382 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
383 brw_set_dest(p
, send
, dst
);
384 brw_set_src0(p
, send
, header
);
385 brw_set_src1(p
, send
, brw_imm_ud(0u));
387 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
388 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
390 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
391 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
393 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
394 brw_inst_set_rlen(p
->devinfo
, send
, inst
->regs_written
);
395 brw_inst_set_header_present(p
->devinfo
, send
, true);
396 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
400 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
404 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
406 brw_set_dest(p
, insn
, brw_null_reg());
407 brw_set_src0(p
, insn
, payload
);
408 brw_set_src1(p
, insn
, brw_imm_d(0));
410 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
411 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
413 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
414 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
415 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
417 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
418 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
419 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
421 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
422 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
423 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
424 brw_inst_set_header_present(p
->devinfo
, insn
, true);
425 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
429 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
431 struct brw_inst
*insn
;
433 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
435 brw_set_dest(p
, insn
, brw_null_reg());
436 brw_set_src0(p
, insn
, payload
);
437 brw_set_src1(p
, insn
, brw_imm_d(0));
439 /* Terminate a compute shader by sending a message to the thread spawner.
441 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
442 brw_inst_set_mlen(devinfo
, insn
, 1);
443 brw_inst_set_rlen(devinfo
, insn
, 0);
444 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
445 brw_inst_set_header_present(devinfo
, insn
, false);
447 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
448 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
450 /* Note that even though the thread has a URB resource associated with it,
451 * we set the "do not dereference URB" bit, because the URB resource is
452 * managed by the fixed-function unit, so it will free it automatically.
454 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
456 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
460 fs_generator::generate_stencil_ref_packing(fs_inst
*inst
,
464 assert(dispatch_width
== 8);
465 assert(devinfo
->gen
>= 9);
467 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
468 * Presumably, in order to save memory bandwidth, the stencil reference
469 * values written from the FS need to be packed into 2 dwords (this makes
470 * sense because the stencil values are limited to 1 byte each and a SIMD8
471 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
473 * The spec is confusing here because in the payload definition of MDP_RTW_S8
474 * (Message Data Payload for Render Target Writes with Stencil 8b) the
475 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
476 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
477 * packed values specified above and diagrammed below:
480 * --------------------------------
484 * --------------------------------
485 * DW1 | STC | STC | STC | STC |
486 * | slot7 | slot6 | slot5 | slot4|
487 * --------------------------------
488 * DW0 | STC | STC | STC | STC |
489 * | slot3 | slot2 | slot1 | slot0|
490 * --------------------------------
493 src
.vstride
= BRW_VERTICAL_STRIDE_4
;
494 src
.width
= BRW_WIDTH_1
;
495 src
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
496 assert(src
.type
== BRW_REGISTER_TYPE_UB
);
497 brw_MOV(p
, retype(dst
, BRW_REGISTER_TYPE_UB
), src
);
501 fs_generator::generate_barrier(fs_inst
*inst
, struct brw_reg src
)
508 fs_generator::generate_blorp_fb_write(fs_inst
*inst
)
511 16 /* dispatch_width */,
512 brw_message_reg(inst
->base_mrf
),
513 brw_reg_from_fs_reg(inst
, &inst
->src
[0], devinfo
->gen
),
514 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
520 inst
->header_size
!= 0);
524 fs_generator::generate_linterp(fs_inst
*inst
,
525 struct brw_reg dst
, struct brw_reg
*src
)
529 * -----------------------------------
530 * | src1+0 | src1+1 | src1+2 | src1+3 |
531 * |-----------------------------------|
532 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
533 * -----------------------------------
535 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
537 * -----------------------------------
538 * | src1+0 | src1+1 | src1+2 | src1+3 |
539 * |-----------------------------------|
540 * |(x0, x1)|(y0, y1)| | | in SIMD8
541 * |-----------------------------------|
542 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
543 * -----------------------------------
545 * See also: emit_interpolation_setup_gen4().
547 struct brw_reg delta_x
= src
[0];
548 struct brw_reg delta_y
= offset(src
[0], dispatch_width
/ 8);
549 struct brw_reg interp
= src
[1];
551 if (devinfo
->has_pln
&&
552 (devinfo
->gen
>= 7 || (delta_x
.nr
& 1) == 0)) {
553 brw_PLN(p
, dst
, interp
, delta_x
);
555 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
556 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
561 fs_generator::generate_math_gen6(fs_inst
*inst
,
566 int op
= brw_math_function(inst
->opcode
);
567 bool binop
= src1
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
;
569 if (dispatch_width
== 8) {
570 gen6_math(p
, dst
, op
, src0
, src1
);
571 } else if (dispatch_width
== 16) {
572 brw_push_insn_state(p
);
573 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
574 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
575 gen6_math(p
, firsthalf(dst
), op
, firsthalf(src0
), firsthalf(src1
));
576 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
577 gen6_math(p
, sechalf(dst
), op
, sechalf(src0
),
578 binop
? sechalf(src1
) : brw_null_reg());
579 brw_pop_insn_state(p
);
584 fs_generator::generate_math_gen4(fs_inst
*inst
,
588 int op
= brw_math_function(inst
->opcode
);
590 assert(inst
->mlen
>= 1);
592 if (dispatch_width
== 8) {
596 BRW_MATH_PRECISION_FULL
);
597 } else if (dispatch_width
== 16) {
598 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
599 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
600 gen4_math(p
, firsthalf(dst
),
602 inst
->base_mrf
, firsthalf(src
),
603 BRW_MATH_PRECISION_FULL
);
604 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
605 gen4_math(p
, sechalf(dst
),
607 inst
->base_mrf
+ 1, sechalf(src
),
608 BRW_MATH_PRECISION_FULL
);
610 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
615 fs_generator::generate_math_g45(fs_inst
*inst
,
619 if (inst
->opcode
== SHADER_OPCODE_POW
||
620 inst
->opcode
== SHADER_OPCODE_INT_QUOTIENT
||
621 inst
->opcode
== SHADER_OPCODE_INT_REMAINDER
) {
622 generate_math_gen4(inst
, dst
, src
);
626 int op
= brw_math_function(inst
->opcode
);
628 assert(inst
->mlen
>= 1);
633 BRW_MATH_PRECISION_FULL
);
637 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
640 struct brw_reg surf_index
)
642 assert(devinfo
->gen
>= 7);
643 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
648 switch (inst
->exec_size
) {
650 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
653 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
656 unreachable("Invalid width for texture instruction");
659 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
665 retype(dst
, BRW_REGISTER_TYPE_UW
),
670 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
671 rlen
, /* response length */
673 inst
->header_size
> 0,
675 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
677 brw_mark_surface_used(prog_data
, surf_index
.ud
);
681 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
682 struct brw_reg surface_index
,
683 struct brw_reg sampler_index
)
688 uint32_t return_format
;
689 bool is_combined_send
= inst
->eot
;
692 case BRW_REGISTER_TYPE_D
:
693 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
695 case BRW_REGISTER_TYPE_UD
:
696 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
699 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
703 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
704 * is set as part of the message descriptor. On gen4, the PRM seems to
705 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
706 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
707 * gone from the message descriptor entirely and you just get UINT32 all
708 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
709 * just stomp it to UINT32 all the time.
711 if (inst
->opcode
== SHADER_OPCODE_TXS
)
712 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
714 switch (inst
->exec_size
) {
716 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
719 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
722 unreachable("Invalid width for texture instruction");
725 if (devinfo
->gen
>= 5) {
726 switch (inst
->opcode
) {
727 case SHADER_OPCODE_TEX
:
728 if (inst
->shadow_compare
) {
729 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
731 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
735 if (inst
->shadow_compare
) {
736 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
738 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
741 case SHADER_OPCODE_TXL
:
742 if (inst
->shadow_compare
) {
743 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
745 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
748 case SHADER_OPCODE_TXS
:
749 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
751 case SHADER_OPCODE_TXD
:
752 if (inst
->shadow_compare
) {
753 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
754 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
755 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
757 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
760 case SHADER_OPCODE_TXF
:
761 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
763 case SHADER_OPCODE_TXF_CMS_W
:
764 assert(devinfo
->gen
>= 9);
765 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
767 case SHADER_OPCODE_TXF_CMS
:
768 if (devinfo
->gen
>= 7)
769 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
771 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
773 case SHADER_OPCODE_TXF_UMS
:
774 assert(devinfo
->gen
>= 7);
775 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
777 case SHADER_OPCODE_TXF_MCS
:
778 assert(devinfo
->gen
>= 7);
779 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
781 case SHADER_OPCODE_LOD
:
782 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
784 case SHADER_OPCODE_TG4
:
785 if (inst
->shadow_compare
) {
786 assert(devinfo
->gen
>= 7);
787 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
789 assert(devinfo
->gen
>= 6);
790 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
793 case SHADER_OPCODE_TG4_OFFSET
:
794 assert(devinfo
->gen
>= 7);
795 if (inst
->shadow_compare
) {
796 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
798 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
801 case SHADER_OPCODE_SAMPLEINFO
:
802 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
805 unreachable("not reached");
808 switch (inst
->opcode
) {
809 case SHADER_OPCODE_TEX
:
810 /* Note that G45 and older determines shadow compare and dispatch width
811 * from message length for most messages.
813 if (inst
->exec_size
== 8) {
814 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
815 if (inst
->shadow_compare
) {
816 assert(inst
->mlen
== 6);
818 assert(inst
->mlen
<= 4);
821 if (inst
->shadow_compare
) {
822 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
823 assert(inst
->mlen
== 9);
825 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
826 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
831 if (inst
->shadow_compare
) {
832 assert(inst
->exec_size
== 8);
833 assert(inst
->mlen
== 6);
834 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
836 assert(inst
->mlen
== 9);
837 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
838 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
841 case SHADER_OPCODE_TXL
:
842 if (inst
->shadow_compare
) {
843 assert(inst
->exec_size
== 8);
844 assert(inst
->mlen
== 6);
845 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
847 assert(inst
->mlen
== 9);
848 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
849 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
852 case SHADER_OPCODE_TXD
:
853 /* There is no sample_d_c message; comparisons are done manually */
854 assert(inst
->exec_size
== 8);
855 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
856 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
858 case SHADER_OPCODE_TXF
:
859 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
860 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
861 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
863 case SHADER_OPCODE_TXS
:
864 assert(inst
->mlen
== 3);
865 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
866 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
869 unreachable("not reached");
872 assert(msg_type
!= -1);
874 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
879 if (is_combined_send
) {
880 assert(devinfo
->gen
>= 9 || devinfo
->is_cherryview
);
884 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
885 src
.file
== BRW_GENERAL_REGISTER_FILE
);
887 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
889 /* Load the message header if present. If there's a texture offset,
890 * we need to set it up explicitly and load the offset bitfield.
891 * Otherwise, we can use an implied move from g0 to the first message reg.
893 if (inst
->header_size
!= 0) {
894 if (devinfo
->gen
< 6 && !inst
->offset
) {
895 /* Set up an implied move from g0 to the MRF. */
896 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
898 struct brw_reg header_reg
;
900 if (devinfo
->gen
>= 7) {
903 assert(inst
->base_mrf
!= -1);
904 header_reg
= brw_message_reg(inst
->base_mrf
);
907 brw_push_insn_state(p
);
908 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
909 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
910 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
911 /* Explicitly set up the message header by copying g0 to the MRF. */
912 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
915 /* Set the offset bits in DWord 2. */
916 brw_MOV(p
, get_element_ud(header_reg
, 2),
917 brw_imm_ud(inst
->offset
));
920 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
);
921 brw_pop_insn_state(p
);
925 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
926 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
927 ? prog_data
->binding_table
.gather_texture_start
928 : prog_data
->binding_table
.texture_start
;
930 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
931 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
932 uint32_t surface
= surface_index
.ud
;
933 uint32_t sampler
= sampler_index
.ud
;
936 retype(dst
, BRW_REGISTER_TYPE_UW
),
939 surface
+ base_binding_table_index
,
944 inst
->header_size
!= 0,
948 brw_mark_surface_used(prog_data
, surface
+ base_binding_table_index
);
950 /* Non-const sampler index */
952 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
953 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
954 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
956 brw_push_insn_state(p
);
957 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
958 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
960 if (memcmp(&surface_reg
, &sampler_reg
, sizeof(surface_reg
)) == 0) {
961 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
963 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
964 brw_OR(p
, addr
, addr
, surface_reg
);
966 if (base_binding_table_index
)
967 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
968 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
970 brw_pop_insn_state(p
);
972 /* dst = send(offset, a0.0 | <descriptor>) */
973 brw_inst
*insn
= brw_send_indirect_message(
974 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
975 brw_set_sampler_message(p
, insn
,
980 inst
->mlen
/* mlen */,
981 inst
->header_size
!= 0 /* header */,
985 /* visitor knows more than we do about the surface limit required,
986 * so has already done marking.
990 if (is_combined_send
) {
991 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
992 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
997 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1000 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1002 * Ideally, we want to produce:
1005 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1006 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1007 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1008 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1009 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1010 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1011 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1012 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1014 * and add another set of two more subspans if in 16-pixel dispatch mode.
1016 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1017 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1018 * pair. But the ideal approximation may impose a huge performance cost on
1019 * sample_d. On at least Haswell, sample_d instruction does some
1020 * optimizations if the same LOD is used for all pixels in the subspan.
1022 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1023 * appropriate swizzling.
1026 fs_generator::generate_ddx(enum opcode opcode
,
1027 struct brw_reg dst
, struct brw_reg src
)
1029 unsigned vstride
, width
;
1031 if (opcode
== FS_OPCODE_DDX_FINE
) {
1032 /* produce accurate derivatives */
1033 vstride
= BRW_VERTICAL_STRIDE_2
;
1034 width
= BRW_WIDTH_2
;
1036 /* replicate the derivative at the top-left pixel to other pixels */
1037 vstride
= BRW_VERTICAL_STRIDE_4
;
1038 width
= BRW_WIDTH_4
;
1041 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
1042 src
.negate
, src
.abs
,
1043 BRW_REGISTER_TYPE_F
,
1046 BRW_HORIZONTAL_STRIDE_0
,
1047 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1048 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1049 src
.negate
, src
.abs
,
1050 BRW_REGISTER_TYPE_F
,
1053 BRW_HORIZONTAL_STRIDE_0
,
1054 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1055 brw_ADD(p
, dst
, src0
, negate(src1
));
1058 /* The negate_value boolean is used to negate the derivative computation for
1059 * FBOs, since they place the origin at the upper left instead of the lower
1063 fs_generator::generate_ddy(enum opcode opcode
,
1064 struct brw_reg dst
, struct brw_reg src
,
1067 if (opcode
== FS_OPCODE_DDY_FINE
) {
1068 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1069 * Region Restrictions):
1071 * In Align16 access mode, SIMD16 is not allowed for DW operations
1072 * and SIMD8 is not allowed for DF operations.
1074 * In this context, "DW operations" means "operations acting on 32-bit
1075 * values", so it includes operations on floats.
1077 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1078 * (Instruction Compression -> Rules and Restrictions):
1080 * A compressed instruction must be in Align1 access mode. Align16
1081 * mode instructions cannot be compressed.
1083 * Similar text exists in the g45 PRM.
1085 * On these platforms, if we're building a SIMD16 shader, we need to
1086 * manually unroll to a pair of SIMD8 instructions.
1088 bool unroll_to_simd8
=
1089 (dispatch_width
== 16 &&
1090 (devinfo
->gen
== 4 || (devinfo
->gen
== 7 && !devinfo
->is_haswell
)));
1092 /* produce accurate derivatives */
1093 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1094 src
.negate
, src
.abs
,
1095 BRW_REGISTER_TYPE_F
,
1096 BRW_VERTICAL_STRIDE_4
,
1098 BRW_HORIZONTAL_STRIDE_1
,
1099 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
1100 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1101 src
.negate
, src
.abs
,
1102 BRW_REGISTER_TYPE_F
,
1103 BRW_VERTICAL_STRIDE_4
,
1105 BRW_HORIZONTAL_STRIDE_1
,
1106 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
1107 brw_push_insn_state(p
);
1108 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1109 if (unroll_to_simd8
) {
1110 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1111 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1113 brw_ADD(p
, firsthalf(dst
), firsthalf(src1
), negate(firsthalf(src0
)));
1114 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1115 brw_ADD(p
, sechalf(dst
), sechalf(src1
), negate(sechalf(src0
)));
1117 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), negate(firsthalf(src1
)));
1118 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1119 brw_ADD(p
, sechalf(dst
), sechalf(src0
), negate(sechalf(src1
)));
1123 brw_ADD(p
, dst
, src1
, negate(src0
));
1125 brw_ADD(p
, dst
, src0
, negate(src1
));
1127 brw_pop_insn_state(p
);
1129 /* replicate the derivative at the top-left pixel to other pixels */
1130 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1131 src
.negate
, src
.abs
,
1132 BRW_REGISTER_TYPE_F
,
1133 BRW_VERTICAL_STRIDE_4
,
1135 BRW_HORIZONTAL_STRIDE_0
,
1136 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1137 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
1138 src
.negate
, src
.abs
,
1139 BRW_REGISTER_TYPE_F
,
1140 BRW_VERTICAL_STRIDE_4
,
1142 BRW_HORIZONTAL_STRIDE_0
,
1143 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1145 brw_ADD(p
, dst
, src1
, negate(src0
));
1147 brw_ADD(p
, dst
, src0
, negate(src1
));
1152 fs_generator::generate_discard_jump(fs_inst
*inst
)
1154 assert(devinfo
->gen
>= 6);
1156 /* This HALT will be patched up at FB write time to point UIP at the end of
1157 * the program, and at brw_uip_jip() JIP will be set to the end of the
1158 * current block (or the program).
1160 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1162 brw_push_insn_state(p
);
1163 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1165 brw_pop_insn_state(p
);
1169 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1171 assert(inst
->mlen
!= 0);
1174 brw_uvec_mrf(inst
->exec_size
, (inst
->base_mrf
+ 1), 0),
1175 retype(src
, BRW_REGISTER_TYPE_UD
));
1176 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1177 inst
->exec_size
/ 8, inst
->offset
);
1181 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1183 assert(inst
->mlen
!= 0);
1185 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1186 inst
->exec_size
/ 8, inst
->offset
);
1190 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1192 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1196 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1198 struct brw_reg index
,
1199 struct brw_reg offset
)
1201 assert(inst
->mlen
!= 0);
1203 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1204 index
.type
== BRW_REGISTER_TYPE_UD
);
1205 uint32_t surf_index
= index
.ud
;
1207 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1208 offset
.type
== BRW_REGISTER_TYPE_UD
);
1209 uint32_t read_offset
= offset
.ud
;
1211 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1212 read_offset
, surf_index
);
1216 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1218 struct brw_reg index
,
1219 struct brw_reg offset
)
1221 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1223 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
1224 /* Reference just the dword we need, to avoid angering validate_reg(). */
1225 offset
= brw_vec1_grf(offset
.nr
, 0);
1227 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1228 * the destination loaded consecutively from the same offset (which appears
1229 * in the first component, and the rest are ignored).
1231 dst
.width
= BRW_WIDTH_4
;
1233 struct brw_reg src
= offset
;
1234 bool header_present
= false;
1236 if (devinfo
->gen
>= 9) {
1237 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1238 src
= retype(brw_vec4_grf(offset
.nr
, 0), BRW_REGISTER_TYPE_UD
);
1239 header_present
= true;
1241 brw_push_insn_state(p
);
1242 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1243 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1244 brw_MOV(p
, vec8(src
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1245 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1247 brw_MOV(p
, get_element_ud(src
, 2),
1248 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1249 brw_pop_insn_state(p
);
1252 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1254 uint32_t surf_index
= index
.ud
;
1256 brw_push_insn_state(p
);
1257 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1258 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1259 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1260 brw_pop_insn_state(p
);
1262 brw_set_dest(p
, send
, dst
);
1263 brw_set_src0(p
, send
, src
);
1264 brw_set_sampler_message(p
, send
,
1266 0, /* LD message ignores sampler unit */
1267 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1271 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1275 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1277 brw_push_insn_state(p
);
1278 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1279 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1281 /* a0.0 = surf_index & 0xff */
1282 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1283 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1284 brw_set_dest(p
, insn_and
, addr
);
1285 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1286 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1288 /* dst = send(payload, a0.0 | <descriptor>) */
1289 brw_inst
*insn
= brw_send_indirect_message(
1290 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1291 brw_set_sampler_message(p
, insn
,
1293 0, /* LD message ignores sampler unit */
1294 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1298 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1301 brw_pop_insn_state(p
);
1306 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
1308 struct brw_reg index
,
1309 struct brw_reg offset
)
1311 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1312 assert(inst
->header_size
!= 0);
1315 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1316 index
.type
== BRW_REGISTER_TYPE_UD
);
1317 uint32_t surf_index
= index
.ud
;
1319 uint32_t simd_mode
, rlen
, msg_type
;
1320 if (dispatch_width
== 16) {
1321 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1324 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1328 if (devinfo
->gen
>= 5)
1329 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1331 /* We always use the SIMD16 message so that we only have to load U, and
1334 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1335 assert(inst
->mlen
== 3);
1336 assert(inst
->regs_written
== 8);
1338 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1341 struct brw_reg offset_mrf
= retype(brw_message_reg(inst
->base_mrf
+ 1),
1342 BRW_REGISTER_TYPE_D
);
1343 brw_MOV(p
, offset_mrf
, offset
);
1345 struct brw_reg header
= brw_vec8_grf(0, 0);
1346 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1348 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1349 brw_inst_set_qtr_control(p
->devinfo
, send
, BRW_COMPRESSION_NONE
);
1350 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1351 brw_set_src0(p
, send
, header
);
1352 if (devinfo
->gen
< 6)
1353 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1355 /* Our surface is set up as floats, regardless of what actual data is
1358 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1359 brw_set_sampler_message(p
, send
,
1361 0, /* sampler (unused) */
1365 inst
->header_size
!= 0,
1371 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1373 struct brw_reg index
,
1374 struct brw_reg offset
)
1376 assert(devinfo
->gen
>= 7);
1377 /* Varying-offset pull constant loads are treated as a normal expression on
1378 * gen7, so the fact that it's a send message is hidden at the IR level.
1380 assert(inst
->header_size
== 0);
1381 assert(!inst
->mlen
);
1382 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1384 uint32_t simd_mode
, rlen
, mlen
;
1385 if (dispatch_width
== 16) {
1388 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1392 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1395 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1397 uint32_t surf_index
= index
.ud
;
1399 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1400 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1401 brw_set_src0(p
, send
, offset
);
1402 brw_set_sampler_message(p
, send
,
1404 0, /* LD message ignores sampler unit */
1405 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1408 false, /* no header */
1414 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1416 brw_push_insn_state(p
);
1417 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1418 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1420 /* a0.0 = surf_index & 0xff */
1421 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1422 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1423 brw_set_dest(p
, insn_and
, addr
);
1424 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1425 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1427 brw_pop_insn_state(p
);
1429 /* dst = send(offset, a0.0 | <descriptor>) */
1430 brw_inst
*insn
= brw_send_indirect_message(
1431 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1433 brw_set_sampler_message(p
, insn
,
1436 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1446 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1447 * into the flags register (f0.0).
1449 * Used only on Gen6 and above.
1452 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1454 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1455 struct brw_reg dispatch_mask
;
1457 if (devinfo
->gen
>= 6)
1458 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1460 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1462 brw_push_insn_state(p
);
1463 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1464 brw_MOV(p
, flags
, dispatch_mask
);
1465 brw_pop_insn_state(p
);
1469 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1472 struct brw_reg msg_data
,
1475 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1477 brw_pixel_interpolator_query(p
,
1478 retype(dst
, BRW_REGISTER_TYPE_UW
),
1480 inst
->pi_noperspective
,
1484 inst
->regs_written
);
1489 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1490 * sampler LD messages.
1492 * We don't want to bake it into the send message's code generation because
1493 * that means we don't get a chance to schedule the instructions.
1496 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
1498 struct brw_reg value
)
1500 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1502 brw_push_insn_state(p
);
1503 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1504 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1505 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1506 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
1507 brw_pop_insn_state(p
);
1510 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1511 * the ADD instruction.
1514 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1516 struct brw_reg src0
,
1517 struct brw_reg src1
)
1519 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1520 dst
.type
== BRW_REGISTER_TYPE_UD
);
1521 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1522 src0
.type
== BRW_REGISTER_TYPE_UD
);
1524 struct brw_reg reg
= stride(src1
, 1, 4, 0);
1525 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
1526 brw_ADD(p
, dst
, src0
, reg
);
1527 } else if (dispatch_width
== 16) {
1528 brw_push_insn_state(p
);
1529 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1530 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1531 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1532 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1533 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1534 brw_pop_insn_state(p
);
1539 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1544 assert(devinfo
->gen
>= 7);
1545 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1546 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1547 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1549 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1551 * Because this instruction does not have a 16-bit floating-point type,
1552 * the destination data type must be Word (W).
1554 * The destination must be DWord-aligned and specify a horizontal stride
1555 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1556 * each destination channel and the upper word is not modified.
1558 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1560 /* Give each 32-bit channel of dst the form below, where "." means
1564 brw_F32TO16(p
, dst_w
, y
);
1569 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1571 /* And, finally the form of packHalf2x16's output:
1574 brw_F32TO16(p
, dst_w
, x
);
1578 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1582 assert(devinfo
->gen
>= 7);
1583 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1584 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1586 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1588 * Because this instruction does not have a 16-bit floating-point type,
1589 * the source data type must be Word (W). The destination type must be
1592 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1594 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1595 * For the Y case, we wish to access only the upper word; therefore
1596 * a 16-bit subregister offset is needed.
1598 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1599 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1600 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1603 brw_F16TO32(p
, dst
, src_w
);
1607 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1608 struct brw_reg payload
,
1609 struct brw_reg offset
,
1610 struct brw_reg value
)
1612 assert(devinfo
->gen
>= 7);
1613 brw_push_insn_state(p
);
1614 brw_set_default_mask_control(p
, true);
1616 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1617 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1619 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1622 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1623 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1624 value
.width
= BRW_WIDTH_1
;
1625 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1626 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1628 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1631 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1632 * case, and we don't really care about squeezing every bit of performance
1633 * out of this path, so we just emit the MOVs from here.
1635 brw_MOV(p
, payload_offset
, offset
);
1636 brw_MOV(p
, payload_value
, value
);
1637 brw_shader_time_add(p
, payload
,
1638 prog_data
->binding_table
.shader_time_start
);
1639 brw_pop_insn_state(p
);
1641 brw_mark_surface_used(prog_data
,
1642 prog_data
->binding_table
.shader_time_start
);
1646 fs_generator::enable_debug(const char *shader_name
)
1649 this->shader_name
= shader_name
;
1653 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1655 /* align to 64 byte boundary. */
1656 while (p
->next_insn_offset
% 64)
1659 this->dispatch_width
= dispatch_width
;
1660 if (dispatch_width
== 16)
1661 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1663 int start_offset
= p
->next_insn_offset
;
1664 int spill_count
= 0, fill_count
= 0;
1667 struct annotation_info annotation
;
1668 memset(&annotation
, 0, sizeof(annotation
));
1670 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1671 struct brw_reg src
[3], dst
;
1672 unsigned int last_insn_offset
= p
->next_insn_offset
;
1673 bool multiple_instructions_emitted
= false;
1675 if (unlikely(debug_flag
))
1676 annotate(p
->devinfo
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1678 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1679 src
[i
] = brw_reg_from_fs_reg(inst
, &inst
->src
[i
], devinfo
->gen
);
1681 /* The accumulator result appears to get used for the
1682 * conditional modifier generation. When negating a UD
1683 * value, there is a 33rd bit generated for the sign in the
1684 * accumulator value, so now you can't check, for example,
1685 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1687 assert(!inst
->conditional_mod
||
1688 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1689 !inst
->src
[i
].negate
);
1691 dst
= brw_reg_from_fs_reg(inst
, &inst
->dst
, devinfo
->gen
);
1693 brw_set_default_predicate_control(p
, inst
->predicate
);
1694 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1695 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1696 brw_set_default_saturate(p
, inst
->saturate
);
1697 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1698 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1699 brw_set_default_exec_size(p
, cvt(inst
->exec_size
) - 1);
1701 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1702 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1704 switch (inst
->exec_size
) {
1708 assert(inst
->force_writemask_all
);
1709 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1712 if (inst
->force_sechalf
) {
1713 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1715 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1720 /* If the instruction writes to more than one register, it needs to
1721 * be a "compressed" instruction on Gen <= 5.
1723 if (inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
)
1724 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1726 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1729 unreachable("Invalid instruction width");
1732 switch (inst
->opcode
) {
1733 case BRW_OPCODE_MOV
:
1734 brw_MOV(p
, dst
, src
[0]);
1736 case BRW_OPCODE_ADD
:
1737 brw_ADD(p
, dst
, src
[0], src
[1]);
1739 case BRW_OPCODE_MUL
:
1740 brw_MUL(p
, dst
, src
[0], src
[1]);
1742 case BRW_OPCODE_AVG
:
1743 brw_AVG(p
, dst
, src
[0], src
[1]);
1745 case BRW_OPCODE_MACH
:
1746 brw_MACH(p
, dst
, src
[0], src
[1]);
1749 case BRW_OPCODE_LINE
:
1750 brw_LINE(p
, dst
, src
[0], src
[1]);
1753 case BRW_OPCODE_MAD
:
1754 assert(devinfo
->gen
>= 6);
1755 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1756 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1757 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1758 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1759 brw_inst
*f
= brw_MAD(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1760 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1761 brw_inst
*s
= brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1762 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1764 if (inst
->conditional_mod
) {
1765 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1766 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1767 multiple_instructions_emitted
= true;
1770 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1772 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1775 case BRW_OPCODE_LRP
:
1776 assert(devinfo
->gen
>= 6);
1777 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1778 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1779 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1780 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1781 brw_inst
*f
= brw_LRP(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1782 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1783 brw_inst
*s
= brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1784 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1786 if (inst
->conditional_mod
) {
1787 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1788 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1789 multiple_instructions_emitted
= true;
1792 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1794 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1797 case BRW_OPCODE_FRC
:
1798 brw_FRC(p
, dst
, src
[0]);
1800 case BRW_OPCODE_RNDD
:
1801 brw_RNDD(p
, dst
, src
[0]);
1803 case BRW_OPCODE_RNDE
:
1804 brw_RNDE(p
, dst
, src
[0]);
1806 case BRW_OPCODE_RNDZ
:
1807 brw_RNDZ(p
, dst
, src
[0]);
1810 case BRW_OPCODE_AND
:
1811 brw_AND(p
, dst
, src
[0], src
[1]);
1814 brw_OR(p
, dst
, src
[0], src
[1]);
1816 case BRW_OPCODE_XOR
:
1817 brw_XOR(p
, dst
, src
[0], src
[1]);
1819 case BRW_OPCODE_NOT
:
1820 brw_NOT(p
, dst
, src
[0]);
1822 case BRW_OPCODE_ASR
:
1823 brw_ASR(p
, dst
, src
[0], src
[1]);
1825 case BRW_OPCODE_SHR
:
1826 brw_SHR(p
, dst
, src
[0], src
[1]);
1828 case BRW_OPCODE_SHL
:
1829 brw_SHL(p
, dst
, src
[0], src
[1]);
1831 case BRW_OPCODE_F32TO16
:
1832 assert(devinfo
->gen
>= 7);
1833 brw_F32TO16(p
, dst
, src
[0]);
1835 case BRW_OPCODE_F16TO32
:
1836 assert(devinfo
->gen
>= 7);
1837 brw_F16TO32(p
, dst
, src
[0]);
1839 case BRW_OPCODE_CMP
:
1840 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1841 * that when the destination is a GRF that the dependency-clear bit on
1842 * the flag register is cleared early.
1844 * Suggested workarounds are to disable coissuing CMP instructions
1845 * or to split CMP(16) instructions into two CMP(8) instructions.
1847 * We choose to split into CMP(8) instructions since disabling
1848 * coissuing would affect CMP instructions not otherwise affected by
1851 if (dispatch_width
== 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1852 if (dst
.file
== BRW_GENERAL_REGISTER_FILE
) {
1853 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1854 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1855 brw_CMP(p
, firsthalf(dst
), inst
->conditional_mod
,
1856 firsthalf(src
[0]), firsthalf(src
[1]));
1857 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1858 brw_CMP(p
, sechalf(dst
), inst
->conditional_mod
,
1859 sechalf(src
[0]), sechalf(src
[1]));
1860 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1862 multiple_instructions_emitted
= true;
1863 } else if (dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1864 /* For unknown reasons, the aforementioned workaround is not
1865 * sufficient. Overriding the type when the destination is the
1866 * null register is necessary but not sufficient by itself.
1868 assert(dst
.nr
== BRW_ARF_NULL
);
1869 dst
.type
= BRW_REGISTER_TYPE_D
;
1870 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1872 unreachable("not reached");
1875 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1878 case BRW_OPCODE_SEL
:
1879 brw_SEL(p
, dst
, src
[0], src
[1]);
1881 case BRW_OPCODE_BFREV
:
1882 assert(devinfo
->gen
>= 7);
1883 /* BFREV only supports UD type for src and dst. */
1884 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1885 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1887 case BRW_OPCODE_FBH
:
1888 assert(devinfo
->gen
>= 7);
1889 /* FBH only supports UD type for dst. */
1890 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1892 case BRW_OPCODE_FBL
:
1893 assert(devinfo
->gen
>= 7);
1894 /* FBL only supports UD type for dst. */
1895 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1897 case BRW_OPCODE_CBIT
:
1898 assert(devinfo
->gen
>= 7);
1899 /* CBIT only supports UD type for dst. */
1900 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1902 case BRW_OPCODE_ADDC
:
1903 assert(devinfo
->gen
>= 7);
1904 brw_ADDC(p
, dst
, src
[0], src
[1]);
1906 case BRW_OPCODE_SUBB
:
1907 assert(devinfo
->gen
>= 7);
1908 brw_SUBB(p
, dst
, src
[0], src
[1]);
1910 case BRW_OPCODE_MAC
:
1911 brw_MAC(p
, dst
, src
[0], src
[1]);
1914 case BRW_OPCODE_BFE
:
1915 assert(devinfo
->gen
>= 7);
1916 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1917 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1918 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1919 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1920 brw_BFE(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1921 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1922 brw_BFE(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1923 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1925 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1927 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1930 case BRW_OPCODE_BFI1
:
1931 assert(devinfo
->gen
>= 7);
1932 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1935 * "Force BFI instructions to be executed always in SIMD8."
1937 if (dispatch_width
== 16 && devinfo
->is_haswell
) {
1938 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1939 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1940 brw_BFI1(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]));
1941 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1942 brw_BFI1(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]));
1943 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1945 brw_BFI1(p
, dst
, src
[0], src
[1]);
1948 case BRW_OPCODE_BFI2
:
1949 assert(devinfo
->gen
>= 7);
1950 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1951 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1954 * "Force BFI instructions to be executed always in SIMD8."
1956 * Otherwise we would be able to emit compressed instructions like we
1957 * do for the other three-source instructions.
1959 if (dispatch_width
== 16 &&
1960 (devinfo
->is_haswell
|| !devinfo
->supports_simd16_3src
)) {
1961 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1962 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1963 brw_BFI2(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1964 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1965 brw_BFI2(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1966 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1968 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1970 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1974 if (inst
->src
[0].file
!= BAD_FILE
) {
1975 /* The instruction has an embedded compare (only allowed on gen6) */
1976 assert(devinfo
->gen
== 6);
1977 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1979 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1983 case BRW_OPCODE_ELSE
:
1986 case BRW_OPCODE_ENDIF
:
1991 brw_DO(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1994 case BRW_OPCODE_BREAK
:
1996 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1998 case BRW_OPCODE_CONTINUE
:
2000 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
2003 case BRW_OPCODE_WHILE
:
2008 case SHADER_OPCODE_RCP
:
2009 case SHADER_OPCODE_RSQ
:
2010 case SHADER_OPCODE_SQRT
:
2011 case SHADER_OPCODE_EXP2
:
2012 case SHADER_OPCODE_LOG2
:
2013 case SHADER_OPCODE_SIN
:
2014 case SHADER_OPCODE_COS
:
2015 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
2016 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2017 if (devinfo
->gen
>= 7) {
2018 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
2020 } else if (devinfo
->gen
== 6) {
2021 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
2022 } else if (devinfo
->gen
== 5 || devinfo
->is_g4x
) {
2023 generate_math_g45(inst
, dst
, src
[0]);
2025 generate_math_gen4(inst
, dst
, src
[0]);
2028 case SHADER_OPCODE_INT_QUOTIENT
:
2029 case SHADER_OPCODE_INT_REMAINDER
:
2030 case SHADER_OPCODE_POW
:
2031 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
2032 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2033 if (devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) {
2034 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
2035 } else if (devinfo
->gen
>= 6) {
2036 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
2038 generate_math_gen4(inst
, dst
, src
[0]);
2041 case FS_OPCODE_CINTERP
:
2042 brw_MOV(p
, dst
, src
[0]);
2044 case FS_OPCODE_LINTERP
:
2045 generate_linterp(inst
, dst
, src
);
2047 case FS_OPCODE_PIXEL_X
:
2048 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2049 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2050 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2052 case FS_OPCODE_PIXEL_Y
:
2053 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2054 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2055 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2057 case FS_OPCODE_GET_BUFFER_SIZE
:
2058 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2060 case SHADER_OPCODE_TEX
:
2062 case SHADER_OPCODE_TXD
:
2063 case SHADER_OPCODE_TXF
:
2064 case SHADER_OPCODE_TXF_CMS
:
2065 case SHADER_OPCODE_TXF_CMS_W
:
2066 case SHADER_OPCODE_TXF_UMS
:
2067 case SHADER_OPCODE_TXF_MCS
:
2068 case SHADER_OPCODE_TXL
:
2069 case SHADER_OPCODE_TXS
:
2070 case SHADER_OPCODE_LOD
:
2071 case SHADER_OPCODE_TG4
:
2072 case SHADER_OPCODE_TG4_OFFSET
:
2073 case SHADER_OPCODE_SAMPLEINFO
:
2074 generate_tex(inst
, dst
, src
[0], src
[1], src
[2]);
2076 case FS_OPCODE_DDX_COARSE
:
2077 case FS_OPCODE_DDX_FINE
:
2078 generate_ddx(inst
->opcode
, dst
, src
[0]);
2080 case FS_OPCODE_DDY_COARSE
:
2081 case FS_OPCODE_DDY_FINE
:
2082 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2083 generate_ddy(inst
->opcode
, dst
, src
[0], src
[1].ud
);
2086 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2087 generate_scratch_write(inst
, src
[0]);
2091 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2092 generate_scratch_read(inst
, dst
);
2096 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2097 generate_scratch_read_gen7(inst
, dst
);
2101 case SHADER_OPCODE_MOV_INDIRECT
:
2102 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2105 case SHADER_OPCODE_URB_READ_SIMD8
:
2106 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2107 generate_urb_read(inst
, dst
, src
[0]);
2110 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2111 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2112 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2113 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2114 generate_urb_write(inst
, src
[0]);
2117 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2118 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2121 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2122 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2125 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
2126 generate_varying_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2129 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
2130 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2133 case FS_OPCODE_REP_FB_WRITE
:
2134 case FS_OPCODE_FB_WRITE
:
2135 generate_fb_write(inst
, src
[0]);
2138 case FS_OPCODE_BLORP_FB_WRITE
:
2139 generate_blorp_fb_write(inst
);
2142 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
2143 generate_mov_dispatch_to_flags(inst
);
2146 case FS_OPCODE_DISCARD_JUMP
:
2147 generate_discard_jump(inst
);
2150 case SHADER_OPCODE_SHADER_TIME_ADD
:
2151 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2154 case SHADER_OPCODE_UNTYPED_ATOMIC
:
2155 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2156 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
,
2157 inst
->mlen
, !inst
->dst
.is_null());
2160 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
2161 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2162 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2163 inst
->mlen
, src
[2].ud
);
2166 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2167 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2168 brw_untyped_surface_write(p
, src
[0], src
[1],
2169 inst
->mlen
, src
[2].ud
);
2172 case SHADER_OPCODE_TYPED_ATOMIC
:
2173 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2174 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2175 src
[2].ud
, inst
->mlen
, !inst
->dst
.is_null());
2178 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2179 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2180 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2181 inst
->mlen
, src
[2].ud
);
2184 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2185 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2186 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].ud
);
2189 case SHADER_OPCODE_MEMORY_FENCE
:
2190 brw_memory_fence(p
, dst
);
2193 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
2194 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
2197 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2198 brw_find_live_channel(p
, dst
);
2201 case SHADER_OPCODE_BROADCAST
:
2202 brw_broadcast(p
, dst
, src
[0], src
[1]);
2205 case FS_OPCODE_SET_SAMPLE_ID
:
2206 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2209 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2210 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2213 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2214 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2215 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2218 case FS_OPCODE_PLACEHOLDER_HALT
:
2219 /* This is the place where the final HALT needs to be inserted if
2220 * we've emitted any discards. If not, this will emit no code.
2222 if (!patch_discard_jumps_to_fb_writes()) {
2223 if (unlikely(debug_flag
)) {
2224 annotation
.ann_count
--;
2229 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
2230 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2231 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID
);
2234 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2235 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2236 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2239 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2240 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2241 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2244 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2245 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2246 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2249 case CS_OPCODE_CS_TERMINATE
:
2250 generate_cs_terminate(inst
, src
[0]);
2253 case SHADER_OPCODE_BARRIER
:
2254 generate_barrier(inst
, src
[0]);
2257 case FS_OPCODE_PACK_STENCIL_REF
:
2258 generate_stencil_ref_packing(inst
, dst
, src
[0]);
2262 unreachable("Unsupported opcode");
2264 case SHADER_OPCODE_LOAD_PAYLOAD
:
2265 unreachable("Should be lowered by lower_load_payload()");
2268 if (multiple_instructions_emitted
)
2271 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2272 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2273 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2274 "emitting more than 1 instruction");
2276 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2278 if (inst
->conditional_mod
)
2279 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2280 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2281 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2286 annotation_finalize(&annotation
, p
->next_insn_offset
);
2289 bool validated
= brw_validate_instructions(p
, start_offset
, &annotation
);
2291 if (unlikely(debug_flag
))
2292 brw_validate_instructions(p
, start_offset
, &annotation
);
2295 int before_size
= p
->next_insn_offset
- start_offset
;
2296 brw_compact_instructions(p
, start_offset
, annotation
.ann_count
,
2298 int after_size
= p
->next_insn_offset
- start_offset
;
2300 if (unlikely(debug_flag
)) {
2301 fprintf(stderr
, "Native code for %s\n"
2302 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2303 " bytes (%.0f%%)\n",
2304 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2305 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2306 100.0f
* (before_size
- after_size
) / before_size
);
2308 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
,
2310 ralloc_free(annotation
.mem_ctx
);
2314 compiler
->shader_debug_log(log_data
,
2315 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2316 "%d:%d spills:fills, Promoted %u constants, "
2317 "compacted %d to %d bytes.\n",
2318 stage_abbrev
, dispatch_width
, before_size
/ 16,
2319 loop_count
, cfg
->cycle_count
, spill_count
,
2320 fill_count
, promoted_constants
, before_size
,
2323 return start_offset
;
2327 fs_generator::get_assembly(unsigned int *assembly_size
)
2329 return brw_get_program(p
, assembly_size
);