2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
25 #include "main/shaderimage.h"
27 #include "brw_fs_surface_builder.h"
29 #include "brw_program.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
43 nir_emit_system_values();
45 /* get the main function and emit it */
46 nir_foreach_function(nir
, function
) {
47 assert(strcmp(function
->name
, "main") == 0);
48 assert(function
->impl
);
49 nir_emit_impl(function
->impl
);
54 fs_visitor::nir_setup_inputs()
56 if (stage
!= MESA_SHADER_FRAGMENT
)
59 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
61 nir_foreach_variable(var
, &nir
->inputs
) {
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
65 if (var
->data
.location
== VARYING_SLOT_POS
) {
66 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
67 var
->data
.origin_upper_left
);
68 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
70 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
71 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
72 reg
.type
= BRW_REGISTER_TYPE_D
;
73 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
74 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
75 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
76 reg
.type
= BRW_REGISTER_TYPE_D
;
77 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 int location
= var
->data
.location
;
80 emit_general_interpolation(&input
, var
->name
, var
->type
,
81 (glsl_interp_qualifier
) var
->data
.interpolation
,
82 &location
, var
->data
.centroid
,
89 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
90 const glsl_type
*type
,
93 if (type
->is_array() || type
->is_matrix()) {
94 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
95 const unsigned length
= glsl_get_length(type
);
97 for (unsigned i
= 0; i
< length
; i
++) {
98 nir_setup_single_output_varying(reg
, elem_type
, location
);
100 } else if (type
->is_record()) {
101 for (unsigned i
= 0; i
< type
->length
; i
++) {
102 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
103 nir_setup_single_output_varying(reg
, field_type
, location
);
106 assert(type
->is_scalar() || type
->is_vector());
107 this->outputs
[*location
] = *reg
;
108 this->output_components
[*location
] = type
->vector_elements
;
109 *reg
= offset(*reg
, bld
, 4);
115 fs_visitor::nir_setup_outputs()
117 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
119 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
121 nir_foreach_variable(var
, &nir
->outputs
) {
122 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
125 case MESA_SHADER_VERTEX
:
126 case MESA_SHADER_TESS_EVAL
:
127 case MESA_SHADER_GEOMETRY
: {
128 unsigned location
= var
->data
.location
;
129 nir_setup_single_output_varying(®
, var
->type
, &location
);
132 case MESA_SHADER_FRAGMENT
:
133 if (key
->force_dual_color_blend
&&
134 var
->data
.location
== FRAG_RESULT_DATA1
) {
135 this->dual_src_output
= reg
;
136 this->do_dual_src
= true;
137 } else if (var
->data
.index
> 0) {
138 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
139 assert(var
->data
.index
== 1);
140 this->dual_src_output
= reg
;
141 this->do_dual_src
= true;
142 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
143 /* Writing gl_FragColor outputs to all color regions. */
144 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
145 this->outputs
[i
] = reg
;
146 this->output_components
[i
] = 4;
148 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
149 this->frag_depth
= reg
;
150 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
151 this->frag_stencil
= reg
;
152 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
153 this->sample_mask
= reg
;
155 int vector_elements
= var
->type
->without_array()->vector_elements
;
157 /* gl_FragData or a user-defined FS output */
158 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
159 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
161 /* General color output. */
162 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
163 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
164 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
165 this->output_components
[output
] = vector_elements
;
170 unreachable("unhandled shader stage");
176 fs_visitor::nir_setup_uniforms()
178 if (dispatch_width
!= 8)
181 uniforms
= nir
->num_uniforms
/ 4;
183 nir_foreach_variable(var
, &nir
->uniforms
) {
184 /* UBO's and atomics don't take up space in the uniform file */
185 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
188 if (type_size_scalar(var
->type
) > 0)
189 param_size
[var
->data
.driver_location
/ 4] = type_size_scalar(var
->type
);
194 emit_system_values_block(nir_block
*block
, void *void_visitor
)
196 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
199 nir_foreach_instr(block
, instr
) {
200 if (instr
->type
!= nir_instr_type_intrinsic
)
203 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
204 switch (intrin
->intrinsic
) {
205 case nir_intrinsic_load_vertex_id
:
206 unreachable("should be lowered by lower_vertex_id().");
208 case nir_intrinsic_load_vertex_id_zero_base
:
209 assert(v
->stage
== MESA_SHADER_VERTEX
);
210 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
211 if (reg
->file
== BAD_FILE
)
212 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
215 case nir_intrinsic_load_base_vertex
:
216 assert(v
->stage
== MESA_SHADER_VERTEX
);
217 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
218 if (reg
->file
== BAD_FILE
)
219 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
222 case nir_intrinsic_load_instance_id
:
223 assert(v
->stage
== MESA_SHADER_VERTEX
);
224 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
225 if (reg
->file
== BAD_FILE
)
226 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
229 case nir_intrinsic_load_base_instance
:
230 assert(v
->stage
== MESA_SHADER_VERTEX
);
231 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
232 if (reg
->file
== BAD_FILE
)
233 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
236 case nir_intrinsic_load_draw_id
:
237 assert(v
->stage
== MESA_SHADER_VERTEX
);
238 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
239 if (reg
->file
== BAD_FILE
)
240 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
243 case nir_intrinsic_load_invocation_id
:
244 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
245 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
246 if (reg
->file
== BAD_FILE
) {
247 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
248 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
249 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
250 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
255 case nir_intrinsic_load_sample_pos
:
256 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
257 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
258 if (reg
->file
== BAD_FILE
)
259 *reg
= *v
->emit_samplepos_setup();
262 case nir_intrinsic_load_sample_id
:
263 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
264 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
265 if (reg
->file
== BAD_FILE
)
266 *reg
= *v
->emit_sampleid_setup();
269 case nir_intrinsic_load_sample_mask_in
:
270 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
271 assert(v
->devinfo
->gen
>= 7);
272 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
273 if (reg
->file
== BAD_FILE
)
274 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
275 BRW_REGISTER_TYPE_D
));
278 case nir_intrinsic_load_local_invocation_id
:
279 assert(v
->stage
== MESA_SHADER_COMPUTE
);
280 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
281 if (reg
->file
== BAD_FILE
)
282 *reg
= *v
->emit_cs_local_invocation_id_setup();
285 case nir_intrinsic_load_work_group_id
:
286 assert(v
->stage
== MESA_SHADER_COMPUTE
);
287 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
288 if (reg
->file
== BAD_FILE
)
289 *reg
= *v
->emit_cs_work_group_id_setup();
292 case nir_intrinsic_load_helper_invocation
:
293 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
294 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
295 if (reg
->file
== BAD_FILE
) {
296 const fs_builder abld
=
297 v
->bld
.annotate("gl_HelperInvocation", NULL
);
299 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
300 * pixel mask is in g1.7 of the thread payload.
302 * We move the per-channel pixel enable bit to the low bit of each
303 * channel by shifting the byte containing the pixel mask by the
304 * vector immediate 0x76543210UV.
306 * The region of <1,8,0> reads only 1 byte (the pixel masks for
307 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
308 * masks for 2 and 3) in SIMD16.
310 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
312 stride(byte_offset(retype(brw_vec1_grf(1, 0),
313 BRW_REGISTER_TYPE_UB
), 28),
315 brw_imm_uv(0x76543210));
317 /* A set bit in the pixel mask means the channel is enabled, but
318 * that is the opposite of gl_HelperInvocation so we need to invert
321 * The negate source-modifier bit of logical instructions on Gen8+
322 * performs 1's complement negation, so we can use that instead of
325 fs_reg inverted
= negate(shifted
);
326 if (v
->devinfo
->gen
< 8) {
327 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
328 abld
.NOT(inverted
, shifted
);
331 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
332 * with 1 and negating.
334 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
335 abld
.AND(anded
, inverted
, brw_imm_uw(1));
337 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
338 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
352 fs_visitor::nir_emit_system_values()
354 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
355 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
356 nir_system_values
[i
] = fs_reg();
359 nir_foreach_function(nir
, function
) {
360 assert(strcmp(function
->name
, "main") == 0);
361 assert(function
->impl
);
362 nir_foreach_block(function
->impl
, emit_system_values_block
, this);
367 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
369 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
370 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
371 nir_locals
[i
] = fs_reg();
374 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
375 unsigned array_elems
=
376 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
377 unsigned size
= array_elems
* reg
->num_components
;
378 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
381 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
384 nir_emit_cf_list(&impl
->body
);
388 fs_visitor::nir_emit_cf_list(exec_list
*list
)
390 exec_list_validate(list
);
391 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
392 switch (node
->type
) {
394 nir_emit_if(nir_cf_node_as_if(node
));
397 case nir_cf_node_loop
:
398 nir_emit_loop(nir_cf_node_as_loop(node
));
401 case nir_cf_node_block
:
402 nir_emit_block(nir_cf_node_as_block(node
));
406 unreachable("Invalid CFG node block");
412 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
414 /* first, put the condition into f0 */
415 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
416 retype(get_nir_src(if_stmt
->condition
),
417 BRW_REGISTER_TYPE_D
));
418 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
420 bld
.IF(BRW_PREDICATE_NORMAL
);
422 nir_emit_cf_list(&if_stmt
->then_list
);
424 /* note: if the else is empty, dead CF elimination will remove it */
425 bld
.emit(BRW_OPCODE_ELSE
);
427 nir_emit_cf_list(&if_stmt
->else_list
);
429 bld
.emit(BRW_OPCODE_ENDIF
);
433 fs_visitor::nir_emit_loop(nir_loop
*loop
)
435 bld
.emit(BRW_OPCODE_DO
);
437 nir_emit_cf_list(&loop
->body
);
439 bld
.emit(BRW_OPCODE_WHILE
);
443 fs_visitor::nir_emit_block(nir_block
*block
)
445 nir_foreach_instr(block
, instr
) {
446 nir_emit_instr(instr
);
451 fs_visitor::nir_emit_instr(nir_instr
*instr
)
453 const fs_builder abld
= bld
.annotate(NULL
, instr
);
455 switch (instr
->type
) {
456 case nir_instr_type_alu
:
457 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
460 case nir_instr_type_intrinsic
:
462 case MESA_SHADER_VERTEX
:
463 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_TESS_EVAL
:
466 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_GEOMETRY
:
469 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_FRAGMENT
:
472 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 case MESA_SHADER_COMPUTE
:
475 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 unreachable("unsupported shader stage");
482 case nir_instr_type_tex
:
483 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
486 case nir_instr_type_load_const
:
487 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
490 case nir_instr_type_ssa_undef
:
491 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
494 case nir_instr_type_jump
:
495 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
499 unreachable("unknown instruction type");
504 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
505 const fs_reg
&result
)
507 if (!instr
->src
[0].src
.is_ssa
||
508 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
511 nir_intrinsic_instr
*src0
=
512 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
514 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
517 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
518 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
521 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
522 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
525 fs_reg tmp
= vgrf(glsl_type::int_type
);
527 if (devinfo
->gen
>= 6) {
528 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
529 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
531 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
533 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
534 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
536 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
538 * This negation looks like it's safe in practice, because bits 0:4 will
539 * surely be TRIANGLES
542 if (value1
->f
[0] == -1.0f
) {
546 tmp
.type
= BRW_REGISTER_TYPE_W
;
547 tmp
.subreg_offset
= 2;
550 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
552 tmp
.type
= BRW_REGISTER_TYPE_D
;
553 tmp
.subreg_offset
= 0;
556 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
557 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
559 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
561 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
562 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
564 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
566 * This negation looks like it's safe in practice, because bits 0:4 will
567 * surely be TRIANGLES
570 if (value1
->f
[0] == -1.0f
) {
574 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
576 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
582 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
584 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
587 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
588 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
591 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
592 op
[i
] = get_nir_src(instr
->src
[i
].src
);
593 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
594 op
[i
].abs
= instr
->src
[i
].abs
;
595 op
[i
].negate
= instr
->src
[i
].negate
;
598 /* We get a bunch of mov's out of the from_ssa pass and they may still
599 * be vectorized. We'll handle them as a special-case. We'll also
600 * handle vecN here because it's basically the same thing.
608 fs_reg temp
= result
;
609 bool need_extra_copy
= false;
610 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
611 if (!instr
->src
[i
].src
.is_ssa
&&
612 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
613 need_extra_copy
= true;
614 temp
= bld
.vgrf(result
.type
, 4);
619 for (unsigned i
= 0; i
< 4; i
++) {
620 if (!(instr
->dest
.write_mask
& (1 << i
)))
623 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
624 inst
= bld
.MOV(offset(temp
, bld
, i
),
625 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
627 inst
= bld
.MOV(offset(temp
, bld
, i
),
628 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
630 inst
->saturate
= instr
->dest
.saturate
;
633 /* In this case the source and destination registers were the same,
634 * so we need to insert an extra set of moves in order to deal with
637 if (need_extra_copy
) {
638 for (unsigned i
= 0; i
< 4; i
++) {
639 if (!(instr
->dest
.write_mask
& (1 << i
)))
642 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
651 /* At this point, we have dealt with any instruction that operates on
652 * more than a single channel. Therefore, we can just adjust the source
653 * and destination registers for that channel and emit the instruction.
655 unsigned channel
= 0;
656 if (nir_op_infos
[instr
->op
].output_size
== 0) {
657 /* Since NIR is doing the scalarizing for us, we should only ever see
658 * vectorized operations with a single channel.
660 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
661 channel
= ffs(instr
->dest
.write_mask
) - 1;
663 result
= offset(result
, bld
, channel
);
666 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
667 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
668 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
674 inst
= bld
.MOV(result
, op
[0]);
675 inst
->saturate
= instr
->dest
.saturate
;
680 bld
.MOV(result
, op
[0]);
684 /* AND(val, 0x80000000) gives the sign bit.
686 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
689 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
691 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
692 op
[0].type
= BRW_REGISTER_TYPE_UD
;
693 result
.type
= BRW_REGISTER_TYPE_UD
;
694 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
696 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
697 inst
->predicate
= BRW_PREDICATE_NORMAL
;
698 if (instr
->dest
.saturate
) {
699 inst
= bld
.MOV(result
, result
);
700 inst
->saturate
= true;
706 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
707 * -> non-negative val generates 0x00000000.
708 * Predicated OR sets 1 if val is positive.
710 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
711 bld
.ASR(result
, op
[0], brw_imm_d(31));
712 inst
= bld
.OR(result
, result
, brw_imm_d(1));
713 inst
->predicate
= BRW_PREDICATE_NORMAL
;
717 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
718 inst
->saturate
= instr
->dest
.saturate
;
722 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
723 inst
->saturate
= instr
->dest
.saturate
;
727 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
728 inst
->saturate
= instr
->dest
.saturate
;
732 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
733 inst
->saturate
= instr
->dest
.saturate
;
737 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
738 inst
->saturate
= instr
->dest
.saturate
;
742 if (fs_key
->high_quality_derivatives
) {
743 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
745 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
747 inst
->saturate
= instr
->dest
.saturate
;
749 case nir_op_fddx_fine
:
750 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
751 inst
->saturate
= instr
->dest
.saturate
;
753 case nir_op_fddx_coarse
:
754 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
755 inst
->saturate
= instr
->dest
.saturate
;
758 if (fs_key
->high_quality_derivatives
) {
759 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
760 brw_imm_d(fs_key
->render_to_fbo
));
762 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
763 brw_imm_d(fs_key
->render_to_fbo
));
765 inst
->saturate
= instr
->dest
.saturate
;
767 case nir_op_fddy_fine
:
768 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
769 brw_imm_d(fs_key
->render_to_fbo
));
770 inst
->saturate
= instr
->dest
.saturate
;
772 case nir_op_fddy_coarse
:
773 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
774 brw_imm_d(fs_key
->render_to_fbo
));
775 inst
->saturate
= instr
->dest
.saturate
;
780 inst
= bld
.ADD(result
, op
[0], op
[1]);
781 inst
->saturate
= instr
->dest
.saturate
;
785 inst
= bld
.MUL(result
, op
[0], op
[1]);
786 inst
->saturate
= instr
->dest
.saturate
;
790 bld
.MUL(result
, op
[0], op
[1]);
793 case nir_op_imul_high
:
794 case nir_op_umul_high
:
795 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
800 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
803 case nir_op_uadd_carry
:
804 unreachable("Should have been lowered by carry_to_arith().");
806 case nir_op_usub_borrow
:
807 unreachable("Should have been lowered by borrow_to_arith().");
810 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
816 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
822 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
827 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
832 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
836 if (devinfo
->gen
>= 8) {
837 op
[0] = resolve_source_modifiers(op
[0]);
839 bld
.NOT(result
, op
[0]);
842 if (devinfo
->gen
>= 8) {
843 op
[0] = resolve_source_modifiers(op
[0]);
844 op
[1] = resolve_source_modifiers(op
[1]);
846 bld
.XOR(result
, op
[0], op
[1]);
849 if (devinfo
->gen
>= 8) {
850 op
[0] = resolve_source_modifiers(op
[0]);
851 op
[1] = resolve_source_modifiers(op
[1]);
853 bld
.OR(result
, op
[0], op
[1]);
856 if (devinfo
->gen
>= 8) {
857 op
[0] = resolve_source_modifiers(op
[0]);
858 op
[1] = resolve_source_modifiers(op
[1]);
860 bld
.AND(result
, op
[0], op
[1]);
866 case nir_op_ball_fequal2
:
867 case nir_op_ball_iequal2
:
868 case nir_op_ball_fequal3
:
869 case nir_op_ball_iequal3
:
870 case nir_op_ball_fequal4
:
871 case nir_op_ball_iequal4
:
872 case nir_op_bany_fnequal2
:
873 case nir_op_bany_inequal2
:
874 case nir_op_bany_fnequal3
:
875 case nir_op_bany_inequal3
:
876 case nir_op_bany_fnequal4
:
877 case nir_op_bany_inequal4
:
878 unreachable("Lowered by nir_lower_alu_reductions");
880 case nir_op_fnoise1_1
:
881 case nir_op_fnoise1_2
:
882 case nir_op_fnoise1_3
:
883 case nir_op_fnoise1_4
:
884 case nir_op_fnoise2_1
:
885 case nir_op_fnoise2_2
:
886 case nir_op_fnoise2_3
:
887 case nir_op_fnoise2_4
:
888 case nir_op_fnoise3_1
:
889 case nir_op_fnoise3_2
:
890 case nir_op_fnoise3_3
:
891 case nir_op_fnoise3_4
:
892 case nir_op_fnoise4_1
:
893 case nir_op_fnoise4_2
:
894 case nir_op_fnoise4_3
:
895 case nir_op_fnoise4_4
:
896 unreachable("not reached: should be handled by lower_noise");
899 unreachable("not reached: should be handled by ldexp_to_arith()");
902 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
903 inst
->saturate
= instr
->dest
.saturate
;
907 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
908 inst
->saturate
= instr
->dest
.saturate
;
913 bld
.MOV(result
, negate(op
[0]));
917 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
920 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
924 inst
= bld
.RNDZ(result
, op
[0]);
925 inst
->saturate
= instr
->dest
.saturate
;
929 op
[0].negate
= !op
[0].negate
;
930 fs_reg temp
= vgrf(glsl_type::float_type
);
931 bld
.RNDD(temp
, op
[0]);
933 inst
= bld
.MOV(result
, temp
);
934 inst
->saturate
= instr
->dest
.saturate
;
938 inst
= bld
.RNDD(result
, op
[0]);
939 inst
->saturate
= instr
->dest
.saturate
;
942 inst
= bld
.FRC(result
, op
[0]);
943 inst
->saturate
= instr
->dest
.saturate
;
945 case nir_op_fround_even
:
946 inst
= bld
.RNDE(result
, op
[0]);
947 inst
->saturate
= instr
->dest
.saturate
;
953 if (devinfo
->gen
>= 6) {
954 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
955 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
957 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
958 inst
= bld
.SEL(result
, op
[0], op
[1]);
959 inst
->predicate
= BRW_PREDICATE_NORMAL
;
961 inst
->saturate
= instr
->dest
.saturate
;
967 if (devinfo
->gen
>= 6) {
968 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
969 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
971 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
972 inst
= bld
.SEL(result
, op
[0], op
[1]);
973 inst
->predicate
= BRW_PREDICATE_NORMAL
;
975 inst
->saturate
= instr
->dest
.saturate
;
978 case nir_op_pack_snorm_2x16
:
979 case nir_op_pack_snorm_4x8
:
980 case nir_op_pack_unorm_2x16
:
981 case nir_op_pack_unorm_4x8
:
982 case nir_op_unpack_snorm_2x16
:
983 case nir_op_unpack_snorm_4x8
:
984 case nir_op_unpack_unorm_2x16
:
985 case nir_op_unpack_unorm_4x8
:
986 case nir_op_unpack_half_2x16
:
987 case nir_op_pack_half_2x16
:
988 unreachable("not reached: should be handled by lower_packing_builtins");
990 case nir_op_unpack_half_2x16_split_x
:
991 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
992 inst
->saturate
= instr
->dest
.saturate
;
994 case nir_op_unpack_half_2x16_split_y
:
995 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
996 inst
->saturate
= instr
->dest
.saturate
;
1000 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1001 inst
->saturate
= instr
->dest
.saturate
;
1004 case nir_op_bitfield_reverse
:
1005 bld
.BFREV(result
, op
[0]);
1008 case nir_op_bit_count
:
1009 bld
.CBIT(result
, op
[0]);
1012 case nir_op_ufind_msb
:
1013 case nir_op_ifind_msb
: {
1014 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1016 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1017 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1018 * subtract the result from 31 to convert the MSB count into an LSB count.
1020 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1022 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1023 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1024 inst
->src
[0].negate
= true;
1028 case nir_op_find_lsb
:
1029 bld
.FBL(result
, op
[0]);
1032 case nir_op_ubitfield_extract
:
1033 case nir_op_ibitfield_extract
:
1034 unreachable("should have been lowered");
1037 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1040 bld
.BFI1(result
, op
[0], op
[1]);
1043 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1046 case nir_op_bitfield_insert
:
1047 unreachable("not reached: should have been lowered");
1050 bld
.SHL(result
, op
[0], op
[1]);
1053 bld
.ASR(result
, op
[0], op
[1]);
1056 bld
.SHR(result
, op
[0], op
[1]);
1059 case nir_op_pack_half_2x16_split
:
1060 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1064 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1065 inst
->saturate
= instr
->dest
.saturate
;
1069 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1070 inst
->saturate
= instr
->dest
.saturate
;
1074 if (optimize_frontfacing_ternary(instr
, result
))
1077 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1078 inst
= bld
.SEL(result
, op
[1], op
[2]);
1079 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1083 unreachable("unhandled instruction");
1086 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1087 * to sign extend the low bit to 0/~0
1089 if (devinfo
->gen
<= 5 &&
1090 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1091 fs_reg masked
= vgrf(glsl_type::int_type
);
1092 bld
.AND(masked
, result
, brw_imm_d(1));
1093 masked
.negate
= true;
1094 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1099 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1100 nir_load_const_instr
*instr
)
1102 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1104 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1105 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i
[i
]));
1107 nir_ssa_values
[instr
->def
.index
] = reg
;
1111 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1113 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1114 instr
->def
.num_components
);
1118 fs_visitor::get_nir_src(nir_src src
)
1122 reg
= nir_ssa_values
[src
.ssa
->index
];
1124 /* We don't handle indirects on locals */
1125 assert(src
.reg
.indirect
== NULL
);
1126 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1127 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1130 /* to avoid floating-point denorm flushing problems, set the type by
1131 * default to D - instructions that need floating point semantics will set
1132 * this to F if they need to
1134 return retype(reg
, BRW_REGISTER_TYPE_D
);
1138 fs_visitor::get_nir_dest(nir_dest dest
)
1141 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1142 dest
.ssa
.num_components
);
1143 return nir_ssa_values
[dest
.ssa
.index
];
1145 /* We don't handle indirects on locals */
1146 assert(dest
.reg
.indirect
== NULL
);
1147 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1148 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1153 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1155 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1156 BRW_REGISTER_TYPE_UD
);
1158 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1159 tail
= tail
->child
) {
1160 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1161 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1162 const unsigned size
= glsl_get_length(tail
->type
);
1163 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1164 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1165 image
= offset(image
, bld
, base
* element_size
);
1167 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1168 fs_reg tmp
= vgrf(glsl_type::int_type
);
1170 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1171 /* IVB hangs when trying to access an invalid surface index with
1172 * the dataport. According to the spec "if the index used to
1173 * select an individual element is negative or greater than or
1174 * equal to the size of the array, the results of the operation
1175 * are undefined but may not lead to termination" -- which is one
1176 * of the possible outcomes of the hang. Clamp the index to
1177 * prevent access outside of the array bounds.
1179 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1180 BRW_REGISTER_TYPE_UD
),
1181 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1183 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1186 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1188 bld
.ADD(*image
.reladdr
, *image
.reladdr
, tmp
);
1190 image
.reladdr
= new(mem_ctx
) fs_reg(tmp
);
1198 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1201 for (unsigned i
= 0; i
< 4; i
++) {
1202 if (!((wr_mask
>> i
) & 1))
1205 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1206 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1207 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1208 if (new_inst
->src
[j
].file
== VGRF
)
1209 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1216 * Get the matching channel register datatype for an image intrinsic of the
1217 * specified GLSL image type.
1220 get_image_base_type(const glsl_type
*type
)
1222 switch ((glsl_base_type
)type
->sampler_type
) {
1223 case GLSL_TYPE_UINT
:
1224 return BRW_REGISTER_TYPE_UD
;
1226 return BRW_REGISTER_TYPE_D
;
1227 case GLSL_TYPE_FLOAT
:
1228 return BRW_REGISTER_TYPE_F
;
1230 unreachable("Not reached.");
1235 * Get the appropriate atomic op for an image atomic intrinsic.
1238 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1241 case nir_intrinsic_image_atomic_add
:
1243 case nir_intrinsic_image_atomic_min
:
1244 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1245 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1246 case nir_intrinsic_image_atomic_max
:
1247 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1248 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1249 case nir_intrinsic_image_atomic_and
:
1251 case nir_intrinsic_image_atomic_or
:
1253 case nir_intrinsic_image_atomic_xor
:
1255 case nir_intrinsic_image_atomic_exchange
:
1257 case nir_intrinsic_image_atomic_comp_swap
:
1258 return BRW_AOP_CMPWR
;
1260 unreachable("Not reachable.");
1265 emit_pixel_interpolater_send(const fs_builder
&bld
,
1270 glsl_interp_qualifier interpolation
)
1276 if (src
.file
== BAD_FILE
) {
1278 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1282 mlen
= 2 * bld
.dispatch_width() / 8;
1285 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1287 /* 2 floats per slot returned */
1288 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1289 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1295 * Computes 1 << x, given a D/UD register containing some value x.
1298 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1300 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1302 fs_reg result
= bld
.vgrf(x
.type
, 1);
1303 fs_reg one
= bld
.vgrf(x
.type
, 1);
1305 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1306 bld
.SHL(result
, one
, x
);
1311 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1313 assert(stage
== MESA_SHADER_GEOMETRY
);
1315 struct brw_gs_prog_data
*gs_prog_data
=
1316 (struct brw_gs_prog_data
*) prog_data
;
1318 /* We can only do EndPrimitive() functionality when the control data
1319 * consists of cut bits. Fortunately, the only time it isn't is when the
1320 * output type is points, in which case EndPrimitive() is a no-op.
1322 if (gs_prog_data
->control_data_format
!=
1323 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1327 /* Cut bits use one bit per vertex. */
1328 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1330 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1331 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1333 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1334 * vertex n, 0 otherwise. So all we need to do here is mark bit
1335 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1336 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1337 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1339 * Note that if EndPrimitive() is called before emitting any vertices, this
1340 * will cause us to set bit 31 of the control_data_bits register to 1.
1341 * That's fine because:
1343 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1344 * output, so the hardware will ignore cut bit 31.
1346 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1347 * last vertex, so setting cut bit 31 has no effect (since the primitive
1348 * is automatically ended when the GS terminates).
1350 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1351 * control_data_bits register to 0 when the first vertex is emitted.
1354 const fs_builder abld
= bld
.annotate("end primitive");
1356 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1357 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1358 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1359 fs_reg mask
= intexp2(abld
, prev_count
);
1360 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1361 * attention to the lower 5 bits of its second source argument, so on this
1362 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1363 * ((vertex_count - 1) % 32).
1365 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1369 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1371 assert(stage
== MESA_SHADER_GEOMETRY
);
1372 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1374 struct brw_gs_prog_data
*gs_prog_data
=
1375 (struct brw_gs_prog_data
*) prog_data
;
1377 const fs_builder abld
= bld
.annotate("emit control data bits");
1378 const fs_builder fwa_bld
= bld
.exec_all();
1380 /* We use a single UD register to accumulate control data bits (32 bits
1381 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1384 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1385 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1386 * use the Channel Mask phase to enable/disable which DWord within that
1387 * group to write. (Remember, different SIMD8 channels may have emitted
1388 * different numbers of vertices, so we may need per-slot offsets.)
1390 * Channel masking presents an annoying problem: we may have to replicate
1391 * the data up to 4 times:
1393 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1395 * To avoid penalizing shaders that emit a small number of vertices, we
1396 * can avoid these sometimes: if the size of the control data header is
1397 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1398 * land in the same 128-bit group, so we can skip per-slot offsets.
1400 * Similarly, if the control data header is <= 32 bits, there is only one
1401 * DWord, so we can skip channel masks.
1403 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1405 fs_reg channel_mask
, per_slot_offset
;
1407 if (gs_compile
->control_data_header_size_bits
> 32) {
1408 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1409 channel_mask
= vgrf(glsl_type::uint_type
);
1412 if (gs_compile
->control_data_header_size_bits
> 128) {
1413 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1414 per_slot_offset
= vgrf(glsl_type::uint_type
);
1417 /* Figure out which DWord we're trying to write to using the formula:
1419 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1421 * Since bits_per_vertex is a power of two, and is known at compile
1422 * time, this can be optimized to:
1424 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1426 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1427 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1428 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1429 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1430 unsigned log2_bits_per_vertex
=
1431 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1432 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1434 if (per_slot_offset
.file
!= BAD_FILE
) {
1435 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1436 * the appropriate OWord within the control data header.
1438 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1441 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1442 * write to the appropriate DWORD within the OWORD.
1444 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1445 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1446 channel_mask
= intexp2(fwa_bld
, channel
);
1447 /* Then the channel masks need to be in bits 23:16. */
1448 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1451 /* Store the control data bits in the message payload and send it. */
1453 if (channel_mask
.file
!= BAD_FILE
)
1454 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1455 if (per_slot_offset
.file
!= BAD_FILE
)
1458 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1459 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1461 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1462 if (per_slot_offset
.file
!= BAD_FILE
)
1463 sources
[i
++] = per_slot_offset
;
1464 if (channel_mask
.file
!= BAD_FILE
)
1465 sources
[i
++] = channel_mask
;
1467 sources
[i
++] = this->control_data_bits
;
1470 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1471 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1473 /* We need to increment Global Offset by 256-bits to make room for
1474 * Broadwell's extra "Vertex Count" payload at the beginning of the
1475 * URB entry. Since this is an OWord message, Global Offset is counted
1476 * in 128-bit units, so we must set it to 2.
1478 if (gs_prog_data
->static_vertex_count
== -1)
1483 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1486 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1488 /* Note: we are calling this *before* increasing vertex_count, so
1489 * this->vertex_count == vertex_count - 1 in the formula above.
1492 /* Stream mode uses 2 bits per vertex */
1493 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1495 /* Must be a valid stream */
1496 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1498 /* Control data bits are initialized to 0 so we don't have to set any
1499 * bits when sending vertices to stream 0.
1504 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1506 /* reg::sid = stream_id */
1507 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1508 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1510 /* reg:shift_count = 2 * (vertex_count - 1) */
1511 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1512 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1514 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1515 * attention to the lower 5 bits of its second source argument, so on this
1516 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1517 * stream_id << ((2 * (vertex_count - 1)) % 32).
1519 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1520 abld
.SHL(mask
, sid
, shift_count
);
1521 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1525 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1528 assert(stage
== MESA_SHADER_GEOMETRY
);
1530 struct brw_gs_prog_data
*gs_prog_data
=
1531 (struct brw_gs_prog_data
*) prog_data
;
1533 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1534 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1536 /* Haswell and later hardware ignores the "Render Stream Select" bits
1537 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1538 * and instead sends all primitives down the pipeline for rasterization.
1539 * If the SOL stage is enabled, "Render Stream Select" is honored and
1540 * primitives bound to non-zero streams are discarded after stream output.
1542 * Since the only purpose of primives sent to non-zero streams is to
1543 * be recorded by transform feedback, we can simply discard all geometry
1544 * bound to these streams when transform feedback is disabled.
1546 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1549 /* If we're outputting 32 control data bits or less, then we can wait
1550 * until the shader is over to output them all. Otherwise we need to
1551 * output them as we go. Now is the time to do it, since we're about to
1552 * output the vertex_count'th vertex, so it's guaranteed that the
1553 * control data bits associated with the (vertex_count - 1)th vertex are
1556 if (gs_compile
->control_data_header_size_bits
> 32) {
1557 const fs_builder abld
=
1558 bld
.annotate("emit vertex: emit control data bits");
1560 /* Only emit control data bits if we've finished accumulating a batch
1561 * of 32 bits. This is the case when:
1563 * (vertex_count * bits_per_vertex) % 32 == 0
1565 * (in other words, when the last 5 bits of vertex_count *
1566 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1567 * integer n (which is always the case, since bits_per_vertex is
1568 * always 1 or 2), this is equivalent to requiring that the last 5-n
1569 * bits of vertex_count are 0:
1571 * vertex_count & (2^(5-n) - 1) == 0
1573 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1576 * vertex_count & (32 / bits_per_vertex - 1) == 0
1578 * TODO: If vertex_count is an immediate, we could do some of this math
1579 * at compile time...
1582 abld
.AND(bld
.null_reg_d(), vertex_count
,
1583 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1584 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1586 abld
.IF(BRW_PREDICATE_NORMAL
);
1587 /* If vertex_count is 0, then no control data bits have been
1588 * accumulated yet, so we can skip emitting them.
1590 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1591 BRW_CONDITIONAL_NEQ
);
1592 abld
.IF(BRW_PREDICATE_NORMAL
);
1593 emit_gs_control_data_bits(vertex_count
);
1594 abld
.emit(BRW_OPCODE_ENDIF
);
1596 /* Reset control_data_bits to 0 so we can start accumulating a new
1599 * Note: in the case where vertex_count == 0, this neutralizes the
1600 * effect of any call to EndPrimitive() that the shader may have
1601 * made before outputting its first vertex.
1603 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1604 inst
->force_writemask_all
= true;
1605 abld
.emit(BRW_OPCODE_ENDIF
);
1608 emit_urb_writes(vertex_count
);
1610 /* In stream mode we have to set control data bits for all vertices
1611 * unless we have disabled control data bits completely (which we do
1612 * do for GL_POINTS outputs that don't use streams).
1614 if (gs_compile
->control_data_header_size_bits
> 0 &&
1615 gs_prog_data
->control_data_format
==
1616 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1617 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1622 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1623 const nir_src
&vertex_src
,
1624 unsigned base_offset
,
1625 const nir_src
&offset_src
,
1626 unsigned num_components
)
1628 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1630 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1631 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1632 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1634 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1635 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1636 * gl_PointSize is available as a GS input, however, so it must be that.
1638 const bool is_point_size
= (base_offset
== 0);
1640 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1641 4 * (base_offset
+ offset_const
->u
[0]) < push_reg_count
) {
1642 int imm_offset
= (base_offset
+ offset_const
->u
[0]) * 4 +
1643 vertex_const
->u
[0] * push_reg_count
;
1644 /* This input was pushed into registers. */
1645 if (is_point_size
) {
1646 /* gl_PointSize comes in .w */
1647 assert(imm_offset
== 0);
1648 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1650 for (unsigned i
= 0; i
< num_components
; i
++) {
1651 bld
.MOV(offset(dst
, bld
, i
),
1652 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1656 /* Resort to the pull model. Ensure the VUE handles are provided. */
1657 gs_prog_data
->base
.include_vue_handles
= true;
1659 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1663 /* The vertex index is constant; just select the proper URB handle. */
1665 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i
[0], 0),
1666 BRW_REGISTER_TYPE_UD
);
1668 /* The vertex index is non-constant. We need to use indirect
1669 * addressing to fetch the proper URB handle.
1671 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1672 * indicating that channel <n> should read the handle from
1673 * DWord <n>. We convert that to bytes by multiplying by 4.
1675 * Next, we convert the vertex index to bytes by multiplying
1676 * by 32 (shifting by 5), and add the two together. This is
1677 * the final indirect byte offset.
1679 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1680 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1681 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1682 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1683 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1685 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1686 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1687 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1688 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1689 /* Convert vertex_index to bytes (multiply by 32) */
1690 bld
.SHL(vertex_offset_bytes
,
1691 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1693 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1695 /* Use first_icp_handle as the base offset. There is one register
1696 * of URB handles per vertex, so inform the register allocator that
1697 * we might read up to nir->info.gs.vertices_in registers.
1699 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1700 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1701 fs_reg(icp_offset_bytes
),
1702 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1707 /* Constant indexing - use global offset. */
1708 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1709 inst
->offset
= base_offset
+ offset_const
->u
[0];
1710 inst
->base_mrf
= -1;
1712 inst
->regs_written
= num_components
;
1714 /* Indirect indexing - use per-slot offsets as well. */
1715 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1716 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1717 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1719 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1720 inst
->offset
= base_offset
;
1721 inst
->base_mrf
= -1;
1723 inst
->regs_written
= num_components
;
1726 if (is_point_size
) {
1727 /* Read the whole VUE header (because of alignment) and read .w. */
1728 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1730 inst
->regs_written
= 4;
1731 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1737 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
1739 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
1740 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
1743 /* The only constant offset we should find is 0. brw_nir.c's
1744 * add_const_offset_to_base() will fold other constant offsets
1745 * into instr->const_index[0].
1747 assert(const_value
->u
[0] == 0);
1751 return get_nir_src(*offset_src
);
1755 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1756 nir_intrinsic_instr
*instr
)
1758 assert(stage
== MESA_SHADER_VERTEX
);
1761 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1762 dest
= get_nir_dest(instr
->dest
);
1764 switch (instr
->intrinsic
) {
1765 case nir_intrinsic_load_vertex_id
:
1766 unreachable("should be lowered by lower_vertex_id()");
1768 case nir_intrinsic_load_vertex_id_zero_base
:
1769 case nir_intrinsic_load_base_vertex
:
1770 case nir_intrinsic_load_instance_id
:
1771 case nir_intrinsic_load_base_instance
:
1772 case nir_intrinsic_load_draw_id
: {
1773 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1774 fs_reg val
= nir_system_values
[sv
];
1775 assert(val
.file
!= BAD_FILE
);
1776 dest
.type
= val
.type
;
1782 nir_emit_intrinsic(bld
, instr
);
1788 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
1789 nir_intrinsic_instr
*instr
)
1791 assert(stage
== MESA_SHADER_TESS_EVAL
);
1792 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
1795 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1796 dest
= get_nir_dest(instr
->dest
);
1798 switch (instr
->intrinsic
) {
1799 case nir_intrinsic_load_primitive_id
:
1800 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
1802 case nir_intrinsic_load_tess_coord
:
1803 /* gl_TessCoord is part of the payload in g1-3 */
1804 for (unsigned i
= 0; i
< 3; i
++) {
1805 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
1809 case nir_intrinsic_load_tess_level_outer
:
1810 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
1811 * appears as a push-model input. So, we can simply use the ATTR file
1812 * rather than issuing URB read messages. The data is stored in the
1813 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
1816 switch (tes_prog_data
->domain
) {
1817 case BRW_TESS_DOMAIN_QUAD
:
1818 for (unsigned i
= 0; i
< 4; i
++)
1819 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1821 case BRW_TESS_DOMAIN_TRI
:
1822 for (unsigned i
= 0; i
< 3; i
++)
1823 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1825 case BRW_TESS_DOMAIN_ISOLINE
:
1826 for (unsigned i
= 0; i
< 2; i
++)
1827 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1832 case nir_intrinsic_load_tess_level_inner
:
1833 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
1834 * appears as a push-model input. So, we can simply use the ATTR file
1835 * rather than issuing URB read messages.
1837 switch (tes_prog_data
->domain
) {
1838 case BRW_TESS_DOMAIN_QUAD
:
1839 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
1840 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
1842 case BRW_TESS_DOMAIN_TRI
:
1843 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
1845 case BRW_TESS_DOMAIN_ISOLINE
:
1846 /* ignore - value is undefined */
1851 case nir_intrinsic_load_input
:
1852 case nir_intrinsic_load_per_vertex_input
: {
1853 fs_reg indirect_offset
= get_indirect_offset(instr
);
1854 unsigned imm_offset
= instr
->const_index
[0];
1857 if (indirect_offset
.file
== BAD_FILE
) {
1858 /* Arbitrarily only push up to 32 vec4 slots worth of data,
1859 * which is 16 registers (since each holds 2 vec4 slots).
1861 const unsigned max_push_slots
= 32;
1862 if (imm_offset
< max_push_slots
) {
1863 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
1864 for (int i
= 0; i
< instr
->num_components
; i
++) {
1865 bld
.MOV(offset(dest
, bld
, i
),
1866 component(src
, 4 * (imm_offset
% 2) + i
));
1868 tes_prog_data
->base
.urb_read_length
=
1869 MAX2(tes_prog_data
->base
.urb_read_length
,
1870 DIV_ROUND_UP(imm_offset
+ 1, 2));
1872 /* Replicate the patch handle to all enabled channels */
1873 const fs_reg srcs
[] = {
1874 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
1876 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1877 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
1879 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
1881 inst
->offset
= imm_offset
;
1882 inst
->base_mrf
= -1;
1883 inst
->regs_written
= instr
->num_components
;
1886 /* Indirect indexing - use per-slot offsets as well. */
1887 const fs_reg srcs
[] = {
1888 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
1891 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1892 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1894 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
1896 inst
->offset
= imm_offset
;
1897 inst
->base_mrf
= -1;
1898 inst
->regs_written
= instr
->num_components
;
1903 nir_emit_intrinsic(bld
, instr
);
1909 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
1910 nir_intrinsic_instr
*instr
)
1912 assert(stage
== MESA_SHADER_GEOMETRY
);
1913 fs_reg indirect_offset
;
1916 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1917 dest
= get_nir_dest(instr
->dest
);
1919 switch (instr
->intrinsic
) {
1920 case nir_intrinsic_load_primitive_id
:
1921 assert(stage
== MESA_SHADER_GEOMETRY
);
1922 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1923 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1924 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1927 case nir_intrinsic_load_input
:
1928 unreachable("load_input intrinsics are invalid for the GS stage");
1930 case nir_intrinsic_load_per_vertex_input
:
1931 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
1932 instr
->src
[1], instr
->num_components
);
1935 case nir_intrinsic_emit_vertex_with_counter
:
1936 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
1939 case nir_intrinsic_end_primitive_with_counter
:
1940 emit_gs_end_primitive(instr
->src
[0]);
1943 case nir_intrinsic_set_vertex_count
:
1944 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
1947 case nir_intrinsic_load_invocation_id
: {
1948 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
1949 assert(val
.file
!= BAD_FILE
);
1950 dest
.type
= val
.type
;
1956 nir_emit_intrinsic(bld
, instr
);
1962 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
1963 nir_intrinsic_instr
*instr
)
1965 assert(stage
== MESA_SHADER_FRAGMENT
);
1966 struct brw_wm_prog_data
*wm_prog_data
=
1967 (struct brw_wm_prog_data
*) prog_data
;
1970 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1971 dest
= get_nir_dest(instr
->dest
);
1973 switch (instr
->intrinsic
) {
1974 case nir_intrinsic_load_front_face
:
1975 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1976 *emit_frontfacing_interpolation());
1979 case nir_intrinsic_load_sample_pos
: {
1980 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1981 assert(sample_pos
.file
!= BAD_FILE
);
1982 dest
.type
= sample_pos
.type
;
1983 bld
.MOV(dest
, sample_pos
);
1984 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1988 case nir_intrinsic_load_helper_invocation
:
1989 case nir_intrinsic_load_sample_mask_in
:
1990 case nir_intrinsic_load_sample_id
: {
1991 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1992 fs_reg val
= nir_system_values
[sv
];
1993 assert(val
.file
!= BAD_FILE
);
1994 dest
.type
= val
.type
;
1999 case nir_intrinsic_discard
:
2000 case nir_intrinsic_discard_if
: {
2001 /* We track our discarded pixels in f0.1. By predicating on it, we can
2002 * update just the flag bits that aren't yet discarded. If there's no
2003 * condition, we emit a CMP of g0 != g0, so all currently executing
2004 * channels will get turned off.
2007 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2008 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2009 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2011 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2012 BRW_REGISTER_TYPE_UW
));
2013 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2015 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2016 cmp
->flag_subreg
= 1;
2018 if (devinfo
->gen
>= 6) {
2019 emit_discard_jump();
2024 case nir_intrinsic_interp_var_at_centroid
:
2025 case nir_intrinsic_interp_var_at_sample
:
2026 case nir_intrinsic_interp_var_at_offset
: {
2027 /* Handle ARB_gpu_shader5 interpolation intrinsics
2029 * It's worth a quick word of explanation as to why we handle the full
2030 * variable-based interpolation intrinsic rather than a lowered version
2031 * with like we do for other inputs. We have to do that because the way
2032 * we set up inputs doesn't allow us to use the already setup inputs for
2033 * interpolation. At the beginning of the shader, we go through all of
2034 * the input variables and do the initial interpolation and put it in
2035 * the nir_inputs array based on its location as determined in
2036 * nir_lower_io. If the input isn't used, dead code cleans up and
2037 * everything works fine. However, when we get to the ARB_gpu_shader5
2038 * interpolation intrinsics, we need to reinterpolate the input
2039 * differently. If we used an intrinsic that just had an index it would
2040 * only give us the offset into the nir_inputs array. However, this is
2041 * useless because that value is post-interpolation and we need
2042 * pre-interpolation. In order to get the actual location of the bits
2043 * we get from the vertex fetching hardware, we need the variable.
2045 wm_prog_data
->pulls_bary
= true;
2047 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2048 const glsl_interp_qualifier interpolation
=
2049 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2051 switch (instr
->intrinsic
) {
2052 case nir_intrinsic_interp_var_at_centroid
:
2053 emit_pixel_interpolater_send(bld
,
2054 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2061 case nir_intrinsic_interp_var_at_sample
: {
2062 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2065 unsigned msg_data
= const_sample
->i
[0] << 4;
2067 emit_pixel_interpolater_send(bld
,
2068 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2071 brw_imm_ud(msg_data
),
2074 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2075 BRW_REGISTER_TYPE_UD
);
2077 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2078 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2079 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2080 bld
.exec_all().group(1, 0)
2081 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2082 emit_pixel_interpolater_send(bld
,
2083 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2089 /* Make a loop that sends a message to the pixel interpolater
2090 * for the sample number in each live channel. If there are
2091 * multiple channels with the same sample number then these
2092 * will be handled simultaneously with a single interation of
2095 bld
.emit(BRW_OPCODE_DO
);
2097 /* Get the next live sample number into sample_id_reg */
2098 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2100 /* Set the flag register so that we can perform the send
2101 * message on all channels that have the same sample number
2103 bld
.CMP(bld
.null_reg_ud(),
2104 sample_src
, sample_id
,
2105 BRW_CONDITIONAL_EQ
);
2106 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2107 bld
.exec_all().group(1, 0)
2108 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2110 emit_pixel_interpolater_send(bld
,
2111 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2116 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2118 /* Continue the loop if there are any live channels left */
2119 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2121 bld
.emit(BRW_OPCODE_WHILE
));
2128 case nir_intrinsic_interp_var_at_offset
: {
2129 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2132 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
2133 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
2135 emit_pixel_interpolater_send(bld
,
2136 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2139 brw_imm_ud(off_x
| (off_y
<< 4)),
2142 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2143 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2144 BRW_REGISTER_TYPE_F
);
2145 for (int i
= 0; i
< 2; i
++) {
2146 fs_reg temp
= vgrf(glsl_type::float_type
);
2147 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2148 fs_reg itemp
= vgrf(glsl_type::int_type
);
2149 bld
.MOV(itemp
, temp
); /* float to int */
2151 /* Clamp the upper end of the range to +7/16.
2152 * ARB_gpu_shader5 requires that we support a maximum offset
2153 * of +0.5, which isn't representable in a S0.4 value -- if
2154 * we didn't clamp it, we'd end up with -8/16, which is the
2155 * opposite of what the shader author wanted.
2157 * This is legal due to ARB_gpu_shader5's quantization
2160 * "Not all values of <offset> may be supported; x and y
2161 * offsets may be rounded to fixed-point values with the
2162 * number of fraction bits given by the
2163 * implementation-dependent constant
2164 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2166 set_condmod(BRW_CONDITIONAL_L
,
2167 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2170 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2171 emit_pixel_interpolater_send(bld
,
2182 unreachable("Invalid intrinsic");
2185 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2186 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2187 src
.type
= dest
.type
;
2189 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2190 dest
= offset(dest
, bld
, 1);
2195 nir_emit_intrinsic(bld
, instr
);
2201 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2202 nir_intrinsic_instr
*instr
)
2204 assert(stage
== MESA_SHADER_COMPUTE
);
2205 struct brw_cs_prog_data
*cs_prog_data
=
2206 (struct brw_cs_prog_data
*) prog_data
;
2209 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2210 dest
= get_nir_dest(instr
->dest
);
2212 switch (instr
->intrinsic
) {
2213 case nir_intrinsic_barrier
:
2215 cs_prog_data
->uses_barrier
= true;
2218 case nir_intrinsic_load_local_invocation_id
:
2219 case nir_intrinsic_load_work_group_id
: {
2220 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2221 fs_reg val
= nir_system_values
[sv
];
2222 assert(val
.file
!= BAD_FILE
);
2223 dest
.type
= val
.type
;
2224 for (unsigned i
= 0; i
< 3; i
++)
2225 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2229 case nir_intrinsic_load_num_work_groups
: {
2230 const unsigned surface
=
2231 cs_prog_data
->binding_table
.work_groups_start
;
2233 cs_prog_data
->uses_num_work_groups
= true;
2235 fs_reg surf_index
= brw_imm_ud(surface
);
2236 brw_mark_surface_used(prog_data
, surface
);
2238 /* Read the 3 GLuint components of gl_NumWorkGroups */
2239 for (unsigned i
= 0; i
< 3; i
++) {
2240 fs_reg read_result
=
2241 emit_untyped_read(bld
, surf_index
,
2243 1 /* dims */, 1 /* size */,
2244 BRW_PREDICATE_NONE
);
2245 read_result
.type
= dest
.type
;
2246 bld
.MOV(dest
, read_result
);
2247 dest
= offset(dest
, bld
, 1);
2252 case nir_intrinsic_shared_atomic_add
:
2253 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2255 case nir_intrinsic_shared_atomic_imin
:
2256 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2258 case nir_intrinsic_shared_atomic_umin
:
2259 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2261 case nir_intrinsic_shared_atomic_imax
:
2262 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2264 case nir_intrinsic_shared_atomic_umax
:
2265 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2267 case nir_intrinsic_shared_atomic_and
:
2268 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2270 case nir_intrinsic_shared_atomic_or
:
2271 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2273 case nir_intrinsic_shared_atomic_xor
:
2274 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2276 case nir_intrinsic_shared_atomic_exchange
:
2277 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2279 case nir_intrinsic_shared_atomic_comp_swap
:
2280 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2284 nir_emit_intrinsic(bld
, instr
);
2290 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2293 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2294 dest
= get_nir_dest(instr
->dest
);
2296 switch (instr
->intrinsic
) {
2297 case nir_intrinsic_atomic_counter_inc
:
2298 case nir_intrinsic_atomic_counter_dec
:
2299 case nir_intrinsic_atomic_counter_read
: {
2300 using namespace surface_access
;
2302 /* Get the arguments of the atomic intrinsic. */
2303 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2304 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2305 instr
->const_index
[0]);
2308 /* Emit a surface read or atomic op. */
2309 switch (instr
->intrinsic
) {
2310 case nir_intrinsic_atomic_counter_read
:
2311 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2314 case nir_intrinsic_atomic_counter_inc
:
2315 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2316 fs_reg(), 1, 1, BRW_AOP_INC
);
2319 case nir_intrinsic_atomic_counter_dec
:
2320 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2321 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2325 unreachable("Unreachable");
2328 /* Assign the result. */
2329 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2331 /* Mark the surface as used. */
2332 brw_mark_surface_used(stage_prog_data
, surface
);
2336 case nir_intrinsic_image_load
:
2337 case nir_intrinsic_image_store
:
2338 case nir_intrinsic_image_atomic_add
:
2339 case nir_intrinsic_image_atomic_min
:
2340 case nir_intrinsic_image_atomic_max
:
2341 case nir_intrinsic_image_atomic_and
:
2342 case nir_intrinsic_image_atomic_or
:
2343 case nir_intrinsic_image_atomic_xor
:
2344 case nir_intrinsic_image_atomic_exchange
:
2345 case nir_intrinsic_image_atomic_comp_swap
: {
2346 using namespace image_access
;
2348 /* Get the referenced image variable and type. */
2349 const nir_variable
*var
= instr
->variables
[0]->var
;
2350 const glsl_type
*type
= var
->type
->without_array();
2351 const brw_reg_type base_type
= get_image_base_type(type
);
2353 /* Get some metadata from the image intrinsic. */
2354 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2355 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2356 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2357 const mesa_format format
=
2358 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2359 _mesa_get_shader_image_format(var
->data
.image
.format
));
2361 /* Get the arguments of the image intrinsic. */
2362 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2363 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2364 BRW_REGISTER_TYPE_UD
);
2365 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2366 retype(get_nir_src(instr
->src
[2]), base_type
) :
2368 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2369 retype(get_nir_src(instr
->src
[3]), base_type
) :
2373 /* Emit an image load, store or atomic op. */
2374 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2375 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2377 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2378 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2381 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2382 surf_dims
, arr_dims
, info
->dest_components
,
2383 get_image_atomic_op(instr
->intrinsic
, type
));
2385 /* Assign the result. */
2386 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2387 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2388 offset(tmp
, bld
, c
));
2392 case nir_intrinsic_memory_barrier_atomic_counter
:
2393 case nir_intrinsic_memory_barrier_buffer
:
2394 case nir_intrinsic_memory_barrier_image
:
2395 case nir_intrinsic_memory_barrier
: {
2396 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2397 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2402 case nir_intrinsic_group_memory_barrier
:
2403 case nir_intrinsic_memory_barrier_shared
:
2404 /* We treat these workgroup-level barriers as no-ops. This should be
2405 * safe at present and as long as:
2407 * - Memory access instructions are not subsequently reordered by the
2408 * compiler back-end.
2410 * - All threads from a given compute shader workgroup fit within a
2411 * single subslice and therefore talk to the same HDC shared unit
2412 * what supposedly guarantees ordering and coherency between threads
2413 * from the same workgroup. This may change in the future when we
2414 * start splitting workgroups across multiple subslices.
2416 * - The context is not in fault-and-stream mode, which could cause
2417 * memory transactions (including to SLM) prior to the barrier to be
2418 * replayed after the barrier if a pagefault occurs. This shouldn't
2419 * be a problem up to and including SKL because fault-and-stream is
2420 * not usable due to hardware issues, but that's likely to change in
2425 case nir_intrinsic_shader_clock
: {
2426 /* We cannot do anything if there is an event, so ignore it for now */
2427 fs_reg shader_clock
= get_timestamp(bld
);
2428 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2430 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2434 case nir_intrinsic_image_size
: {
2435 /* Get the referenced image variable and type. */
2436 const nir_variable
*var
= instr
->variables
[0]->var
;
2437 const glsl_type
*type
= var
->type
->without_array();
2439 /* Get the size of the image. */
2440 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2441 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2443 /* For 1DArray image types, the array index is stored in the Z component.
2444 * Fix this by swizzling the Z component to the Y component.
2446 const bool is_1d_array_image
=
2447 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2448 type
->sampler_array
;
2450 /* For CubeArray images, we should count the number of cubes instead
2451 * of the number of faces. Fix it by dividing the (Z component) by 6.
2453 const bool is_cube_array_image
=
2454 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2455 type
->sampler_array
;
2457 /* Copy all the components. */
2458 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2459 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2460 if ((int)c
>= type
->coordinate_components()) {
2461 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2463 } else if (c
== 1 && is_1d_array_image
) {
2464 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2465 offset(size
, bld
, 2));
2466 } else if (c
== 2 && is_cube_array_image
) {
2467 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2468 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2469 offset(size
, bld
, c
), brw_imm_d(6));
2471 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2472 offset(size
, bld
, c
));
2479 case nir_intrinsic_image_samples
:
2480 /* The driver does not support multi-sampled images. */
2481 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2484 case nir_intrinsic_load_uniform
: {
2485 /* Offsets are in bytes but they should always be multiples of 4 */
2486 assert(instr
->const_index
[0] % 4 == 0);
2488 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
2490 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2492 /* Offsets are in bytes but they should always be multiples of 4 */
2493 assert(const_offset
->u
[0] % 4 == 0);
2494 src
.reg_offset
= const_offset
->u
[0] / 4;
2496 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2499 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2500 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2505 case nir_intrinsic_load_ubo
: {
2506 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2510 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2512 surf_index
= brw_imm_ud(index
);
2513 brw_mark_surface_used(prog_data
, index
);
2515 /* The block index is not a constant. Evaluate the index expression
2516 * per-channel and add the base UBO index; we have to select a value
2517 * from any live channel.
2519 surf_index
= vgrf(glsl_type::uint_type
);
2520 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2521 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2522 surf_index
= bld
.emit_uniformize(surf_index
);
2524 /* Assume this may touch any UBO. It would be nice to provide
2525 * a tighter bound, but the array information is already lowered away.
2527 brw_mark_surface_used(prog_data
,
2528 stage_prog_data
->binding_table
.ubo_start
+
2529 nir
->info
.num_ubos
- 1);
2532 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2533 if (const_offset
== NULL
) {
2534 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
2535 BRW_REGISTER_TYPE_D
);
2537 for (int i
= 0; i
< instr
->num_components
; i
++)
2538 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2539 base_offset
, i
* 4);
2541 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2542 packed_consts
.type
= dest
.type
;
2544 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u
[0] & ~15);
2545 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2546 surf_index
, const_offset_reg
);
2548 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2549 packed_consts
.set_smear(const_offset
->u
[0] % 16 / 4 + i
);
2551 /* The std140 packing rules don't allow vectors to cross 16-byte
2552 * boundaries, and a reg is 32 bytes.
2554 assert(packed_consts
.subreg_offset
< 32);
2556 bld
.MOV(dest
, packed_consts
);
2557 dest
= offset(dest
, bld
, 1);
2563 case nir_intrinsic_load_ssbo
: {
2564 assert(devinfo
->gen
>= 7);
2566 nir_const_value
*const_uniform_block
=
2567 nir_src_as_const_value(instr
->src
[0]);
2570 if (const_uniform_block
) {
2571 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2572 const_uniform_block
->u
[0];
2573 surf_index
= brw_imm_ud(index
);
2574 brw_mark_surface_used(prog_data
, index
);
2576 surf_index
= vgrf(glsl_type::uint_type
);
2577 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2578 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2580 /* Assume this may touch any UBO. It would be nice to provide
2581 * a tighter bound, but the array information is already lowered away.
2583 brw_mark_surface_used(prog_data
,
2584 stage_prog_data
->binding_table
.ssbo_start
+
2585 nir
->info
.num_ssbos
- 1);
2589 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2591 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
2593 offset_reg
= get_nir_src(instr
->src
[1]);
2596 /* Read the vector */
2597 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2599 instr
->num_components
,
2600 BRW_PREDICATE_NONE
);
2601 read_result
.type
= dest
.type
;
2602 for (int i
= 0; i
< instr
->num_components
; i
++)
2603 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2608 case nir_intrinsic_load_shared
: {
2609 assert(devinfo
->gen
>= 7);
2611 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2613 /* Get the offset to read from */
2615 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2617 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0]);
2619 offset_reg
= vgrf(glsl_type::uint_type
);
2621 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2622 brw_imm_ud(instr
->const_index
[0]));
2625 /* Read the vector */
2626 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2628 instr
->num_components
,
2629 BRW_PREDICATE_NONE
);
2630 read_result
.type
= dest
.type
;
2631 for (int i
= 0; i
< instr
->num_components
; i
++)
2632 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2637 case nir_intrinsic_store_shared
: {
2638 assert(devinfo
->gen
>= 7);
2641 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2644 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2647 unsigned writemask
= instr
->const_index
[1];
2649 /* Combine groups of consecutive enabled channels in one write
2650 * message. We use ffs to find the first enabled channel and then ffs on
2651 * the bit-inverse, down-shifted writemask to determine the length of
2652 * the block of enabled bits.
2655 unsigned first_component
= ffs(writemask
) - 1;
2656 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2659 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2661 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0] +
2662 4 * first_component
);
2664 offset_reg
= vgrf(glsl_type::uint_type
);
2666 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2667 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2670 emit_untyped_write(bld
, surf_index
, offset_reg
,
2671 offset(val_reg
, bld
, first_component
),
2672 1 /* dims */, length
,
2673 BRW_PREDICATE_NONE
);
2675 /* Clear the bits in the writemask that we just wrote, then try
2676 * again to see if more channels are left.
2678 writemask
&= (15 << (first_component
+ length
));
2684 case nir_intrinsic_load_input
: {
2686 if (stage
== MESA_SHADER_VERTEX
) {
2687 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2689 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2690 instr
->const_index
[0]);
2693 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2694 assert(const_offset
&& "Indirect input loads not allowed");
2695 src
= offset(src
, bld
, const_offset
->u
[0]);
2697 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2698 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2703 case nir_intrinsic_store_ssbo
: {
2704 assert(devinfo
->gen
>= 7);
2708 nir_const_value
*const_uniform_block
=
2709 nir_src_as_const_value(instr
->src
[1]);
2710 if (const_uniform_block
) {
2711 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2712 const_uniform_block
->u
[0];
2713 surf_index
= brw_imm_ud(index
);
2714 brw_mark_surface_used(prog_data
, index
);
2716 surf_index
= vgrf(glsl_type::uint_type
);
2717 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2718 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2720 brw_mark_surface_used(prog_data
,
2721 stage_prog_data
->binding_table
.ssbo_start
+
2722 nir
->info
.num_ssbos
- 1);
2726 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2729 unsigned writemask
= instr
->const_index
[0];
2731 /* Combine groups of consecutive enabled channels in one write
2732 * message. We use ffs to find the first enabled channel and then ffs on
2733 * the bit-inverse, down-shifted writemask to determine the length of
2734 * the block of enabled bits.
2737 unsigned first_component
= ffs(writemask
) - 1;
2738 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2741 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
2743 offset_reg
= brw_imm_ud(const_offset
->u
[0] + 4 * first_component
);
2745 offset_reg
= vgrf(glsl_type::uint_type
);
2747 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2748 brw_imm_ud(4 * first_component
));
2751 emit_untyped_write(bld
, surf_index
, offset_reg
,
2752 offset(val_reg
, bld
, first_component
),
2753 1 /* dims */, length
,
2754 BRW_PREDICATE_NONE
);
2756 /* Clear the bits in the writemask that we just wrote, then try
2757 * again to see if more channels are left.
2759 writemask
&= (15 << (first_component
+ length
));
2764 case nir_intrinsic_store_output
: {
2765 fs_reg src
= get_nir_src(instr
->src
[0]);
2766 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2767 instr
->const_index
[0]);
2769 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2770 assert(const_offset
&& "Indirect output stores not allowed");
2771 new_dest
= offset(new_dest
, bld
, const_offset
->u
[0]);
2773 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2774 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
2779 case nir_intrinsic_ssbo_atomic_add
:
2780 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2782 case nir_intrinsic_ssbo_atomic_imin
:
2783 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2785 case nir_intrinsic_ssbo_atomic_umin
:
2786 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2788 case nir_intrinsic_ssbo_atomic_imax
:
2789 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2791 case nir_intrinsic_ssbo_atomic_umax
:
2792 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2794 case nir_intrinsic_ssbo_atomic_and
:
2795 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2797 case nir_intrinsic_ssbo_atomic_or
:
2798 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2800 case nir_intrinsic_ssbo_atomic_xor
:
2801 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2803 case nir_intrinsic_ssbo_atomic_exchange
:
2804 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2806 case nir_intrinsic_ssbo_atomic_comp_swap
:
2807 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2810 case nir_intrinsic_get_buffer_size
: {
2811 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2812 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
2813 int reg_width
= dispatch_width
/ 8;
2816 fs_reg source
= brw_imm_d(0);
2818 int mlen
= 1 * reg_width
;
2820 /* A resinfo's sampler message is used to get the buffer size.
2821 * The SIMD8's writeback message consists of four registers and
2822 * SIMD16's writeback message consists of 8 destination registers
2823 * (two per each component), although we are only interested on the
2824 * first component, where resinfo returns the buffer size for
2827 int regs_written
= 4 * mlen
;
2828 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2829 BRW_REGISTER_TYPE_UD
);
2830 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2831 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2832 BRW_REGISTER_TYPE_UD
);
2833 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2834 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2835 src_payload
, brw_imm_ud(index
));
2836 inst
->header_size
= 0;
2838 inst
->regs_written
= regs_written
;
2840 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2842 brw_mark_surface_used(prog_data
, index
);
2847 unreachable("unknown intrinsic");
2852 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2853 int op
, nir_intrinsic_instr
*instr
)
2856 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2857 dest
= get_nir_dest(instr
->dest
);
2860 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2861 if (const_surface
) {
2862 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2863 const_surface
->u
[0];
2864 surface
= brw_imm_ud(surf_index
);
2865 brw_mark_surface_used(prog_data
, surf_index
);
2867 surface
= vgrf(glsl_type::uint_type
);
2868 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
2869 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2871 /* Assume this may touch any SSBO. This is the same we do for other
2872 * UBO/SSBO accesses with non-constant surface.
2874 brw_mark_surface_used(prog_data
,
2875 stage_prog_data
->binding_table
.ssbo_start
+
2876 nir
->info
.num_ssbos
- 1);
2879 fs_reg offset
= get_nir_src(instr
->src
[1]);
2880 fs_reg data1
= get_nir_src(instr
->src
[2]);
2882 if (op
== BRW_AOP_CMPWR
)
2883 data2
= get_nir_src(instr
->src
[3]);
2885 /* Emit the actual atomic operation operation */
2887 fs_reg atomic_result
=
2888 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2890 1 /* dims */, 1 /* rsize */,
2892 BRW_PREDICATE_NONE
);
2893 dest
.type
= atomic_result
.type
;
2894 bld
.MOV(dest
, atomic_result
);
2898 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
2899 int op
, nir_intrinsic_instr
*instr
)
2902 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2903 dest
= get_nir_dest(instr
->dest
);
2905 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
2906 fs_reg offset
= get_nir_src(instr
->src
[0]);
2907 fs_reg data1
= get_nir_src(instr
->src
[1]);
2909 if (op
== BRW_AOP_CMPWR
)
2910 data2
= get_nir_src(instr
->src
[2]);
2912 /* Emit the actual atomic operation operation */
2914 fs_reg atomic_result
=
2915 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2917 1 /* dims */, 1 /* rsize */,
2919 BRW_PREDICATE_NONE
);
2920 dest
.type
= atomic_result
.type
;
2921 bld
.MOV(dest
, atomic_result
);
2925 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
2927 unsigned sampler
= instr
->sampler_index
;
2928 fs_reg
sampler_reg(brw_imm_ud(sampler
));
2930 int gather_component
= instr
->component
;
2932 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
2935 int lod_components
= 0;
2936 int UNUSED offset_components
= 0;
2938 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
2940 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2941 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
2942 switch (instr
->src
[i
].src_type
) {
2943 case nir_tex_src_bias
:
2944 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2946 case nir_tex_src_comparitor
:
2947 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
2949 case nir_tex_src_coord
:
2950 switch (instr
->op
) {
2952 case nir_texop_txf_ms
:
2953 case nir_texop_samples_identical
:
2954 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2957 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2961 case nir_tex_src_ddx
:
2962 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2963 lod_components
= nir_tex_instr_src_size(instr
, i
);
2965 case nir_tex_src_ddy
:
2966 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2968 case nir_tex_src_lod
:
2969 switch (instr
->op
) {
2971 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2974 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2977 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2981 case nir_tex_src_ms_index
:
2982 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
2984 case nir_tex_src_offset
:
2985 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
2986 if (instr
->is_array
)
2987 offset_components
= instr
->coord_components
- 1;
2989 offset_components
= instr
->coord_components
;
2991 case nir_tex_src_projector
:
2992 unreachable("should be lowered");
2994 case nir_tex_src_sampler_offset
: {
2995 /* Figure out the highest possible sampler index and mark it as used */
2996 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
2997 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
2998 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
3000 max_used
+= stage_prog_data
->binding_table
.texture_start
;
3002 brw_mark_surface_used(prog_data
, max_used
);
3004 /* Emit code to evaluate the actual indexing expression */
3005 sampler_reg
= vgrf(glsl_type::uint_type
);
3006 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
3007 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
3012 unreachable("unknown texture source");
3016 if (instr
->op
== nir_texop_txf_ms
||
3017 instr
->op
== nir_texop_samples_identical
) {
3018 if (devinfo
->gen
>= 7 &&
3019 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
3020 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
3022 mcs
= brw_imm_ud(0u);
3026 for (unsigned i
= 0; i
< 3; i
++) {
3027 if (instr
->const_offset
[i
] != 0) {
3028 assert(offset_components
== 0);
3029 tex_offset
= brw_imm_ud(brw_texture_offset(instr
->const_offset
, 3));
3034 enum glsl_base_type dest_base_type
=
3035 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
3037 const glsl_type
*dest_type
=
3038 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
3041 ir_texture_opcode op
;
3042 switch (instr
->op
) {
3043 case nir_texop_lod
: op
= ir_lod
; break;
3044 case nir_texop_query_levels
: op
= ir_query_levels
; break;
3045 case nir_texop_tex
: op
= ir_tex
; break;
3046 case nir_texop_tg4
: op
= ir_tg4
; break;
3047 case nir_texop_txb
: op
= ir_txb
; break;
3048 case nir_texop_txd
: op
= ir_txd
; break;
3049 case nir_texop_txf
: op
= ir_txf
; break;
3050 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
3051 case nir_texop_txl
: op
= ir_txl
; break;
3052 case nir_texop_txs
: op
= ir_txs
; break;
3053 case nir_texop_texture_samples
: {
3054 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3055 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
3056 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3059 inst
->header_size
= 1;
3060 inst
->base_mrf
= -1;
3063 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
3065 unreachable("unknown texture opcode");
3068 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
3069 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
3070 tex_offset
, mcs
, gather_component
,
3071 is_cube_array
, sampler
, sampler_reg
);
3073 fs_reg dest
= get_nir_dest(instr
->dest
);
3074 dest
.type
= this->result
.type
;
3075 unsigned num_components
= nir_tex_instr_dest_size(instr
);
3076 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
3077 dest
, this->result
),
3078 (1 << num_components
) - 1);
3082 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3084 switch (instr
->type
) {
3085 case nir_jump_break
:
3086 bld
.emit(BRW_OPCODE_BREAK
);
3088 case nir_jump_continue
:
3089 bld
.emit(BRW_OPCODE_CONTINUE
);
3091 case nir_jump_return
:
3093 unreachable("unknown jump");